2 * Performance event support - powerpc architecture code
4 * Copyright 2008-2009 Paul Mackerras, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/sched.h>
13 #include <linux/perf_event.h>
14 #include <linux/percpu.h>
15 #include <linux/hardirq.h>
16 #include <linux/uaccess.h>
19 #include <asm/machdep.h>
20 #include <asm/firmware.h>
21 #include <asm/ptrace.h>
22 #include <asm/code-patching.h>
24 #define BHRB_MAX_ENTRIES 32
25 #define BHRB_TARGET 0x0000000000000002
26 #define BHRB_PREDICTION 0x0000000000000001
27 #define BHRB_EA 0xFFFFFFFFFFFFFFFCUL
29 struct cpu_hw_events {
36 struct perf_event *event[MAX_HWEVENTS];
37 u64 events[MAX_HWEVENTS];
38 unsigned int flags[MAX_HWEVENTS];
40 * The order of the MMCR array is:
41 * - 64-bit, MMCR0, MMCR1, MMCRA, MMCR2
42 * - 32-bit, MMCR0, MMCR1, MMCR2
44 unsigned long mmcr[4];
45 struct perf_event *limited_counter[MAX_LIMITED_HWCOUNTERS];
46 u8 limited_hwidx[MAX_LIMITED_HWCOUNTERS];
47 u64 alternatives[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
48 unsigned long amasks[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
49 unsigned long avalues[MAX_HWEVENTS][MAX_EVENT_ALTERNATIVES];
51 unsigned int txn_flags;
55 u64 bhrb_filter; /* BHRB HW branch filter */
56 unsigned int bhrb_users;
58 struct perf_branch_stack bhrb_stack;
59 struct perf_branch_entry bhrb_entries[BHRB_MAX_ENTRIES];
62 static DEFINE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
64 static struct power_pmu *ppmu;
67 * Normally, to ignore kernel events we set the FCS (freeze counters
68 * in supervisor mode) bit in MMCR0, but if the kernel runs with the
69 * hypervisor bit set in the MSR, or if we are running on a processor
70 * where the hypervisor bit is forced to 1 (as on Apple G5 processors),
71 * then we need to use the FCHV bit to ignore kernel events.
73 static unsigned int freeze_events_kernel = MMCR0_FCS;
76 * 32-bit doesn't have MMCRA but does have an MMCR2,
77 * and a few other names are different.
82 #define MMCR0_PMCjCE MMCR0_PMCnCE
88 #define MMCR0_PMCC_U6 0
90 #define SPRN_MMCRA SPRN_MMCR2
91 #define MMCRA_SAMPLE_ENABLE 0
93 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
97 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp) { }
98 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
102 static inline void perf_read_regs(struct pt_regs *regs)
106 static inline int perf_intr_is_nmi(struct pt_regs *regs)
111 static inline int siar_valid(struct pt_regs *regs)
116 static bool is_ebb_event(struct perf_event *event) { return false; }
117 static int ebb_event_check(struct perf_event *event) { return 0; }
118 static void ebb_event_add(struct perf_event *event) { }
119 static void ebb_switch_out(unsigned long mmcr0) { }
120 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
122 return cpuhw->mmcr[0];
125 static inline void power_pmu_bhrb_enable(struct perf_event *event) {}
126 static inline void power_pmu_bhrb_disable(struct perf_event *event) {}
127 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in) {}
128 static inline void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw) {}
129 static void pmao_restore_workaround(bool ebb) { }
130 #endif /* CONFIG_PPC32 */
132 static bool regs_use_siar(struct pt_regs *regs)
135 * When we take a performance monitor exception the regs are setup
136 * using perf_read_regs() which overloads some fields, in particular
137 * regs->result to tell us whether to use SIAR.
139 * However if the regs are from another exception, eg. a syscall, then
140 * they have not been setup using perf_read_regs() and so regs->result
141 * is something random.
143 return ((TRAP(regs) == 0xf00) && regs->result);
147 * Things that are specific to 64-bit implementations.
151 static inline unsigned long perf_ip_adjust(struct pt_regs *regs)
153 unsigned long mmcra = regs->dsisr;
155 if ((ppmu->flags & PPMU_HAS_SSLOT) && (mmcra & MMCRA_SAMPLE_ENABLE)) {
156 unsigned long slot = (mmcra & MMCRA_SLOT) >> MMCRA_SLOT_SHIFT;
158 return 4 * (slot - 1);
165 * The user wants a data address recorded.
166 * If we're not doing instruction sampling, give them the SDAR
167 * (sampled data address). If we are doing instruction sampling, then
168 * only give them the SDAR if it corresponds to the instruction
169 * pointed to by SIAR; this is indicated by the [POWER6_]MMCRA_SDSYNC, the
170 * [POWER7P_]MMCRA_SDAR_VALID bit in MMCRA, or the SDAR_VALID bit in SIER.
172 static inline void perf_get_data_addr(struct pt_regs *regs, u64 *addrp)
174 unsigned long mmcra = regs->dsisr;
177 if (ppmu->flags & PPMU_HAS_SIER)
178 sdar_valid = regs->dar & SIER_SDAR_VALID;
180 unsigned long sdsync;
182 if (ppmu->flags & PPMU_SIAR_VALID)
183 sdsync = POWER7P_MMCRA_SDAR_VALID;
184 else if (ppmu->flags & PPMU_ALT_SIPR)
185 sdsync = POWER6_MMCRA_SDSYNC;
187 sdsync = MMCRA_SDSYNC;
189 sdar_valid = mmcra & sdsync;
192 if (!(mmcra & MMCRA_SAMPLE_ENABLE) || sdar_valid)
193 *addrp = mfspr(SPRN_SDAR);
196 static bool regs_sihv(struct pt_regs *regs)
198 unsigned long sihv = MMCRA_SIHV;
200 if (ppmu->flags & PPMU_HAS_SIER)
201 return !!(regs->dar & SIER_SIHV);
203 if (ppmu->flags & PPMU_ALT_SIPR)
204 sihv = POWER6_MMCRA_SIHV;
206 return !!(regs->dsisr & sihv);
209 static bool regs_sipr(struct pt_regs *regs)
211 unsigned long sipr = MMCRA_SIPR;
213 if (ppmu->flags & PPMU_HAS_SIER)
214 return !!(regs->dar & SIER_SIPR);
216 if (ppmu->flags & PPMU_ALT_SIPR)
217 sipr = POWER6_MMCRA_SIPR;
219 return !!(regs->dsisr & sipr);
222 static inline u32 perf_flags_from_msr(struct pt_regs *regs)
224 if (regs->msr & MSR_PR)
225 return PERF_RECORD_MISC_USER;
226 if ((regs->msr & MSR_HV) && freeze_events_kernel != MMCR0_FCHV)
227 return PERF_RECORD_MISC_HYPERVISOR;
228 return PERF_RECORD_MISC_KERNEL;
231 static inline u32 perf_get_misc_flags(struct pt_regs *regs)
233 bool use_siar = regs_use_siar(regs);
236 return perf_flags_from_msr(regs);
239 * If we don't have flags in MMCRA, rather than using
240 * the MSR, we intuit the flags from the address in
241 * SIAR which should give slightly more reliable
244 if (ppmu->flags & PPMU_NO_SIPR) {
245 unsigned long siar = mfspr(SPRN_SIAR);
246 if (siar >= PAGE_OFFSET)
247 return PERF_RECORD_MISC_KERNEL;
248 return PERF_RECORD_MISC_USER;
251 /* PR has priority over HV, so order below is important */
253 return PERF_RECORD_MISC_USER;
255 if (regs_sihv(regs) && (freeze_events_kernel != MMCR0_FCHV))
256 return PERF_RECORD_MISC_HYPERVISOR;
258 return PERF_RECORD_MISC_KERNEL;
262 * Overload regs->dsisr to store MMCRA so we only need to read it once
264 * Overload regs->dar to store SIER if we have it.
265 * Overload regs->result to specify whether we should use the MSR (result
266 * is zero) or the SIAR (result is non zero).
268 static inline void perf_read_regs(struct pt_regs *regs)
270 unsigned long mmcra = mfspr(SPRN_MMCRA);
271 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
276 if (ppmu->flags & PPMU_HAS_SIER)
277 regs->dar = mfspr(SPRN_SIER);
280 * If this isn't a PMU exception (eg a software event) the SIAR is
281 * not valid. Use pt_regs.
283 * If it is a marked event use the SIAR.
285 * If the PMU doesn't update the SIAR for non marked events use
288 * If the PMU has HV/PR flags then check to see if they
289 * place the exception in userspace. If so, use pt_regs. In
290 * continuous sampling mode the SIAR and the PMU exception are
291 * not synchronised, so they may be many instructions apart.
292 * This can result in confusing backtraces. We still want
293 * hypervisor samples as well as samples in the kernel with
294 * interrupts off hence the userspace check.
296 if (TRAP(regs) != 0xf00)
300 else if ((ppmu->flags & PPMU_NO_CONT_SAMPLING))
302 else if (!(ppmu->flags & PPMU_NO_SIPR) && regs_sipr(regs))
307 regs->result = use_siar;
311 * If interrupts were soft-disabled when a PMU interrupt occurs, treat
314 static inline int perf_intr_is_nmi(struct pt_regs *regs)
320 * On processors like P7+ that have the SIAR-Valid bit, marked instructions
321 * must be sampled only if the SIAR-valid bit is set.
323 * For unmarked instructions and for processors that don't have the SIAR-Valid
324 * bit, assume that SIAR is valid.
326 static inline int siar_valid(struct pt_regs *regs)
328 unsigned long mmcra = regs->dsisr;
329 int marked = mmcra & MMCRA_SAMPLE_ENABLE;
332 if (ppmu->flags & PPMU_HAS_SIER)
333 return regs->dar & SIER_SIAR_VALID;
335 if (ppmu->flags & PPMU_SIAR_VALID)
336 return mmcra & POWER7P_MMCRA_SIAR_VALID;
343 /* Reset all possible BHRB entries */
344 static void power_pmu_bhrb_reset(void)
346 asm volatile(PPC_CLRBHRB);
349 static void power_pmu_bhrb_enable(struct perf_event *event)
351 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
356 /* Clear BHRB if we changed task context to avoid data leaks */
357 if (event->ctx->task && cpuhw->bhrb_context != event->ctx) {
358 power_pmu_bhrb_reset();
359 cpuhw->bhrb_context = event->ctx;
362 perf_sched_cb_inc(event->ctx->pmu);
365 static void power_pmu_bhrb_disable(struct perf_event *event)
367 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
372 WARN_ON_ONCE(!cpuhw->bhrb_users);
374 perf_sched_cb_dec(event->ctx->pmu);
376 if (!cpuhw->disabled && !cpuhw->bhrb_users) {
377 /* BHRB cannot be turned off when other
378 * events are active on the PMU.
381 /* avoid stale pointer */
382 cpuhw->bhrb_context = NULL;
386 /* Called from ctxsw to prevent one process's branch entries to
387 * mingle with the other process's entries during context switch.
389 static void power_pmu_sched_task(struct perf_event_context *ctx, bool sched_in)
395 power_pmu_bhrb_reset();
397 /* Calculate the to address for a branch */
398 static __u64 power_pmu_bhrb_to(u64 addr)
404 if (is_kernel_addr(addr)) {
405 if (probe_kernel_read(&instr, (void *)addr, sizeof(instr)))
408 return branch_target(&instr);
411 /* Userspace: need copy instruction here then translate it */
413 ret = __get_user_inatomic(instr, (unsigned int __user *)addr);
420 target = branch_target(&instr);
421 if ((!target) || (instr & BRANCH_ABSOLUTE))
424 /* Translate relative branch target from kernel to user address */
425 return target - (unsigned long)&instr + addr;
428 /* Processing BHRB entries */
429 static void power_pmu_bhrb_read(struct cpu_hw_events *cpuhw)
433 int r_index, u_index, pred;
437 while (r_index < ppmu->bhrb_nr) {
438 /* Assembly read function */
439 val = read_bhrb(r_index++);
441 /* Terminal marker: End of valid BHRB entries */
444 addr = val & BHRB_EA;
445 pred = val & BHRB_PREDICTION;
452 * BHRB rolling buffer could very much contain the kernel
453 * addresses at this point. Check the privileges before
454 * exporting it to userspace (avoid exposure of regions
455 * where we could have speculative execution)
457 if (perf_paranoid_kernel() && !capable(CAP_SYS_ADMIN) &&
458 is_kernel_addr(addr))
461 /* Branches are read most recent first (ie. mfbhrb 0 is
462 * the most recent branch).
463 * There are two types of valid entries:
464 * 1) a target entry which is the to address of a
465 * computed goto like a blr,bctr,btar. The next
466 * entry read from the bhrb will be branch
467 * corresponding to this target (ie. the actual
468 * blr/bctr/btar instruction).
469 * 2) a from address which is an actual branch. If a
470 * target entry proceeds this, then this is the
471 * matching branch for that target. If this is not
472 * following a target entry, then this is a branch
473 * where the target is given as an immediate field
474 * in the instruction (ie. an i or b form branch).
475 * In this case we need to read the instruction from
476 * memory to determine the target/to address.
479 if (val & BHRB_TARGET) {
480 /* Target branches use two entries
481 * (ie. computed gotos/XL form)
483 cpuhw->bhrb_entries[u_index].to = addr;
484 cpuhw->bhrb_entries[u_index].mispred = pred;
485 cpuhw->bhrb_entries[u_index].predicted = ~pred;
487 /* Get from address in next entry */
488 val = read_bhrb(r_index++);
489 addr = val & BHRB_EA;
490 if (val & BHRB_TARGET) {
491 /* Shouldn't have two targets in a
492 row.. Reset index and try again */
496 cpuhw->bhrb_entries[u_index].from = addr;
498 /* Branches to immediate field
500 cpuhw->bhrb_entries[u_index].from = addr;
501 cpuhw->bhrb_entries[u_index].to =
502 power_pmu_bhrb_to(addr);
503 cpuhw->bhrb_entries[u_index].mispred = pred;
504 cpuhw->bhrb_entries[u_index].predicted = ~pred;
510 cpuhw->bhrb_stack.nr = u_index;
514 static bool is_ebb_event(struct perf_event *event)
517 * This could be a per-PMU callback, but we'd rather avoid the cost. We
518 * check that the PMU supports EBB, meaning those that don't can still
519 * use bit 63 of the event code for something else if they wish.
521 return (ppmu->flags & PPMU_ARCH_207S) &&
522 ((event->attr.config >> PERF_EVENT_CONFIG_EBB_SHIFT) & 1);
525 static int ebb_event_check(struct perf_event *event)
527 struct perf_event *leader = event->group_leader;
529 /* Event and group leader must agree on EBB */
530 if (is_ebb_event(leader) != is_ebb_event(event))
533 if (is_ebb_event(event)) {
534 if (!(event->attach_state & PERF_ATTACH_TASK))
537 if (!leader->attr.pinned || !leader->attr.exclusive)
540 if (event->attr.freq ||
541 event->attr.inherit ||
542 event->attr.sample_type ||
543 event->attr.sample_period ||
544 event->attr.enable_on_exec)
551 static void ebb_event_add(struct perf_event *event)
553 if (!is_ebb_event(event) || current->thread.used_ebb)
557 * IFF this is the first time we've added an EBB event, set
558 * PMXE in the user MMCR0 so we can detect when it's cleared by
559 * userspace. We need this so that we can context switch while
560 * userspace is in the EBB handler (where PMXE is 0).
562 current->thread.used_ebb = 1;
563 current->thread.mmcr0 |= MMCR0_PMXE;
566 static void ebb_switch_out(unsigned long mmcr0)
568 if (!(mmcr0 & MMCR0_EBE))
571 current->thread.siar = mfspr(SPRN_SIAR);
572 current->thread.sier = mfspr(SPRN_SIER);
573 current->thread.sdar = mfspr(SPRN_SDAR);
574 current->thread.mmcr0 = mmcr0 & MMCR0_USER_MASK;
575 current->thread.mmcr2 = mfspr(SPRN_MMCR2) & MMCR2_USER_MASK;
578 static unsigned long ebb_switch_in(bool ebb, struct cpu_hw_events *cpuhw)
580 unsigned long mmcr0 = cpuhw->mmcr[0];
585 /* Enable EBB and read/write to all 6 PMCs and BHRB for userspace */
586 mmcr0 |= MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC_U6;
589 * Add any bits from the user MMCR0, FC or PMAO. This is compatible
590 * with pmao_restore_workaround() because we may add PMAO but we never
593 mmcr0 |= current->thread.mmcr0;
596 * Be careful not to set PMXE if userspace had it cleared. This is also
597 * compatible with pmao_restore_workaround() because it has already
598 * cleared PMXE and we leave PMAO alone.
600 if (!(current->thread.mmcr0 & MMCR0_PMXE))
601 mmcr0 &= ~MMCR0_PMXE;
603 mtspr(SPRN_SIAR, current->thread.siar);
604 mtspr(SPRN_SIER, current->thread.sier);
605 mtspr(SPRN_SDAR, current->thread.sdar);
608 * Merge the kernel & user values of MMCR2. The semantics we implement
609 * are that the user MMCR2 can set bits, ie. cause counters to freeze,
610 * but not clear bits. If a task wants to be able to clear bits, ie.
611 * unfreeze counters, it should not set exclude_xxx in its events and
612 * instead manage the MMCR2 entirely by itself.
614 mtspr(SPRN_MMCR2, cpuhw->mmcr[3] | current->thread.mmcr2);
619 static void pmao_restore_workaround(bool ebb)
623 if (!cpu_has_feature(CPU_FTR_PMAO_BUG))
627 * On POWER8E there is a hardware defect which affects the PMU context
628 * switch logic, ie. power_pmu_disable/enable().
630 * When a counter overflows PMXE is cleared and FC/PMAO is set in MMCR0
631 * by the hardware. Sometime later the actual PMU exception is
634 * If we context switch, or simply disable/enable, the PMU prior to the
635 * exception arriving, the exception will be lost when we clear PMAO.
637 * When we reenable the PMU, we will write the saved MMCR0 with PMAO
638 * set, and this _should_ generate an exception. However because of the
639 * defect no exception is generated when we write PMAO, and we get
640 * stuck with no counters counting but no exception delivered.
642 * The workaround is to detect this case and tweak the hardware to
643 * create another pending PMU exception.
645 * We do that by setting up PMC6 (cycles) for an imminent overflow and
646 * enabling the PMU. That causes a new exception to be generated in the
647 * chip, but we don't take it yet because we have interrupts hard
648 * disabled. We then write back the PMU state as we want it to be seen
649 * by the exception handler. When we reenable interrupts the exception
650 * handler will be called and see the correct state.
652 * The logic is the same for EBB, except that the exception is gated by
653 * us having interrupts hard disabled as well as the fact that we are
654 * not in userspace. The exception is finally delivered when we return
658 /* Only if PMAO is set and PMAO_SYNC is clear */
659 if ((current->thread.mmcr0 & (MMCR0_PMAO | MMCR0_PMAO_SYNC)) != MMCR0_PMAO)
662 /* If we're doing EBB, only if BESCR[GE] is set */
663 if (ebb && !(current->thread.bescr & BESCR_GE))
667 * We are already soft-disabled in power_pmu_enable(). We need to hard
668 * enable to actually prevent the PMU exception from firing.
673 * This is a bit gross, but we know we're on POWER8E and have 6 PMCs.
674 * Using read/write_pmc() in a for loop adds 12 function calls and
675 * almost doubles our code size.
677 pmcs[0] = mfspr(SPRN_PMC1);
678 pmcs[1] = mfspr(SPRN_PMC2);
679 pmcs[2] = mfspr(SPRN_PMC3);
680 pmcs[3] = mfspr(SPRN_PMC4);
681 pmcs[4] = mfspr(SPRN_PMC5);
682 pmcs[5] = mfspr(SPRN_PMC6);
684 /* Ensure all freeze bits are unset */
685 mtspr(SPRN_MMCR2, 0);
687 /* Set up PMC6 to overflow in one cycle */
688 mtspr(SPRN_PMC6, 0x7FFFFFFE);
690 /* Enable exceptions and unfreeze PMC6 */
691 mtspr(SPRN_MMCR0, MMCR0_PMXE | MMCR0_PMCjCE | MMCR0_PMAO);
693 /* Now we need to refreeze and restore the PMCs */
694 mtspr(SPRN_MMCR0, MMCR0_FC | MMCR0_PMAO);
696 mtspr(SPRN_PMC1, pmcs[0]);
697 mtspr(SPRN_PMC2, pmcs[1]);
698 mtspr(SPRN_PMC3, pmcs[2]);
699 mtspr(SPRN_PMC4, pmcs[3]);
700 mtspr(SPRN_PMC5, pmcs[4]);
701 mtspr(SPRN_PMC6, pmcs[5]);
703 #endif /* CONFIG_PPC64 */
705 static void perf_event_interrupt(struct pt_regs *regs);
708 * Read one performance monitor counter (PMC).
710 static unsigned long read_pmc(int idx)
716 val = mfspr(SPRN_PMC1);
719 val = mfspr(SPRN_PMC2);
722 val = mfspr(SPRN_PMC3);
725 val = mfspr(SPRN_PMC4);
728 val = mfspr(SPRN_PMC5);
731 val = mfspr(SPRN_PMC6);
735 val = mfspr(SPRN_PMC7);
738 val = mfspr(SPRN_PMC8);
740 #endif /* CONFIG_PPC64 */
742 printk(KERN_ERR "oops trying to read PMC%d\n", idx);
751 static void write_pmc(int idx, unsigned long val)
755 mtspr(SPRN_PMC1, val);
758 mtspr(SPRN_PMC2, val);
761 mtspr(SPRN_PMC3, val);
764 mtspr(SPRN_PMC4, val);
767 mtspr(SPRN_PMC5, val);
770 mtspr(SPRN_PMC6, val);
774 mtspr(SPRN_PMC7, val);
777 mtspr(SPRN_PMC8, val);
779 #endif /* CONFIG_PPC64 */
781 printk(KERN_ERR "oops trying to write PMC%d\n", idx);
785 /* Called from sysrq_handle_showregs() */
786 void perf_event_print_debug(void)
788 unsigned long sdar, sier, flags;
789 u32 pmcs[MAX_HWEVENTS];
792 if (!ppmu->n_counter)
795 local_irq_save(flags);
797 pr_info("CPU: %d PMU registers, ppmu = %s n_counters = %d",
798 smp_processor_id(), ppmu->name, ppmu->n_counter);
800 for (i = 0; i < ppmu->n_counter; i++)
801 pmcs[i] = read_pmc(i + 1);
803 for (; i < MAX_HWEVENTS; i++)
804 pmcs[i] = 0xdeadbeef;
806 pr_info("PMC1: %08x PMC2: %08x PMC3: %08x PMC4: %08x\n",
807 pmcs[0], pmcs[1], pmcs[2], pmcs[3]);
809 if (ppmu->n_counter > 4)
810 pr_info("PMC5: %08x PMC6: %08x PMC7: %08x PMC8: %08x\n",
811 pmcs[4], pmcs[5], pmcs[6], pmcs[7]);
813 pr_info("MMCR0: %016lx MMCR1: %016lx MMCRA: %016lx\n",
814 mfspr(SPRN_MMCR0), mfspr(SPRN_MMCR1), mfspr(SPRN_MMCRA));
818 sdar = mfspr(SPRN_SDAR);
820 if (ppmu->flags & PPMU_HAS_SIER)
821 sier = mfspr(SPRN_SIER);
823 if (ppmu->flags & PPMU_ARCH_207S) {
824 pr_info("MMCR2: %016lx EBBHR: %016lx\n",
825 mfspr(SPRN_MMCR2), mfspr(SPRN_EBBHR));
826 pr_info("EBBRR: %016lx BESCR: %016lx\n",
827 mfspr(SPRN_EBBRR), mfspr(SPRN_BESCR));
830 pr_info("SIAR: %016lx SDAR: %016lx SIER: %016lx\n",
831 mfspr(SPRN_SIAR), sdar, sier);
833 local_irq_restore(flags);
837 * Check if a set of events can all go on the PMU at once.
838 * If they can't, this will look at alternative codes for the events
839 * and see if any combination of alternative codes is feasible.
840 * The feasible set is returned in event_id[].
842 static int power_check_constraints(struct cpu_hw_events *cpuhw,
843 u64 event_id[], unsigned int cflags[],
846 unsigned long mask, value, nv;
847 unsigned long smasks[MAX_HWEVENTS], svalues[MAX_HWEVENTS];
848 int n_alt[MAX_HWEVENTS], choice[MAX_HWEVENTS];
850 unsigned long addf = ppmu->add_fields;
851 unsigned long tadd = ppmu->test_adder;
853 if (n_ev > ppmu->n_counter)
856 /* First see if the events will go on as-is */
857 for (i = 0; i < n_ev; ++i) {
858 if ((cflags[i] & PPMU_LIMITED_PMC_REQD)
859 && !ppmu->limited_pmc_event(event_id[i])) {
860 ppmu->get_alternatives(event_id[i], cflags[i],
861 cpuhw->alternatives[i]);
862 event_id[i] = cpuhw->alternatives[i][0];
864 if (ppmu->get_constraint(event_id[i], &cpuhw->amasks[i][0],
865 &cpuhw->avalues[i][0]))
869 for (i = 0; i < n_ev; ++i) {
870 nv = (value | cpuhw->avalues[i][0]) +
871 (value & cpuhw->avalues[i][0] & addf);
872 if ((((nv + tadd) ^ value) & mask) != 0 ||
873 (((nv + tadd) ^ cpuhw->avalues[i][0]) &
874 cpuhw->amasks[i][0]) != 0)
877 mask |= cpuhw->amasks[i][0];
880 return 0; /* all OK */
882 /* doesn't work, gather alternatives... */
883 if (!ppmu->get_alternatives)
885 for (i = 0; i < n_ev; ++i) {
887 n_alt[i] = ppmu->get_alternatives(event_id[i], cflags[i],
888 cpuhw->alternatives[i]);
889 for (j = 1; j < n_alt[i]; ++j)
890 ppmu->get_constraint(cpuhw->alternatives[i][j],
891 &cpuhw->amasks[i][j],
892 &cpuhw->avalues[i][j]);
895 /* enumerate all possibilities and see if any will work */
898 value = mask = nv = 0;
901 /* we're backtracking, restore context */
907 * See if any alternative k for event_id i,
908 * where k > j, will satisfy the constraints.
910 while (++j < n_alt[i]) {
911 nv = (value | cpuhw->avalues[i][j]) +
912 (value & cpuhw->avalues[i][j] & addf);
913 if ((((nv + tadd) ^ value) & mask) == 0 &&
914 (((nv + tadd) ^ cpuhw->avalues[i][j])
915 & cpuhw->amasks[i][j]) == 0)
920 * No feasible alternative, backtrack
921 * to event_id i-1 and continue enumerating its
922 * alternatives from where we got up to.
928 * Found a feasible alternative for event_id i,
929 * remember where we got up to with this event_id,
930 * go on to the next event_id, and start with
931 * the first alternative for it.
937 mask |= cpuhw->amasks[i][j];
943 /* OK, we have a feasible combination, tell the caller the solution */
944 for (i = 0; i < n_ev; ++i)
945 event_id[i] = cpuhw->alternatives[i][choice[i]];
950 * Check if newly-added events have consistent settings for
951 * exclude_{user,kernel,hv} with each other and any previously
954 static int check_excludes(struct perf_event **ctrs, unsigned int cflags[],
955 int n_prev, int n_new)
957 int eu = 0, ek = 0, eh = 0;
959 struct perf_event *event;
962 * If the PMU we're on supports per event exclude settings then we
963 * don't need to do any of this logic. NB. This assumes no PMU has both
964 * per event exclude and limited PMCs.
966 if (ppmu->flags & PPMU_ARCH_207S)
974 for (i = 0; i < n; ++i) {
975 if (cflags[i] & PPMU_LIMITED_PMC_OK) {
976 cflags[i] &= ~PPMU_LIMITED_PMC_REQD;
981 eu = event->attr.exclude_user;
982 ek = event->attr.exclude_kernel;
983 eh = event->attr.exclude_hv;
985 } else if (event->attr.exclude_user != eu ||
986 event->attr.exclude_kernel != ek ||
987 event->attr.exclude_hv != eh) {
993 for (i = 0; i < n; ++i)
994 if (cflags[i] & PPMU_LIMITED_PMC_OK)
995 cflags[i] |= PPMU_LIMITED_PMC_REQD;
1000 static u64 check_and_compute_delta(u64 prev, u64 val)
1002 u64 delta = (val - prev) & 0xfffffffful;
1005 * POWER7 can roll back counter values, if the new value is smaller
1006 * than the previous value it will cause the delta and the counter to
1007 * have bogus values unless we rolled a counter over. If a coutner is
1008 * rolled back, it will be smaller, but within 256, which is the maximum
1009 * number of events to rollback at once. If we dectect a rollback
1010 * return 0. This can lead to a small lack of precision in the
1013 if (prev > val && (prev - val) < 256)
1019 static void power_pmu_read(struct perf_event *event)
1021 s64 val, delta, prev;
1023 if (event->hw.state & PERF_HES_STOPPED)
1029 if (is_ebb_event(event)) {
1030 val = read_pmc(event->hw.idx);
1031 local64_set(&event->hw.prev_count, val);
1036 * Performance monitor interrupts come even when interrupts
1037 * are soft-disabled, as long as interrupts are hard-enabled.
1038 * Therefore we treat them like NMIs.
1041 prev = local64_read(&event->hw.prev_count);
1043 val = read_pmc(event->hw.idx);
1044 delta = check_and_compute_delta(prev, val);
1047 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
1049 local64_add(delta, &event->count);
1052 * A number of places program the PMC with (0x80000000 - period_left).
1053 * We never want period_left to be less than 1 because we will program
1054 * the PMC with a value >= 0x800000000 and an edge detected PMC will
1055 * roll around to 0 before taking an exception. We have seen this
1058 * To fix this, clamp the minimum value of period_left to 1.
1061 prev = local64_read(&event->hw.period_left);
1065 } while (local64_cmpxchg(&event->hw.period_left, prev, val) != prev);
1069 * On some machines, PMC5 and PMC6 can't be written, don't respect
1070 * the freeze conditions, and don't generate interrupts. This tells
1071 * us if `event' is using such a PMC.
1073 static int is_limited_pmc(int pmcnum)
1075 return (ppmu->flags & PPMU_LIMITED_PMC5_6)
1076 && (pmcnum == 5 || pmcnum == 6);
1079 static void freeze_limited_counters(struct cpu_hw_events *cpuhw,
1080 unsigned long pmc5, unsigned long pmc6)
1082 struct perf_event *event;
1083 u64 val, prev, delta;
1086 for (i = 0; i < cpuhw->n_limited; ++i) {
1087 event = cpuhw->limited_counter[i];
1090 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1091 prev = local64_read(&event->hw.prev_count);
1093 delta = check_and_compute_delta(prev, val);
1095 local64_add(delta, &event->count);
1099 static void thaw_limited_counters(struct cpu_hw_events *cpuhw,
1100 unsigned long pmc5, unsigned long pmc6)
1102 struct perf_event *event;
1106 for (i = 0; i < cpuhw->n_limited; ++i) {
1107 event = cpuhw->limited_counter[i];
1108 event->hw.idx = cpuhw->limited_hwidx[i];
1109 val = (event->hw.idx == 5) ? pmc5 : pmc6;
1110 prev = local64_read(&event->hw.prev_count);
1111 if (check_and_compute_delta(prev, val))
1112 local64_set(&event->hw.prev_count, val);
1113 perf_event_update_userpage(event);
1118 * Since limited events don't respect the freeze conditions, we
1119 * have to read them immediately after freezing or unfreezing the
1120 * other events. We try to keep the values from the limited
1121 * events as consistent as possible by keeping the delay (in
1122 * cycles and instructions) between freezing/unfreezing and reading
1123 * the limited events as small and consistent as possible.
1124 * Therefore, if any limited events are in use, we read them
1125 * both, and always in the same order, to minimize variability,
1126 * and do it inside the same asm that writes MMCR0.
1128 static void write_mmcr0(struct cpu_hw_events *cpuhw, unsigned long mmcr0)
1130 unsigned long pmc5, pmc6;
1132 if (!cpuhw->n_limited) {
1133 mtspr(SPRN_MMCR0, mmcr0);
1138 * Write MMCR0, then read PMC5 and PMC6 immediately.
1139 * To ensure we don't get a performance monitor interrupt
1140 * between writing MMCR0 and freezing/thawing the limited
1141 * events, we first write MMCR0 with the event overflow
1142 * interrupt enable bits turned off.
1144 asm volatile("mtspr %3,%2; mfspr %0,%4; mfspr %1,%5"
1145 : "=&r" (pmc5), "=&r" (pmc6)
1146 : "r" (mmcr0 & ~(MMCR0_PMC1CE | MMCR0_PMCjCE)),
1148 "i" (SPRN_PMC5), "i" (SPRN_PMC6));
1150 if (mmcr0 & MMCR0_FC)
1151 freeze_limited_counters(cpuhw, pmc5, pmc6);
1153 thaw_limited_counters(cpuhw, pmc5, pmc6);
1156 * Write the full MMCR0 including the event overflow interrupt
1157 * enable bits, if necessary.
1159 if (mmcr0 & (MMCR0_PMC1CE | MMCR0_PMCjCE))
1160 mtspr(SPRN_MMCR0, mmcr0);
1164 * Disable all events to prevent PMU interrupts and to allow
1165 * events to be added or removed.
1167 static void power_pmu_disable(struct pmu *pmu)
1169 struct cpu_hw_events *cpuhw;
1170 unsigned long flags, mmcr0, val;
1174 local_irq_save(flags);
1175 cpuhw = this_cpu_ptr(&cpu_hw_events);
1177 if (!cpuhw->disabled) {
1179 * Check if we ever enabled the PMU on this cpu.
1181 if (!cpuhw->pmcs_enabled) {
1183 cpuhw->pmcs_enabled = 1;
1187 * Set the 'freeze counters' bit, clear EBE/BHRBA/PMCC/PMAO/FC56
1189 val = mmcr0 = mfspr(SPRN_MMCR0);
1191 val &= ~(MMCR0_EBE | MMCR0_BHRBA | MMCR0_PMCC | MMCR0_PMAO |
1195 * The barrier is to make sure the mtspr has been
1196 * executed and the PMU has frozen the events etc.
1199 write_mmcr0(cpuhw, val);
1204 * Disable instruction sampling if it was enabled
1206 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1208 cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1213 cpuhw->disabled = 1;
1216 ebb_switch_out(mmcr0);
1220 * These are readable by userspace, may contain kernel
1221 * addresses and are not switched by context switch, so clear
1222 * them now to avoid leaking anything to userspace in general
1223 * including to another process.
1225 if (ppmu->flags & PPMU_ARCH_207S) {
1226 mtspr(SPRN_SDAR, 0);
1227 mtspr(SPRN_SIAR, 0);
1232 local_irq_restore(flags);
1236 * Re-enable all events if disable == 0.
1237 * If we were previously disabled and events were added, then
1238 * put the new config on the PMU.
1240 static void power_pmu_enable(struct pmu *pmu)
1242 struct perf_event *event;
1243 struct cpu_hw_events *cpuhw;
1244 unsigned long flags;
1246 unsigned long val, mmcr0;
1248 unsigned int hwc_index[MAX_HWEVENTS];
1255 local_irq_save(flags);
1257 cpuhw = this_cpu_ptr(&cpu_hw_events);
1258 if (!cpuhw->disabled)
1261 if (cpuhw->n_events == 0) {
1262 ppc_set_pmu_inuse(0);
1266 cpuhw->disabled = 0;
1269 * EBB requires an exclusive group and all events must have the EBB
1270 * flag set, or not set, so we can just check a single event. Also we
1271 * know we have at least one event.
1273 ebb = is_ebb_event(cpuhw->event[0]);
1276 * If we didn't change anything, or only removed events,
1277 * no need to recalculate MMCR* settings and reset the PMCs.
1278 * Just reenable the PMU with the current MMCR* settings
1279 * (possibly updated for removal of events).
1281 if (!cpuhw->n_added) {
1282 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1283 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1288 * Clear all MMCR settings and recompute them for the new set of events.
1290 memset(cpuhw->mmcr, 0, sizeof(cpuhw->mmcr));
1292 if (ppmu->compute_mmcr(cpuhw->events, cpuhw->n_events, hwc_index,
1293 cpuhw->mmcr, cpuhw->event)) {
1294 /* shouldn't ever get here */
1295 printk(KERN_ERR "oops compute_mmcr failed\n");
1299 if (!(ppmu->flags & PPMU_ARCH_207S)) {
1301 * Add in MMCR0 freeze bits corresponding to the attr.exclude_*
1302 * bits for the first event. We have already checked that all
1303 * events have the same value for these bits as the first event.
1305 event = cpuhw->event[0];
1306 if (event->attr.exclude_user)
1307 cpuhw->mmcr[0] |= MMCR0_FCP;
1308 if (event->attr.exclude_kernel)
1309 cpuhw->mmcr[0] |= freeze_events_kernel;
1310 if (event->attr.exclude_hv)
1311 cpuhw->mmcr[0] |= MMCR0_FCHV;
1315 * Write the new configuration to MMCR* with the freeze
1316 * bit set and set the hardware events to their initial values.
1317 * Then unfreeze the events.
1319 ppc_set_pmu_inuse(1);
1320 mtspr(SPRN_MMCRA, cpuhw->mmcr[2] & ~MMCRA_SAMPLE_ENABLE);
1321 mtspr(SPRN_MMCR1, cpuhw->mmcr[1]);
1322 mtspr(SPRN_MMCR0, (cpuhw->mmcr[0] & ~(MMCR0_PMC1CE | MMCR0_PMCjCE))
1324 if (ppmu->flags & PPMU_ARCH_207S)
1325 mtspr(SPRN_MMCR2, cpuhw->mmcr[3]);
1328 * Read off any pre-existing events that need to move
1331 for (i = 0; i < cpuhw->n_events; ++i) {
1332 event = cpuhw->event[i];
1333 if (event->hw.idx && event->hw.idx != hwc_index[i] + 1) {
1334 power_pmu_read(event);
1335 write_pmc(event->hw.idx, 0);
1341 * Initialize the PMCs for all the new and moved events.
1343 cpuhw->n_limited = n_lim = 0;
1344 for (i = 0; i < cpuhw->n_events; ++i) {
1345 event = cpuhw->event[i];
1348 idx = hwc_index[i] + 1;
1349 if (is_limited_pmc(idx)) {
1350 cpuhw->limited_counter[n_lim] = event;
1351 cpuhw->limited_hwidx[n_lim] = idx;
1357 val = local64_read(&event->hw.prev_count);
1360 if (event->hw.sample_period) {
1361 left = local64_read(&event->hw.period_left);
1362 if (left < 0x80000000L)
1363 val = 0x80000000L - left;
1365 local64_set(&event->hw.prev_count, val);
1368 event->hw.idx = idx;
1369 if (event->hw.state & PERF_HES_STOPPED)
1371 write_pmc(idx, val);
1373 perf_event_update_userpage(event);
1375 cpuhw->n_limited = n_lim;
1376 cpuhw->mmcr[0] |= MMCR0_PMXE | MMCR0_FCECE;
1379 pmao_restore_workaround(ebb);
1381 mmcr0 = ebb_switch_in(ebb, cpuhw);
1384 if (cpuhw->bhrb_users)
1385 ppmu->config_bhrb(cpuhw->bhrb_filter);
1387 write_mmcr0(cpuhw, mmcr0);
1390 * Enable instruction sampling if necessary
1392 if (cpuhw->mmcr[2] & MMCRA_SAMPLE_ENABLE) {
1394 mtspr(SPRN_MMCRA, cpuhw->mmcr[2]);
1399 local_irq_restore(flags);
1402 static int collect_events(struct perf_event *group, int max_count,
1403 struct perf_event *ctrs[], u64 *events,
1404 unsigned int *flags)
1407 struct perf_event *event;
1409 if (group->pmu->task_ctx_nr == perf_hw_context) {
1413 flags[n] = group->hw.event_base;
1414 events[n++] = group->hw.config;
1416 list_for_each_entry(event, &group->sibling_list, group_entry) {
1417 if (event->pmu->task_ctx_nr == perf_hw_context &&
1418 event->state != PERF_EVENT_STATE_OFF) {
1422 flags[n] = event->hw.event_base;
1423 events[n++] = event->hw.config;
1430 * Add a event to the PMU.
1431 * If all events are not already frozen, then we disable and
1432 * re-enable the PMU in order to get hw_perf_enable to do the
1433 * actual work of reconfiguring the PMU.
1435 static int power_pmu_add(struct perf_event *event, int ef_flags)
1437 struct cpu_hw_events *cpuhw;
1438 unsigned long flags;
1442 local_irq_save(flags);
1443 perf_pmu_disable(event->pmu);
1446 * Add the event to the list (if there is room)
1447 * and check whether the total set is still feasible.
1449 cpuhw = this_cpu_ptr(&cpu_hw_events);
1450 n0 = cpuhw->n_events;
1451 if (n0 >= ppmu->n_counter)
1453 cpuhw->event[n0] = event;
1454 cpuhw->events[n0] = event->hw.config;
1455 cpuhw->flags[n0] = event->hw.event_base;
1458 * This event may have been disabled/stopped in record_and_restart()
1459 * because we exceeded the ->event_limit. If re-starting the event,
1460 * clear the ->hw.state (STOPPED and UPTODATE flags), so the user
1461 * notification is re-enabled.
1463 if (!(ef_flags & PERF_EF_START))
1464 event->hw.state = PERF_HES_STOPPED | PERF_HES_UPTODATE;
1466 event->hw.state = 0;
1469 * If group events scheduling transaction was started,
1470 * skip the schedulability test here, it will be performed
1471 * at commit time(->commit_txn) as a whole
1473 if (cpuhw->txn_flags & PERF_PMU_TXN_ADD)
1476 if (check_excludes(cpuhw->event, cpuhw->flags, n0, 1))
1478 if (power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n0 + 1))
1480 event->hw.config = cpuhw->events[n0];
1483 ebb_event_add(event);
1490 if (has_branch_stack(event)) {
1491 power_pmu_bhrb_enable(event);
1492 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1493 event->attr.branch_sample_type);
1496 perf_pmu_enable(event->pmu);
1497 local_irq_restore(flags);
1502 * Remove a event from the PMU.
1504 static void power_pmu_del(struct perf_event *event, int ef_flags)
1506 struct cpu_hw_events *cpuhw;
1508 unsigned long flags;
1510 local_irq_save(flags);
1511 perf_pmu_disable(event->pmu);
1513 power_pmu_read(event);
1515 cpuhw = this_cpu_ptr(&cpu_hw_events);
1516 for (i = 0; i < cpuhw->n_events; ++i) {
1517 if (event == cpuhw->event[i]) {
1518 while (++i < cpuhw->n_events) {
1519 cpuhw->event[i-1] = cpuhw->event[i];
1520 cpuhw->events[i-1] = cpuhw->events[i];
1521 cpuhw->flags[i-1] = cpuhw->flags[i];
1524 ppmu->disable_pmc(event->hw.idx - 1, cpuhw->mmcr);
1525 if (event->hw.idx) {
1526 write_pmc(event->hw.idx, 0);
1529 perf_event_update_userpage(event);
1533 for (i = 0; i < cpuhw->n_limited; ++i)
1534 if (event == cpuhw->limited_counter[i])
1536 if (i < cpuhw->n_limited) {
1537 while (++i < cpuhw->n_limited) {
1538 cpuhw->limited_counter[i-1] = cpuhw->limited_counter[i];
1539 cpuhw->limited_hwidx[i-1] = cpuhw->limited_hwidx[i];
1543 if (cpuhw->n_events == 0) {
1544 /* disable exceptions if no events are running */
1545 cpuhw->mmcr[0] &= ~(MMCR0_PMXE | MMCR0_FCECE);
1548 if (has_branch_stack(event))
1549 power_pmu_bhrb_disable(event);
1551 perf_pmu_enable(event->pmu);
1552 local_irq_restore(flags);
1556 * POWER-PMU does not support disabling individual counters, hence
1557 * program their cycle counter to their max value and ignore the interrupts.
1560 static void power_pmu_start(struct perf_event *event, int ef_flags)
1562 unsigned long flags;
1566 if (!event->hw.idx || !event->hw.sample_period)
1569 if (!(event->hw.state & PERF_HES_STOPPED))
1572 if (ef_flags & PERF_EF_RELOAD)
1573 WARN_ON_ONCE(!(event->hw.state & PERF_HES_UPTODATE));
1575 local_irq_save(flags);
1576 perf_pmu_disable(event->pmu);
1578 event->hw.state = 0;
1579 left = local64_read(&event->hw.period_left);
1582 if (left < 0x80000000L)
1583 val = 0x80000000L - left;
1585 write_pmc(event->hw.idx, val);
1587 perf_event_update_userpage(event);
1588 perf_pmu_enable(event->pmu);
1589 local_irq_restore(flags);
1592 static void power_pmu_stop(struct perf_event *event, int ef_flags)
1594 unsigned long flags;
1596 if (!event->hw.idx || !event->hw.sample_period)
1599 if (event->hw.state & PERF_HES_STOPPED)
1602 local_irq_save(flags);
1603 perf_pmu_disable(event->pmu);
1605 power_pmu_read(event);
1606 event->hw.state |= PERF_HES_STOPPED | PERF_HES_UPTODATE;
1607 write_pmc(event->hw.idx, 0);
1609 perf_event_update_userpage(event);
1610 perf_pmu_enable(event->pmu);
1611 local_irq_restore(flags);
1615 * Start group events scheduling transaction
1616 * Set the flag to make pmu::enable() not perform the
1617 * schedulability test, it will be performed at commit time
1619 * We only support PERF_PMU_TXN_ADD transactions. Save the
1620 * transaction flags but otherwise ignore non-PERF_PMU_TXN_ADD
1623 static void power_pmu_start_txn(struct pmu *pmu, unsigned int txn_flags)
1625 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1627 WARN_ON_ONCE(cpuhw->txn_flags); /* txn already in flight */
1629 cpuhw->txn_flags = txn_flags;
1630 if (txn_flags & ~PERF_PMU_TXN_ADD)
1633 perf_pmu_disable(pmu);
1634 cpuhw->n_txn_start = cpuhw->n_events;
1638 * Stop group events scheduling transaction
1639 * Clear the flag and pmu::enable() will perform the
1640 * schedulability test.
1642 static void power_pmu_cancel_txn(struct pmu *pmu)
1644 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
1645 unsigned int txn_flags;
1647 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1649 txn_flags = cpuhw->txn_flags;
1650 cpuhw->txn_flags = 0;
1651 if (txn_flags & ~PERF_PMU_TXN_ADD)
1654 perf_pmu_enable(pmu);
1658 * Commit group events scheduling transaction
1659 * Perform the group schedulability test as a whole
1660 * Return 0 if success
1662 static int power_pmu_commit_txn(struct pmu *pmu)
1664 struct cpu_hw_events *cpuhw;
1670 cpuhw = this_cpu_ptr(&cpu_hw_events);
1671 WARN_ON_ONCE(!cpuhw->txn_flags); /* no txn in flight */
1673 if (cpuhw->txn_flags & ~PERF_PMU_TXN_ADD) {
1674 cpuhw->txn_flags = 0;
1678 n = cpuhw->n_events;
1679 if (check_excludes(cpuhw->event, cpuhw->flags, 0, n))
1681 i = power_check_constraints(cpuhw, cpuhw->events, cpuhw->flags, n);
1685 for (i = cpuhw->n_txn_start; i < n; ++i)
1686 cpuhw->event[i]->hw.config = cpuhw->events[i];
1688 cpuhw->txn_flags = 0;
1689 perf_pmu_enable(pmu);
1694 * Return 1 if we might be able to put event on a limited PMC,
1696 * A event can only go on a limited PMC if it counts something
1697 * that a limited PMC can count, doesn't require interrupts, and
1698 * doesn't exclude any processor mode.
1700 static int can_go_on_limited_pmc(struct perf_event *event, u64 ev,
1704 u64 alt[MAX_EVENT_ALTERNATIVES];
1706 if (event->attr.exclude_user
1707 || event->attr.exclude_kernel
1708 || event->attr.exclude_hv
1709 || event->attr.sample_period)
1712 if (ppmu->limited_pmc_event(ev))
1716 * The requested event_id isn't on a limited PMC already;
1717 * see if any alternative code goes on a limited PMC.
1719 if (!ppmu->get_alternatives)
1722 flags |= PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD;
1723 n = ppmu->get_alternatives(ev, flags, alt);
1729 * Find an alternative event_id that goes on a normal PMC, if possible,
1730 * and return the event_id code, or 0 if there is no such alternative.
1731 * (Note: event_id code 0 is "don't count" on all machines.)
1733 static u64 normal_pmc_alternative(u64 ev, unsigned long flags)
1735 u64 alt[MAX_EVENT_ALTERNATIVES];
1738 flags &= ~(PPMU_LIMITED_PMC_OK | PPMU_LIMITED_PMC_REQD);
1739 n = ppmu->get_alternatives(ev, flags, alt);
1745 /* Number of perf_events counting hardware events */
1746 static atomic_t num_events;
1747 /* Used to avoid races in calling reserve/release_pmc_hardware */
1748 static DEFINE_MUTEX(pmc_reserve_mutex);
1751 * Release the PMU if this is the last perf_event.
1753 static void hw_perf_event_destroy(struct perf_event *event)
1755 if (!atomic_add_unless(&num_events, -1, 1)) {
1756 mutex_lock(&pmc_reserve_mutex);
1757 if (atomic_dec_return(&num_events) == 0)
1758 release_pmc_hardware();
1759 mutex_unlock(&pmc_reserve_mutex);
1764 * Translate a generic cache event_id config to a raw event_id code.
1766 static int hw_perf_cache_event(u64 config, u64 *eventp)
1768 unsigned long type, op, result;
1771 if (!ppmu->cache_events)
1775 type = config & 0xff;
1776 op = (config >> 8) & 0xff;
1777 result = (config >> 16) & 0xff;
1779 if (type >= PERF_COUNT_HW_CACHE_MAX ||
1780 op >= PERF_COUNT_HW_CACHE_OP_MAX ||
1781 result >= PERF_COUNT_HW_CACHE_RESULT_MAX)
1784 ev = (*ppmu->cache_events)[type][op][result];
1793 static int power_pmu_event_init(struct perf_event *event)
1796 unsigned long flags;
1797 struct perf_event *ctrs[MAX_HWEVENTS];
1798 u64 events[MAX_HWEVENTS];
1799 unsigned int cflags[MAX_HWEVENTS];
1802 struct cpu_hw_events *cpuhw;
1807 if (has_branch_stack(event)) {
1808 /* PMU has BHRB enabled */
1809 if (!(ppmu->flags & PPMU_ARCH_207S))
1813 switch (event->attr.type) {
1814 case PERF_TYPE_HARDWARE:
1815 ev = event->attr.config;
1816 if (ev >= ppmu->n_generic || ppmu->generic_events[ev] == 0)
1818 ev = ppmu->generic_events[ev];
1820 case PERF_TYPE_HW_CACHE:
1821 err = hw_perf_cache_event(event->attr.config, &ev);
1826 ev = event->attr.config;
1832 event->hw.config_base = ev;
1836 * If we are not running on a hypervisor, force the
1837 * exclude_hv bit to 0 so that we don't care what
1838 * the user set it to.
1840 if (!firmware_has_feature(FW_FEATURE_LPAR))
1841 event->attr.exclude_hv = 0;
1844 * If this is a per-task event, then we can use
1845 * PM_RUN_* events interchangeably with their non RUN_*
1846 * equivalents, e.g. PM_RUN_CYC instead of PM_CYC.
1847 * XXX we should check if the task is an idle task.
1850 if (event->attach_state & PERF_ATTACH_TASK)
1851 flags |= PPMU_ONLY_COUNT_RUN;
1854 * If this machine has limited events, check whether this
1855 * event_id could go on a limited event.
1857 if (ppmu->flags & PPMU_LIMITED_PMC5_6) {
1858 if (can_go_on_limited_pmc(event, ev, flags)) {
1859 flags |= PPMU_LIMITED_PMC_OK;
1860 } else if (ppmu->limited_pmc_event(ev)) {
1862 * The requested event_id is on a limited PMC,
1863 * but we can't use a limited PMC; see if any
1864 * alternative goes on a normal PMC.
1866 ev = normal_pmc_alternative(ev, flags);
1872 /* Extra checks for EBB */
1873 err = ebb_event_check(event);
1878 * If this is in a group, check if it can go on with all the
1879 * other hardware events in the group. We assume the event
1880 * hasn't been linked into its leader's sibling list at this point.
1883 if (event->group_leader != event) {
1884 n = collect_events(event->group_leader, ppmu->n_counter - 1,
1885 ctrs, events, cflags);
1892 if (check_excludes(ctrs, cflags, n, 1))
1895 cpuhw = &get_cpu_var(cpu_hw_events);
1896 err = power_check_constraints(cpuhw, events, cflags, n + 1);
1898 if (has_branch_stack(event)) {
1899 cpuhw->bhrb_filter = ppmu->bhrb_filter_map(
1900 event->attr.branch_sample_type);
1902 if (cpuhw->bhrb_filter == -1) {
1903 put_cpu_var(cpu_hw_events);
1908 put_cpu_var(cpu_hw_events);
1912 event->hw.config = events[n];
1913 event->hw.event_base = cflags[n];
1914 event->hw.last_period = event->hw.sample_period;
1915 local64_set(&event->hw.period_left, event->hw.last_period);
1918 * For EBB events we just context switch the PMC value, we don't do any
1919 * of the sample_period logic. We use hw.prev_count for this.
1921 if (is_ebb_event(event))
1922 local64_set(&event->hw.prev_count, 0);
1925 * See if we need to reserve the PMU.
1926 * If no events are currently in use, then we have to take a
1927 * mutex to ensure that we don't race with another task doing
1928 * reserve_pmc_hardware or release_pmc_hardware.
1931 if (!atomic_inc_not_zero(&num_events)) {
1932 mutex_lock(&pmc_reserve_mutex);
1933 if (atomic_read(&num_events) == 0 &&
1934 reserve_pmc_hardware(perf_event_interrupt))
1937 atomic_inc(&num_events);
1938 mutex_unlock(&pmc_reserve_mutex);
1940 event->destroy = hw_perf_event_destroy;
1945 static int power_pmu_event_idx(struct perf_event *event)
1947 return event->hw.idx;
1950 ssize_t power_events_sysfs_show(struct device *dev,
1951 struct device_attribute *attr, char *page)
1953 struct perf_pmu_events_attr *pmu_attr;
1955 pmu_attr = container_of(attr, struct perf_pmu_events_attr, attr);
1957 return sprintf(page, "event=0x%02llx\n", pmu_attr->id);
1960 static struct pmu power_pmu = {
1961 .pmu_enable = power_pmu_enable,
1962 .pmu_disable = power_pmu_disable,
1963 .event_init = power_pmu_event_init,
1964 .add = power_pmu_add,
1965 .del = power_pmu_del,
1966 .start = power_pmu_start,
1967 .stop = power_pmu_stop,
1968 .read = power_pmu_read,
1969 .start_txn = power_pmu_start_txn,
1970 .cancel_txn = power_pmu_cancel_txn,
1971 .commit_txn = power_pmu_commit_txn,
1972 .event_idx = power_pmu_event_idx,
1973 .sched_task = power_pmu_sched_task,
1977 * A counter has overflowed; update its count and record
1978 * things if requested. Note that interrupts are hard-disabled
1979 * here so there is no possibility of being interrupted.
1981 static void record_and_restart(struct perf_event *event, unsigned long val,
1982 struct pt_regs *regs)
1984 u64 period = event->hw.sample_period;
1985 s64 prev, delta, left;
1988 if (event->hw.state & PERF_HES_STOPPED) {
1989 write_pmc(event->hw.idx, 0);
1993 /* we don't have to worry about interrupts here */
1994 prev = local64_read(&event->hw.prev_count);
1995 delta = check_and_compute_delta(prev, val);
1996 local64_add(delta, &event->count);
1999 * See if the total period for this event has expired,
2000 * and update for the next period.
2003 left = local64_read(&event->hw.period_left) - delta;
2013 * If address is not requested in the sample via
2014 * PERF_SAMPLE_IP, just record that sample irrespective
2015 * of SIAR valid check.
2017 if (event->attr.sample_type & PERF_SAMPLE_IP)
2018 record = siar_valid(regs);
2022 event->hw.last_period = event->hw.sample_period;
2024 if (left < 0x80000000LL)
2025 val = 0x80000000LL - left;
2028 write_pmc(event->hw.idx, val);
2029 local64_set(&event->hw.prev_count, val);
2030 local64_set(&event->hw.period_left, left);
2031 perf_event_update_userpage(event);
2034 * Due to hardware limitation, sometimes SIAR could sample a kernel
2035 * address even when freeze on supervisor state (kernel) is set in
2036 * MMCR2. Check attr.exclude_kernel and address to drop the sample in
2039 if (event->attr.exclude_kernel &&
2040 (event->attr.sample_type & PERF_SAMPLE_IP) &&
2041 is_kernel_addr(mfspr(SPRN_SIAR)))
2045 * Finally record data if requested.
2048 struct perf_sample_data data;
2050 perf_sample_data_init(&data, ~0ULL, event->hw.last_period);
2052 if (event->attr.sample_type & PERF_SAMPLE_ADDR)
2053 perf_get_data_addr(regs, &data.addr);
2055 if (event->attr.sample_type & PERF_SAMPLE_BRANCH_STACK) {
2056 struct cpu_hw_events *cpuhw;
2057 cpuhw = this_cpu_ptr(&cpu_hw_events);
2058 power_pmu_bhrb_read(cpuhw);
2059 data.br_stack = &cpuhw->bhrb_stack;
2062 if (perf_event_overflow(event, &data, regs))
2063 power_pmu_stop(event, 0);
2068 * Called from generic code to get the misc flags (i.e. processor mode)
2071 unsigned long perf_misc_flags(struct pt_regs *regs)
2073 u32 flags = perf_get_misc_flags(regs);
2077 return user_mode(regs) ? PERF_RECORD_MISC_USER :
2078 PERF_RECORD_MISC_KERNEL;
2082 * Called from generic code to get the instruction pointer
2085 unsigned long perf_instruction_pointer(struct pt_regs *regs)
2087 bool use_siar = regs_use_siar(regs);
2089 if (use_siar && siar_valid(regs))
2090 return mfspr(SPRN_SIAR) + perf_ip_adjust(regs);
2092 return 0; // no valid instruction pointer
2097 static bool pmc_overflow_power7(unsigned long val)
2100 * Events on POWER7 can roll back if a speculative event doesn't
2101 * eventually complete. Unfortunately in some rare cases they will
2102 * raise a performance monitor exception. We need to catch this to
2103 * ensure we reset the PMC. In all cases the PMC will be 256 or less
2104 * cycles from overflow.
2106 * We only do this if the first pass fails to find any overflowing
2107 * PMCs because a user might set a period of less than 256 and we
2108 * don't want to mistakenly reset them.
2110 if ((0x80000000 - val) <= 256)
2116 static bool pmc_overflow(unsigned long val)
2125 * Performance monitor interrupt stuff
2127 static void perf_event_interrupt(struct pt_regs *regs)
2130 struct cpu_hw_events *cpuhw = this_cpu_ptr(&cpu_hw_events);
2131 struct perf_event *event;
2132 unsigned long val[8];
2136 if (cpuhw->n_limited)
2137 freeze_limited_counters(cpuhw, mfspr(SPRN_PMC5),
2140 perf_read_regs(regs);
2142 nmi = perf_intr_is_nmi(regs);
2148 /* Read all the PMCs since we'll need them a bunch of times */
2149 for (i = 0; i < ppmu->n_counter; ++i)
2150 val[i] = read_pmc(i + 1);
2152 /* Try to find what caused the IRQ */
2154 for (i = 0; i < ppmu->n_counter; ++i) {
2155 if (!pmc_overflow(val[i]))
2157 if (is_limited_pmc(i + 1))
2158 continue; /* these won't generate IRQs */
2160 * We've found one that's overflowed. For active
2161 * counters we need to log this. For inactive
2162 * counters, we need to reset it anyway
2166 for (j = 0; j < cpuhw->n_events; ++j) {
2167 event = cpuhw->event[j];
2168 if (event->hw.idx == (i + 1)) {
2170 record_and_restart(event, val[i], regs);
2175 /* reset non active counters that have overflowed */
2176 write_pmc(i + 1, 0);
2178 if (!found && pvr_version_is(PVR_POWER7)) {
2179 /* check active counters for special buggy p7 overflow */
2180 for (i = 0; i < cpuhw->n_events; ++i) {
2181 event = cpuhw->event[i];
2182 if (!event->hw.idx || is_limited_pmc(event->hw.idx))
2184 if (pmc_overflow_power7(val[event->hw.idx - 1])) {
2185 /* event has overflowed in a buggy way*/
2187 record_and_restart(event,
2188 val[event->hw.idx - 1],
2193 if (!found && !nmi && printk_ratelimit())
2194 printk(KERN_WARNING "Can't find PMC that caused IRQ\n");
2197 * Reset MMCR0 to its normal value. This will set PMXE and
2198 * clear FC (freeze counters) and PMAO (perf mon alert occurred)
2199 * and thus allow interrupts to occur again.
2200 * XXX might want to use MSR.PM to keep the events frozen until
2201 * we get back out of this interrupt.
2203 write_mmcr0(cpuhw, cpuhw->mmcr[0]);
2211 static void power_pmu_setup(int cpu)
2213 struct cpu_hw_events *cpuhw = &per_cpu(cpu_hw_events, cpu);
2217 memset(cpuhw, 0, sizeof(*cpuhw));
2218 cpuhw->mmcr[0] = MMCR0_FC;
2222 power_pmu_notifier(struct notifier_block *self, unsigned long action, void *hcpu)
2224 unsigned int cpu = (long)hcpu;
2226 switch (action & ~CPU_TASKS_FROZEN) {
2227 case CPU_UP_PREPARE:
2228 power_pmu_setup(cpu);
2238 int register_power_pmu(struct power_pmu *pmu)
2241 return -EBUSY; /* something's already registered */
2244 pr_info("%s performance monitor hardware support registered\n",
2247 power_pmu.attr_groups = ppmu->attr_groups;
2251 * Use FCHV to ignore kernel events if MSR.HV is set.
2253 if (mfmsr() & MSR_HV)
2254 freeze_events_kernel = MMCR0_FCHV;
2255 #endif /* CONFIG_PPC64 */
2257 perf_pmu_register(&power_pmu, "cpu", PERF_TYPE_RAW);
2258 perf_cpu_notifier(power_pmu_notifier);