1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Performance event support - PPC 8xx
5 * Copyright 2016 Christophe Leroy, CS Systemes d'Information
8 #include <linux/kernel.h>
9 #include <linux/sched.h>
10 #include <linux/perf_event.h>
11 #include <linux/percpu.h>
12 #include <linux/hardirq.h>
14 #include <asm/machdep.h>
15 #include <asm/firmware.h>
16 #include <asm/ptrace.h>
17 #include <asm/code-patching.h>
20 #define PERF_8xx_ID_CPU_CYCLES 1
21 #define PERF_8xx_ID_HW_INSTRUCTIONS 2
22 #define PERF_8xx_ID_ITLB_LOAD_MISS 3
23 #define PERF_8xx_ID_DTLB_LOAD_MISS 4
25 #define C(x) PERF_COUNT_HW_CACHE_##x
26 #define DTLB_LOAD_MISS (C(DTLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16))
27 #define ITLB_LOAD_MISS (C(ITLB) | (C(OP_READ) << 8) | (C(RESULT_MISS) << 16))
29 extern unsigned long itlb_miss_counter, dtlb_miss_counter;
30 extern atomic_t instruction_counter;
32 static atomic_t insn_ctr_ref;
33 static atomic_t itlb_miss_ref;
34 static atomic_t dtlb_miss_ref;
36 static s64 get_insn_ctr(void)
42 ctr = atomic_read(&instruction_counter);
43 counta = mfspr(SPRN_COUNTA);
44 } while (ctr != atomic_read(&instruction_counter));
46 return ((s64)ctr << 16) | (counta >> 16);
49 static int event_type(struct perf_event *event)
51 switch (event->attr.type) {
52 case PERF_TYPE_HARDWARE:
53 if (event->attr.config == PERF_COUNT_HW_CPU_CYCLES)
54 return PERF_8xx_ID_CPU_CYCLES;
55 if (event->attr.config == PERF_COUNT_HW_INSTRUCTIONS)
56 return PERF_8xx_ID_HW_INSTRUCTIONS;
58 case PERF_TYPE_HW_CACHE:
59 if (event->attr.config == ITLB_LOAD_MISS)
60 return PERF_8xx_ID_ITLB_LOAD_MISS;
61 if (event->attr.config == DTLB_LOAD_MISS)
62 return PERF_8xx_ID_DTLB_LOAD_MISS;
72 static int mpc8xx_pmu_event_init(struct perf_event *event)
74 int type = event_type(event);
81 static int mpc8xx_pmu_add(struct perf_event *event, int flags)
83 int type = event_type(event);
90 case PERF_8xx_ID_CPU_CYCLES:
93 case PERF_8xx_ID_HW_INSTRUCTIONS:
94 if (atomic_inc_return(&insn_ctr_ref) == 1)
95 mtspr(SPRN_ICTRL, 0xc0080007);
98 case PERF_8xx_ID_ITLB_LOAD_MISS:
99 if (atomic_inc_return(&itlb_miss_ref) == 1) {
100 unsigned long target = patch_site_addr(&patch__itlbmiss_perf);
102 patch_branch_site(&patch__itlbmiss_exit_1, target, 0);
104 val = itlb_miss_counter;
106 case PERF_8xx_ID_DTLB_LOAD_MISS:
107 if (atomic_inc_return(&dtlb_miss_ref) == 1) {
108 unsigned long target = patch_site_addr(&patch__dtlbmiss_perf);
110 patch_branch_site(&patch__dtlbmiss_exit_1, target, 0);
112 val = dtlb_miss_counter;
115 local64_set(&event->hw.prev_count, val);
119 static void mpc8xx_pmu_read(struct perf_event *event)
121 int type = event_type(event);
122 s64 prev, val = 0, delta = 0;
128 prev = local64_read(&event->hw.prev_count);
130 case PERF_8xx_ID_CPU_CYCLES:
132 delta = 16 * (val - prev);
134 case PERF_8xx_ID_HW_INSTRUCTIONS:
135 val = get_insn_ctr();
138 delta += 0x1000000000000LL;
140 case PERF_8xx_ID_ITLB_LOAD_MISS:
141 val = itlb_miss_counter;
142 delta = (s64)((s32)val - (s32)prev);
144 case PERF_8xx_ID_DTLB_LOAD_MISS:
145 val = dtlb_miss_counter;
146 delta = (s64)((s32)val - (s32)prev);
149 } while (local64_cmpxchg(&event->hw.prev_count, prev, val) != prev);
151 local64_add(delta, &event->count);
154 static void mpc8xx_pmu_del(struct perf_event *event, int flags)
156 struct ppc_inst insn = ppc_inst(PPC_RAW_MFSPR(10, SPRN_SPRG_SCRATCH2));
158 mpc8xx_pmu_read(event);
160 /* If it was the last user, stop counting to avoid useles overhead */
161 switch (event_type(event)) {
162 case PERF_8xx_ID_CPU_CYCLES:
164 case PERF_8xx_ID_HW_INSTRUCTIONS:
165 if (atomic_dec_return(&insn_ctr_ref) == 0)
166 mtspr(SPRN_ICTRL, 7);
168 case PERF_8xx_ID_ITLB_LOAD_MISS:
169 if (atomic_dec_return(&itlb_miss_ref) == 0)
170 patch_instruction_site(&patch__itlbmiss_exit_1, insn);
172 case PERF_8xx_ID_DTLB_LOAD_MISS:
173 if (atomic_dec_return(&dtlb_miss_ref) == 0)
174 patch_instruction_site(&patch__dtlbmiss_exit_1, insn);
179 static struct pmu mpc8xx_pmu = {
180 .event_init = mpc8xx_pmu_event_init,
181 .add = mpc8xx_pmu_add,
182 .del = mpc8xx_pmu_del,
183 .read = mpc8xx_pmu_read,
184 .capabilities = PERF_PMU_CAP_NO_INTERRUPT |
188 static int init_mpc8xx_pmu(void)
190 mtspr(SPRN_ICTRL, 7);
192 mtspr(SPRN_COUNTA, 0xffff);
194 return perf_pmu_register(&mpc8xx_pmu, "cpu", PERF_TYPE_RAW);
197 early_initcall(init_mpc8xx_pmu);