1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Freescale Embedded oprofile support, based on ppc64 oprofile support
4 * Copyright (C) 2004 Anton Blanchard <anton@au.ibm.com>, IBM
6 * Copyright (c) 2004, 2010 Freescale Semiconductor, Inc
9 * Maintainer: Kumar Gala <galak@kernel.crashing.org>
12 #include <linux/oprofile.h>
13 #include <linux/smp.h>
14 #include <asm/ptrace.h>
15 #include <asm/processor.h>
16 #include <asm/cputable.h>
17 #include <asm/reg_fsl_emb.h>
20 #include <asm/oprofile_impl.h>
22 static unsigned long reset_value[OP_MAX_COUNTER];
24 static int num_counters;
25 static int oprofile_running;
27 static inline u32 get_pmlca(int ctr)
33 pmlca = mfpmr(PMRN_PMLCA0);
36 pmlca = mfpmr(PMRN_PMLCA1);
39 pmlca = mfpmr(PMRN_PMLCA2);
42 pmlca = mfpmr(PMRN_PMLCA3);
45 pmlca = mfpmr(PMRN_PMLCA4);
48 pmlca = mfpmr(PMRN_PMLCA5);
51 panic("Bad ctr number\n");
57 static inline void set_pmlca(int ctr, u32 pmlca)
61 mtpmr(PMRN_PMLCA0, pmlca);
64 mtpmr(PMRN_PMLCA1, pmlca);
67 mtpmr(PMRN_PMLCA2, pmlca);
70 mtpmr(PMRN_PMLCA3, pmlca);
73 mtpmr(PMRN_PMLCA4, pmlca);
76 mtpmr(PMRN_PMLCA5, pmlca);
79 panic("Bad ctr number\n");
83 static inline unsigned int ctr_read(unsigned int i)
87 return mfpmr(PMRN_PMC0);
89 return mfpmr(PMRN_PMC1);
91 return mfpmr(PMRN_PMC2);
93 return mfpmr(PMRN_PMC3);
95 return mfpmr(PMRN_PMC4);
97 return mfpmr(PMRN_PMC5);
103 static inline void ctr_write(unsigned int i, unsigned int val)
107 mtpmr(PMRN_PMC0, val);
110 mtpmr(PMRN_PMC1, val);
113 mtpmr(PMRN_PMC2, val);
116 mtpmr(PMRN_PMC3, val);
119 mtpmr(PMRN_PMC4, val);
122 mtpmr(PMRN_PMC5, val);
130 static void init_pmc_stop(int ctr)
132 u32 pmlca = (PMLCA_FC | PMLCA_FCS | PMLCA_FCU |
133 PMLCA_FCM1 | PMLCA_FCM0);
138 mtpmr(PMRN_PMLCA0, pmlca);
139 mtpmr(PMRN_PMLCB0, pmlcb);
142 mtpmr(PMRN_PMLCA1, pmlca);
143 mtpmr(PMRN_PMLCB1, pmlcb);
146 mtpmr(PMRN_PMLCA2, pmlca);
147 mtpmr(PMRN_PMLCB2, pmlcb);
150 mtpmr(PMRN_PMLCA3, pmlca);
151 mtpmr(PMRN_PMLCB3, pmlcb);
154 mtpmr(PMRN_PMLCA4, pmlca);
155 mtpmr(PMRN_PMLCB4, pmlcb);
158 mtpmr(PMRN_PMLCA5, pmlca);
159 mtpmr(PMRN_PMLCB5, pmlcb);
162 panic("Bad ctr number!\n");
166 static void set_pmc_event(int ctr, int event)
170 pmlca = get_pmlca(ctr);
172 pmlca = (pmlca & ~PMLCA_EVENT_MASK) |
173 ((event << PMLCA_EVENT_SHIFT) &
176 set_pmlca(ctr, pmlca);
179 static void set_pmc_user_kernel(int ctr, int user, int kernel)
183 pmlca = get_pmlca(ctr);
195 set_pmlca(ctr, pmlca);
198 static void set_pmc_marked(int ctr, int mark0, int mark1)
200 u32 pmlca = get_pmlca(ctr);
203 pmlca &= ~PMLCA_FCM0;
208 pmlca &= ~PMLCA_FCM1;
212 set_pmlca(ctr, pmlca);
215 static void pmc_start_ctr(int ctr, int enable)
217 u32 pmlca = get_pmlca(ctr);
226 set_pmlca(ctr, pmlca);
229 static void pmc_start_ctrs(int enable)
231 u32 pmgc0 = mfpmr(PMRN_PMGC0);
234 pmgc0 |= PMGC0_FCECE;
239 pmgc0 &= ~PMGC0_PMIE;
241 mtpmr(PMRN_PMGC0, pmgc0);
244 static void pmc_stop_ctrs(void)
246 u32 pmgc0 = mfpmr(PMRN_PMGC0);
250 pmgc0 &= ~(PMGC0_PMIE | PMGC0_FCECE);
252 mtpmr(PMRN_PMGC0, pmgc0);
255 static int fsl_emb_cpu_setup(struct op_counter_config *ctr)
259 /* freeze all counters */
262 for (i = 0;i < num_counters;i++) {
265 set_pmc_event(i, ctr[i].event);
267 set_pmc_user_kernel(i, ctr[i].user, ctr[i].kernel);
273 static int fsl_emb_reg_setup(struct op_counter_config *ctr,
274 struct op_system_config *sys,
279 num_counters = num_ctrs;
281 /* Our counters count up, and "count" refers to
282 * how much before the next interrupt, and we interrupt
283 * on overflow. So we calculate the starting value
284 * which will give us "count" until overflow.
285 * Then we set the events on the enabled counters */
286 for (i = 0; i < num_counters; ++i)
287 reset_value[i] = 0x80000000UL - ctr[i].count;
292 static int fsl_emb_start(struct op_counter_config *ctr)
296 mtmsr(mfmsr() | MSR_PMM);
298 for (i = 0; i < num_counters; ++i) {
299 if (ctr[i].enabled) {
300 ctr_write(i, reset_value[i]);
301 /* Set each enabled counter to only
302 * count when the Mark bit is *not* set */
303 set_pmc_marked(i, 1, 0);
308 /* Set the ctr to be stopped */
313 /* Clear the freeze bit, and enable the interrupt.
314 * The counters won't actually start until the rfi clears
318 oprofile_running = 1;
320 pr_debug("start on cpu %d, pmgc0 %x\n", smp_processor_id(),
326 static void fsl_emb_stop(void)
328 /* freeze counters */
331 oprofile_running = 0;
333 pr_debug("stop on cpu %d, pmgc0 %x\n", smp_processor_id(),
340 static void fsl_emb_handle_interrupt(struct pt_regs *regs,
341 struct op_counter_config *ctr)
349 is_kernel = is_kernel_addr(pc);
351 for (i = 0; i < num_counters; ++i) {
354 if (oprofile_running && ctr[i].enabled) {
355 oprofile_add_ext_sample(pc, regs, i, is_kernel);
356 ctr_write(i, reset_value[i]);
363 /* The freeze bit was set by the interrupt. */
364 /* Clear the freeze bit, and reenable the interrupt. The
365 * counters won't actually start until the rfi clears the PMM
366 * bit. The PMM bit should not be set until after the interrupt
367 * is cleared to avoid it getting lost in some hypervisor
370 mtmsr(mfmsr() | MSR_PMM);
374 struct op_powerpc_model op_model_fsl_emb = {
375 .reg_setup = fsl_emb_reg_setup,
376 .cpu_setup = fsl_emb_cpu_setup,
377 .start = fsl_emb_start,
378 .stop = fsl_emb_stop,
379 .handle_interrupt = fsl_emb_handle_interrupt,