2 * This file contains the routines for TLB flushing.
3 * On machines where the MMU does not use a hash table to store virtual to
4 * physical translations (ie, SW loaded TLBs or Book3E compilant processors,
5 * this does -not- include 603 however which shares the implementation with
6 * hash based processors)
10 * Copyright 2008,2009 Ben Herrenschmidt <benh@kernel.crashing.org>
13 * Derived from arch/ppc/mm/init.c:
14 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
16 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
17 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
18 * Copyright (C) 1996 Paul Mackerras
20 * Derived from "arch/i386/mm/init.c"
21 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
23 * This program is free software; you can redistribute it and/or
24 * modify it under the terms of the GNU General Public License
25 * as published by the Free Software Foundation; either version
26 * 2 of the License, or (at your option) any later version.
30 #include <linux/kernel.h>
31 #include <linux/export.h>
33 #include <linux/init.h>
34 #include <linux/highmem.h>
35 #include <linux/pagemap.h>
36 #include <linux/preempt.h>
37 #include <linux/spinlock.h>
38 #include <linux/memblock.h>
39 #include <linux/of_fdt.h>
40 #include <linux/hugetlb.h>
42 #include <asm/tlbflush.h>
44 #include <asm/code-patching.h>
45 #include <asm/cputhreads.h>
46 #include <asm/hugetlb.h>
52 * This struct lists the sw-supported page sizes. The hardawre MMU may support
53 * other sizes not listed here. The .ind field is only used on MMUs that have
54 * indirect page table entries.
56 #if defined(CONFIG_PPC_BOOK3E_MMU) || defined(CONFIG_PPC_8xx)
57 #ifdef CONFIG_PPC_FSL_BOOK3E
58 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
61 .enc = BOOK3E_PAGESZ_4K,
65 .enc = BOOK3E_PAGESZ_2M,
69 .enc = BOOK3E_PAGESZ_4M,
73 .enc = BOOK3E_PAGESZ_16M,
77 .enc = BOOK3E_PAGESZ_64M,
81 .enc = BOOK3E_PAGESZ_256M,
85 .enc = BOOK3E_PAGESZ_1GB,
88 #elif defined(CONFIG_PPC_8xx)
89 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
90 /* we only manage 4k and 16k pages as normal pages */
91 #ifdef CONFIG_PPC_4K_PAGES
108 struct mmu_psize_def mmu_psize_defs[MMU_PAGE_COUNT] = {
112 .enc = BOOK3E_PAGESZ_4K,
116 .enc = BOOK3E_PAGESZ_16K,
121 .enc = BOOK3E_PAGESZ_64K,
125 .enc = BOOK3E_PAGESZ_1M,
130 .enc = BOOK3E_PAGESZ_16M,
134 .enc = BOOK3E_PAGESZ_256M,
138 .enc = BOOK3E_PAGESZ_1GB,
141 #endif /* CONFIG_FSL_BOOKE */
143 static inline int mmu_get_tsize(int psize)
145 return mmu_psize_defs[psize].enc;
148 static inline int mmu_get_tsize(int psize)
150 /* This isn't used on !Book3E for now */
153 #endif /* CONFIG_PPC_BOOK3E_MMU */
155 /* The variables below are currently only used on 64-bit Book3E
156 * though this will probably be made common with other nohash
157 * implementations at some point
161 int mmu_linear_psize; /* Page size used for the linear mapping */
162 int mmu_pte_psize; /* Page size used for PTE pages */
163 int mmu_vmemmap_psize; /* Page size used for the virtual mem map */
164 int book3e_htw_mode; /* HW tablewalk? Value is PPC_HTW_* */
165 unsigned long linear_map_top; /* Top of linear mapping */
169 * Number of bytes to add to SPRN_SPRG_TLB_EXFRAME on crit/mcheck/debug
170 * exceptions. This is used for bolted and e6500 TLB miss handlers which
171 * do not modify this SPRG in the TLB miss code; for other TLB miss handlers,
172 * this is set to zero.
176 #endif /* CONFIG_PPC64 */
178 #ifdef CONFIG_PPC_FSL_BOOK3E
179 /* next_tlbcam_idx is used to round-robin tlbcam entry assignment */
180 DEFINE_PER_CPU(int, next_tlbcam_idx);
181 EXPORT_PER_CPU_SYMBOL(next_tlbcam_idx);
185 * Base TLB flushing operations:
187 * - flush_tlb_mm(mm) flushes the specified mm context TLB's
188 * - flush_tlb_page(vma, vmaddr) flushes one page
189 * - flush_tlb_range(vma, start, end) flushes a range of pages
190 * - flush_tlb_kernel_range(start, end) flushes kernel pages
192 * - local_* variants of page and mm only apply to the current
197 * These are the base non-SMP variants of page and mm flushing
199 void local_flush_tlb_mm(struct mm_struct *mm)
204 pid = mm->context.id;
205 if (pid != MMU_NO_CONTEXT)
209 EXPORT_SYMBOL(local_flush_tlb_mm);
211 void __local_flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
217 pid = mm ? mm->context.id : 0;
218 if (pid != MMU_NO_CONTEXT)
219 _tlbil_va(vmaddr, pid, tsize, ind);
223 void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
225 __local_flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
226 mmu_get_tsize(mmu_virtual_psize), 0);
228 EXPORT_SYMBOL(local_flush_tlb_page);
231 * And here are the SMP non-local implementations
235 static DEFINE_RAW_SPINLOCK(tlbivax_lock);
237 struct tlb_flush_param {
244 static void do_flush_tlb_mm_ipi(void *param)
246 struct tlb_flush_param *p = param;
248 _tlbil_pid(p ? p->pid : 0);
251 static void do_flush_tlb_page_ipi(void *param)
253 struct tlb_flush_param *p = param;
255 _tlbil_va(p->addr, p->pid, p->tsize, p->ind);
259 /* Note on invalidations and PID:
261 * We snapshot the PID with preempt disabled. At this point, it can still
262 * change either because:
263 * - our context is being stolen (PID -> NO_CONTEXT) on another CPU
264 * - we are invaliating some target that isn't currently running here
265 * and is concurrently acquiring a new PID on another CPU
266 * - some other CPU is re-acquiring a lost PID for this mm
269 * However, this shouldn't be a problem as we only guarantee
270 * invalidation of TLB entries present prior to this call, so we
271 * don't care about the PID changing, and invalidating a stale PID
272 * is generally harmless.
275 void flush_tlb_mm(struct mm_struct *mm)
280 pid = mm->context.id;
281 if (unlikely(pid == MMU_NO_CONTEXT))
283 if (!mm_is_core_local(mm)) {
284 struct tlb_flush_param p = { .pid = pid };
285 /* Ignores smp_processor_id() even if set. */
286 smp_call_function_many(mm_cpumask(mm),
287 do_flush_tlb_mm_ipi, &p, 1);
293 EXPORT_SYMBOL(flush_tlb_mm);
295 void __flush_tlb_page(struct mm_struct *mm, unsigned long vmaddr,
298 struct cpumask *cpu_mask;
302 * This function as well as __local_flush_tlb_page() must only be called
305 if (unlikely(WARN_ON(!mm)))
309 pid = mm->context.id;
310 if (unlikely(pid == MMU_NO_CONTEXT))
312 cpu_mask = mm_cpumask(mm);
313 if (!mm_is_core_local(mm)) {
314 /* If broadcast tlbivax is supported, use it */
315 if (mmu_has_feature(MMU_FTR_USE_TLBIVAX_BCAST)) {
316 int lock = mmu_has_feature(MMU_FTR_LOCK_BCAST_INVAL);
318 raw_spin_lock(&tlbivax_lock);
319 _tlbivax_bcast(vmaddr, pid, tsize, ind);
321 raw_spin_unlock(&tlbivax_lock);
324 struct tlb_flush_param p = {
330 /* Ignores smp_processor_id() even if set in cpu_mask */
331 smp_call_function_many(cpu_mask,
332 do_flush_tlb_page_ipi, &p, 1);
335 _tlbil_va(vmaddr, pid, tsize, ind);
340 void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr)
342 #ifdef CONFIG_HUGETLB_PAGE
343 if (vma && is_vm_hugetlb_page(vma))
344 flush_hugetlb_page(vma, vmaddr);
347 __flush_tlb_page(vma ? vma->vm_mm : NULL, vmaddr,
348 mmu_get_tsize(mmu_virtual_psize), 0);
350 EXPORT_SYMBOL(flush_tlb_page);
352 #endif /* CONFIG_SMP */
354 #ifdef CONFIG_PPC_47x
355 void __init early_init_mmu_47x(void)
358 unsigned long root = of_get_flat_dt_root();
359 if (of_get_flat_dt_prop(root, "cooperative-partition", NULL))
360 mmu_clear_feature(MMU_FTR_USE_TLBIVAX_BCAST);
361 #endif /* CONFIG_SMP */
363 #endif /* CONFIG_PPC_47x */
366 * Flush kernel TLB entries in the given range
368 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
372 smp_call_function(do_flush_tlb_mm_ipi, NULL, 1);
379 EXPORT_SYMBOL(flush_tlb_kernel_range);
382 * Currently, for range flushing, we just do a full mm flush. This should
383 * be optimized based on a threshold on the size of the range, since
384 * some implementation can stack multiple tlbivax before a tlbsync but
385 * for now, we keep it that way
387 void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
391 flush_tlb_mm(vma->vm_mm);
393 EXPORT_SYMBOL(flush_tlb_range);
395 void tlb_flush(struct mmu_gather *tlb)
397 flush_tlb_mm(tlb->mm);
401 * Below are functions specific to the 64-bit variant of Book3E though that
402 * may change in the future
408 * Handling of virtual linear page tables or indirect TLB entries
409 * flushing when PTE pages are freed
411 void tlb_flush_pgtable(struct mmu_gather *tlb, unsigned long address)
413 int tsize = mmu_psize_defs[mmu_pte_psize].enc;
415 if (book3e_htw_mode != PPC_HTW_NONE) {
416 unsigned long start = address & PMD_MASK;
417 unsigned long end = address + PMD_SIZE;
418 unsigned long size = 1UL << mmu_psize_defs[mmu_pte_psize].shift;
420 /* This isn't the most optimal, ideally we would factor out the
421 * while preempt & CPU mask mucking around, or even the IPI but
424 while (start < end) {
425 __flush_tlb_page(tlb->mm, start, tsize, 1);
429 unsigned long rmask = 0xf000000000000000ul;
430 unsigned long rid = (address & rmask) | 0x1000000000000000ul;
431 unsigned long vpte = address & ~rmask;
433 #ifdef CONFIG_PPC_64K_PAGES
434 vpte = (vpte >> (PAGE_SHIFT - 4)) & ~0xfffful;
436 vpte = (vpte >> (PAGE_SHIFT - 3)) & ~0xffful;
439 __flush_tlb_page(tlb->mm, vpte, tsize, 0);
443 static void setup_page_sizes(void)
445 unsigned int tlb0cfg;
450 #ifdef CONFIG_PPC_FSL_BOOK3E
451 unsigned int mmucfg = mfspr(SPRN_MMUCFG);
452 int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
454 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
455 unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
456 unsigned int min_pg, max_pg;
458 min_pg = (tlb1cfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
459 max_pg = (tlb1cfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
461 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
462 struct mmu_psize_def *def;
465 def = &mmu_psize_defs[psize];
468 if (shift == 0 || shift & 1)
471 /* adjust to be in terms of 4^shift Kb */
472 shift = (shift - 10) >> 1;
474 if ((shift >= min_pg) && (shift <= max_pg))
475 def->flags |= MMU_PAGE_SIZE_DIRECT;
481 if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
484 tlb0cfg = mfspr(SPRN_TLB0CFG);
485 tlb1cfg = mfspr(SPRN_TLB1CFG);
486 tlb1ps = mfspr(SPRN_TLB1PS);
487 eptcfg = mfspr(SPRN_EPTCFG);
489 if ((tlb1cfg & TLBnCFG_IND) && (tlb0cfg & TLBnCFG_PT))
490 book3e_htw_mode = PPC_HTW_E6500;
493 * We expect 4K subpage size and unrestricted indirect size.
494 * The lack of a restriction on indirect size is a Freescale
495 * extension, indicated by PSn = 0 but SPSn != 0.
498 book3e_htw_mode = PPC_HTW_NONE;
500 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
501 struct mmu_psize_def *def = &mmu_psize_defs[psize];
506 if (tlb1ps & (1U << (def->shift - 10))) {
507 def->flags |= MMU_PAGE_SIZE_DIRECT;
509 if (book3e_htw_mode && psize == MMU_PAGE_2M)
510 def->flags |= MMU_PAGE_SIZE_INDIRECT;
518 tlb0cfg = mfspr(SPRN_TLB0CFG);
519 tlb0ps = mfspr(SPRN_TLB0PS);
520 eptcfg = mfspr(SPRN_EPTCFG);
522 /* Look for supported direct sizes */
523 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
524 struct mmu_psize_def *def = &mmu_psize_defs[psize];
526 if (tlb0ps & (1U << (def->shift - 10)))
527 def->flags |= MMU_PAGE_SIZE_DIRECT;
530 /* Indirect page sizes supported ? */
531 if ((tlb0cfg & TLBnCFG_IND) == 0 ||
532 (tlb0cfg & TLBnCFG_PT) == 0)
535 book3e_htw_mode = PPC_HTW_IBM;
537 /* Now, we only deal with one IND page size for each
538 * direct size. Hopefully all implementations today are
539 * unambiguous, but we might want to be careful in the
542 for (i = 0; i < 3; i++) {
543 unsigned int ps, sps;
551 for (psize = 0; psize < MMU_PAGE_COUNT; psize++) {
552 struct mmu_psize_def *def = &mmu_psize_defs[psize];
554 if (ps == (def->shift - 10))
555 def->flags |= MMU_PAGE_SIZE_INDIRECT;
556 if (sps == (def->shift - 10))
562 /* Cleanup array and print summary */
563 pr_info("MMU: Supported page sizes\n");
564 for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
565 struct mmu_psize_def *def = &mmu_psize_defs[psize];
566 const char *__page_type_names[] = {
572 if (def->flags == 0) {
576 pr_info(" %8ld KB as %s\n", 1ul << (def->shift - 10),
577 __page_type_names[def->flags & 0x3]);
581 static void setup_mmu_htw(void)
584 * If we want to use HW tablewalk, enable it by patching the TLB miss
585 * handlers to branch to the one dedicated to it.
588 switch (book3e_htw_mode) {
590 patch_exception(0x1c0, exc_data_tlb_miss_htw_book3e);
591 patch_exception(0x1e0, exc_instruction_tlb_miss_htw_book3e);
593 #ifdef CONFIG_PPC_FSL_BOOK3E
595 extlb_level_exc = EX_TLB_SIZE;
596 patch_exception(0x1c0, exc_data_tlb_miss_e6500_book3e);
597 patch_exception(0x1e0, exc_instruction_tlb_miss_e6500_book3e);
601 pr_info("MMU: Book3E HW tablewalk %s\n",
602 book3e_htw_mode != PPC_HTW_NONE ? "enabled" : "not supported");
606 * Early initialization of the MMU TLB code
608 static void early_init_this_mmu(void)
612 /* Set MAS4 based on page table setting */
614 mas4 = 0x4 << MAS4_WIMGED_SHIFT;
615 switch (book3e_htw_mode) {
618 mas4 |= BOOK3E_PAGESZ_2M << MAS4_TSIZED_SHIFT;
619 mas4 |= MAS4_TLBSELD(1);
620 mmu_pte_psize = MMU_PAGE_2M;
625 #ifdef CONFIG_PPC_64K_PAGES
626 mas4 |= BOOK3E_PAGESZ_256M << MAS4_TSIZED_SHIFT;
627 mmu_pte_psize = MMU_PAGE_256M;
629 mas4 |= BOOK3E_PAGESZ_1M << MAS4_TSIZED_SHIFT;
630 mmu_pte_psize = MMU_PAGE_1M;
635 #ifdef CONFIG_PPC_64K_PAGES
636 mas4 |= BOOK3E_PAGESZ_64K << MAS4_TSIZED_SHIFT;
638 mas4 |= BOOK3E_PAGESZ_4K << MAS4_TSIZED_SHIFT;
640 mmu_pte_psize = mmu_virtual_psize;
643 mtspr(SPRN_MAS4, mas4);
645 #ifdef CONFIG_PPC_FSL_BOOK3E
646 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
647 unsigned int num_cams;
648 int __maybe_unused cpu = smp_processor_id();
651 /* use a quarter of the TLBCAM for bolted linear map */
652 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
655 * Only do the mapping once per core, or else the
656 * transient mapping would cause problems.
659 if (hweight32(get_tensr()) > 1)
664 linear_map_top = map_mem_in_cams(linear_map_top,
669 /* A sync won't hurt us after mucking around with
670 * the MMU configuration
675 static void __init early_init_mmu_global(void)
677 /* XXX This will have to be decided at runtime, but right
678 * now our boot and TLB miss code hard wires it. Ideally
679 * we should find out a suitable page size and patch the
680 * TLB miss code (either that or use the PACA to store
683 mmu_linear_psize = MMU_PAGE_1G;
685 /* XXX This should be decided at runtime based on supported
686 * page sizes in the TLB, but for now let's assume 16M is
687 * always there and a good fit (which it probably is)
689 * Freescale booke only supports 4K pages in TLB0, so use that.
691 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
692 mmu_vmemmap_psize = MMU_PAGE_4K;
694 mmu_vmemmap_psize = MMU_PAGE_16M;
696 /* XXX This code only checks for TLB 0 capabilities and doesn't
697 * check what page size combos are supported by the HW. It
698 * also doesn't handle the case where a separate array holds
699 * the IND entries from the array loaded by the PT.
701 /* Look for supported page sizes */
704 /* Look for HW tablewalk support */
707 #ifdef CONFIG_PPC_FSL_BOOK3E
708 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
709 if (book3e_htw_mode == PPC_HTW_NONE) {
710 extlb_level_exc = EX_TLB_SIZE;
711 patch_exception(0x1c0, exc_data_tlb_miss_bolted_book3e);
712 patch_exception(0x1e0,
713 exc_instruction_tlb_miss_bolted_book3e);
718 /* Set the global containing the top of the linear mapping
719 * for use by the TLB miss code
721 linear_map_top = memblock_end_of_DRAM();
724 static void __init early_mmu_set_memory_limit(void)
726 #ifdef CONFIG_PPC_FSL_BOOK3E
727 if (mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
729 * Limit memory so we dont have linear faults.
730 * Unlike memblock_set_current_limit, which limits
731 * memory available during early boot, this permanently
732 * reduces the memory available to Linux. We need to
733 * do this because highmem is not supported on 64-bit.
735 memblock_enforce_memory_limit(linear_map_top);
739 memblock_set_current_limit(linear_map_top);
743 void __init early_init_mmu(void)
745 early_init_mmu_global();
746 early_init_this_mmu();
747 early_mmu_set_memory_limit();
750 void early_init_mmu_secondary(void)
752 early_init_this_mmu();
755 void setup_initial_memory_limit(phys_addr_t first_memblock_base,
756 phys_addr_t first_memblock_size)
758 /* On non-FSL Embedded 64-bit, we adjust the RMA size to match
759 * the bolted TLB entry. We know for now that only 1G
760 * entries are supported though that may eventually
763 * on FSL Embedded 64-bit, usually all RAM is bolted, but with
764 * unusual memory sizes it's possible for some RAM to not be mapped
765 * (such RAM is not used at all by Linux, since we don't support
766 * highmem on 64-bit). We limit ppc64_rma_size to what would be
767 * mappable if this memblock is the only one. Additional memblocks
768 * can only increase, not decrease, the amount that ends up getting
769 * mapped. We still limit max to 1G even if we'll eventually map
770 * more. This is due to what the early init code is set up to do.
772 * We crop it to the size of the first MEMBLOCK to
773 * avoid going over total available memory just in case...
775 #ifdef CONFIG_PPC_FSL_BOOK3E
776 if (early_mmu_has_feature(MMU_FTR_TYPE_FSL_E)) {
777 unsigned long linear_sz;
778 unsigned int num_cams;
780 /* use a quarter of the TLBCAM for bolted linear map */
781 num_cams = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) / 4;
783 linear_sz = map_mem_in_cams(first_memblock_size, num_cams,
786 ppc64_rma_size = min_t(u64, linear_sz, 0x40000000);
789 ppc64_rma_size = min_t(u64, first_memblock_size, 0x40000000);
791 /* Finally limit subsequent allocations */
792 memblock_set_current_limit(first_memblock_base + ppc64_rma_size);
794 #else /* ! CONFIG_PPC64 */
795 void __init early_init_mmu(void)
797 #ifdef CONFIG_PPC_47x
798 early_init_mmu_47x();
801 #endif /* CONFIG_PPC64 */