2 * Low level TLB miss handlers for Book3E
4 * Copyright (C) 2008-2009
5 * Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <asm/processor.h>
17 #include <asm/ppc_asm.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/cputable.h>
20 #include <asm/pgtable.h>
21 #include <asm/exception-64e.h>
22 #include <asm/ppc-opcode.h>
23 #include <asm/kvm_asm.h>
24 #include <asm/kvm_booke_hv_asm.h>
26 #ifdef CONFIG_PPC_64K_PAGES
27 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1)
29 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE)
31 #define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE)
32 #define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
33 #define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
35 /**********************************************************************
37 * TLB miss handling for Book3E with a bolted linear mapping *
38 * No virtual page table, no nested TLB misses *
40 **********************************************************************/
43 * Note that, unlike non-bolted handlers, TLB_EXFRAME is not
44 * modified by the TLB miss handlers themselves, since the TLB miss
45 * handler code will not itself cause a recursive TLB miss.
47 * TLB_EXFRAME will be modified when crit/mc/debug exceptions are
50 .macro tlb_prolog_bolted intnum addr
51 mtspr SPRN_SPRG_GEN_SCRATCH,r12
52 mfspr r12,SPRN_SPRG_TLB_EXFRAME
53 std r13,EX_TLB_R13(r12)
54 std r10,EX_TLB_R10(r12)
55 mfspr r13,SPRN_SPRG_PACA
58 std r11,EX_TLB_R11(r12)
59 #ifdef CONFIG_KVM_BOOKE_HV
62 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
64 DO_KVM \intnum, SPRN_SRR1
65 std r16,EX_TLB_R16(r12)
66 mfspr r16,\addr /* get faulting address */
67 std r14,EX_TLB_R14(r12)
69 std r15,EX_TLB_R15(r12)
70 std r10,EX_TLB_CR(r12)
71 #ifdef CONFIG_PPC_FSL_BOOK3E
72 START_BTB_FLUSH_SECTION
84 .macro tlb_epilog_bolted
86 #ifdef CONFIG_PPC_FSL_BOOK3E
89 ld r10,EX_TLB_R10(r12)
90 ld r11,EX_TLB_R11(r12)
91 ld r13,EX_TLB_R13(r12)
93 ld r14,EX_TLB_R14(r12)
94 ld r15,EX_TLB_R15(r12)
95 TLB_MISS_RESTORE_STATS
96 ld r16,EX_TLB_R16(r12)
97 mfspr r12,SPRN_SPRG_GEN_SCRATCH
101 START_EXCEPTION(data_tlb_miss_bolted)
102 tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
104 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
106 /* We do the user/kernel test for the PID here along with the RW test
108 /* We pre-test some combination of permissions to avoid double
111 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
112 * ESR_ST is 0x00800000
113 * _PAGE_BAP_SW is 0x00000010
114 * So the shift is >> 19. This tests for supervisor writeability.
115 * If the page happens to be supervisor writeable and not user
116 * writeable, we will take a new fault later, but that should be
117 * a rare enough case.
119 * We also move ESR_ST in _PAGE_DIRTY position
120 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
122 * MAS1 is preset for all we need except for TID that needs to
123 * be cleared for kernel translations
128 srdi r15,r16,60 /* get region */
129 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
130 bne- dtlb_miss_fault_bolted /* Bail if fault addr is invalid */
132 rlwinm r10,r11,32-19,27,27
133 rlwimi r10,r11,32-16,19,19
134 cmpwi r15,0 /* user vs kernel check */
135 ori r10,r10,_PAGE_PRESENT
136 oris r11,r10,_PAGE_ACCESSED@h
138 TLB_MISS_STATS_SAVE_INFO_BOLTED
139 bne tlb_miss_kernel_bolted
141 tlb_miss_common_bolted:
143 * This is the guts of the TLB miss handler for bolted-linear.
144 * We are entered with:
146 * r16 = faulting address
147 * r15 = crap (free to use)
148 * r14 = page table base
150 * r11 = PTE permission mask
151 * r10 = crap (free to use)
153 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
156 beq tlb_miss_fault_bolted /* No PGDIR, bail */
158 BEGIN_MMU_FTR_SECTION
159 /* Set the TLB reservation and search for existing entry. Then load
162 PPC_TLBSRX_DOT(0,R16)
163 ldx r14,r14,r15 /* grab pgd entry */
164 beq tlb_miss_done_bolted /* tlb exists already, bail */
166 ldx r14,r14,r15 /* grab pgd entry */
167 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
169 #ifndef CONFIG_PPC_64K_PAGES
170 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
173 bge tlb_miss_fault_bolted /* Bad pgd entry or hugepage; bail */
174 ldx r14,r14,r15 /* grab pud entry */
175 #endif /* CONFIG_PPC_64K_PAGES */
177 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
180 bge tlb_miss_fault_bolted
181 ldx r14,r14,r15 /* Grab pmd entry */
183 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
186 bge tlb_miss_fault_bolted
187 ldx r14,r14,r15 /* Grab PTE, normal (!huge) page */
189 /* Check if required permissions are met */
191 rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
192 bne- tlb_miss_fault_bolted
194 /* Now we build the MAS:
196 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
197 * MAS 1 : Almost fully setup
198 * - PID already updated by caller if necessary
199 * - TSIZE need change if !base page size, not
200 * yet implemented for now
201 * MAS 2 : Defaults not useful, need to be redone
202 * MAS 3+7 : Needs to be done
204 clrrdi r11,r16,12 /* Clear low crap in EA */
205 clrldi r15,r15,12 /* Clear crap at the top */
206 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
207 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
209 andi. r11,r14,_PAGE_DIRTY
210 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
212 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
214 li r11,MAS3_SW|MAS3_UW
217 mtspr SPRN_MAS7_MAS3,r15
220 tlb_miss_done_bolted:
221 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
225 itlb_miss_kernel_bolted:
226 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
227 oris r11,r11,_PAGE_ACCESSED@h
228 tlb_miss_kernel_bolted:
230 ld r14,PACA_KERNELPGD(r13)
231 cmpldi cr0,r15,8 /* Check for vmalloc region */
232 rlwinm r10,r10,0,16,1 /* Clear TID */
234 beq+ tlb_miss_common_bolted
236 tlb_miss_fault_bolted:
237 /* We need to check if it was an instruction miss */
238 andi. r10,r11,_PAGE_EXEC|_PAGE_BAP_SX
239 bne itlb_miss_fault_bolted
240 dtlb_miss_fault_bolted:
241 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
243 b exc_data_storage_book3e
244 itlb_miss_fault_bolted:
245 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
247 b exc_instruction_storage_book3e
249 /* Instruction TLB miss */
250 START_EXCEPTION(instruction_tlb_miss_bolted)
251 tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
253 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
254 srdi r15,r16,60 /* get region */
255 TLB_MISS_STATS_SAVE_INFO_BOLTED
256 bne- itlb_miss_fault_bolted
258 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
260 /* We do the user/kernel test for the PID here along with the RW test
263 cmpldi cr0,r15,0 /* Check for user region */
264 oris r11,r11,_PAGE_ACCESSED@h
265 beq tlb_miss_common_bolted
266 b itlb_miss_kernel_bolted
268 #ifdef CONFIG_PPC_FSL_BOOK3E
270 * TLB miss handling for e6500 and derivatives, using hardware tablewalk.
272 * Linear mapping is bolted: no virtual page table or nested TLB misses
273 * Indirect entries in TLB1, hardware loads resulting direct entries
275 * No HES or NV hint on TLB1, so we need to do software round-robin
276 * No tlbsrx. so we need a spinlock, and we have to deal
277 * with MAS-damage caused by tlbsx
281 START_EXCEPTION(instruction_tlb_miss_e6500)
282 tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
284 ld r11,PACA_TCD_PTR(r13)
285 srdi. r15,r16,60 /* get region */
288 TLB_MISS_STATS_SAVE_INFO_BOLTED
289 bne tlb_miss_kernel_e6500 /* user/kernel test */
291 b tlb_miss_common_e6500
293 START_EXCEPTION(data_tlb_miss_e6500)
294 tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
296 ld r11,PACA_TCD_PTR(r13)
297 srdi. r15,r16,60 /* get region */
300 TLB_MISS_STATS_SAVE_INFO_BOLTED
301 bne tlb_miss_kernel_e6500 /* user vs kernel check */
304 * This is the guts of the TLB miss handler for e6500 and derivatives.
305 * We are entered with:
307 * r16 = page of faulting address (low bit 0 if data, 1 if instruction)
308 * r15 = crap (free to use)
309 * r14 = page table base
311 * r11 = tlb_per_core ptr
312 * r10 = crap (free to use)
315 tlb_miss_common_e6500:
316 crmove cr2*4+2,cr0*4+2 /* cr2.eq != 0 if kernel address */
318 BEGIN_FTR_SECTION /* CPU_FTR_SMT */
320 * Search if we already have an indirect entry for that virtual
321 * address, and if we do, bail out.
323 * MAS6:IND should be already set based on MAS4
325 lhz r10,PACAPACAINDEX(r13)
327 crclr cr1*4+eq /* set cr1.eq = 0 for non-recursive */
335 2: cmpd cr1,r15,r10 /* recursive lock due to mcheck/crit/etc? */
336 beq cr1,3b /* unlock will happen if cr1.eq = 0 */
342 END_FTR_SECTION_IFSET(CPU_FTR_SMT)
344 lbz r7,TCD_ESEL_NEXT(r11)
346 BEGIN_FTR_SECTION /* CPU_FTR_SMT */
348 * Erratum A-008139 says that we can't use tlbwe to change
349 * an indirect entry in any way (including replacing or
350 * invalidating) if the other thread could be in the process
351 * of a lookup. The workaround is to invalidate the entry
352 * with tlbilx before overwriting.
355 rlwinm r10,r7,16,0xff0000
356 oris r10,r10,MAS0_TLBSEL(1)@h
361 andis. r15,r15,MAS1_VALID@h
364 BEGIN_FTR_SECTION_NESTED(532)
366 rlwinm r10,r10,0,0x80000fff /* tgs,tlpid -> sgs,slpid */
368 END_FTR_SECTION_NESTED(CPU_FTR_EMB_HV,CPU_FTR_EMB_HV,532)
371 rlwinm r15,r10,0,0x3fff0000 /* tid -> spid */
372 rlwimi r15,r10,20,0x00000003 /* ind,ts -> sind,sas */
384 BEGIN_FTR_SECTION_NESTED(532)
388 END_FTR_SECTION_NESTED(CPU_FTR_EMB_HV,CPU_FTR_EMB_HV,532)
392 andis. r15,r10,MAS1_VALID@h
393 bne tlb_miss_done_e6500
396 ALT_FTR_SECTION_END_IFSET(CPU_FTR_SMT)
398 oris r10,r10,MAS1_VALID@h
400 rlwinm r10,r10,0,16,1 /* Clear TID */
401 4: mtspr SPRN_MAS1,r10
403 /* Now, we need to walk the page tables. First check if we are in
406 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
407 bne- tlb_miss_fault_e6500
409 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
412 beq- tlb_miss_fault_e6500 /* No PGDIR, bail */
413 ldx r14,r14,r15 /* grab pgd entry */
415 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
418 bge tlb_miss_huge_e6500 /* Bad pgd entry or hugepage; bail */
419 ldx r14,r14,r15 /* grab pud entry */
421 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
424 bge tlb_miss_huge_e6500
425 ldx r14,r14,r15 /* Grab pmd entry */
429 bge tlb_miss_huge_e6500
431 /* Now we build the MAS for a 2M indirect page:
433 * MAS 0 : ESEL needs to be filled by software round-robin
434 * MAS 1 : Fully set up
435 * - PID already updated by caller if necessary
436 * - TSIZE for now is base ind page size always
437 * - TID already cleared if necessary
438 * MAS 2 : Default not 2M-aligned, need to be redone
439 * MAS 3+7 : Needs to be done
442 ori r14,r14,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
443 mtspr SPRN_MAS7_MAS3,r14
445 clrrdi r15,r16,21 /* make EA 2M-aligned */
448 tlb_miss_huge_done_e6500:
449 lbz r16,TCD_ESEL_MAX(r11)
450 lbz r14,TCD_ESEL_FIRST(r11)
451 rlwimi r10,r7,16,0x00ff0000 /* insert esel_next into MAS0 */
452 addi r7,r7,1 /* increment esel_next */
455 iseleq r7,r14,r7 /* if next == last use first */
456 stb r7,TCD_ESEL_NEXT(r11)
461 .macro tlb_unlock_e6500
463 beq cr1,1f /* no unlock if lock was recursively grabbed */
468 END_FTR_SECTION_IFSET(CPU_FTR_SMT)
472 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
477 beq tlb_miss_fault_e6500
479 andi. r15,r14,HUGEPD_SHIFT_MASK@l /* r15 = psize */
480 rldimi r14,r10,63,0 /* Set PD_HUGE */
481 xor r14,r14,r15 /* Clear size bits */
485 * Now we build the MAS for a huge page.
487 * MAS 0 : ESEL needs to be filled by software round-robin
488 * - can be handled by indirect code
489 * MAS 1 : Need to clear IND and set TSIZE
490 * MAS 2,3+7: Needs to be redone similar to non-tablewalk handler
493 subi r15,r15,10 /* Convert psize to tsize */
495 rlwinm r10,r10,0,~MAS1_IND
496 rlwimi r10,r15,MAS1_TSIZE_SHIFT,MAS1_TSIZE_MASK
500 sld r15,r10,r15 /* Generate mask based on size */
502 rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
503 rlwimi r10,r14,32-19,27,31 /* Insert WIMGE */
504 clrldi r15,r15,PAGE_SHIFT /* Clear crap at the top */
505 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
507 andi. r10,r14,_PAGE_DIRTY
508 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
510 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
512 li r10,MAS3_SW|MAS3_UW
515 mtspr SPRN_MAS7_MAS3,r15
518 b tlb_miss_huge_done_e6500
520 tlb_miss_kernel_e6500:
521 ld r14,PACA_KERNELPGD(r13)
522 cmpldi cr1,r15,8 /* Check for vmalloc region */
523 beq+ cr1,tlb_miss_common_e6500
525 tlb_miss_fault_e6500:
527 /* We need to check if it was an instruction miss */
529 bne itlb_miss_fault_e6500
530 dtlb_miss_fault_e6500:
531 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
533 b exc_data_storage_book3e
534 itlb_miss_fault_e6500:
535 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
537 b exc_instruction_storage_book3e
538 #endif /* CONFIG_PPC_FSL_BOOK3E */
540 /**********************************************************************
542 * TLB miss handling for Book3E with TLB reservation and HES support *
544 **********************************************************************/
548 START_EXCEPTION(data_tlb_miss)
551 /* Now we handle the fault proper. We only save DEAR in normal
552 * fault case since that's the only interesting values here.
553 * We could probably also optimize by not saving SRR0/1 in the
554 * linear mapping case but I'll leave that for later
557 mfspr r16,SPRN_DEAR /* get faulting address */
558 srdi r15,r16,60 /* get region */
559 cmpldi cr0,r15,0xc /* linear mapping ? */
560 TLB_MISS_STATS_SAVE_INFO
561 beq tlb_load_linear /* yes -> go to linear map load */
563 /* The page tables are mapped virtually linear. At this point, though,
564 * we don't know whether we are trying to fault in a first level
565 * virtual address or a virtual page table address. We can get that
566 * from bit 0x1 of the region ID which we have set for a page table
569 bne- virt_page_table_tlb_miss
571 std r14,EX_TLB_ESR(r12); /* save ESR */
572 std r16,EX_TLB_DEAR(r12); /* save DEAR */
574 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
576 oris r11,r11,_PAGE_ACCESSED@h
578 /* We do the user/kernel test for the PID here along with the RW test
580 cmpldi cr0,r15,0 /* Check for user region */
582 /* We pre-test some combination of permissions to avoid double
585 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
586 * ESR_ST is 0x00800000
587 * _PAGE_BAP_SW is 0x00000010
588 * So the shift is >> 19. This tests for supervisor writeability.
589 * If the page happens to be supervisor writeable and not user
590 * writeable, we will take a new fault later, but that should be
591 * a rare enough case.
593 * We also move ESR_ST in _PAGE_DIRTY position
594 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
596 * MAS1 is preset for all we need except for TID that needs to
597 * be cleared for kernel translations
599 rlwimi r11,r14,32-19,27,27
600 rlwimi r11,r14,32-16,19,19
602 /* XXX replace the RMW cycles with immediate loads + writes */
603 1: mfspr r10,SPRN_MAS1
604 cmpldi cr0,r15,8 /* Check for vmalloc region */
605 rlwinm r10,r10,0,16,1 /* Clear TID */
609 /* We got a crappy address, just fault with whatever DEAR and ESR
612 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
613 TLB_MISS_EPILOG_ERROR
614 b exc_data_storage_book3e
616 /* Instruction TLB miss */
617 START_EXCEPTION(instruction_tlb_miss)
620 /* If we take a recursive fault, the second level handler may need
621 * to know whether we are handling a data or instruction fault in
622 * order to get to the right store fault handler. We provide that
623 * info by writing a crazy value in ESR in our exception frame
625 li r14,-1 /* store to exception frame is done later */
627 /* Now we handle the fault proper. We only save DEAR in the non
628 * linear mapping case since we know the linear mapping case will
629 * not re-enter. We could indeed optimize and also not save SRR0/1
630 * in the linear mapping case but I'll leave that for later
632 * Faulting address is SRR0 which is already in r16
634 srdi r15,r16,60 /* get region */
635 cmpldi cr0,r15,0xc /* linear mapping ? */
636 TLB_MISS_STATS_SAVE_INFO
637 beq tlb_load_linear /* yes -> go to linear map load */
639 /* We do the user/kernel test for the PID here along with the RW test
641 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
642 oris r11,r11,_PAGE_ACCESSED@h
644 cmpldi cr0,r15,0 /* Check for user region */
645 std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */
648 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
649 oris r11,r11,_PAGE_ACCESSED@h
650 /* XXX replace the RMW cycles with immediate loads + writes */
652 cmpldi cr0,r15,8 /* Check for vmalloc region */
653 rlwinm r10,r10,0,16,1 /* Clear TID */
657 /* We got a crappy address, just fault */
658 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
659 TLB_MISS_EPILOG_ERROR
660 b exc_instruction_storage_book3e
663 * This is the guts of the first-level TLB miss handler for direct
664 * misses. We are entered with:
666 * r16 = faulting address
668 * r14 = crap (free to use)
670 * r12 = TLB exception frame in PACA
671 * r11 = PTE permission mask
672 * r10 = crap (free to use)
675 /* So we first construct the page table address. We do that by
676 * shifting the bottom of the address (not the region ID) by
677 * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and
678 * or'ing the fourth high bit.
680 * NOTE: For 64K pages, we do things slightly differently in
681 * order to handle the weird page table format used by linux
684 #ifdef CONFIG_PPC_64K_PAGES
685 /* For the top bits, 16 bytes per PTE */
686 rldicl r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4
687 /* Now create the bottom bits as 0 in position 0x8000 and
688 * the rest calculated for 8 bytes per PTE
690 rldicl r15,r16,64-(PAGE_SHIFT-3),64-15
691 /* Insert the bottom bits in */
692 rlwimi r14,r15,0,16,31
694 rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
700 BEGIN_MMU_FTR_SECTION
701 /* Set the TLB reservation and search for existing entry. Then load
704 PPC_TLBSRX_DOT(0,R16)
706 beq normal_tlb_miss_done
709 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
711 finish_normal_tlb_miss:
712 /* Check if required permissions are met */
714 bne- normal_tlb_miss_access_fault
716 /* Now we build the MAS:
718 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
719 * MAS 1 : Almost fully setup
720 * - PID already updated by caller if necessary
721 * - TSIZE need change if !base page size, not
722 * yet implemented for now
723 * MAS 2 : Defaults not useful, need to be redone
724 * MAS 3+7 : Needs to be done
726 * TODO: mix up code below for better scheduling
728 clrrdi r11,r16,12 /* Clear low crap in EA */
729 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
732 /* Check page size, if not standard, update MAS1 */
733 rldicl r11,r14,64-8,64-8
734 #ifdef CONFIG_PPC_64K_PAGES
735 cmpldi cr0,r11,BOOK3E_PAGESZ_64K
737 cmpldi cr0,r11,BOOK3E_PAGESZ_4K
741 rlwimi r11,r14,31,21,24
742 rlwinm r11,r11,0,21,19
745 /* Move RPN in position */
746 rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
747 clrldi r15,r11,12 /* Clear crap at the top */
748 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
749 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
751 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
752 andi. r11,r14,_PAGE_DIRTY
754 li r11,MAS3_SW|MAS3_UW
757 BEGIN_MMU_FTR_SECTION
762 mtspr SPRN_MAS7_MAS3,r15
763 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
767 normal_tlb_miss_done:
768 /* We don't bother with restoring DEAR or ESR since we know we are
769 * level 0 and just going back to userland. They are only needed
770 * if you are going to take an access fault
772 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
773 TLB_MISS_EPILOG_SUCCESS
776 normal_tlb_miss_access_fault:
777 /* We need to check if it was an instruction miss */
778 andi. r10,r11,_PAGE_EXEC
780 ld r14,EX_TLB_DEAR(r12)
781 ld r15,EX_TLB_ESR(r12)
784 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
785 TLB_MISS_EPILOG_ERROR
786 b exc_data_storage_book3e
787 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
788 TLB_MISS_EPILOG_ERROR
789 b exc_instruction_storage_book3e
793 * This is the guts of the second-level TLB miss handler for direct
794 * misses. We are entered with:
796 * r16 = virtual page table faulting address
797 * r15 = region (top 4 bits of address)
798 * r14 = crap (free to use)
800 * r12 = TLB exception frame in PACA
801 * r11 = crap (free to use)
802 * r10 = crap (free to use)
804 * Note that this should only ever be called as a second level handler
805 * with the current scheme when using SW load.
806 * That means we can always get the original fault DEAR at
807 * EX_TLB_DEAR-EX_TLB_SIZE(r12)
809 * It can be re-entered by the linear mapping miss handler. However, to
810 * avoid too much complication, it will restart the whole fault at level
811 * 0 so we don't care too much about clobbers
813 * XXX That code was written back when we couldn't clobber r14. We can now,
814 * so we could probably optimize things a bit
816 virt_page_table_tlb_miss:
817 /* Are we hitting a kernel page table ? */
820 /* The cool thing now is that r10 contains 0 for user and 8 for kernel,
821 * and we happen to have the swapper_pg_dir at offset 8 from the user
822 * pgdir in the PACA :-).
826 /* If kernel, we need to clear MAS1 TID */
828 /* XXX replace the RMW cycles with immediate loads + writes */
830 rlwinm r10,r10,0,16,1 /* Clear TID */
833 BEGIN_MMU_FTR_SECTION
834 /* Search if we already have a TLB entry for that virtual address, and
835 * if we do, bail out.
837 PPC_TLBSRX_DOT(0,R16)
838 beq virt_page_table_tlb_miss_done
839 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
841 /* Now, we need to walk the page tables. First check if we are in
844 rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4
845 bne- virt_page_table_tlb_miss_fault
847 /* Get the PGD pointer */
850 beq- virt_page_table_tlb_miss_fault
852 /* Get to PGD entry */
853 rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3
857 bge virt_page_table_tlb_miss_fault
859 #ifndef CONFIG_PPC_64K_PAGES
860 /* Get to PUD entry */
861 rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
865 bge virt_page_table_tlb_miss_fault
866 #endif /* CONFIG_PPC_64K_PAGES */
868 /* Get to PMD entry */
869 rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
873 bge virt_page_table_tlb_miss_fault
875 /* Ok, we're all right, we can now create a kernel translation for
876 * a 4K or 64K page from r16 -> r15.
878 /* Now we build the MAS:
880 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
881 * MAS 1 : Almost fully setup
882 * - PID already updated by caller if necessary
883 * - TSIZE for now is base page size always
884 * MAS 2 : Use defaults
885 * MAS 3+7 : Needs to be done
887 * So we only do MAS 2 and 3 for now...
889 clrldi r11,r15,4 /* remove region ID from RPN */
890 ori r10,r11,1 /* Or-in SR */
892 BEGIN_MMU_FTR_SECTION
897 mtspr SPRN_MAS7_MAS3,r10
898 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
902 BEGIN_MMU_FTR_SECTION
903 virt_page_table_tlb_miss_done:
905 /* We have overridden MAS2:EPN but currently our primary TLB miss
906 * handler will always restore it so that should not be an issue,
907 * if we ever optimize the primary handler to not write MAS2 on
908 * some cases, we'll have to restore MAS2:EPN here based on the
909 * original fault's DEAR. If we do that we have to modify the
910 * ITLB miss handler to also store SRR0 in the exception frame
913 * However, one nasty thing we did is we cleared the reservation
914 * (well, potentially we did). We do a trick here thus if we
915 * are not a level 0 exception (we interrupted the TLB miss) we
916 * offset the return address by -4 in order to replay the tlbsrx
920 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
922 ld r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
924 std r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
926 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
927 /* Return to caller, normal case */
928 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK);
929 TLB_MISS_EPILOG_SUCCESS
932 virt_page_table_tlb_miss_fault:
933 /* If we fault here, things are a little bit tricky. We need to call
934 * either data or instruction store fault, and we need to retrieve
935 * the original fault address and ESR (for data).
937 * The thing is, we know that in normal circumstances, this is
938 * always called as a second level tlb miss for SW load or as a first
939 * level TLB miss for HW load, so we should be able to peek at the
940 * relevant information in the first exception frame in the PACA.
942 * However, we do need to double check that, because we may just hit
943 * a stray kernel pointer or a userland attack trying to hit those
944 * areas. If that is the case, we do a data fault. (We can't get here
945 * from an instruction tlb miss anyway).
947 * Note also that when going to a fault, we must unwind the previous
948 * level as well. Since we are doing that, we don't need to clear or
949 * restore the TLB reservation neither.
952 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
953 bne- virt_page_table_tlb_miss_whacko_fault
955 /* We dig the original DEAR and ESR from slot 0 */
956 ld r15,EX_TLB_DEAR+PACA_EXTLB(r13)
957 ld r16,EX_TLB_ESR+PACA_EXTLB(r13)
959 /* We check for the "special" ESR value for instruction faults */
964 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT);
965 TLB_MISS_EPILOG_ERROR
966 b exc_data_storage_book3e
967 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT);
968 TLB_MISS_EPILOG_ERROR
969 b exc_instruction_storage_book3e
971 virt_page_table_tlb_miss_whacko_fault:
972 /* The linear fault will restart everything so ESR and DEAR will
973 * not have been clobbered, let's just fault with what we have
975 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT);
976 TLB_MISS_EPILOG_ERROR
977 b exc_data_storage_book3e
980 /**************************************************************
982 * TLB miss handling for Book3E with hw page table support *
984 **************************************************************/
988 START_EXCEPTION(data_tlb_miss_htw)
991 /* Now we handle the fault proper. We only save DEAR in normal
992 * fault case since that's the only interesting values here.
993 * We could probably also optimize by not saving SRR0/1 in the
994 * linear mapping case but I'll leave that for later
997 mfspr r16,SPRN_DEAR /* get faulting address */
998 srdi r11,r16,60 /* get region */
999 cmpldi cr0,r11,0xc /* linear mapping ? */
1000 TLB_MISS_STATS_SAVE_INFO
1001 beq tlb_load_linear /* yes -> go to linear map load */
1003 /* We do the user/kernel test for the PID here along with the RW test
1005 cmpldi cr0,r11,0 /* Check for user region */
1006 ld r15,PACAPGD(r13) /* Load user pgdir */
1009 /* XXX replace the RMW cycles with immediate loads + writes */
1010 1: mfspr r10,SPRN_MAS1
1011 cmpldi cr0,r11,8 /* Check for vmalloc region */
1012 rlwinm r10,r10,0,16,1 /* Clear TID */
1014 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
1017 /* We got a crappy address, just fault with whatever DEAR and ESR
1020 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
1021 TLB_MISS_EPILOG_ERROR
1022 b exc_data_storage_book3e
1024 /* Instruction TLB miss */
1025 START_EXCEPTION(instruction_tlb_miss_htw)
1028 /* If we take a recursive fault, the second level handler may need
1029 * to know whether we are handling a data or instruction fault in
1030 * order to get to the right store fault handler. We provide that
1031 * info by keeping a crazy value for ESR in r14
1033 li r14,-1 /* store to exception frame is done later */
1035 /* Now we handle the fault proper. We only save DEAR in the non
1036 * linear mapping case since we know the linear mapping case will
1037 * not re-enter. We could indeed optimize and also not save SRR0/1
1038 * in the linear mapping case but I'll leave that for later
1040 * Faulting address is SRR0 which is already in r16
1042 srdi r11,r16,60 /* get region */
1043 cmpldi cr0,r11,0xc /* linear mapping ? */
1044 TLB_MISS_STATS_SAVE_INFO
1045 beq tlb_load_linear /* yes -> go to linear map load */
1047 /* We do the user/kernel test for the PID here along with the RW test
1049 cmpldi cr0,r11,0 /* Check for user region */
1050 ld r15,PACAPGD(r13) /* Load user pgdir */
1053 /* XXX replace the RMW cycles with immediate loads + writes */
1054 1: mfspr r10,SPRN_MAS1
1055 cmpldi cr0,r11,8 /* Check for vmalloc region */
1056 rlwinm r10,r10,0,16,1 /* Clear TID */
1058 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
1061 /* We got a crappy address, just fault */
1062 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
1063 TLB_MISS_EPILOG_ERROR
1064 b exc_instruction_storage_book3e
1068 * This is the guts of the second-level TLB miss handler for direct
1069 * misses. We are entered with:
1071 * r16 = virtual page table faulting address
1075 * r12 = TLB exception frame in PACA
1076 * r11 = crap (free to use)
1077 * r10 = crap (free to use)
1079 * It can be re-entered by the linear mapping miss handler. However, to
1080 * avoid too much complication, it will save/restore things for us
1083 /* Search if we already have a TLB entry for that virtual address, and
1084 * if we do, bail out.
1086 * MAS1:IND should be already set based on MAS4
1088 PPC_TLBSRX_DOT(0,R16)
1089 beq htw_tlb_miss_done
1091 /* Now, we need to walk the page tables. First check if we are in
1094 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
1095 bne- htw_tlb_miss_fault
1097 /* Get the PGD pointer */
1099 beq- htw_tlb_miss_fault
1101 /* Get to PGD entry */
1102 rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3
1106 bge htw_tlb_miss_fault
1108 #ifndef CONFIG_PPC_64K_PAGES
1109 /* Get to PUD entry */
1110 rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
1114 bge htw_tlb_miss_fault
1115 #endif /* CONFIG_PPC_64K_PAGES */
1117 /* Get to PMD entry */
1118 rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
1122 bge htw_tlb_miss_fault
1124 /* Ok, we're all right, we can now create an indirect entry for
1125 * a 1M or 256M page.
1127 * The last trick is now that because we use "half" pages for
1128 * the HTW (1M IND is 2K and 256M IND is 32K) we need to account
1129 * for an added LSB bit to the RPN. For 64K pages, there is no
1130 * problem as we already use 32K arrays (half PTE pages), but for
1131 * 4K page we need to extract a bit from the virtual address and
1132 * insert it into the "PA52" bit of the RPN.
1134 #ifndef CONFIG_PPC_64K_PAGES
1135 rlwimi r15,r16,32-9,20,20
1137 /* Now we build the MAS:
1139 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
1140 * MAS 1 : Almost fully setup
1141 * - PID already updated by caller if necessary
1142 * - TSIZE for now is base ind page size always
1143 * MAS 2 : Use defaults
1144 * MAS 3+7 : Needs to be done
1146 #ifdef CONFIG_PPC_64K_PAGES
1147 ori r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT)
1149 ori r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
1152 BEGIN_MMU_FTR_SECTION
1156 MMU_FTR_SECTION_ELSE
1157 mtspr SPRN_MAS7_MAS3,r10
1158 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
1163 /* We don't bother with restoring DEAR or ESR since we know we are
1164 * level 0 and just going back to userland. They are only needed
1165 * if you are going to take an access fault
1167 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK)
1168 TLB_MISS_EPILOG_SUCCESS
1172 /* We need to check if it was an instruction miss. We know this
1173 * though because r14 would contain -1
1179 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT)
1180 TLB_MISS_EPILOG_ERROR
1181 b exc_data_storage_book3e
1182 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT)
1183 TLB_MISS_EPILOG_ERROR
1184 b exc_instruction_storage_book3e
1187 * This is the guts of "any" level TLB miss handler for kernel linear
1188 * mapping misses. We are entered with:
1191 * r16 = faulting address
1192 * r15 = crap (free to use)
1193 * r14 = ESR (data) or -1 (instruction)
1195 * r12 = TLB exception frame in PACA
1196 * r11 = crap (free to use)
1197 * r10 = crap (free to use)
1199 * In addition we know that we will not re-enter, so in theory, we could
1200 * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later.
1202 * We also need to be careful about MAS registers here & TLB reservation,
1203 * as we know we'll have clobbered them if we interrupt the main TLB miss
1204 * handlers in which case we probably want to do a full restart at level
1205 * 0 rather than saving / restoring the MAS.
1207 * Note: If we care about performance of that core, we can easily shuffle
1208 * a few things around
1211 /* For now, we assume the linear mapping is contiguous and stops at
1212 * linear_map_top. We also assume the size is a multiple of 1G, thus
1213 * we only use 1G pages for now. That might have to be changed in a
1214 * final implementation, especially when dealing with hypervisors
1217 ld r11,linear_map_top@got(r11)
1221 bge tlb_load_linear_fault
1223 /* MAS1 need whole new setup. */
1224 li r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT)
1225 oris r15,r15,MAS1_VALID@h /* MAS1 needs V and TSIZE */
1228 /* Already somebody there ? */
1229 PPC_TLBSRX_DOT(0,R16)
1230 beq tlb_load_linear_done
1232 /* Now we build the remaining MAS. MAS0 and 2 should be fine
1233 * with their defaults, which leaves us with MAS 3 and 7. The
1234 * mapping is linear, so we just take the address, clear the
1235 * region bits, and or in the permission bits which are currently
1238 clrrdi r10,r16,30 /* 1G page index */
1239 clrldi r10,r10,4 /* clear region bits */
1240 ori r10,r10,MAS3_SR|MAS3_SW|MAS3_SX
1242 BEGIN_MMU_FTR_SECTION
1246 MMU_FTR_SECTION_ELSE
1247 mtspr SPRN_MAS7_MAS3,r10
1248 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
1252 tlb_load_linear_done:
1253 /* We use the "error" epilog for success as we do want to
1254 * restore to the initial faulting context, whatever it was.
1255 * We do that because we can't resume a fault within a TLB
1256 * miss handler, due to MAS and TLB reservation being clobbered.
1258 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR)
1259 TLB_MISS_EPILOG_ERROR
1262 tlb_load_linear_fault:
1263 /* We keep the DEAR and ESR around, this shouldn't have happened */
1266 TLB_MISS_EPILOG_ERROR_SPECIAL
1267 b exc_data_storage_book3e
1268 1: TLB_MISS_EPILOG_ERROR_SPECIAL
1269 b exc_instruction_storage_book3e
1272 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS