2 * Low level TLB miss handlers for Book3E
4 * Copyright (C) 2008-2009
5 * Ben. Herrenschmidt (benh@kernel.crashing.org), IBM Corp.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version
10 * 2 of the License, or (at your option) any later version.
13 #include <asm/processor.h>
17 #include <asm/ppc_asm.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/cputable.h>
20 #include <asm/pgtable.h>
21 #include <asm/exception-64e.h>
22 #include <asm/ppc-opcode.h>
23 #include <asm/kvm_asm.h>
24 #include <asm/kvm_booke_hv_asm.h>
25 #include <asm/feature-fixups.h>
27 #ifdef CONFIG_PPC_64K_PAGES
28 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE+1)
30 #define VPTE_PMD_SHIFT (PTE_INDEX_SIZE)
32 #define VPTE_PUD_SHIFT (VPTE_PMD_SHIFT + PMD_INDEX_SIZE)
33 #define VPTE_PGD_SHIFT (VPTE_PUD_SHIFT + PUD_INDEX_SIZE)
34 #define VPTE_INDEX_SIZE (VPTE_PGD_SHIFT + PGD_INDEX_SIZE)
36 /**********************************************************************
38 * TLB miss handling for Book3E with a bolted linear mapping *
39 * No virtual page table, no nested TLB misses *
41 **********************************************************************/
44 * Note that, unlike non-bolted handlers, TLB_EXFRAME is not
45 * modified by the TLB miss handlers themselves, since the TLB miss
46 * handler code will not itself cause a recursive TLB miss.
48 * TLB_EXFRAME will be modified when crit/mc/debug exceptions are
51 .macro tlb_prolog_bolted intnum addr
52 mtspr SPRN_SPRG_GEN_SCRATCH,r12
53 mfspr r12,SPRN_SPRG_TLB_EXFRAME
54 std r13,EX_TLB_R13(r12)
55 std r10,EX_TLB_R10(r12)
56 mfspr r13,SPRN_SPRG_PACA
59 std r11,EX_TLB_R11(r12)
60 #ifdef CONFIG_KVM_BOOKE_HV
63 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
65 DO_KVM \intnum, SPRN_SRR1
66 std r16,EX_TLB_R16(r12)
67 mfspr r16,\addr /* get faulting address */
68 std r14,EX_TLB_R14(r12)
70 std r15,EX_TLB_R15(r12)
71 std r10,EX_TLB_CR(r12)
72 #ifdef CONFIG_PPC_FSL_BOOK3E
73 START_BTB_FLUSH_SECTION
85 .macro tlb_epilog_bolted
87 #ifdef CONFIG_PPC_FSL_BOOK3E
90 ld r10,EX_TLB_R10(r12)
91 ld r11,EX_TLB_R11(r12)
92 ld r13,EX_TLB_R13(r12)
94 ld r14,EX_TLB_R14(r12)
95 ld r15,EX_TLB_R15(r12)
96 TLB_MISS_RESTORE_STATS
97 ld r16,EX_TLB_R16(r12)
98 mfspr r12,SPRN_SPRG_GEN_SCRATCH
102 START_EXCEPTION(data_tlb_miss_bolted)
103 tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
105 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
107 /* We do the user/kernel test for the PID here along with the RW test
109 /* We pre-test some combination of permissions to avoid double
112 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
113 * ESR_ST is 0x00800000
114 * _PAGE_BAP_SW is 0x00000010
115 * So the shift is >> 19. This tests for supervisor writeability.
116 * If the page happens to be supervisor writeable and not user
117 * writeable, we will take a new fault later, but that should be
118 * a rare enough case.
120 * We also move ESR_ST in _PAGE_DIRTY position
121 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
123 * MAS1 is preset for all we need except for TID that needs to
124 * be cleared for kernel translations
129 srdi r15,r16,60 /* get region */
130 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
131 bne- dtlb_miss_fault_bolted /* Bail if fault addr is invalid */
133 rlwinm r10,r11,32-19,27,27
134 rlwimi r10,r11,32-16,19,19
135 cmpwi r15,0 /* user vs kernel check */
136 ori r10,r10,_PAGE_PRESENT
137 oris r11,r10,_PAGE_ACCESSED@h
139 TLB_MISS_STATS_SAVE_INFO_BOLTED
140 bne tlb_miss_kernel_bolted
142 tlb_miss_common_bolted:
144 * This is the guts of the TLB miss handler for bolted-linear.
145 * We are entered with:
147 * r16 = faulting address
148 * r15 = crap (free to use)
149 * r14 = page table base
151 * r11 = PTE permission mask
152 * r10 = crap (free to use)
154 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
157 beq tlb_miss_fault_bolted /* No PGDIR, bail */
159 BEGIN_MMU_FTR_SECTION
160 /* Set the TLB reservation and search for existing entry. Then load
163 PPC_TLBSRX_DOT(0,R16)
164 ldx r14,r14,r15 /* grab pgd entry */
165 beq tlb_miss_done_bolted /* tlb exists already, bail */
167 ldx r14,r14,r15 /* grab pgd entry */
168 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
170 #ifndef CONFIG_PPC_64K_PAGES
171 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
174 bge tlb_miss_fault_bolted /* Bad pgd entry or hugepage; bail */
175 ldx r14,r14,r15 /* grab pud entry */
176 #endif /* CONFIG_PPC_64K_PAGES */
178 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
181 bge tlb_miss_fault_bolted
182 ldx r14,r14,r15 /* Grab pmd entry */
184 rldicl r15,r16,64-PAGE_SHIFT+3,64-PTE_INDEX_SIZE-3
187 bge tlb_miss_fault_bolted
188 ldx r14,r14,r15 /* Grab PTE, normal (!huge) page */
190 /* Check if required permissions are met */
192 rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
193 bne- tlb_miss_fault_bolted
195 /* Now we build the MAS:
197 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
198 * MAS 1 : Almost fully setup
199 * - PID already updated by caller if necessary
200 * - TSIZE need change if !base page size, not
201 * yet implemented for now
202 * MAS 2 : Defaults not useful, need to be redone
203 * MAS 3+7 : Needs to be done
205 clrrdi r11,r16,12 /* Clear low crap in EA */
206 clrldi r15,r15,12 /* Clear crap at the top */
207 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
208 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
210 andi. r11,r14,_PAGE_DIRTY
211 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
213 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
215 li r11,MAS3_SW|MAS3_UW
218 mtspr SPRN_MAS7_MAS3,r15
221 tlb_miss_done_bolted:
222 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
226 itlb_miss_kernel_bolted:
227 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
228 oris r11,r11,_PAGE_ACCESSED@h
229 tlb_miss_kernel_bolted:
231 ld r14,PACA_KERNELPGD(r13)
232 cmpldi cr0,r15,8 /* Check for vmalloc region */
233 rlwinm r10,r10,0,16,1 /* Clear TID */
235 beq+ tlb_miss_common_bolted
237 tlb_miss_fault_bolted:
238 /* We need to check if it was an instruction miss */
239 andi. r10,r11,_PAGE_EXEC|_PAGE_BAP_SX
240 bne itlb_miss_fault_bolted
241 dtlb_miss_fault_bolted:
242 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
244 b exc_data_storage_book3e
245 itlb_miss_fault_bolted:
246 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
248 b exc_instruction_storage_book3e
250 /* Instruction TLB miss */
251 START_EXCEPTION(instruction_tlb_miss_bolted)
252 tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
254 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
255 srdi r15,r16,60 /* get region */
256 TLB_MISS_STATS_SAVE_INFO_BOLTED
257 bne- itlb_miss_fault_bolted
259 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
261 /* We do the user/kernel test for the PID here along with the RW test
264 cmpldi cr0,r15,0 /* Check for user region */
265 oris r11,r11,_PAGE_ACCESSED@h
266 beq tlb_miss_common_bolted
267 b itlb_miss_kernel_bolted
269 #ifdef CONFIG_PPC_FSL_BOOK3E
271 * TLB miss handling for e6500 and derivatives, using hardware tablewalk.
273 * Linear mapping is bolted: no virtual page table or nested TLB misses
274 * Indirect entries in TLB1, hardware loads resulting direct entries
276 * No HES or NV hint on TLB1, so we need to do software round-robin
277 * No tlbsrx. so we need a spinlock, and we have to deal
278 * with MAS-damage caused by tlbsx
282 START_EXCEPTION(instruction_tlb_miss_e6500)
283 tlb_prolog_bolted BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR0
285 ld r11,PACA_TCD_PTR(r13)
286 srdi. r15,r16,60 /* get region */
289 TLB_MISS_STATS_SAVE_INFO_BOLTED
290 bne tlb_miss_kernel_e6500 /* user/kernel test */
292 b tlb_miss_common_e6500
294 START_EXCEPTION(data_tlb_miss_e6500)
295 tlb_prolog_bolted BOOKE_INTERRUPT_DTLB_MISS SPRN_DEAR
297 ld r11,PACA_TCD_PTR(r13)
298 srdi. r15,r16,60 /* get region */
301 TLB_MISS_STATS_SAVE_INFO_BOLTED
302 bne tlb_miss_kernel_e6500 /* user vs kernel check */
305 * This is the guts of the TLB miss handler for e6500 and derivatives.
306 * We are entered with:
308 * r16 = page of faulting address (low bit 0 if data, 1 if instruction)
309 * r15 = crap (free to use)
310 * r14 = page table base
312 * r11 = tlb_per_core ptr
313 * r10 = crap (free to use)
316 tlb_miss_common_e6500:
317 crmove cr2*4+2,cr0*4+2 /* cr2.eq != 0 if kernel address */
319 BEGIN_FTR_SECTION /* CPU_FTR_SMT */
321 * Search if we already have an indirect entry for that virtual
322 * address, and if we do, bail out.
324 * MAS6:IND should be already set based on MAS4
326 lhz r10,PACAPACAINDEX(r13)
328 crclr cr1*4+eq /* set cr1.eq = 0 for non-recursive */
336 2: cmpd cr1,r15,r10 /* recursive lock due to mcheck/crit/etc? */
337 beq cr1,3b /* unlock will happen if cr1.eq = 0 */
343 END_FTR_SECTION_IFSET(CPU_FTR_SMT)
345 lbz r7,TCD_ESEL_NEXT(r11)
347 BEGIN_FTR_SECTION /* CPU_FTR_SMT */
349 * Erratum A-008139 says that we can't use tlbwe to change
350 * an indirect entry in any way (including replacing or
351 * invalidating) if the other thread could be in the process
352 * of a lookup. The workaround is to invalidate the entry
353 * with tlbilx before overwriting.
356 rlwinm r10,r7,16,0xff0000
357 oris r10,r10,MAS0_TLBSEL(1)@h
362 andis. r15,r15,MAS1_VALID@h
365 BEGIN_FTR_SECTION_NESTED(532)
367 rlwinm r10,r10,0,0x80000fff /* tgs,tlpid -> sgs,slpid */
369 END_FTR_SECTION_NESTED(CPU_FTR_EMB_HV,CPU_FTR_EMB_HV,532)
372 rlwinm r15,r10,0,0x3fff0000 /* tid -> spid */
373 rlwimi r15,r10,20,0x00000003 /* ind,ts -> sind,sas */
385 BEGIN_FTR_SECTION_NESTED(532)
389 END_FTR_SECTION_NESTED(CPU_FTR_EMB_HV,CPU_FTR_EMB_HV,532)
393 andis. r15,r10,MAS1_VALID@h
394 bne tlb_miss_done_e6500
397 ALT_FTR_SECTION_END_IFSET(CPU_FTR_SMT)
399 oris r10,r10,MAS1_VALID@h
401 rlwinm r10,r10,0,16,1 /* Clear TID */
402 4: mtspr SPRN_MAS1,r10
404 /* Now, we need to walk the page tables. First check if we are in
407 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
408 bne- tlb_miss_fault_e6500
410 rldicl r15,r16,64-PGDIR_SHIFT+3,64-PGD_INDEX_SIZE-3
413 beq- tlb_miss_fault_e6500 /* No PGDIR, bail */
414 ldx r14,r14,r15 /* grab pgd entry */
416 rldicl r15,r16,64-PUD_SHIFT+3,64-PUD_INDEX_SIZE-3
419 bge tlb_miss_huge_e6500 /* Bad pgd entry or hugepage; bail */
420 ldx r14,r14,r15 /* grab pud entry */
422 rldicl r15,r16,64-PMD_SHIFT+3,64-PMD_INDEX_SIZE-3
425 bge tlb_miss_huge_e6500
426 ldx r14,r14,r15 /* Grab pmd entry */
430 bge tlb_miss_huge_e6500
432 /* Now we build the MAS for a 2M indirect page:
434 * MAS 0 : ESEL needs to be filled by software round-robin
435 * MAS 1 : Fully set up
436 * - PID already updated by caller if necessary
437 * - TSIZE for now is base ind page size always
438 * - TID already cleared if necessary
439 * MAS 2 : Default not 2M-aligned, need to be redone
440 * MAS 3+7 : Needs to be done
443 ori r14,r14,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
444 mtspr SPRN_MAS7_MAS3,r14
446 clrrdi r15,r16,21 /* make EA 2M-aligned */
449 tlb_miss_huge_done_e6500:
450 lbz r16,TCD_ESEL_MAX(r11)
451 lbz r14,TCD_ESEL_FIRST(r11)
452 rlwimi r10,r7,16,0x00ff0000 /* insert esel_next into MAS0 */
453 addi r7,r7,1 /* increment esel_next */
456 iseleq r7,r14,r7 /* if next == last use first */
457 stb r7,TCD_ESEL_NEXT(r11)
462 .macro tlb_unlock_e6500
464 beq cr1,1f /* no unlock if lock was recursively grabbed */
469 END_FTR_SECTION_IFSET(CPU_FTR_SMT)
473 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
478 beq tlb_miss_fault_e6500
480 andi. r15,r14,HUGEPD_SHIFT_MASK@l /* r15 = psize */
481 rldimi r14,r10,63,0 /* Set PD_HUGE */
482 xor r14,r14,r15 /* Clear size bits */
486 * Now we build the MAS for a huge page.
488 * MAS 0 : ESEL needs to be filled by software round-robin
489 * - can be handled by indirect code
490 * MAS 1 : Need to clear IND and set TSIZE
491 * MAS 2,3+7: Needs to be redone similar to non-tablewalk handler
494 subi r15,r15,10 /* Convert psize to tsize */
496 rlwinm r10,r10,0,~MAS1_IND
497 rlwimi r10,r15,MAS1_TSIZE_SHIFT,MAS1_TSIZE_MASK
501 sld r15,r10,r15 /* Generate mask based on size */
503 rldicr r15,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
504 rlwimi r10,r14,32-19,27,31 /* Insert WIMGE */
505 clrldi r15,r15,PAGE_SHIFT /* Clear crap at the top */
506 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
508 andi. r10,r14,_PAGE_DIRTY
509 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
511 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
513 li r10,MAS3_SW|MAS3_UW
516 mtspr SPRN_MAS7_MAS3,r15
519 b tlb_miss_huge_done_e6500
521 tlb_miss_kernel_e6500:
522 ld r14,PACA_KERNELPGD(r13)
523 cmpldi cr1,r15,8 /* Check for vmalloc region */
524 beq+ cr1,tlb_miss_common_e6500
526 tlb_miss_fault_e6500:
528 /* We need to check if it was an instruction miss */
530 bne itlb_miss_fault_e6500
531 dtlb_miss_fault_e6500:
532 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
534 b exc_data_storage_book3e
535 itlb_miss_fault_e6500:
536 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
538 b exc_instruction_storage_book3e
539 #endif /* CONFIG_PPC_FSL_BOOK3E */
541 /**********************************************************************
543 * TLB miss handling for Book3E with TLB reservation and HES support *
545 **********************************************************************/
549 START_EXCEPTION(data_tlb_miss)
552 /* Now we handle the fault proper. We only save DEAR in normal
553 * fault case since that's the only interesting values here.
554 * We could probably also optimize by not saving SRR0/1 in the
555 * linear mapping case but I'll leave that for later
558 mfspr r16,SPRN_DEAR /* get faulting address */
559 srdi r15,r16,60 /* get region */
560 cmpldi cr0,r15,0xc /* linear mapping ? */
561 TLB_MISS_STATS_SAVE_INFO
562 beq tlb_load_linear /* yes -> go to linear map load */
564 /* The page tables are mapped virtually linear. At this point, though,
565 * we don't know whether we are trying to fault in a first level
566 * virtual address or a virtual page table address. We can get that
567 * from bit 0x1 of the region ID which we have set for a page table
570 bne- virt_page_table_tlb_miss
572 std r14,EX_TLB_ESR(r12); /* save ESR */
573 std r16,EX_TLB_DEAR(r12); /* save DEAR */
575 /* We need _PAGE_PRESENT and _PAGE_ACCESSED set */
577 oris r11,r11,_PAGE_ACCESSED@h
579 /* We do the user/kernel test for the PID here along with the RW test
581 cmpldi cr0,r15,0 /* Check for user region */
583 /* We pre-test some combination of permissions to avoid double
586 * We move the ESR:ST bit into the position of _PAGE_BAP_SW in the PTE
587 * ESR_ST is 0x00800000
588 * _PAGE_BAP_SW is 0x00000010
589 * So the shift is >> 19. This tests for supervisor writeability.
590 * If the page happens to be supervisor writeable and not user
591 * writeable, we will take a new fault later, but that should be
592 * a rare enough case.
594 * We also move ESR_ST in _PAGE_DIRTY position
595 * _PAGE_DIRTY is 0x00001000 so the shift is >> 11
597 * MAS1 is preset for all we need except for TID that needs to
598 * be cleared for kernel translations
600 rlwimi r11,r14,32-19,27,27
601 rlwimi r11,r14,32-16,19,19
603 /* XXX replace the RMW cycles with immediate loads + writes */
604 1: mfspr r10,SPRN_MAS1
605 cmpldi cr0,r15,8 /* Check for vmalloc region */
606 rlwinm r10,r10,0,16,1 /* Clear TID */
610 /* We got a crappy address, just fault with whatever DEAR and ESR
613 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
614 TLB_MISS_EPILOG_ERROR
615 b exc_data_storage_book3e
617 /* Instruction TLB miss */
618 START_EXCEPTION(instruction_tlb_miss)
621 /* If we take a recursive fault, the second level handler may need
622 * to know whether we are handling a data or instruction fault in
623 * order to get to the right store fault handler. We provide that
624 * info by writing a crazy value in ESR in our exception frame
626 li r14,-1 /* store to exception frame is done later */
628 /* Now we handle the fault proper. We only save DEAR in the non
629 * linear mapping case since we know the linear mapping case will
630 * not re-enter. We could indeed optimize and also not save SRR0/1
631 * in the linear mapping case but I'll leave that for later
633 * Faulting address is SRR0 which is already in r16
635 srdi r15,r16,60 /* get region */
636 cmpldi cr0,r15,0xc /* linear mapping ? */
637 TLB_MISS_STATS_SAVE_INFO
638 beq tlb_load_linear /* yes -> go to linear map load */
640 /* We do the user/kernel test for the PID here along with the RW test
642 li r11,_PAGE_PRESENT|_PAGE_EXEC /* Base perm */
643 oris r11,r11,_PAGE_ACCESSED@h
645 cmpldi cr0,r15,0 /* Check for user region */
646 std r14,EX_TLB_ESR(r12) /* write crazy -1 to frame */
649 li r11,_PAGE_PRESENT|_PAGE_BAP_SX /* Base perm */
650 oris r11,r11,_PAGE_ACCESSED@h
651 /* XXX replace the RMW cycles with immediate loads + writes */
653 cmpldi cr0,r15,8 /* Check for vmalloc region */
654 rlwinm r10,r10,0,16,1 /* Clear TID */
658 /* We got a crappy address, just fault */
659 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
660 TLB_MISS_EPILOG_ERROR
661 b exc_instruction_storage_book3e
664 * This is the guts of the first-level TLB miss handler for direct
665 * misses. We are entered with:
667 * r16 = faulting address
669 * r14 = crap (free to use)
671 * r12 = TLB exception frame in PACA
672 * r11 = PTE permission mask
673 * r10 = crap (free to use)
676 /* So we first construct the page table address. We do that by
677 * shifting the bottom of the address (not the region ID) by
678 * PAGE_SHIFT-3, clearing the bottom 3 bits (get a PTE ptr) and
679 * or'ing the fourth high bit.
681 * NOTE: For 64K pages, we do things slightly differently in
682 * order to handle the weird page table format used by linux
685 #ifdef CONFIG_PPC_64K_PAGES
686 /* For the top bits, 16 bytes per PTE */
687 rldicl r14,r16,64-(PAGE_SHIFT-4),PAGE_SHIFT-4+4
688 /* Now create the bottom bits as 0 in position 0x8000 and
689 * the rest calculated for 8 bytes per PTE
691 rldicl r15,r16,64-(PAGE_SHIFT-3),64-15
692 /* Insert the bottom bits in */
693 rlwimi r14,r15,0,16,31
695 rldicl r14,r16,64-(PAGE_SHIFT-3),PAGE_SHIFT-3+4
701 BEGIN_MMU_FTR_SECTION
702 /* Set the TLB reservation and search for existing entry. Then load
705 PPC_TLBSRX_DOT(0,R16)
707 beq normal_tlb_miss_done
710 ALT_MMU_FTR_SECTION_END_IFSET(MMU_FTR_USE_TLBRSRV)
712 finish_normal_tlb_miss:
713 /* Check if required permissions are met */
715 bne- normal_tlb_miss_access_fault
717 /* Now we build the MAS:
719 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
720 * MAS 1 : Almost fully setup
721 * - PID already updated by caller if necessary
722 * - TSIZE need change if !base page size, not
723 * yet implemented for now
724 * MAS 2 : Defaults not useful, need to be redone
725 * MAS 3+7 : Needs to be done
727 * TODO: mix up code below for better scheduling
729 clrrdi r11,r16,12 /* Clear low crap in EA */
730 rlwimi r11,r14,32-19,27,31 /* Insert WIMGE */
733 /* Check page size, if not standard, update MAS1 */
734 rldicl r11,r14,64-8,64-8
735 #ifdef CONFIG_PPC_64K_PAGES
736 cmpldi cr0,r11,BOOK3E_PAGESZ_64K
738 cmpldi cr0,r11,BOOK3E_PAGESZ_4K
742 rlwimi r11,r14,31,21,24
743 rlwinm r11,r11,0,21,19
746 /* Move RPN in position */
747 rldicr r11,r14,64-(PTE_RPN_SHIFT-PAGE_SHIFT),63-PAGE_SHIFT
748 clrldi r15,r11,12 /* Clear crap at the top */
749 rlwimi r15,r14,32-8,22,25 /* Move in U bits */
750 rlwimi r15,r14,32-2,26,31 /* Move in BAP bits */
752 /* Mask out SW and UW if !DIRTY (XXX optimize this !) */
753 andi. r11,r14,_PAGE_DIRTY
755 li r11,MAS3_SW|MAS3_UW
758 BEGIN_MMU_FTR_SECTION
763 mtspr SPRN_MAS7_MAS3,r15
764 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
768 normal_tlb_miss_done:
769 /* We don't bother with restoring DEAR or ESR since we know we are
770 * level 0 and just going back to userland. They are only needed
771 * if you are going to take an access fault
773 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_NORM_OK)
774 TLB_MISS_EPILOG_SUCCESS
777 normal_tlb_miss_access_fault:
778 /* We need to check if it was an instruction miss */
779 andi. r10,r11,_PAGE_EXEC
781 ld r14,EX_TLB_DEAR(r12)
782 ld r15,EX_TLB_ESR(r12)
785 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
786 TLB_MISS_EPILOG_ERROR
787 b exc_data_storage_book3e
788 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
789 TLB_MISS_EPILOG_ERROR
790 b exc_instruction_storage_book3e
794 * This is the guts of the second-level TLB miss handler for direct
795 * misses. We are entered with:
797 * r16 = virtual page table faulting address
798 * r15 = region (top 4 bits of address)
799 * r14 = crap (free to use)
801 * r12 = TLB exception frame in PACA
802 * r11 = crap (free to use)
803 * r10 = crap (free to use)
805 * Note that this should only ever be called as a second level handler
806 * with the current scheme when using SW load.
807 * That means we can always get the original fault DEAR at
808 * EX_TLB_DEAR-EX_TLB_SIZE(r12)
810 * It can be re-entered by the linear mapping miss handler. However, to
811 * avoid too much complication, it will restart the whole fault at level
812 * 0 so we don't care too much about clobbers
814 * XXX That code was written back when we couldn't clobber r14. We can now,
815 * so we could probably optimize things a bit
817 virt_page_table_tlb_miss:
818 /* Are we hitting a kernel page table ? */
821 /* The cool thing now is that r10 contains 0 for user and 8 for kernel,
822 * and we happen to have the swapper_pg_dir at offset 8 from the user
823 * pgdir in the PACA :-).
827 /* If kernel, we need to clear MAS1 TID */
829 /* XXX replace the RMW cycles with immediate loads + writes */
831 rlwinm r10,r10,0,16,1 /* Clear TID */
834 BEGIN_MMU_FTR_SECTION
835 /* Search if we already have a TLB entry for that virtual address, and
836 * if we do, bail out.
838 PPC_TLBSRX_DOT(0,R16)
839 beq virt_page_table_tlb_miss_done
840 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
842 /* Now, we need to walk the page tables. First check if we are in
845 rldicl. r10,r16,64-(VPTE_INDEX_SIZE+3),VPTE_INDEX_SIZE+3+4
846 bne- virt_page_table_tlb_miss_fault
848 /* Get the PGD pointer */
851 beq- virt_page_table_tlb_miss_fault
853 /* Get to PGD entry */
854 rldicl r11,r16,64-VPTE_PGD_SHIFT,64-PGD_INDEX_SIZE-3
858 bge virt_page_table_tlb_miss_fault
860 #ifndef CONFIG_PPC_64K_PAGES
861 /* Get to PUD entry */
862 rldicl r11,r16,64-VPTE_PUD_SHIFT,64-PUD_INDEX_SIZE-3
866 bge virt_page_table_tlb_miss_fault
867 #endif /* CONFIG_PPC_64K_PAGES */
869 /* Get to PMD entry */
870 rldicl r11,r16,64-VPTE_PMD_SHIFT,64-PMD_INDEX_SIZE-3
874 bge virt_page_table_tlb_miss_fault
876 /* Ok, we're all right, we can now create a kernel translation for
877 * a 4K or 64K page from r16 -> r15.
879 /* Now we build the MAS:
881 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
882 * MAS 1 : Almost fully setup
883 * - PID already updated by caller if necessary
884 * - TSIZE for now is base page size always
885 * MAS 2 : Use defaults
886 * MAS 3+7 : Needs to be done
888 * So we only do MAS 2 and 3 for now...
890 clrldi r11,r15,4 /* remove region ID from RPN */
891 ori r10,r11,1 /* Or-in SR */
893 BEGIN_MMU_FTR_SECTION
898 mtspr SPRN_MAS7_MAS3,r10
899 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
903 BEGIN_MMU_FTR_SECTION
904 virt_page_table_tlb_miss_done:
906 /* We have overridden MAS2:EPN but currently our primary TLB miss
907 * handler will always restore it so that should not be an issue,
908 * if we ever optimize the primary handler to not write MAS2 on
909 * some cases, we'll have to restore MAS2:EPN here based on the
910 * original fault's DEAR. If we do that we have to modify the
911 * ITLB miss handler to also store SRR0 in the exception frame
914 * However, one nasty thing we did is we cleared the reservation
915 * (well, potentially we did). We do a trick here thus if we
916 * are not a level 0 exception (we interrupted the TLB miss) we
917 * offset the return address by -4 in order to replay the tlbsrx
921 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
923 ld r11,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
925 std r10,PACA_EXTLB+EX_TLB_SIZE+EX_TLB_SRR0(r13)
927 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_TLBRSRV)
928 /* Return to caller, normal case */
929 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK);
930 TLB_MISS_EPILOG_SUCCESS
933 virt_page_table_tlb_miss_fault:
934 /* If we fault here, things are a little bit tricky. We need to call
935 * either data or instruction store fault, and we need to retrieve
936 * the original fault address and ESR (for data).
938 * The thing is, we know that in normal circumstances, this is
939 * always called as a second level tlb miss for SW load or as a first
940 * level TLB miss for HW load, so we should be able to peek at the
941 * relevant information in the first exception frame in the PACA.
943 * However, we do need to double check that, because we may just hit
944 * a stray kernel pointer or a userland attack trying to hit those
945 * areas. If that is the case, we do a data fault. (We can't get here
946 * from an instruction tlb miss anyway).
948 * Note also that when going to a fault, we must unwind the previous
949 * level as well. Since we are doing that, we don't need to clear or
950 * restore the TLB reservation neither.
953 cmpldi cr0,r10,PACA_EXTLB+EX_TLB_SIZE
954 bne- virt_page_table_tlb_miss_whacko_fault
956 /* We dig the original DEAR and ESR from slot 0 */
957 ld r15,EX_TLB_DEAR+PACA_EXTLB(r13)
958 ld r16,EX_TLB_ESR+PACA_EXTLB(r13)
960 /* We check for the "special" ESR value for instruction faults */
965 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT);
966 TLB_MISS_EPILOG_ERROR
967 b exc_data_storage_book3e
968 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT);
969 TLB_MISS_EPILOG_ERROR
970 b exc_instruction_storage_book3e
972 virt_page_table_tlb_miss_whacko_fault:
973 /* The linear fault will restart everything so ESR and DEAR will
974 * not have been clobbered, let's just fault with what we have
976 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_FAULT);
977 TLB_MISS_EPILOG_ERROR
978 b exc_data_storage_book3e
981 /**************************************************************
983 * TLB miss handling for Book3E with hw page table support *
985 **************************************************************/
989 START_EXCEPTION(data_tlb_miss_htw)
992 /* Now we handle the fault proper. We only save DEAR in normal
993 * fault case since that's the only interesting values here.
994 * We could probably also optimize by not saving SRR0/1 in the
995 * linear mapping case but I'll leave that for later
998 mfspr r16,SPRN_DEAR /* get faulting address */
999 srdi r11,r16,60 /* get region */
1000 cmpldi cr0,r11,0xc /* linear mapping ? */
1001 TLB_MISS_STATS_SAVE_INFO
1002 beq tlb_load_linear /* yes -> go to linear map load */
1004 /* We do the user/kernel test for the PID here along with the RW test
1006 cmpldi cr0,r11,0 /* Check for user region */
1007 ld r15,PACAPGD(r13) /* Load user pgdir */
1010 /* XXX replace the RMW cycles with immediate loads + writes */
1011 1: mfspr r10,SPRN_MAS1
1012 cmpldi cr0,r11,8 /* Check for vmalloc region */
1013 rlwinm r10,r10,0,16,1 /* Clear TID */
1015 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
1018 /* We got a crappy address, just fault with whatever DEAR and ESR
1021 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_NORM_FAULT)
1022 TLB_MISS_EPILOG_ERROR
1023 b exc_data_storage_book3e
1025 /* Instruction TLB miss */
1026 START_EXCEPTION(instruction_tlb_miss_htw)
1029 /* If we take a recursive fault, the second level handler may need
1030 * to know whether we are handling a data or instruction fault in
1031 * order to get to the right store fault handler. We provide that
1032 * info by keeping a crazy value for ESR in r14
1034 li r14,-1 /* store to exception frame is done later */
1036 /* Now we handle the fault proper. We only save DEAR in the non
1037 * linear mapping case since we know the linear mapping case will
1038 * not re-enter. We could indeed optimize and also not save SRR0/1
1039 * in the linear mapping case but I'll leave that for later
1041 * Faulting address is SRR0 which is already in r16
1043 srdi r11,r16,60 /* get region */
1044 cmpldi cr0,r11,0xc /* linear mapping ? */
1045 TLB_MISS_STATS_SAVE_INFO
1046 beq tlb_load_linear /* yes -> go to linear map load */
1048 /* We do the user/kernel test for the PID here along with the RW test
1050 cmpldi cr0,r11,0 /* Check for user region */
1051 ld r15,PACAPGD(r13) /* Load user pgdir */
1054 /* XXX replace the RMW cycles with immediate loads + writes */
1055 1: mfspr r10,SPRN_MAS1
1056 cmpldi cr0,r11,8 /* Check for vmalloc region */
1057 rlwinm r10,r10,0,16,1 /* Clear TID */
1059 ld r15,PACA_KERNELPGD(r13) /* Load kernel pgdir */
1062 /* We got a crappy address, just fault */
1063 TLB_MISS_STATS_I(MMSTAT_TLB_MISS_NORM_FAULT)
1064 TLB_MISS_EPILOG_ERROR
1065 b exc_instruction_storage_book3e
1069 * This is the guts of the second-level TLB miss handler for direct
1070 * misses. We are entered with:
1072 * r16 = virtual page table faulting address
1076 * r12 = TLB exception frame in PACA
1077 * r11 = crap (free to use)
1078 * r10 = crap (free to use)
1080 * It can be re-entered by the linear mapping miss handler. However, to
1081 * avoid too much complication, it will save/restore things for us
1084 /* Search if we already have a TLB entry for that virtual address, and
1085 * if we do, bail out.
1087 * MAS1:IND should be already set based on MAS4
1089 PPC_TLBSRX_DOT(0,R16)
1090 beq htw_tlb_miss_done
1092 /* Now, we need to walk the page tables. First check if we are in
1095 rldicl. r10,r16,64-PGTABLE_EADDR_SIZE,PGTABLE_EADDR_SIZE+4
1096 bne- htw_tlb_miss_fault
1098 /* Get the PGD pointer */
1100 beq- htw_tlb_miss_fault
1102 /* Get to PGD entry */
1103 rldicl r11,r16,64-(PGDIR_SHIFT-3),64-PGD_INDEX_SIZE-3
1107 bge htw_tlb_miss_fault
1109 #ifndef CONFIG_PPC_64K_PAGES
1110 /* Get to PUD entry */
1111 rldicl r11,r16,64-(PUD_SHIFT-3),64-PUD_INDEX_SIZE-3
1115 bge htw_tlb_miss_fault
1116 #endif /* CONFIG_PPC_64K_PAGES */
1118 /* Get to PMD entry */
1119 rldicl r11,r16,64-(PMD_SHIFT-3),64-PMD_INDEX_SIZE-3
1123 bge htw_tlb_miss_fault
1125 /* Ok, we're all right, we can now create an indirect entry for
1126 * a 1M or 256M page.
1128 * The last trick is now that because we use "half" pages for
1129 * the HTW (1M IND is 2K and 256M IND is 32K) we need to account
1130 * for an added LSB bit to the RPN. For 64K pages, there is no
1131 * problem as we already use 32K arrays (half PTE pages), but for
1132 * 4K page we need to extract a bit from the virtual address and
1133 * insert it into the "PA52" bit of the RPN.
1135 #ifndef CONFIG_PPC_64K_PAGES
1136 rlwimi r15,r16,32-9,20,20
1138 /* Now we build the MAS:
1140 * MAS 0 : Fully setup with defaults in MAS4 and TLBnCFG
1141 * MAS 1 : Almost fully setup
1142 * - PID already updated by caller if necessary
1143 * - TSIZE for now is base ind page size always
1144 * MAS 2 : Use defaults
1145 * MAS 3+7 : Needs to be done
1147 #ifdef CONFIG_PPC_64K_PAGES
1148 ori r10,r15,(BOOK3E_PAGESZ_64K << MAS3_SPSIZE_SHIFT)
1150 ori r10,r15,(BOOK3E_PAGESZ_4K << MAS3_SPSIZE_SHIFT)
1153 BEGIN_MMU_FTR_SECTION
1157 MMU_FTR_SECTION_ELSE
1158 mtspr SPRN_MAS7_MAS3,r10
1159 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
1164 /* We don't bother with restoring DEAR or ESR since we know we are
1165 * level 0 and just going back to userland. They are only needed
1166 * if you are going to take an access fault
1168 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_PT_OK)
1169 TLB_MISS_EPILOG_SUCCESS
1173 /* We need to check if it was an instruction miss. We know this
1174 * though because r14 would contain -1
1180 TLB_MISS_STATS_D(MMSTAT_TLB_MISS_PT_FAULT)
1181 TLB_MISS_EPILOG_ERROR
1182 b exc_data_storage_book3e
1183 1: TLB_MISS_STATS_I(MMSTAT_TLB_MISS_PT_FAULT)
1184 TLB_MISS_EPILOG_ERROR
1185 b exc_instruction_storage_book3e
1188 * This is the guts of "any" level TLB miss handler for kernel linear
1189 * mapping misses. We are entered with:
1192 * r16 = faulting address
1193 * r15 = crap (free to use)
1194 * r14 = ESR (data) or -1 (instruction)
1196 * r12 = TLB exception frame in PACA
1197 * r11 = crap (free to use)
1198 * r10 = crap (free to use)
1200 * In addition we know that we will not re-enter, so in theory, we could
1201 * use a simpler epilog not restoring SRR0/1 etc.. but we'll do that later.
1203 * We also need to be careful about MAS registers here & TLB reservation,
1204 * as we know we'll have clobbered them if we interrupt the main TLB miss
1205 * handlers in which case we probably want to do a full restart at level
1206 * 0 rather than saving / restoring the MAS.
1208 * Note: If we care about performance of that core, we can easily shuffle
1209 * a few things around
1212 /* For now, we assume the linear mapping is contiguous and stops at
1213 * linear_map_top. We also assume the size is a multiple of 1G, thus
1214 * we only use 1G pages for now. That might have to be changed in a
1215 * final implementation, especially when dealing with hypervisors
1218 ld r11,linear_map_top@got(r11)
1222 bge tlb_load_linear_fault
1224 /* MAS1 need whole new setup. */
1225 li r15,(BOOK3E_PAGESZ_1GB<<MAS1_TSIZE_SHIFT)
1226 oris r15,r15,MAS1_VALID@h /* MAS1 needs V and TSIZE */
1229 /* Already somebody there ? */
1230 PPC_TLBSRX_DOT(0,R16)
1231 beq tlb_load_linear_done
1233 /* Now we build the remaining MAS. MAS0 and 2 should be fine
1234 * with their defaults, which leaves us with MAS 3 and 7. The
1235 * mapping is linear, so we just take the address, clear the
1236 * region bits, and or in the permission bits which are currently
1239 clrrdi r10,r16,30 /* 1G page index */
1240 clrldi r10,r10,4 /* clear region bits */
1241 ori r10,r10,MAS3_SR|MAS3_SW|MAS3_SX
1243 BEGIN_MMU_FTR_SECTION
1247 MMU_FTR_SECTION_ELSE
1248 mtspr SPRN_MAS7_MAS3,r10
1249 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_PAIRED_MAS)
1253 tlb_load_linear_done:
1254 /* We use the "error" epilog for success as we do want to
1255 * restore to the initial faulting context, whatever it was.
1256 * We do that because we can't resume a fault within a TLB
1257 * miss handler, due to MAS and TLB reservation being clobbered.
1259 TLB_MISS_STATS_X(MMSTAT_TLB_MISS_LINEAR)
1260 TLB_MISS_EPILOG_ERROR
1263 tlb_load_linear_fault:
1264 /* We keep the DEAR and ESR around, this shouldn't have happened */
1267 TLB_MISS_EPILOG_ERROR_SPECIAL
1268 b exc_data_storage_book3e
1269 1: TLB_MISS_EPILOG_ERROR_SPECIAL
1270 b exc_instruction_storage_book3e
1273 #ifdef CONFIG_BOOK3E_MMU_TLB_STATS