1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * This file contains common routines for dealing with free of page tables
4 * Along with common page table handling code
6 * Derived from arch/powerpc/mm/tlb_64.c:
7 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
9 * Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
10 * and Cort Dougan (PReP) (cort@cs.nmt.edu)
11 * Copyright (C) 1996 Paul Mackerras
13 * Derived from "arch/i386/mm/init.c"
14 * Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
16 * Dave Engebretsen <engebret@us.ibm.com>
17 * Rework for PPC64 port.
20 #include <linux/kernel.h>
21 #include <linux/gfp.h>
23 #include <linux/percpu.h>
24 #include <linux/hardirq.h>
25 #include <linux/hugetlb.h>
26 #include <asm/tlbflush.h>
28 #include <asm/hugetlb.h>
29 #include <asm/pte-walk.h>
32 #define PGD_ALIGN (sizeof(pgd_t) * MAX_PTRS_PER_PGD)
34 #define PGD_ALIGN PAGE_SIZE
37 pgd_t swapper_pg_dir[MAX_PTRS_PER_PGD] __section(".bss..page_aligned") __aligned(PGD_ALIGN);
39 static inline int is_exec_fault(void)
41 return current->thread.regs && TRAP(current->thread.regs) == 0x400;
44 /* We only try to do i/d cache coherency on stuff that looks like
45 * reasonably "normal" PTEs. We currently require a PTE to be present
46 * and we avoid _PAGE_SPECIAL and cache inhibited pte. We also only do that
49 static inline int pte_looks_normal(pte_t pte, unsigned long addr)
52 if (pte_present(pte) && !pte_special(pte)) {
55 if (!is_kernel_addr(addr))
61 static struct folio *maybe_pte_to_folio(pte_t pte)
63 unsigned long pfn = pte_pfn(pte);
66 if (unlikely(!pfn_valid(pfn)))
68 page = pfn_to_page(pfn);
69 if (PageReserved(page))
71 return page_folio(page);
74 #ifdef CONFIG_PPC_BOOK3S
76 /* Server-style MMU handles coherency when hashing if HW exec permission
77 * is supposed per page (currently 64-bit only). If not, then, we always
78 * flush the cache for valid PTEs in set_pte. Embedded CPU without HW exec
79 * support falls into the same category.
82 static pte_t set_pte_filter_hash(pte_t pte, unsigned long addr)
84 pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
85 if (pte_looks_normal(pte, addr) && !(cpu_has_feature(CPU_FTR_COHERENT_ICACHE) ||
86 cpu_has_feature(CPU_FTR_NOEXECUTE))) {
87 struct folio *folio = maybe_pte_to_folio(pte);
90 if (!test_bit(PG_dcache_clean, &folio->flags)) {
91 flush_dcache_icache_folio(folio);
92 set_bit(PG_dcache_clean, &folio->flags);
98 #else /* CONFIG_PPC_BOOK3S */
100 static pte_t set_pte_filter_hash(pte_t pte, unsigned long addr) { return pte; }
102 #endif /* CONFIG_PPC_BOOK3S */
104 /* Embedded type MMU with HW exec support. This is a bit more complicated
105 * as we don't have two bits to spare for _PAGE_EXEC and _PAGE_HWEXEC so
106 * instead we "filter out" the exec permission for non clean pages.
108 * This is also called once for the folio. So only work with folio->flags here.
110 static inline pte_t set_pte_filter(pte_t pte, unsigned long addr)
117 if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
118 return set_pte_filter_hash(pte, addr);
120 /* No exec permission in the first place, move on */
121 if (!pte_exec(pte) || !pte_looks_normal(pte, addr))
124 /* If you set _PAGE_EXEC on weird pages you're on your own */
125 folio = maybe_pte_to_folio(pte);
126 if (unlikely(!folio))
129 /* If the page clean, we move on */
130 if (test_bit(PG_dcache_clean, &folio->flags))
133 /* If it's an exec fault, we flush the cache and make it clean */
134 if (is_exec_fault()) {
135 flush_dcache_icache_folio(folio);
136 set_bit(PG_dcache_clean, &folio->flags);
140 /* Else, we filter out _PAGE_EXEC */
141 return pte_exprotect(pte);
144 static pte_t set_access_flags_filter(pte_t pte, struct vm_area_struct *vma,
149 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64))
152 if (mmu_has_feature(MMU_FTR_HPTE_TABLE))
155 /* So here, we only care about exec faults, as we use them
156 * to recover lost _PAGE_EXEC and perform I$/D$ coherency
157 * if necessary. Also if _PAGE_EXEC is already set, same deal,
160 if (dirty || pte_exec(pte) || !is_exec_fault())
163 #ifdef CONFIG_DEBUG_VM
164 /* So this is an exec fault, _PAGE_EXEC is not set. If it was
165 * an error we would have bailed out earlier in do_page_fault()
166 * but let's make sure of it
168 if (WARN_ON(!(vma->vm_flags & VM_EXEC)))
170 #endif /* CONFIG_DEBUG_VM */
172 /* If you set _PAGE_EXEC on weird pages you're on your own */
173 folio = maybe_pte_to_folio(pte);
174 if (unlikely(!folio))
177 /* If the page is already clean, we move on */
178 if (test_bit(PG_dcache_clean, &folio->flags))
181 /* Clean the page and set PG_dcache_clean */
182 flush_dcache_icache_folio(folio);
183 set_bit(PG_dcache_clean, &folio->flags);
186 return pte_mkexec(pte);
190 * set_pte stores a linux PTE into the linux page table.
192 void set_ptes(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
193 pte_t pte, unsigned int nr)
196 /* Note: mm->context.id might not yet have been assigned as
197 * this context might not have been activated yet when this
198 * is called. Filter the pte value and use the filtered value
199 * to setup all the ptes in the range.
201 pte = set_pte_filter(pte, addr);
204 * We don't need to call arch_enter/leave_lazy_mmu_mode()
205 * because we expect set_ptes to be only be used on not present
206 * and not hw_valid ptes. Hence there is no translation cache flush
207 * involved that need to be batched.
212 * Make sure hardware valid bit is not set. We don't do
213 * tlb flush for this update.
215 VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
217 /* Perform the setting of the PTE */
218 __set_pte_at(mm, addr, ptep, pte, 0);
226 pte = pfn_pte(pte_pfn(pte) + 1, pte_pgprot((pte)));
230 void unmap_kernel_page(unsigned long va)
232 pmd_t *pmdp = pmd_off_k(va);
233 pte_t *ptep = pte_offset_kernel(pmdp, va);
235 pte_clear(&init_mm, va, ptep);
236 flush_tlb_kernel_range(va, va + PAGE_SIZE);
240 * This is called when relaxing access to a PTE. It's also called in the page
241 * fault path when we don't hit any of the major fault cases, ie, a minor
242 * update of _PAGE_ACCESSED, _PAGE_DIRTY, etc... The generic code will have
243 * handled those two for us, we additionally deal with missing execute
244 * permission here on some processors
246 int ptep_set_access_flags(struct vm_area_struct *vma, unsigned long address,
247 pte_t *ptep, pte_t entry, int dirty)
250 entry = set_access_flags_filter(entry, vma, dirty);
251 changed = !pte_same(*(ptep), entry);
253 assert_pte_locked(vma->vm_mm, address);
254 __ptep_set_access_flags(vma, ptep, entry,
255 address, mmu_virtual_psize);
260 #ifdef CONFIG_HUGETLB_PAGE
261 int huge_ptep_set_access_flags(struct vm_area_struct *vma,
262 unsigned long addr, pte_t *ptep,
263 pte_t pte, int dirty)
265 #ifdef HUGETLB_NEED_PRELOAD
267 * The "return 1" forces a call of update_mmu_cache, which will write a
268 * TLB entry. Without this, platforms that don't do a write of the TLB
269 * entry in the TLB miss handler asm will fault ad infinitum.
271 ptep_set_access_flags(vma, addr, ptep, pte, dirty);
276 pte = set_access_flags_filter(pte, vma, dirty);
277 changed = !pte_same(*(ptep), pte);
280 #ifdef CONFIG_PPC_BOOK3S_64
281 struct hstate *h = hstate_vma(vma);
283 psize = hstate_get_psize(h);
284 #ifdef CONFIG_DEBUG_VM
285 assert_spin_locked(huge_pte_lockptr(h, vma->vm_mm, ptep));
290 * Not used on non book3s64 platforms.
291 * 8xx compares it with mmu_virtual_psize to
292 * know if it is a huge page or not.
294 psize = MMU_PAGE_COUNT;
296 __ptep_set_access_flags(vma, ptep, pte, addr, psize);
302 #if defined(CONFIG_PPC_8xx)
303 void set_huge_pte_at(struct mm_struct *mm, unsigned long addr, pte_t *ptep,
304 pte_t pte, unsigned long sz)
306 pmd_t *pmd = pmd_off(mm, addr);
308 pte_basic_t *entry = (pte_basic_t *)ptep;
312 * Make sure hardware valid bit is not set. We don't do
313 * tlb flush for this update.
315 VM_WARN_ON(pte_hw_valid(*ptep) && !pte_protnone(*ptep));
317 pte = set_pte_filter(pte, addr);
321 num = number_of_cells_per_pte(pmd, val, 1);
323 for (i = 0; i < num; i++, entry++, val += SZ_4K)
327 #endif /* CONFIG_HUGETLB_PAGE */
329 #ifdef CONFIG_DEBUG_VM
330 void assert_pte_locked(struct mm_struct *mm, unsigned long addr)
341 pgd = mm->pgd + pgd_index(addr);
342 BUG_ON(pgd_none(*pgd));
343 p4d = p4d_offset(pgd, addr);
344 BUG_ON(p4d_none(*p4d));
345 pud = pud_offset(p4d, addr);
346 BUG_ON(pud_none(*pud));
347 pmd = pmd_offset(pud, addr);
349 * khugepaged to collapse normal pages to hugepage, first set
350 * pmd to none to force page fault/gup to take mmap_lock. After
351 * pmd is set to none, we do a pte_clear which does this assertion
352 * so if we find pmd none, return.
356 pte = pte_offset_map_nolock(mm, pmd, addr, &ptl);
358 assert_spin_locked(ptl);
361 #endif /* CONFIG_DEBUG_VM */
363 unsigned long vmalloc_to_phys(void *va)
365 unsigned long pfn = vmalloc_to_pfn(va);
368 return __pa(pfn_to_kaddr(pfn)) + offset_in_page(va);
370 EXPORT_SYMBOL_GPL(vmalloc_to_phys);
373 * We have 4 cases for pgds and pmds:
374 * (1) invalid (all zeroes)
375 * (2) pointer to next table, as normal; bottom 6 bits == 0
376 * (3) leaf pte for huge page _PAGE_PTE set
377 * (4) hugepd pointer, _PAGE_PTE = 0 and bits [2..6] indicate size of table
379 * So long as we atomically load page table pointers we are safe against teardown,
380 * we can follow the address down to the page and take a ref on it.
381 * This function need to be called with interrupts disabled. We use this variant
382 * when we have MSR[EE] = 0 but the paca->irq_soft_mask = IRQS_ENABLED
384 pte_t *__find_linux_pte(pgd_t *pgdir, unsigned long ea,
385 bool *is_thp, unsigned *hpage_shift)
392 hugepd_t *hpdp = NULL;
402 * Always operate on the local stack value. This make sure the
403 * value don't get updated by a parallel THP split/collapse,
404 * page fault or a page unmap. The return pte_t * is still not
405 * stable. So should be checked there for above conditions.
406 * Top level is an exception because it is folded into p4d.
408 pgdp = pgdir + pgd_index(ea);
409 p4dp = p4d_offset(pgdp, ea);
410 p4d = READ_ONCE(*p4dp);
416 if (p4d_is_leaf(p4d)) {
417 ret_pte = (pte_t *)p4dp;
421 if (is_hugepd(__hugepd(p4d_val(p4d)))) {
422 hpdp = (hugepd_t *)&p4d;
427 * Even if we end up with an unmap, the pgtable will not
428 * be freed, because we do an rcu free and here we are
432 pudp = pud_offset(&p4d, ea);
433 pud = READ_ONCE(*pudp);
438 if (pud_is_leaf(pud)) {
439 ret_pte = (pte_t *)pudp;
443 if (is_hugepd(__hugepd(pud_val(pud)))) {
444 hpdp = (hugepd_t *)&pud;
449 pmdp = pmd_offset(&pud, ea);
450 pmd = READ_ONCE(*pmdp);
453 * A hugepage collapse is captured by this condition, see
454 * pmdp_collapse_flush.
459 #ifdef CONFIG_PPC_BOOK3S_64
461 * A hugepage split is captured by this condition, see
464 * Huge page modification can be caught here too.
466 if (pmd_is_serializing(pmd))
470 if (pmd_trans_huge(pmd) || pmd_devmap(pmd)) {
473 ret_pte = (pte_t *)pmdp;
477 if (pmd_is_leaf(pmd)) {
478 ret_pte = (pte_t *)pmdp;
482 if (is_hugepd(__hugepd(pmd_val(pmd)))) {
483 hpdp = (hugepd_t *)&pmd;
487 return pte_offset_kernel(&pmd, ea);
493 ret_pte = hugepte_offset(*hpdp, ea, pdshift);
494 pdshift = hugepd_shift(*hpdp);
497 *hpage_shift = pdshift;
500 EXPORT_SYMBOL_GPL(__find_linux_pte);
502 /* Note due to the way vm flags are laid out, the bits are XWR */
503 const pgprot_t protection_map[16] = {
504 [VM_NONE] = PAGE_NONE,
505 [VM_READ] = PAGE_READONLY,
506 [VM_WRITE] = PAGE_COPY,
507 [VM_WRITE | VM_READ] = PAGE_COPY,
508 [VM_EXEC] = PAGE_EXECONLY_X,
509 [VM_EXEC | VM_READ] = PAGE_READONLY_X,
510 [VM_EXEC | VM_WRITE] = PAGE_COPY_X,
511 [VM_EXEC | VM_WRITE | VM_READ] = PAGE_COPY_X,
512 [VM_SHARED] = PAGE_NONE,
513 [VM_SHARED | VM_READ] = PAGE_READONLY,
514 [VM_SHARED | VM_WRITE] = PAGE_SHARED,
515 [VM_SHARED | VM_WRITE | VM_READ] = PAGE_SHARED,
516 [VM_SHARED | VM_EXEC] = PAGE_EXECONLY_X,
517 [VM_SHARED | VM_EXEC | VM_READ] = PAGE_READONLY_X,
518 [VM_SHARED | VM_EXEC | VM_WRITE] = PAGE_SHARED_X,
519 [VM_SHARED | VM_EXEC | VM_WRITE | VM_READ] = PAGE_SHARED_X
522 #ifndef CONFIG_PPC_BOOK3S_64
523 DECLARE_VM_GET_PAGE_PROT