2 * Page table handling routines for radix page table.
4 * Copyright 2015-2016, Aneesh Kumar K.V, IBM Corporation.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
12 #define pr_fmt(fmt) "radix-mmu: " fmt
14 #include <linux/kernel.h>
15 #include <linux/sched/mm.h>
16 #include <linux/memblock.h>
17 #include <linux/of_fdt.h>
19 #include <linux/string_helpers.h>
20 #include <linux/stop_machine.h>
22 #include <asm/pgtable.h>
23 #include <asm/pgalloc.h>
24 #include <asm/mmu_context.h>
26 #include <asm/machdep.h>
28 #include <asm/firmware.h>
29 #include <asm/powernv.h>
30 #include <asm/sections.h>
31 #include <asm/trace.h>
33 #include <trace/events/thp.h>
35 unsigned int mmu_pid_bits;
36 unsigned int mmu_base_pid;
38 static int native_register_process_table(unsigned long base, unsigned long pg_sz,
39 unsigned long table_size)
41 unsigned long patb0, patb1;
43 patb0 = be64_to_cpu(partition_tb[0].patb0);
44 patb1 = base | table_size | PATB_GR;
46 mmu_partition_table_set_entry(0, patb0, patb1);
51 static __ref void *early_alloc_pgtable(unsigned long size, int nid,
52 unsigned long region_start, unsigned long region_end)
57 if (region_start || region_end) /* has region hint */
58 pa = memblock_alloc_range(size, size, region_start, region_end,
60 else if (nid != -1) /* has node hint */
61 pa = memblock_alloc_base_nid(size, size,
62 MEMBLOCK_ALLOC_ANYWHERE,
66 pa = memblock_alloc_base(size, size, MEMBLOCK_ALLOC_ANYWHERE);
76 static int early_map_kernel_page(unsigned long ea, unsigned long pa,
78 unsigned int map_page_size,
80 unsigned long region_start, unsigned long region_end)
82 unsigned long pfn = pa >> PAGE_SHIFT;
88 pgdp = pgd_offset_k(ea);
89 if (pgd_none(*pgdp)) {
90 pudp = early_alloc_pgtable(PUD_TABLE_SIZE, nid,
91 region_start, region_end);
92 pgd_populate(&init_mm, pgdp, pudp);
94 pudp = pud_offset(pgdp, ea);
95 if (map_page_size == PUD_SIZE) {
99 if (pud_none(*pudp)) {
100 pmdp = early_alloc_pgtable(PMD_TABLE_SIZE, nid,
101 region_start, region_end);
102 pud_populate(&init_mm, pudp, pmdp);
104 pmdp = pmd_offset(pudp, ea);
105 if (map_page_size == PMD_SIZE) {
106 ptep = pmdp_ptep(pmdp);
109 if (!pmd_present(*pmdp)) {
110 ptep = early_alloc_pgtable(PAGE_SIZE, nid,
111 region_start, region_end);
112 pmd_populate_kernel(&init_mm, pmdp, ptep);
114 ptep = pte_offset_kernel(pmdp, ea);
117 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
118 asm volatile("ptesync": : :"memory");
123 * nid, region_start, and region_end are hints to try to place the page
124 * table memory in the same node or region.
126 static int __map_kernel_page(unsigned long ea, unsigned long pa,
128 unsigned int map_page_size,
130 unsigned long region_start, unsigned long region_end)
132 unsigned long pfn = pa >> PAGE_SHIFT;
138 * Make sure task size is correct as per the max adddr
140 BUILD_BUG_ON(TASK_SIZE_USER64 > RADIX_PGTABLE_RANGE);
142 if (unlikely(!slab_is_available()))
143 return early_map_kernel_page(ea, pa, flags, map_page_size,
144 nid, region_start, region_end);
147 * Should make page table allocation functions be able to take a
148 * node, so we can place kernel page tables on the right nodes after
151 pgdp = pgd_offset_k(ea);
152 pudp = pud_alloc(&init_mm, pgdp, ea);
155 if (map_page_size == PUD_SIZE) {
156 ptep = (pte_t *)pudp;
159 pmdp = pmd_alloc(&init_mm, pudp, ea);
162 if (map_page_size == PMD_SIZE) {
163 ptep = pmdp_ptep(pmdp);
166 ptep = pte_alloc_kernel(pmdp, ea);
171 set_pte_at(&init_mm, ea, ptep, pfn_pte(pfn, flags));
172 asm volatile("ptesync": : :"memory");
176 int radix__map_kernel_page(unsigned long ea, unsigned long pa,
178 unsigned int map_page_size)
180 return __map_kernel_page(ea, pa, flags, map_page_size, -1, 0, 0);
183 #ifdef CONFIG_STRICT_KERNEL_RWX
184 void radix__change_memory_range(unsigned long start, unsigned long end,
193 start = ALIGN_DOWN(start, PAGE_SIZE);
194 end = PAGE_ALIGN(end); // aligns up
196 pr_debug("Changing flags on range %lx-%lx removing 0x%lx\n",
199 for (idx = start; idx < end; idx += PAGE_SIZE) {
200 pgdp = pgd_offset_k(idx);
201 pudp = pud_alloc(&init_mm, pgdp, idx);
204 if (pud_huge(*pudp)) {
205 ptep = (pte_t *)pudp;
208 pmdp = pmd_alloc(&init_mm, pudp, idx);
211 if (pmd_huge(*pmdp)) {
212 ptep = pmdp_ptep(pmdp);
215 ptep = pte_alloc_kernel(pmdp, idx);
219 radix__pte_update(&init_mm, idx, ptep, clear, 0, 0);
222 radix__flush_tlb_kernel_range(start, end);
225 void radix__mark_rodata_ro(void)
227 unsigned long start, end;
229 start = (unsigned long)_stext;
230 end = (unsigned long)__init_begin;
232 radix__change_memory_range(start, end, _PAGE_WRITE);
235 void radix__mark_initmem_nx(void)
237 unsigned long start = (unsigned long)__init_begin;
238 unsigned long end = (unsigned long)__init_end;
240 radix__change_memory_range(start, end, _PAGE_EXEC);
242 #endif /* CONFIG_STRICT_KERNEL_RWX */
244 static inline void __meminit print_mapping(unsigned long start,
253 string_get_size(size, 1, STRING_UNITS_2, buf, sizeof(buf));
255 pr_info("Mapped 0x%016lx-0x%016lx with %s pages\n", start, end, buf);
258 static int __meminit create_physical_mapping(unsigned long start,
262 unsigned long vaddr, addr, mapping_size = 0;
264 unsigned long max_mapping_size;
265 #ifdef CONFIG_STRICT_KERNEL_RWX
266 int split_text_mapping = 1;
268 int split_text_mapping = 0;
272 start = _ALIGN_UP(start, PAGE_SIZE);
273 for (addr = start; addr < end; addr += mapping_size) {
274 unsigned long gap, previous_size;
278 previous_size = mapping_size;
279 max_mapping_size = PUD_SIZE;
282 if (IS_ALIGNED(addr, PUD_SIZE) && gap >= PUD_SIZE &&
283 mmu_psize_defs[MMU_PAGE_1G].shift &&
284 PUD_SIZE <= max_mapping_size) {
285 mapping_size = PUD_SIZE;
287 } else if (IS_ALIGNED(addr, PMD_SIZE) && gap >= PMD_SIZE &&
288 mmu_psize_defs[MMU_PAGE_2M].shift) {
289 mapping_size = PMD_SIZE;
292 mapping_size = PAGE_SIZE;
293 psize = mmu_virtual_psize;
296 if (split_text_mapping && (mapping_size == PUD_SIZE) &&
297 (addr < __pa_symbol(__init_begin)) &&
298 (addr + mapping_size) > __pa_symbol(__init_begin)) {
299 max_mapping_size = PMD_SIZE;
303 if (split_text_mapping && (mapping_size == PMD_SIZE) &&
304 (addr < __pa_symbol(__init_begin)) &&
305 (addr + mapping_size) > __pa_symbol(__init_begin)) {
306 mapping_size = PAGE_SIZE;
307 psize = mmu_virtual_psize;
310 if (mapping_size != previous_size) {
311 print_mapping(start, addr, previous_size);
315 vaddr = (unsigned long)__va(addr);
317 if (overlaps_kernel_text(vaddr, vaddr + mapping_size) ||
318 overlaps_interrupt_vector_text(vaddr, vaddr + mapping_size))
319 prot = PAGE_KERNEL_X;
323 rc = __map_kernel_page(vaddr, addr, prot, mapping_size, nid, start, end);
327 update_page_count(psize, 1);
330 print_mapping(start, addr, mapping_size);
334 void __init radix_init_pgtable(void)
336 unsigned long rts_field;
337 struct memblock_region *reg;
339 /* We don't support slb for radix */
342 * Create the linear mapping, using standard page size for now
344 for_each_memblock(memory, reg) {
346 * The memblock allocator is up at this point, so the
347 * page tables will be allocated within the range. No
348 * need or a node (which we don't have yet).
350 WARN_ON(create_physical_mapping(reg->base,
351 reg->base + reg->size,
355 /* Find out how many PID bits are supported */
356 if (cpu_has_feature(CPU_FTR_HVMODE)) {
359 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
361 * When KVM is possible, we only use the top half of the
362 * PID space to avoid collisions between host and guest PIDs
363 * which can cause problems due to prefetch when exiting the
366 mmu_base_pid = 1 << (mmu_pid_bits - 1);
371 /* The guest uses the bottom half of the PID space */
378 * Allocate Partition table and process table for the
381 BUG_ON(PRTB_SIZE_SHIFT > 36);
382 process_tb = early_alloc_pgtable(1UL << PRTB_SIZE_SHIFT, -1, 0, 0);
384 * Fill in the process table.
386 rts_field = radix__get_tree_size();
387 process_tb->prtb0 = cpu_to_be64(rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE);
389 * Fill in the partition table. We are suppose to use effective address
390 * of process table here. But our linear mapping also enable us to use
391 * physical address here.
393 register_process_table(__pa(process_tb), 0, PRTB_SIZE_SHIFT - 12);
394 pr_info("Process table %p and radix root for kernel: %p\n", process_tb, init_mm.pgd);
395 asm volatile("ptesync" : : : "memory");
396 asm volatile(PPC_TLBIE_5(%0,%1,2,1,1) : :
397 "r" (TLBIEL_INVAL_SET_LPID), "r" (0));
398 asm volatile("eieio; tlbsync; ptesync" : : : "memory");
399 trace_tlbie(0, 0, TLBIEL_INVAL_SET_LPID, 0, 2, 1, 1);
402 * The init_mm context is given the first available (non-zero) PID,
403 * which is the "guard PID" and contains no page table. PIDR should
404 * never be set to zero because that duplicates the kernel address
405 * space at the 0x0... offset (quadrant 0)!
407 * An arbitrary PID that may later be allocated by the PID allocator
408 * for userspace processes must not be used either, because that
409 * would cause stale user mappings for that PID on CPUs outside of
410 * the TLB invalidation scheme (because it won't be in mm_cpumask).
412 * So permanently carve out one PID for the purpose of a guard PID.
414 init_mm.context.id = mmu_base_pid;
418 static void __init radix_init_partition_table(void)
420 unsigned long rts_field, dw0;
422 mmu_partition_table_init();
423 rts_field = radix__get_tree_size();
424 dw0 = rts_field | __pa(init_mm.pgd) | RADIX_PGD_INDEX_SIZE | PATB_HR;
425 mmu_partition_table_set_entry(0, dw0, 0);
427 pr_info("Initializing Radix MMU\n");
428 pr_info("Partition table %p\n", partition_tb);
431 void __init radix_init_native(void)
433 register_process_table = native_register_process_table;
436 static int __init get_idx_from_shift(unsigned int shift)
457 static int __init radix_dt_scan_page_sizes(unsigned long node,
458 const char *uname, int depth,
465 const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
467 /* We are scanning "cpu" nodes only */
468 if (type == NULL || strcmp(type, "cpu") != 0)
471 /* Find MMU PID size */
472 prop = of_get_flat_dt_prop(node, "ibm,mmu-pid-bits", &size);
473 if (prop && size == 4)
474 mmu_pid_bits = be32_to_cpup(prop);
476 /* Grab page size encodings */
477 prop = of_get_flat_dt_prop(node, "ibm,processor-radix-AP-encodings", &size);
481 pr_info("Page sizes from device-tree:\n");
482 for (; size >= 4; size -= 4, ++prop) {
484 struct mmu_psize_def *def;
486 /* top 3 bit is AP encoding */
487 shift = be32_to_cpu(prop[0]) & ~(0xe << 28);
488 ap = be32_to_cpu(prop[0]) >> 29;
489 pr_info("Page size shift = %d AP=0x%x\n", shift, ap);
491 idx = get_idx_from_shift(shift);
495 def = &mmu_psize_defs[idx];
501 cur_cpu_spec->mmu_features &= ~MMU_FTR_NO_SLBIE_B;
505 void __init radix__early_init_devtree(void)
510 * Try to find the available page sizes in the device-tree
512 rc = of_scan_flat_dt(radix_dt_scan_page_sizes, NULL);
513 if (rc != 0) /* Found */
516 * let's assume we have page 4k and 64k support
518 mmu_psize_defs[MMU_PAGE_4K].shift = 12;
519 mmu_psize_defs[MMU_PAGE_4K].ap = 0x0;
521 mmu_psize_defs[MMU_PAGE_64K].shift = 16;
522 mmu_psize_defs[MMU_PAGE_64K].ap = 0x5;
527 static void radix_init_amor(void)
530 * In HV mode, we init AMOR (Authority Mask Override Register) so that
531 * the hypervisor and guest can setup IAMR (Instruction Authority Mask
532 * Register), enable key 0 and set it to 1.
534 * AMOR = 0b1100 .... 0000 (Mask for key 0 is 11)
536 mtspr(SPRN_AMOR, (3ul << 62));
539 static void radix_init_iamr(void)
542 * Radix always uses key0 of the IAMR to determine if an access is
543 * allowed. We set bit 0 (IBM bit 1) of key0, to prevent instruction
546 mtspr(SPRN_IAMR, (1ul << 62));
549 void __init radix__early_init_mmu(void)
553 #ifdef CONFIG_PPC_64K_PAGES
554 /* PAGE_SIZE mappings */
555 mmu_virtual_psize = MMU_PAGE_64K;
557 mmu_virtual_psize = MMU_PAGE_4K;
560 #ifdef CONFIG_SPARSEMEM_VMEMMAP
561 /* vmemmap mapping */
562 if (mmu_psize_defs[MMU_PAGE_2M].shift) {
564 * map vmemmap using 2M if available
566 mmu_vmemmap_psize = MMU_PAGE_2M;
568 mmu_vmemmap_psize = mmu_virtual_psize;
571 * initialize page table size
573 __pte_index_size = RADIX_PTE_INDEX_SIZE;
574 __pmd_index_size = RADIX_PMD_INDEX_SIZE;
575 __pud_index_size = RADIX_PUD_INDEX_SIZE;
576 __pgd_index_size = RADIX_PGD_INDEX_SIZE;
577 __pud_cache_index = RADIX_PUD_INDEX_SIZE;
578 __pte_table_size = RADIX_PTE_TABLE_SIZE;
579 __pmd_table_size = RADIX_PMD_TABLE_SIZE;
580 __pud_table_size = RADIX_PUD_TABLE_SIZE;
581 __pgd_table_size = RADIX_PGD_TABLE_SIZE;
583 __pmd_val_bits = RADIX_PMD_VAL_BITS;
584 __pud_val_bits = RADIX_PUD_VAL_BITS;
585 __pgd_val_bits = RADIX_PGD_VAL_BITS;
587 __kernel_virt_start = RADIX_KERN_VIRT_START;
588 __kernel_virt_size = RADIX_KERN_VIRT_SIZE;
589 __vmalloc_start = RADIX_VMALLOC_START;
590 __vmalloc_end = RADIX_VMALLOC_END;
591 __kernel_io_start = RADIX_KERN_IO_START;
592 vmemmap = (struct page *)RADIX_VMEMMAP_BASE;
593 ioremap_bot = IOREMAP_BASE;
596 pci_io_base = ISA_IO_BASE;
598 __pte_frag_nr = RADIX_PTE_FRAG_NR;
599 __pte_frag_size_shift = RADIX_PTE_FRAG_SIZE_SHIFT;
600 __pmd_frag_nr = RADIX_PMD_FRAG_NR;
601 __pmd_frag_size_shift = RADIX_PMD_FRAG_SIZE_SHIFT;
603 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
605 lpcr = mfspr(SPRN_LPCR);
606 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
607 radix_init_partition_table();
610 radix_init_pseries();
613 memblock_set_current_limit(MEMBLOCK_ALLOC_ANYWHERE);
616 radix_init_pgtable();
617 /* Switch to the guard PID before turning on MMU */
618 radix__switch_mmu_context(NULL, &init_mm);
619 if (cpu_has_feature(CPU_FTR_HVMODE))
623 void radix__early_init_mmu_secondary(void)
627 * update partition table control register and UPRT
629 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
630 lpcr = mfspr(SPRN_LPCR);
631 mtspr(SPRN_LPCR, lpcr | LPCR_UPRT | LPCR_HR);
634 __pa(partition_tb) | (PATB_SIZE_SHIFT - 12));
639 radix__switch_mmu_context(NULL, &init_mm);
640 if (cpu_has_feature(CPU_FTR_HVMODE))
644 void radix__mmu_cleanup_all(void)
648 if (!firmware_has_feature(FW_FEATURE_LPAR)) {
649 lpcr = mfspr(SPRN_LPCR);
650 mtspr(SPRN_LPCR, lpcr & ~LPCR_UPRT);
652 powernv_set_nmmu_ptcr(0);
653 radix__flush_tlb_all();
657 void radix__setup_initial_memory_limit(phys_addr_t first_memblock_base,
658 phys_addr_t first_memblock_size)
660 /* We don't currently support the first MEMBLOCK not mapping 0
661 * physical on those processors
663 BUG_ON(first_memblock_base != 0);
666 * Radix mode is not limited by RMA / VRMA addressing.
668 ppc64_rma_size = ULONG_MAX;
671 #ifdef CONFIG_MEMORY_HOTPLUG
672 static void free_pte_table(pte_t *pte_start, pmd_t *pmd)
677 for (i = 0; i < PTRS_PER_PTE; i++) {
683 pte_free_kernel(&init_mm, pte_start);
687 static void free_pmd_table(pmd_t *pmd_start, pud_t *pud)
692 for (i = 0; i < PTRS_PER_PMD; i++) {
698 pmd_free(&init_mm, pmd_start);
702 struct change_mapping_params {
706 unsigned long aligned_start;
707 unsigned long aligned_end;
710 static int __meminit stop_machine_change_mapping(void *data)
712 struct change_mapping_params *params =
713 (struct change_mapping_params *)data;
718 spin_unlock(&init_mm.page_table_lock);
719 pte_clear(&init_mm, params->aligned_start, params->pte);
720 create_physical_mapping(__pa(params->aligned_start), __pa(params->start), -1);
721 create_physical_mapping(__pa(params->end), __pa(params->aligned_end), -1);
722 spin_lock(&init_mm.page_table_lock);
726 static void remove_pte_table(pte_t *pte_start, unsigned long addr,
732 pte = pte_start + pte_index(addr);
733 for (; addr < end; addr = next, pte++) {
734 next = (addr + PAGE_SIZE) & PAGE_MASK;
738 if (!pte_present(*pte))
741 if (!PAGE_ALIGNED(addr) || !PAGE_ALIGNED(next)) {
743 * The vmemmap_free() and remove_section_mapping()
744 * codepaths call us with aligned addresses.
746 WARN_ONCE(1, "%s: unaligned range\n", __func__);
750 pte_clear(&init_mm, addr, pte);
755 * clear the pte and potentially split the mapping helper
757 static void __meminit split_kernel_mapping(unsigned long addr, unsigned long end,
758 unsigned long size, pte_t *pte)
760 unsigned long mask = ~(size - 1);
761 unsigned long aligned_start = addr & mask;
762 unsigned long aligned_end = addr + size;
763 struct change_mapping_params params;
764 bool split_region = false;
766 if ((end - addr) < size) {
768 * We're going to clear the PTE, but not flushed
769 * the mapping, time to remap and flush. The
770 * effects if visible outside the processor or
771 * if we are running in code close to the
772 * mapping we cleared, we are in trouble.
774 if (overlaps_kernel_text(aligned_start, addr) ||
775 overlaps_kernel_text(end, aligned_end)) {
777 * Hack, just return, don't pte_clear
779 WARN_ONCE(1, "Linear mapping %lx->%lx overlaps kernel "
780 "text, not splitting\n", addr, end);
790 params.aligned_start = addr & ~(size - 1);
791 params.aligned_end = min_t(unsigned long, aligned_end,
792 (unsigned long)__va(memblock_end_of_DRAM()));
793 stop_machine(stop_machine_change_mapping, ¶ms, NULL);
797 pte_clear(&init_mm, addr, pte);
800 static void remove_pmd_table(pmd_t *pmd_start, unsigned long addr,
807 pmd = pmd_start + pmd_index(addr);
808 for (; addr < end; addr = next, pmd++) {
809 next = pmd_addr_end(addr, end);
811 if (!pmd_present(*pmd))
814 if (pmd_huge(*pmd)) {
815 split_kernel_mapping(addr, end, PMD_SIZE, (pte_t *)pmd);
819 pte_base = (pte_t *)pmd_page_vaddr(*pmd);
820 remove_pte_table(pte_base, addr, next);
821 free_pte_table(pte_base, pmd);
825 static void remove_pud_table(pud_t *pud_start, unsigned long addr,
832 pud = pud_start + pud_index(addr);
833 for (; addr < end; addr = next, pud++) {
834 next = pud_addr_end(addr, end);
836 if (!pud_present(*pud))
839 if (pud_huge(*pud)) {
840 split_kernel_mapping(addr, end, PUD_SIZE, (pte_t *)pud);
844 pmd_base = (pmd_t *)pud_page_vaddr(*pud);
845 remove_pmd_table(pmd_base, addr, next);
846 free_pmd_table(pmd_base, pud);
850 static void __meminit remove_pagetable(unsigned long start, unsigned long end)
852 unsigned long addr, next;
856 spin_lock(&init_mm.page_table_lock);
858 for (addr = start; addr < end; addr = next) {
859 next = pgd_addr_end(addr, end);
861 pgd = pgd_offset_k(addr);
862 if (!pgd_present(*pgd))
865 if (pgd_huge(*pgd)) {
866 split_kernel_mapping(addr, end, PGDIR_SIZE, (pte_t *)pgd);
870 pud_base = (pud_t *)pgd_page_vaddr(*pgd);
871 remove_pud_table(pud_base, addr, next);
874 spin_unlock(&init_mm.page_table_lock);
875 radix__flush_tlb_kernel_range(start, end);
878 int __meminit radix__create_section_mapping(unsigned long start, unsigned long end, int nid)
880 return create_physical_mapping(start, end, nid);
883 int __meminit radix__remove_section_mapping(unsigned long start, unsigned long end)
885 remove_pagetable(start, end);
888 #endif /* CONFIG_MEMORY_HOTPLUG */
890 #ifdef CONFIG_SPARSEMEM_VMEMMAP
891 static int __map_kernel_page_nid(unsigned long ea, unsigned long pa,
892 pgprot_t flags, unsigned int map_page_size,
895 return __map_kernel_page(ea, pa, flags, map_page_size, nid, 0, 0);
898 int __meminit radix__vmemmap_create_mapping(unsigned long start,
899 unsigned long page_size,
902 /* Create a PTE encoding */
903 unsigned long flags = _PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_KERNEL_RW;
904 int nid = early_pfn_to_nid(phys >> PAGE_SHIFT);
907 ret = __map_kernel_page_nid(start, phys, __pgprot(flags), page_size, nid);
913 #ifdef CONFIG_MEMORY_HOTPLUG
914 void __meminit radix__vmemmap_remove_mapping(unsigned long start, unsigned long page_size)
916 remove_pagetable(start, start + page_size);
921 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
923 unsigned long radix__pmd_hugepage_update(struct mm_struct *mm, unsigned long addr,
924 pmd_t *pmdp, unsigned long clr,
929 #ifdef CONFIG_DEBUG_VM
930 WARN_ON(!radix__pmd_trans_huge(*pmdp) && !pmd_devmap(*pmdp));
931 assert_spin_locked(pmd_lockptr(mm, pmdp));
934 old = radix__pte_update(mm, addr, (pte_t *)pmdp, clr, set, 1);
935 trace_hugepage_update(addr, old, clr, set);
940 pmd_t radix__pmdp_collapse_flush(struct vm_area_struct *vma, unsigned long address,
946 VM_BUG_ON(address & ~HPAGE_PMD_MASK);
947 VM_BUG_ON(radix__pmd_trans_huge(*pmdp));
948 VM_BUG_ON(pmd_devmap(*pmdp));
950 * khugepaged calls this for normal pmd
955 /*FIXME!! Verify whether we need this kick below */
956 serialize_against_pte_lookup(vma->vm_mm);
958 radix__flush_tlb_collapsed_pmd(vma->vm_mm, address);
964 * For us pgtable_t is pte_t *. Inorder to save the deposisted
965 * page table, we consider the allocated page table as a list
966 * head. On withdraw we need to make sure we zero out the used
967 * list_head memory area.
969 void radix__pgtable_trans_huge_deposit(struct mm_struct *mm, pmd_t *pmdp,
972 struct list_head *lh = (struct list_head *) pgtable;
974 assert_spin_locked(pmd_lockptr(mm, pmdp));
977 if (!pmd_huge_pte(mm, pmdp))
980 list_add(lh, (struct list_head *) pmd_huge_pte(mm, pmdp));
981 pmd_huge_pte(mm, pmdp) = pgtable;
984 pgtable_t radix__pgtable_trans_huge_withdraw(struct mm_struct *mm, pmd_t *pmdp)
988 struct list_head *lh;
990 assert_spin_locked(pmd_lockptr(mm, pmdp));
993 pgtable = pmd_huge_pte(mm, pmdp);
994 lh = (struct list_head *) pgtable;
996 pmd_huge_pte(mm, pmdp) = NULL;
998 pmd_huge_pte(mm, pmdp) = (pgtable_t) lh->next;
1001 ptep = (pte_t *) pgtable;
1009 pmd_t radix__pmdp_huge_get_and_clear(struct mm_struct *mm,
1010 unsigned long addr, pmd_t *pmdp)
1015 old = radix__pmd_hugepage_update(mm, addr, pmdp, ~0UL, 0);
1016 old_pmd = __pmd(old);
1018 * Serialize against find_current_mm_pte which does lock-less
1019 * lookup in page tables with local interrupts disabled. For huge pages
1020 * it casts pmd_t to pte_t. Since format of pte_t is different from
1021 * pmd_t we want to prevent transit from pmd pointing to page table
1022 * to pmd pointing to huge page (and back) while interrupts are disabled.
1023 * We clear pmd to possibly replace it with page table pointer in
1024 * different code paths. So make sure we wait for the parallel
1025 * find_current_mm_pte to finish.
1027 serialize_against_pte_lookup(mm);
1031 int radix__has_transparent_hugepage(void)
1033 /* For radix 2M at PMD level means thp */
1034 if (mmu_psize_defs[MMU_PAGE_2M].shift == PMD_SHIFT)
1038 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
1040 void radix__ptep_set_access_flags(struct vm_area_struct *vma, pte_t *ptep,
1041 pte_t entry, unsigned long address, int psize)
1043 struct mm_struct *mm = vma->vm_mm;
1044 unsigned long set = pte_val(entry) & (_PAGE_DIRTY | _PAGE_ACCESSED |
1045 _PAGE_RW | _PAGE_EXEC);
1047 unsigned long change = pte_val(entry) ^ pte_val(*ptep);
1049 * To avoid NMMU hang while relaxing access, we need mark
1050 * the pte invalid in between.
1052 if ((change & _PAGE_RW) && atomic_read(&mm->context.copros) > 0) {
1053 unsigned long old_pte, new_pte;
1055 old_pte = __radix_pte_update(ptep, _PAGE_PRESENT, _PAGE_INVALID);
1059 new_pte = old_pte | set;
1060 radix__flush_tlb_page_psize(mm, address, psize);
1061 __radix_pte_update(ptep, _PAGE_INVALID, new_pte);
1063 __radix_pte_update(ptep, 0, set);
1065 * Book3S does not require a TLB flush when relaxing access
1066 * restrictions when the address space is not attached to a
1067 * NMMU, because the core MMU will reload the pte after taking
1068 * an access fault, which is defined by the architectue.
1071 /* See ptesync comment in radix__set_pte_at */