1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * native hashtable management.
5 * SMP scalability work:
6 * Copyright (C) 2001 Anton Blanchard <anton@au.ibm.com>, IBM
11 #include <linux/spinlock.h>
12 #include <linux/bitops.h>
14 #include <linux/processor.h>
15 #include <linux/threads.h>
16 #include <linux/smp.h>
17 #include <linux/pgtable.h>
19 #include <asm/machdep.h>
21 #include <asm/mmu_context.h>
22 #include <asm/trace.h>
24 #include <asm/cputable.h>
26 #include <asm/kexec.h>
27 #include <asm/ppc-opcode.h>
28 #include <asm/feature-fixups.h>
30 #include <misc/cxl-base.h>
33 #define DBG_LOW(fmt...) udbg_printf(fmt)
35 #define DBG_LOW(fmt...)
39 #define HPTE_LOCK_BIT 3
41 #define HPTE_LOCK_BIT (56+3)
44 static DEFINE_RAW_SPINLOCK(native_tlbie_lock);
46 static inline unsigned long ___tlbie(unsigned long vpn, int psize,
47 int apsize, int ssize)
54 * We need 14 to 65 bits of va for a tlibe of 4K page
55 * With vpn we ignore the lower VPN_SHIFT bits already.
56 * And top two bits are already ignored because we can
57 * only accomodate 76 bits in a 64 bit vpn with a VPN_SHIFT
60 va = vpn << VPN_SHIFT;
62 * clear top 16 bits of 64bit va, non SLS segment
63 * Older versions of the architecture (2.02 and earler) require the
64 * masking of the top 16 bits.
66 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
67 va &= ~(0xffffULL << 48);
71 /* clear out bits after (52) [0....52.....63] */
72 va &= ~((1ul << (64 - 52)) - 1);
74 sllp = get_sllp_encoding(apsize);
76 asm volatile(ASM_FTR_IFCLR("tlbie %0,0", PPC_TLBIE(%1,%0), %2)
77 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
81 /* We need 14 to 14 + i bits of va */
82 penc = mmu_psize_defs[psize].penc[apsize];
83 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
88 * We don't need all the bits, but rest of the bits
89 * must be ignored by the processor.
90 * vpn cover upto 65 bits of va. (0...65) and we need
93 va |= (vpn & 0xfe); /* AVAL */
95 asm volatile(ASM_FTR_IFCLR("tlbie %0,1", PPC_TLBIE(%1,%0), %2)
96 : : "r" (va), "r"(0), "i" (CPU_FTR_ARCH_206)
103 static inline void fixup_tlbie_vpn(unsigned long vpn, int psize,
104 int apsize, int ssize)
106 if (cpu_has_feature(CPU_FTR_P9_TLBIE_ERAT_BUG)) {
107 /* Radix flush for a hash guest */
109 unsigned long rb,rs,prs,r,ric;
111 rb = PPC_BIT(52); /* IS = 2 */
112 rs = 0; /* lpid = 0 */
113 prs = 0; /* partition scoped */
114 r = 1; /* radix format */
115 ric = 0; /* RIC_FLSUH_TLB */
118 * Need the extra ptesync to make sure we don't
121 asm volatile("ptesync": : :"memory");
122 asm volatile(PPC_TLBIE_5(%0, %4, %3, %2, %1)
123 : : "r"(rb), "i"(r), "i"(prs),
124 "i"(ric), "r"(rs) : "memory");
128 if (cpu_has_feature(CPU_FTR_P9_TLBIE_STQ_BUG)) {
129 /* Need the extra ptesync to ensure we don't reorder tlbie*/
130 asm volatile("ptesync": : :"memory");
131 ___tlbie(vpn, psize, apsize, ssize);
135 static inline void __tlbie(unsigned long vpn, int psize, int apsize, int ssize)
139 rb = ___tlbie(vpn, psize, apsize, ssize);
140 trace_tlbie(0, 0, rb, 0, 0, 0, 0);
143 static inline void __tlbiel(unsigned long vpn, int psize, int apsize, int ssize)
149 /* VPN_SHIFT can be atmost 12 */
150 va = vpn << VPN_SHIFT;
152 * clear top 16 bits of 64 bit va, non SLS segment
153 * Older versions of the architecture (2.02 and earler) require the
154 * masking of the top 16 bits.
156 if (mmu_has_feature(MMU_FTR_TLBIE_CROP_VA))
157 va &= ~(0xffffULL << 48);
161 /* clear out bits after(52) [0....52.....63] */
162 va &= ~((1ul << (64 - 52)) - 1);
164 sllp = get_sllp_encoding(apsize);
166 asm volatile(ASM_FTR_IFSET("tlbiel %0", PPC_TLBIEL_v205(%0, 0), %1)
167 : : "r" (va), "i" (CPU_FTR_ARCH_206)
171 /* We need 14 to 14 + i bits of va */
172 penc = mmu_psize_defs[psize].penc[apsize];
173 va &= ~((1ul << mmu_psize_defs[apsize].shift) - 1);
178 * We don't need all the bits, but rest of the bits
179 * must be ignored by the processor.
180 * vpn cover upto 65 bits of va. (0...65) and we need
185 asm volatile(ASM_FTR_IFSET("tlbiel %0", PPC_TLBIEL_v205(%0, 1), %1)
186 : : "r" (va), "i" (CPU_FTR_ARCH_206)
190 trace_tlbie(0, 1, va, 0, 0, 0, 0);
194 static inline void tlbie(unsigned long vpn, int psize, int apsize,
195 int ssize, int local)
197 unsigned int use_local;
198 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
200 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) && !cxl_ctx_in_use();
203 use_local = mmu_psize_defs[psize].tlbiel;
204 if (lock_tlbie && !use_local)
205 raw_spin_lock(&native_tlbie_lock);
206 asm volatile("ptesync": : :"memory");
208 __tlbiel(vpn, psize, apsize, ssize);
209 ppc_after_tlbiel_barrier();
211 __tlbie(vpn, psize, apsize, ssize);
212 fixup_tlbie_vpn(vpn, psize, apsize, ssize);
213 asm volatile("eieio; tlbsync; ptesync": : :"memory");
215 if (lock_tlbie && !use_local)
216 raw_spin_unlock(&native_tlbie_lock);
219 static inline void native_lock_hpte(struct hash_pte *hptep)
221 unsigned long *word = (unsigned long *)&hptep->v;
224 if (!test_and_set_bit_lock(HPTE_LOCK_BIT, word))
227 while(test_bit(HPTE_LOCK_BIT, word))
233 static inline void native_unlock_hpte(struct hash_pte *hptep)
235 unsigned long *word = (unsigned long *)&hptep->v;
237 clear_bit_unlock(HPTE_LOCK_BIT, word);
240 static long native_hpte_insert(unsigned long hpte_group, unsigned long vpn,
241 unsigned long pa, unsigned long rflags,
242 unsigned long vflags, int psize, int apsize, int ssize)
244 struct hash_pte *hptep = htab_address + hpte_group;
245 unsigned long hpte_v, hpte_r;
248 if (!(vflags & HPTE_V_BOLTED)) {
249 DBG_LOW(" insert(group=%lx, vpn=%016lx, pa=%016lx,"
250 " rflags=%lx, vflags=%lx, psize=%d)\n",
251 hpte_group, vpn, pa, rflags, vflags, psize);
254 for (i = 0; i < HPTES_PER_GROUP; i++) {
255 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID)) {
256 /* retry with lock held */
257 native_lock_hpte(hptep);
258 if (! (be64_to_cpu(hptep->v) & HPTE_V_VALID))
260 native_unlock_hpte(hptep);
266 if (i == HPTES_PER_GROUP)
269 hpte_v = hpte_encode_v(vpn, psize, apsize, ssize) | vflags | HPTE_V_VALID;
270 hpte_r = hpte_encode_r(pa, psize, apsize) | rflags;
272 if (!(vflags & HPTE_V_BOLTED)) {
273 DBG_LOW(" i=%x hpte_v=%016lx, hpte_r=%016lx\n",
277 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
278 hpte_r = hpte_old_to_new_r(hpte_v, hpte_r);
279 hpte_v = hpte_old_to_new_v(hpte_v);
282 hptep->r = cpu_to_be64(hpte_r);
283 /* Guarantee the second dword is visible before the valid bit */
286 * Now set the first dword including the valid bit
287 * NOTE: this also unlocks the hpte
289 hptep->v = cpu_to_be64(hpte_v);
291 __asm__ __volatile__ ("ptesync" : : : "memory");
293 return i | (!!(vflags & HPTE_V_SECONDARY) << 3);
296 static long native_hpte_remove(unsigned long hpte_group)
298 struct hash_pte *hptep;
301 unsigned long hpte_v;
303 DBG_LOW(" remove(group=%lx)\n", hpte_group);
305 /* pick a random entry to start at */
306 slot_offset = mftb() & 0x7;
308 for (i = 0; i < HPTES_PER_GROUP; i++) {
309 hptep = htab_address + hpte_group + slot_offset;
310 hpte_v = be64_to_cpu(hptep->v);
312 if ((hpte_v & HPTE_V_VALID) && !(hpte_v & HPTE_V_BOLTED)) {
313 /* retry with lock held */
314 native_lock_hpte(hptep);
315 hpte_v = be64_to_cpu(hptep->v);
316 if ((hpte_v & HPTE_V_VALID)
317 && !(hpte_v & HPTE_V_BOLTED))
319 native_unlock_hpte(hptep);
326 if (i == HPTES_PER_GROUP)
329 /* Invalidate the hpte. NOTE: this also unlocks it */
335 static long native_hpte_updatepp(unsigned long slot, unsigned long newpp,
336 unsigned long vpn, int bpsize,
337 int apsize, int ssize, unsigned long flags)
339 struct hash_pte *hptep = htab_address + slot;
340 unsigned long hpte_v, want_v;
341 int ret = 0, local = 0;
343 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
345 DBG_LOW(" update(vpn=%016lx, avpnv=%016lx, group=%lx, newpp=%lx)",
346 vpn, want_v & HPTE_V_AVPN, slot, newpp);
348 hpte_v = hpte_get_old_v(hptep);
350 * We need to invalidate the TLB always because hpte_remove doesn't do
351 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
352 * random entry from it. When we do that we don't invalidate the TLB
353 * (hpte_remove) because we assume the old translation is still
354 * technically "valid".
356 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID)) {
357 DBG_LOW(" -> miss\n");
360 native_lock_hpte(hptep);
361 /* recheck with locks held */
362 hpte_v = hpte_get_old_v(hptep);
363 if (unlikely(!HPTE_V_COMPARE(hpte_v, want_v) ||
364 !(hpte_v & HPTE_V_VALID))) {
367 DBG_LOW(" -> hit\n");
368 /* Update the HPTE */
369 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
370 ~(HPTE_R_PPP | HPTE_R_N)) |
371 (newpp & (HPTE_R_PPP | HPTE_R_N |
374 native_unlock_hpte(hptep);
377 if (flags & HPTE_LOCAL_UPDATE)
380 * Ensure it is out of the tlb too if it is not a nohpte fault
382 if (!(flags & HPTE_NOHPTE_UPDATE))
383 tlbie(vpn, bpsize, apsize, ssize, local);
388 static long __native_hpte_find(unsigned long want_v, unsigned long slot)
390 struct hash_pte *hptep;
391 unsigned long hpte_v;
394 for (i = 0; i < HPTES_PER_GROUP; i++) {
396 hptep = htab_address + slot;
397 hpte_v = hpte_get_old_v(hptep);
398 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID))
407 static long native_hpte_find(unsigned long vpn, int psize, int ssize)
409 unsigned long hpte_group;
410 unsigned long want_v;
414 hash = hpt_hash(vpn, mmu_psize_defs[psize].shift, ssize);
415 want_v = hpte_encode_avpn(vpn, psize, ssize);
418 * We try to keep bolted entries always in primary hash
419 * But in some case we can find them in secondary too.
421 hpte_group = (hash & htab_hash_mask) * HPTES_PER_GROUP;
422 slot = __native_hpte_find(want_v, hpte_group);
424 /* Try in secondary */
425 hpte_group = (~hash & htab_hash_mask) * HPTES_PER_GROUP;
426 slot = __native_hpte_find(want_v, hpte_group);
435 * Update the page protection bits. Intended to be used to create
436 * guard pages for kernel data structures on pages which are bolted
437 * in the HPT. Assumes pages being operated on will not be stolen.
439 * No need to lock here because we should be the only user.
441 static void native_hpte_updateboltedpp(unsigned long newpp, unsigned long ea,
442 int psize, int ssize)
447 struct hash_pte *hptep;
449 vsid = get_kernel_vsid(ea, ssize);
450 vpn = hpt_vpn(ea, vsid, ssize);
452 slot = native_hpte_find(vpn, psize, ssize);
454 panic("could not find page to bolt\n");
455 hptep = htab_address + slot;
457 /* Update the HPTE */
458 hptep->r = cpu_to_be64((be64_to_cpu(hptep->r) &
459 ~(HPTE_R_PPP | HPTE_R_N)) |
460 (newpp & (HPTE_R_PPP | HPTE_R_N)));
462 * Ensure it is out of the tlb too. Bolted entries base and
463 * actual page size will be same.
465 tlbie(vpn, psize, psize, ssize, 0);
469 * Remove a bolted kernel entry. Memory hotplug uses this.
471 * No need to lock here because we should be the only user.
473 static int native_hpte_removebolted(unsigned long ea, int psize, int ssize)
478 struct hash_pte *hptep;
480 vsid = get_kernel_vsid(ea, ssize);
481 vpn = hpt_vpn(ea, vsid, ssize);
483 slot = native_hpte_find(vpn, psize, ssize);
487 hptep = htab_address + slot;
489 VM_WARN_ON(!(be64_to_cpu(hptep->v) & HPTE_V_BOLTED));
491 /* Invalidate the hpte */
494 /* Invalidate the TLB */
495 tlbie(vpn, psize, psize, ssize, 0);
500 static void native_hpte_invalidate(unsigned long slot, unsigned long vpn,
501 int bpsize, int apsize, int ssize, int local)
503 struct hash_pte *hptep = htab_address + slot;
504 unsigned long hpte_v;
505 unsigned long want_v;
508 local_irq_save(flags);
510 DBG_LOW(" invalidate(vpn=%016lx, hash: %lx)\n", vpn, slot);
512 want_v = hpte_encode_avpn(vpn, bpsize, ssize);
513 hpte_v = hpte_get_old_v(hptep);
515 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) {
516 native_lock_hpte(hptep);
517 /* recheck with locks held */
518 hpte_v = hpte_get_old_v(hptep);
520 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID))
521 /* Invalidate the hpte. NOTE: this also unlocks it */
524 native_unlock_hpte(hptep);
527 * We need to invalidate the TLB always because hpte_remove doesn't do
528 * a tlb invalidate. If a hash bucket gets full, we "evict" a more/less
529 * random entry from it. When we do that we don't invalidate the TLB
530 * (hpte_remove) because we assume the old translation is still
531 * technically "valid".
533 tlbie(vpn, bpsize, apsize, ssize, local);
535 local_irq_restore(flags);
538 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
539 static void native_hugepage_invalidate(unsigned long vsid,
541 unsigned char *hpte_slot_array,
542 int psize, int ssize, int local)
545 struct hash_pte *hptep;
546 int actual_psize = MMU_PAGE_16M;
547 unsigned int max_hpte_count, valid;
548 unsigned long flags, s_addr = addr;
549 unsigned long hpte_v, want_v, shift;
550 unsigned long hidx, vpn = 0, hash, slot;
552 shift = mmu_psize_defs[psize].shift;
553 max_hpte_count = 1U << (PMD_SHIFT - shift);
555 local_irq_save(flags);
556 for (i = 0; i < max_hpte_count; i++) {
557 valid = hpte_valid(hpte_slot_array, i);
560 hidx = hpte_hash_index(hpte_slot_array, i);
563 addr = s_addr + (i * (1ul << shift));
564 vpn = hpt_vpn(addr, vsid, ssize);
565 hash = hpt_hash(vpn, shift, ssize);
566 if (hidx & _PTEIDX_SECONDARY)
569 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
570 slot += hidx & _PTEIDX_GROUP_IX;
572 hptep = htab_address + slot;
573 want_v = hpte_encode_avpn(vpn, psize, ssize);
574 hpte_v = hpte_get_old_v(hptep);
576 /* Even if we miss, we need to invalidate the TLB */
577 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) {
578 /* recheck with locks held */
579 native_lock_hpte(hptep);
580 hpte_v = hpte_get_old_v(hptep);
582 if (HPTE_V_COMPARE(hpte_v, want_v) && (hpte_v & HPTE_V_VALID)) {
584 * Invalidate the hpte. NOTE: this also unlocks it
589 native_unlock_hpte(hptep);
592 * We need to do tlb invalidate for all the address, tlbie
593 * instruction compares entry_VA in tlb with the VA specified
596 tlbie(vpn, psize, actual_psize, ssize, local);
598 local_irq_restore(flags);
601 static void native_hugepage_invalidate(unsigned long vsid,
603 unsigned char *hpte_slot_array,
604 int psize, int ssize, int local)
606 WARN(1, "%s called without THP support\n", __func__);
610 static void hpte_decode(struct hash_pte *hpte, unsigned long slot,
611 int *psize, int *apsize, int *ssize, unsigned long *vpn)
613 unsigned long avpn, pteg, vpi;
614 unsigned long hpte_v = be64_to_cpu(hpte->v);
615 unsigned long hpte_r = be64_to_cpu(hpte->r);
616 unsigned long vsid, seg_off;
617 int size, a_size, shift;
618 /* Look at the 8 bit LP value */
619 unsigned int lp = (hpte_r >> LP_SHIFT) & ((1 << LP_BITS) - 1);
621 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
622 hpte_v = hpte_new_to_old_v(hpte_v, hpte_r);
623 hpte_r = hpte_new_to_old_r(hpte_r);
625 if (!(hpte_v & HPTE_V_LARGE)) {
627 a_size = MMU_PAGE_4K;
629 size = hpte_page_sizes[lp] & 0xf;
630 a_size = hpte_page_sizes[lp] >> 4;
632 /* This works for all page sizes, and for 256M and 1T segments */
633 *ssize = hpte_v >> HPTE_V_SSIZE_SHIFT;
634 shift = mmu_psize_defs[size].shift;
636 avpn = (HPTE_V_AVPN_VAL(hpte_v) & ~mmu_psize_defs[size].avpnm);
637 pteg = slot / HPTES_PER_GROUP;
638 if (hpte_v & HPTE_V_SECONDARY)
642 case MMU_SEGSIZE_256M:
643 /* We only have 28 - 23 bits of seg_off in avpn */
644 seg_off = (avpn & 0x1f) << 23;
646 /* We can find more bits from the pteg value */
648 vpi = (vsid ^ pteg) & htab_hash_mask;
649 seg_off |= vpi << shift;
651 *vpn = vsid << (SID_SHIFT - VPN_SHIFT) | seg_off >> VPN_SHIFT;
654 /* We only have 40 - 23 bits of seg_off in avpn */
655 seg_off = (avpn & 0x1ffff) << 23;
658 vpi = (vsid ^ (vsid << 25) ^ pteg) & htab_hash_mask;
659 seg_off |= vpi << shift;
661 *vpn = vsid << (SID_SHIFT_1T - VPN_SHIFT) | seg_off >> VPN_SHIFT;
671 * clear all mappings on kexec. All cpus are in real mode (or they will
672 * be when they isi), and we are the only one left. We rely on our kernel
673 * mapping being 0xC0's and the hardware ignoring those two real bits.
675 * This must be called with interrupts disabled.
677 * Taking the native_tlbie_lock is unsafe here due to the possibility of
678 * lockdep being on. On pre POWER5 hardware, not taking the lock could
679 * cause deadlock. POWER5 and newer not taking the lock is fine. This only
680 * gets called during boot before secondary CPUs have come up and during
681 * crashdump and all bets are off anyway.
683 * TODO: add batching support when enabled. remember, no dynamic memory here,
684 * although there is the control page available...
686 static notrace void native_hpte_clear(void)
688 unsigned long vpn = 0;
689 unsigned long slot, slots;
690 struct hash_pte *hptep = htab_address;
691 unsigned long hpte_v;
692 unsigned long pteg_count;
693 int psize, apsize, ssize;
695 pteg_count = htab_hash_mask + 1;
697 slots = pteg_count * HPTES_PER_GROUP;
699 for (slot = 0; slot < slots; slot++, hptep++) {
701 * we could lock the pte here, but we are the only cpu
702 * running, right? and for crash dump, we probably
703 * don't want to wait for a maybe bad cpu.
705 hpte_v = be64_to_cpu(hptep->v);
708 * Call __tlbie() here rather than tlbie() since we can't take the
711 if (hpte_v & HPTE_V_VALID) {
712 hpte_decode(hptep, slot, &psize, &apsize, &ssize, &vpn);
714 ___tlbie(vpn, psize, apsize, ssize);
718 asm volatile("eieio; tlbsync; ptesync":::"memory");
722 * Batched hash table flush, we batch the tlbie's to avoid taking/releasing
723 * the lock all the time
725 static void native_flush_hash_range(unsigned long number, int local)
727 unsigned long vpn = 0;
728 unsigned long hash, index, hidx, shift, slot;
729 struct hash_pte *hptep;
730 unsigned long hpte_v;
731 unsigned long want_v;
734 struct ppc64_tlb_batch *batch = this_cpu_ptr(&ppc64_tlb_batch);
735 unsigned long psize = batch->psize;
736 int ssize = batch->ssize;
738 unsigned int use_local;
740 use_local = local && mmu_has_feature(MMU_FTR_TLBIEL) &&
741 mmu_psize_defs[psize].tlbiel && !cxl_ctx_in_use();
743 local_irq_save(flags);
745 for (i = 0; i < number; i++) {
749 pte_iterate_hashed_subpages(pte, psize, vpn, index, shift) {
750 hash = hpt_hash(vpn, shift, ssize);
751 hidx = __rpte_to_hidx(pte, index);
752 if (hidx & _PTEIDX_SECONDARY)
754 slot = (hash & htab_hash_mask) * HPTES_PER_GROUP;
755 slot += hidx & _PTEIDX_GROUP_IX;
756 hptep = htab_address + slot;
757 want_v = hpte_encode_avpn(vpn, psize, ssize);
758 hpte_v = hpte_get_old_v(hptep);
760 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
762 /* lock and try again */
763 native_lock_hpte(hptep);
764 hpte_v = hpte_get_old_v(hptep);
766 if (!HPTE_V_COMPARE(hpte_v, want_v) || !(hpte_v & HPTE_V_VALID))
767 native_unlock_hpte(hptep);
771 } pte_iterate_hashed_end();
775 asm volatile("ptesync":::"memory");
776 for (i = 0; i < number; i++) {
780 pte_iterate_hashed_subpages(pte, psize,
782 __tlbiel(vpn, psize, psize, ssize);
783 } pte_iterate_hashed_end();
785 ppc_after_tlbiel_barrier();
787 int lock_tlbie = !mmu_has_feature(MMU_FTR_LOCKLESS_TLBIE);
790 raw_spin_lock(&native_tlbie_lock);
792 asm volatile("ptesync":::"memory");
793 for (i = 0; i < number; i++) {
797 pte_iterate_hashed_subpages(pte, psize,
799 __tlbie(vpn, psize, psize, ssize);
800 } pte_iterate_hashed_end();
803 * Just do one more with the last used values.
805 fixup_tlbie_vpn(vpn, psize, psize, ssize);
806 asm volatile("eieio; tlbsync; ptesync":::"memory");
809 raw_spin_unlock(&native_tlbie_lock);
812 local_irq_restore(flags);
815 void __init hpte_init_native(void)
817 mmu_hash_ops.hpte_invalidate = native_hpte_invalidate;
818 mmu_hash_ops.hpte_updatepp = native_hpte_updatepp;
819 mmu_hash_ops.hpte_updateboltedpp = native_hpte_updateboltedpp;
820 mmu_hash_ops.hpte_removebolted = native_hpte_removebolted;
821 mmu_hash_ops.hpte_insert = native_hpte_insert;
822 mmu_hash_ops.hpte_remove = native_hpte_remove;
823 mmu_hash_ops.hpte_clear_all = native_hpte_clear;
824 mmu_hash_ops.flush_hash_range = native_flush_hash_range;
825 mmu_hash_ops.hugepage_invalidate = native_hugepage_invalidate;