1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * arch/powerpc/math-emu/math_efp.c
5 * Copyright (C) 2006-2008, 2010 Freescale Semiconductor, Inc.
7 * Author: Ebony Zhu, <ebony.zhu@freescale.com>
8 * Yu Liu, <yu.liu@freescale.com>
10 * Derived from arch/alpha/math-emu/math.c
11 * arch/powerpc/math-emu/math.c
14 * This file is the exception handler to make E500 SPE instructions
15 * fully comply with IEEE-754 floating point standard.
18 #include <linux/types.h>
19 #include <linux/prctl.h>
20 #include <linux/module.h>
22 #include <linux/uaccess.h>
25 #define FP_EX_BOOKE_E500_SPE
26 #include <asm/sfp-machine.h>
28 #include <math-emu/soft-fp.h>
29 #include <math-emu/single.h>
30 #include <math-emu/double.h>
45 #define EFSCMPGT 0x2cc
46 #define EFSCMPLT 0x2cd
47 #define EFSCMPEQ 0x2ce
54 #define EFSCTUIZ 0x2d8
55 #define EFSCTSIZ 0x2da
60 #define EVFSNABS 0x285
64 #define EVFSCMPGT 0x28c
65 #define EVFSCMPLT 0x28d
66 #define EVFSCMPEQ 0x28e
67 #define EVFSCTUI 0x294
68 #define EVFSCTSI 0x295
69 #define EVFSCTUF 0x296
70 #define EVFSCTSF 0x297
71 #define EVFSCTUIZ 0x298
72 #define EVFSCTSIZ 0x29a
81 #define EFDCTUIDZ 0x2ea
82 #define EFDCTSIDZ 0x2eb
83 #define EFDCMPGT 0x2ec
84 #define EFDCMPLT 0x2ed
85 #define EFDCMPEQ 0x2ee
91 #define EFDCTUIZ 0x2f8
92 #define EFDCTSIZ 0x2fa
100 #define SIGN_BIT_S (1UL << 31)
101 #define SIGN_BIT_D (1ULL << 63)
102 #define FP_EX_MASK (FP_EX_INEXACT | FP_EX_INVALID | FP_EX_DIVZERO | \
103 FP_EX_UNDERFLOW | FP_EX_OVERFLOW)
105 static int have_e500_cpu_a005_erratum;
112 static unsigned long insn_type(unsigned long speinsn)
114 unsigned long ret = NOTYPE;
116 switch (speinsn & 0x7ff) {
117 case EFSABS: ret = XA; break;
118 case EFSADD: ret = AB; break;
119 case EFSCFD: ret = XB; break;
120 case EFSCMPEQ: ret = XCR; break;
121 case EFSCMPGT: ret = XCR; break;
122 case EFSCMPLT: ret = XCR; break;
123 case EFSCTSF: ret = XB; break;
124 case EFSCTSI: ret = XB; break;
125 case EFSCTSIZ: ret = XB; break;
126 case EFSCTUF: ret = XB; break;
127 case EFSCTUI: ret = XB; break;
128 case EFSCTUIZ: ret = XB; break;
129 case EFSDIV: ret = AB; break;
130 case EFSMUL: ret = AB; break;
131 case EFSNABS: ret = XA; break;
132 case EFSNEG: ret = XA; break;
133 case EFSSUB: ret = AB; break;
134 case EFSCFSI: ret = XB; break;
136 case EVFSABS: ret = XA; break;
137 case EVFSADD: ret = AB; break;
138 case EVFSCMPEQ: ret = XCR; break;
139 case EVFSCMPGT: ret = XCR; break;
140 case EVFSCMPLT: ret = XCR; break;
141 case EVFSCTSF: ret = XB; break;
142 case EVFSCTSI: ret = XB; break;
143 case EVFSCTSIZ: ret = XB; break;
144 case EVFSCTUF: ret = XB; break;
145 case EVFSCTUI: ret = XB; break;
146 case EVFSCTUIZ: ret = XB; break;
147 case EVFSDIV: ret = AB; break;
148 case EVFSMUL: ret = AB; break;
149 case EVFSNABS: ret = XA; break;
150 case EVFSNEG: ret = XA; break;
151 case EVFSSUB: ret = AB; break;
153 case EFDABS: ret = XA; break;
154 case EFDADD: ret = AB; break;
155 case EFDCFS: ret = XB; break;
156 case EFDCMPEQ: ret = XCR; break;
157 case EFDCMPGT: ret = XCR; break;
158 case EFDCMPLT: ret = XCR; break;
159 case EFDCTSF: ret = XB; break;
160 case EFDCTSI: ret = XB; break;
161 case EFDCTSIDZ: ret = XB; break;
162 case EFDCTSIZ: ret = XB; break;
163 case EFDCTUF: ret = XB; break;
164 case EFDCTUI: ret = XB; break;
165 case EFDCTUIDZ: ret = XB; break;
166 case EFDCTUIZ: ret = XB; break;
167 case EFDDIV: ret = AB; break;
168 case EFDMUL: ret = AB; break;
169 case EFDNABS: ret = XA; break;
170 case EFDNEG: ret = XA; break;
171 case EFDSUB: ret = AB; break;
177 int do_spe_mathemu(struct pt_regs *regs)
182 unsigned long type, func, fc, fa, fb, src, speinsn;
183 union dw_union vc, va, vb;
185 if (get_user(speinsn, (unsigned int __user *) regs->nip))
187 if ((speinsn >> 26) != EFAPU)
188 return -EINVAL; /* not an spe instruction */
190 type = insn_type(speinsn);
194 func = speinsn & 0x7ff;
195 fc = (speinsn >> 21) & 0x1f;
196 fa = (speinsn >> 16) & 0x1f;
197 fb = (speinsn >> 11) & 0x1f;
198 src = (speinsn >> 5) & 0x7;
200 vc.wp[0] = current->thread.evr[fc];
201 vc.wp[1] = regs->gpr[fc];
202 va.wp[0] = current->thread.evr[fa];
203 va.wp[1] = regs->gpr[fa];
204 vb.wp[0] = current->thread.evr[fb];
205 vb.wp[1] = regs->gpr[fb];
207 __FPU_FPSCR = mfspr(SPRN_SPEFSCR);
209 pr_debug("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR);
210 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]);
211 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]);
212 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]);
216 FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
221 FP_UNPACK_SP(SA, va.wp + 1);
223 FP_UNPACK_SP(SB, vb.wp + 1);
226 FP_UNPACK_SP(SA, va.wp + 1);
230 pr_debug("SA: %ld %08lx %ld (%ld)\n", SA_s, SA_f, SA_e, SA_c);
231 pr_debug("SB: %ld %08lx %ld (%ld)\n", SB_s, SB_f, SB_e, SB_c);
235 vc.wp[1] = va.wp[1] & ~SIGN_BIT_S;
239 vc.wp[1] = va.wp[1] | SIGN_BIT_S;
243 vc.wp[1] = va.wp[1] ^ SIGN_BIT_S;
247 FP_ADD_S(SR, SA, SB);
251 FP_SUB_S(SR, SA, SB);
255 FP_MUL_S(SR, SA, SB);
259 FP_DIV_S(SR, SA, SB);
276 if (SB_c == FP_CLS_NAN) {
278 FP_SET_EXCEPTION(FP_EX_INVALID);
280 SB_e += (func == EFSCTSF ? 31 : 32);
281 FP_TO_INT_ROUND_S(vc.wp[1], SB, 32,
289 FP_UNPACK_DP(DB, vb.dp);
291 pr_debug("DB: %ld %08lx %08lx %ld (%ld)\n",
292 DB_s, DB_f1, DB_f0, DB_e, DB_c);
294 FP_CONV(S, D, 1, 2, SR, DB);
300 if (SB_c == FP_CLS_NAN) {
302 FP_SET_EXCEPTION(FP_EX_INVALID);
304 FP_TO_INT_ROUND_S(vc.wp[1], SB, 32,
305 ((func & 0x3) != 0));
311 if (SB_c == FP_CLS_NAN) {
313 FP_SET_EXCEPTION(FP_EX_INVALID);
315 FP_TO_INT_S(vc.wp[1], SB, 32,
316 ((func & 0x3) != 0));
326 pr_debug("SR: %ld %08lx %ld (%ld)\n", SR_s, SR_f, SR_e, SR_c);
328 FP_PACK_SP(vc.wp + 1, SR);
332 FP_CMP_S(IR, SA, SB, 3);
333 if (IR == 3 && (FP_ISSIGNAN_S(SA) || FP_ISSIGNAN_S(SB)))
334 FP_SET_EXCEPTION(FP_EX_INVALID);
344 FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
349 FP_UNPACK_DP(DA, va.dp);
351 FP_UNPACK_DP(DB, vb.dp);
354 FP_UNPACK_DP(DA, va.dp);
358 pr_debug("DA: %ld %08lx %08lx %ld (%ld)\n",
359 DA_s, DA_f1, DA_f0, DA_e, DA_c);
360 pr_debug("DB: %ld %08lx %08lx %ld (%ld)\n",
361 DB_s, DB_f1, DB_f0, DB_e, DB_c);
365 vc.dp[0] = va.dp[0] & ~SIGN_BIT_D;
369 vc.dp[0] = va.dp[0] | SIGN_BIT_D;
373 vc.dp[0] = va.dp[0] ^ SIGN_BIT_D;
377 FP_ADD_D(DR, DA, DB);
381 FP_SUB_D(DR, DA, DB);
385 FP_MUL_D(DR, DA, DB);
389 FP_DIV_D(DR, DA, DB);
406 if (DB_c == FP_CLS_NAN) {
408 FP_SET_EXCEPTION(FP_EX_INVALID);
410 DB_e += (func == EFDCTSF ? 31 : 32);
411 FP_TO_INT_ROUND_D(vc.wp[1], DB, 32,
419 FP_UNPACK_SP(SB, vb.wp + 1);
421 pr_debug("SB: %ld %08lx %ld (%ld)\n",
422 SB_s, SB_f, SB_e, SB_c);
424 FP_CONV(D, S, 2, 1, DR, SB);
430 if (DB_c == FP_CLS_NAN) {
432 FP_SET_EXCEPTION(FP_EX_INVALID);
434 FP_TO_INT_D(vc.dp[0], DB, 64,
435 ((func & 0x1) == 0));
441 if (DB_c == FP_CLS_NAN) {
443 FP_SET_EXCEPTION(FP_EX_INVALID);
445 FP_TO_INT_ROUND_D(vc.wp[1], DB, 32,
446 ((func & 0x3) != 0));
452 if (DB_c == FP_CLS_NAN) {
454 FP_SET_EXCEPTION(FP_EX_INVALID);
456 FP_TO_INT_D(vc.wp[1], DB, 32,
457 ((func & 0x3) != 0));
467 pr_debug("DR: %ld %08lx %08lx %ld (%ld)\n",
468 DR_s, DR_f1, DR_f0, DR_e, DR_c);
470 FP_PACK_DP(vc.dp, DR);
474 FP_CMP_D(IR, DA, DB, 3);
475 if (IR == 3 && (FP_ISSIGNAN_D(DA) || FP_ISSIGNAN_D(DB)))
476 FP_SET_EXCEPTION(FP_EX_INVALID);
487 FP_DECL_S(SA0); FP_DECL_S(SB0); FP_DECL_S(SR0);
488 FP_DECL_S(SA1); FP_DECL_S(SB1); FP_DECL_S(SR1);
494 FP_UNPACK_SP(SA0, va.wp);
495 FP_UNPACK_SP(SA1, va.wp + 1);
497 FP_UNPACK_SP(SB0, vb.wp);
498 FP_UNPACK_SP(SB1, vb.wp + 1);
501 FP_UNPACK_SP(SA0, va.wp);
502 FP_UNPACK_SP(SA1, va.wp + 1);
506 pr_debug("SA0: %ld %08lx %ld (%ld)\n",
507 SA0_s, SA0_f, SA0_e, SA0_c);
508 pr_debug("SA1: %ld %08lx %ld (%ld)\n",
509 SA1_s, SA1_f, SA1_e, SA1_c);
510 pr_debug("SB0: %ld %08lx %ld (%ld)\n",
511 SB0_s, SB0_f, SB0_e, SB0_c);
512 pr_debug("SB1: %ld %08lx %ld (%ld)\n",
513 SB1_s, SB1_f, SB1_e, SB1_c);
517 vc.wp[0] = va.wp[0] & ~SIGN_BIT_S;
518 vc.wp[1] = va.wp[1] & ~SIGN_BIT_S;
522 vc.wp[0] = va.wp[0] | SIGN_BIT_S;
523 vc.wp[1] = va.wp[1] | SIGN_BIT_S;
527 vc.wp[0] = va.wp[0] ^ SIGN_BIT_S;
528 vc.wp[1] = va.wp[1] ^ SIGN_BIT_S;
532 FP_ADD_S(SR0, SA0, SB0);
533 FP_ADD_S(SR1, SA1, SB1);
537 FP_SUB_S(SR0, SA0, SB0);
538 FP_SUB_S(SR1, SA1, SB1);
542 FP_MUL_S(SR0, SA0, SB0);
543 FP_MUL_S(SR1, SA1, SB1);
547 FP_DIV_S(SR0, SA0, SB0);
548 FP_DIV_S(SR1, SA1, SB1);
565 if (SB0_c == FP_CLS_NAN) {
567 FP_SET_EXCEPTION(FP_EX_INVALID);
569 SB0_e += (func == EVFSCTSF ? 31 : 32);
570 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32,
573 if (SB1_c == FP_CLS_NAN) {
575 FP_SET_EXCEPTION(FP_EX_INVALID);
577 SB1_e += (func == EVFSCTSF ? 31 : 32);
578 FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32,
585 if (SB0_c == FP_CLS_NAN) {
587 FP_SET_EXCEPTION(FP_EX_INVALID);
589 FP_TO_INT_ROUND_S(vc.wp[0], SB0, 32,
590 ((func & 0x3) != 0));
592 if (SB1_c == FP_CLS_NAN) {
594 FP_SET_EXCEPTION(FP_EX_INVALID);
596 FP_TO_INT_ROUND_S(vc.wp[1], SB1, 32,
597 ((func & 0x3) != 0));
603 if (SB0_c == FP_CLS_NAN) {
605 FP_SET_EXCEPTION(FP_EX_INVALID);
607 FP_TO_INT_S(vc.wp[0], SB0, 32,
608 ((func & 0x3) != 0));
610 if (SB1_c == FP_CLS_NAN) {
612 FP_SET_EXCEPTION(FP_EX_INVALID);
614 FP_TO_INT_S(vc.wp[1], SB1, 32,
615 ((func & 0x3) != 0));
625 pr_debug("SR0: %ld %08lx %ld (%ld)\n",
626 SR0_s, SR0_f, SR0_e, SR0_c);
627 pr_debug("SR1: %ld %08lx %ld (%ld)\n",
628 SR1_s, SR1_f, SR1_e, SR1_c);
630 FP_PACK_SP(vc.wp, SR0);
631 FP_PACK_SP(vc.wp + 1, SR1);
638 FP_CMP_S(IR0, SA0, SB0, 3);
639 FP_CMP_S(IR1, SA1, SB1, 3);
640 if (IR0 == 3 && (FP_ISSIGNAN_S(SA0) || FP_ISSIGNAN_S(SB0)))
641 FP_SET_EXCEPTION(FP_EX_INVALID);
642 if (IR1 == 3 && (FP_ISSIGNAN_S(SA1) || FP_ISSIGNAN_S(SB1)))
643 FP_SET_EXCEPTION(FP_EX_INVALID);
644 ch = (IR0 == cmp) ? 1 : 0;
645 cl = (IR1 == cmp) ? 1 : 0;
646 IR = (ch << 3) | (cl << 2) | ((ch | cl) << 1) |
656 regs->ccr &= ~(15 << ((7 - ((speinsn >> 23) & 0x7)) << 2));
657 regs->ccr |= (IR << ((7 - ((speinsn >> 23) & 0x7)) << 2));
661 * If the "invalid" exception sticky bit was set by the
662 * processor for non-finite input, but was not set before the
663 * instruction being emulated, clear it. Likewise for the
664 * "underflow" bit, which may have been set by the processor
665 * for exact underflow, not just inexact underflow when the
666 * flag should be set for IEEE 754 semantics. Other sticky
667 * exceptions will only be set by the processor when they are
668 * correct according to IEEE 754 semantics, and we must not
669 * clear sticky bits that were already set before the emulated
670 * instruction as they represent the user-visible sticky
671 * exception status. "inexact" traps to kernel are not
672 * required for IEEE semantics and are not enabled by default,
673 * so the "inexact" sticky bit may have been set by a previous
674 * instruction without the kernel being aware of it.
677 &= ~(FP_EX_INVALID | FP_EX_UNDERFLOW) | current->thread.spefscr_last;
678 __FPU_FPSCR |= (FP_CUR_EXCEPTIONS & FP_EX_MASK);
679 mtspr(SPRN_SPEFSCR, __FPU_FPSCR);
680 current->thread.spefscr_last = __FPU_FPSCR;
682 current->thread.evr[fc] = vc.wp[0];
683 regs->gpr[fc] = vc.wp[1];
685 pr_debug("ccr = %08lx\n", regs->ccr);
686 pr_debug("cur exceptions = %08x spefscr = %08lx\n",
687 FP_CUR_EXCEPTIONS, __FPU_FPSCR);
688 pr_debug("vc: %08x %08x\n", vc.wp[0], vc.wp[1]);
689 pr_debug("va: %08x %08x\n", va.wp[0], va.wp[1]);
690 pr_debug("vb: %08x %08x\n", vb.wp[0], vb.wp[1]);
692 if (current->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) {
693 if ((FP_CUR_EXCEPTIONS & FP_EX_DIVZERO)
694 && (current->thread.fpexc_mode & PR_FP_EXC_DIV))
696 if ((FP_CUR_EXCEPTIONS & FP_EX_OVERFLOW)
697 && (current->thread.fpexc_mode & PR_FP_EXC_OVF))
699 if ((FP_CUR_EXCEPTIONS & FP_EX_UNDERFLOW)
700 && (current->thread.fpexc_mode & PR_FP_EXC_UND))
702 if ((FP_CUR_EXCEPTIONS & FP_EX_INEXACT)
703 && (current->thread.fpexc_mode & PR_FP_EXC_RES))
705 if ((FP_CUR_EXCEPTIONS & FP_EX_INVALID)
706 && (current->thread.fpexc_mode & PR_FP_EXC_INV))
712 if (have_e500_cpu_a005_erratum) {
713 /* according to e500 cpu a005 erratum, reissue efp inst */
715 pr_debug("re-issue efp inst: %08lx\n", speinsn);
719 printk(KERN_ERR "\nOoops! IEEE-754 compliance handler encountered un-supported instruction.\ninst code: %08lx\n", speinsn);
723 int speround_handler(struct pt_regs *regs)
727 int lo_inexact, hi_inexact;
729 unsigned long speinsn, type, fb, fc, fptype, func;
731 if (get_user(speinsn, (unsigned int __user *) regs->nip))
733 if ((speinsn >> 26) != 4)
734 return -EINVAL; /* not an spe instruction */
736 func = speinsn & 0x7ff;
737 type = insn_type(func);
738 if (type == XCR) return -ENOSYS;
740 __FPU_FPSCR = mfspr(SPRN_SPEFSCR);
741 pr_debug("speinsn:%08lx spefscr:%08lx\n", speinsn, __FPU_FPSCR);
743 fptype = (speinsn >> 5) & 0x7;
745 /* No need to round if the result is exact */
746 lo_inexact = __FPU_FPSCR & (SPEFSCR_FG | SPEFSCR_FX);
747 hi_inexact = __FPU_FPSCR & (SPEFSCR_FGH | SPEFSCR_FXH);
748 if (!(lo_inexact || (hi_inexact && fptype == VCT)))
751 fc = (speinsn >> 21) & 0x1f;
752 s_lo = regs->gpr[fc] & SIGN_BIT_S;
753 s_hi = current->thread.evr[fc] & SIGN_BIT_S;
754 fgpr.wp[0] = current->thread.evr[fc];
755 fgpr.wp[1] = regs->gpr[fc];
757 fb = (speinsn >> 11) & 0x1f;
768 * These instructions always round to zero,
769 * independent of the rounding mode.
787 /* Recover the sign of a zero result if possible. */
789 s_lo = regs->gpr[fb] & SIGN_BIT_S;
795 /* Recover the sign of a zero result if possible. */
797 s_lo = regs->gpr[fb] & SIGN_BIT_S;
799 s_hi = current->thread.evr[fb] & SIGN_BIT_S;
806 /* Recover the sign of a zero result if possible. */
808 s_hi = current->thread.evr[fb] & SIGN_BIT_S;
816 pr_debug("round fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]);
819 /* Since SPE instructions on E500 core can handle round to nearest
820 * and round toward zero with IEEE-754 complied, we just need
821 * to handle round toward +Inf and round toward -Inf by software.
824 if ((FP_ROUNDMODE) == FP_RND_PINF) {
825 if (!s_lo) fgpr.wp[1]++; /* Z > 0, choose Z1 */
826 } else { /* round to -Inf */
829 fgpr.wp[1]++; /* Z < 0, choose Z2 */
831 fgpr.wp[1]--; /* Z < 0, choose Z2 */
837 if (FP_ROUNDMODE == FP_RND_PINF) {
840 fgpr.dp[0]++; /* Z > 0, choose Z1 */
842 fgpr.wp[1]++; /* Z > 0, choose Z1 */
844 } else { /* round to -Inf */
847 fgpr.dp[0]++; /* Z < 0, choose Z2 */
849 fgpr.wp[1]--; /* Z < 0, choose Z2 */
855 if (FP_ROUNDMODE == FP_RND_PINF) {
856 if (lo_inexact && !s_lo)
857 fgpr.wp[1]++; /* Z_low > 0, choose Z1 */
858 if (hi_inexact && !s_hi)
859 fgpr.wp[0]++; /* Z_high word > 0, choose Z1 */
860 } else { /* round to -Inf */
861 if (lo_inexact && s_lo) {
863 fgpr.wp[1]++; /* Z_low < 0, choose Z2 */
865 fgpr.wp[1]--; /* Z_low < 0, choose Z2 */
867 if (hi_inexact && s_hi) {
869 fgpr.wp[0]++; /* Z_high < 0, choose Z2 */
871 fgpr.wp[0]--; /* Z_high < 0, choose Z2 */
880 current->thread.evr[fc] = fgpr.wp[0];
881 regs->gpr[fc] = fgpr.wp[1];
883 pr_debug(" to fgpr: %08x %08x\n", fgpr.wp[0], fgpr.wp[1]);
885 if (current->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
886 return (current->thread.fpexc_mode & PR_FP_EXC_RES) ? 1 : 0;
890 int __init spe_mathemu_init(void)
894 pvr = mfspr(SPRN_PVR);
896 if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
897 (PVR_VER(pvr) == PVR_VER_E500V2)) {
902 * E500 revision below 1.1, 2.3, 3.1, 4.1, 5.1
903 * need cpu a005 errata workaround
908 have_e500_cpu_a005_erratum = 1;
912 have_e500_cpu_a005_erratum = 1;
918 have_e500_cpu_a005_erratum = 1;
928 module_init(spe_mathemu_init);