4 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/kprobes.h>
13 #include <linux/ptrace.h>
14 #include <linux/prefetch.h>
15 #include <asm/sstep.h>
16 #include <asm/processor.h>
17 #include <linux/uaccess.h>
18 #include <asm/cpu_has_feature.h>
19 #include <asm/cputable.h>
21 extern char system_call_common[];
24 /* Bits in SRR1 that are copied from MSR */
25 #define MSR_MASK 0xffffffff87c0ffffUL
27 #define MSR_MASK 0x87c0ffff
31 #define XER_SO 0x80000000U
32 #define XER_OV 0x40000000U
33 #define XER_CA 0x20000000U
37 * Functions in ldstfp.S
39 extern void get_fpr(int rn, double *p);
40 extern void put_fpr(int rn, const double *p);
41 extern void get_vr(int rn, __vector128 *p);
42 extern void put_vr(int rn, __vector128 *p);
43 extern void load_vsrn(int vsr, const void *p);
44 extern void store_vsrn(int vsr, void *p);
45 extern void conv_sp_to_dp(const float *sp, double *dp);
46 extern void conv_dp_to_sp(const double *dp, float *sp);
53 extern int do_lq(unsigned long ea, unsigned long *regs);
54 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
55 extern int do_lqarx(unsigned long ea, unsigned long *regs);
56 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
60 #ifdef __LITTLE_ENDIAN__
69 * Emulate the truncation of 64 bit values in 32-bit mode.
71 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
75 if ((msr & MSR_64BIT) == 0)
82 * Determine whether a conditional branch instruction would branch.
84 static nokprobe_inline int branch_taken(unsigned int instr,
85 const struct pt_regs *regs,
86 struct instruction_op *op)
88 unsigned int bo = (instr >> 21) & 0x1f;
92 /* decrement counter */
94 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
97 if ((bo & 0x10) == 0) {
98 /* check bit from CR */
99 bi = (instr >> 16) & 0x1f;
100 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
106 static nokprobe_inline long address_ok(struct pt_regs *regs,
107 unsigned long ea, int nb)
109 if (!user_mode(regs))
111 if (__access_ok(ea, nb, USER_DS))
113 if (__access_ok(ea, 1, USER_DS))
114 /* Access overlaps the end of the user region */
115 regs->dar = USER_DS.seg;
122 * Calculate effective address for a D-form instruction
124 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
125 const struct pt_regs *regs)
130 ra = (instr >> 16) & 0x1f;
131 ea = (signed short) instr; /* sign-extend */
140 * Calculate effective address for a DS-form instruction
142 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
143 const struct pt_regs *regs)
148 ra = (instr >> 16) & 0x1f;
149 ea = (signed short) (instr & ~3); /* sign-extend */
157 * Calculate effective address for a DQ-form instruction
159 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
160 const struct pt_regs *regs)
165 ra = (instr >> 16) & 0x1f;
166 ea = (signed short) (instr & ~0xf); /* sign-extend */
172 #endif /* __powerpc64 */
175 * Calculate effective address for an X-form instruction
177 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
178 const struct pt_regs *regs)
183 ra = (instr >> 16) & 0x1f;
184 rb = (instr >> 11) & 0x1f;
193 * Return the largest power of 2, not greater than sizeof(unsigned long),
194 * such that x is a multiple of it.
196 static nokprobe_inline unsigned long max_align(unsigned long x)
198 x |= sizeof(unsigned long);
199 return x & -x; /* isolates rightmost bit */
202 static nokprobe_inline unsigned long byterev_2(unsigned long x)
204 return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
207 static nokprobe_inline unsigned long byterev_4(unsigned long x)
209 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
210 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
214 static nokprobe_inline unsigned long byterev_8(unsigned long x)
216 return (byterev_4(x) << 32) | byterev_4(x >> 32);
220 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
224 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
227 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
231 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
234 unsigned long *up = (unsigned long *)ptr;
236 tmp = byterev_8(up[0]);
237 up[0] = byterev_8(up[1]);
247 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
248 unsigned long ea, int nb,
249 struct pt_regs *regs)
256 err = __get_user(x, (unsigned char __user *) ea);
259 err = __get_user(x, (unsigned short __user *) ea);
262 err = __get_user(x, (unsigned int __user *) ea);
266 err = __get_user(x, (unsigned long __user *) ea);
278 * Copy from userspace to a buffer, using the largest possible
279 * aligned accesses, up to sizeof(long).
281 static int nokprobe_inline copy_mem_in(u8 *dest, unsigned long ea, int nb,
282 struct pt_regs *regs)
287 for (; nb > 0; nb -= c) {
293 err = __get_user(*dest, (unsigned char __user *) ea);
296 err = __get_user(*(u16 *)dest,
297 (unsigned short __user *) ea);
300 err = __get_user(*(u32 *)dest,
301 (unsigned int __user *) ea);
305 err = __get_user(*(unsigned long *)dest,
306 (unsigned long __user *) ea);
320 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
321 unsigned long ea, int nb,
322 struct pt_regs *regs)
326 u8 b[sizeof(unsigned long)];
332 i = IS_BE ? sizeof(unsigned long) - nb : 0;
333 err = copy_mem_in(&u.b[i], ea, nb, regs);
340 * Read memory at address ea for nb bytes, return 0 for success
341 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
342 * If nb < sizeof(long), the result is right-justified on BE systems.
344 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
345 struct pt_regs *regs)
347 if (!address_ok(regs, ea, nb))
349 if ((ea & (nb - 1)) == 0)
350 return read_mem_aligned(dest, ea, nb, regs);
351 return read_mem_unaligned(dest, ea, nb, regs);
353 NOKPROBE_SYMBOL(read_mem);
355 static nokprobe_inline int write_mem_aligned(unsigned long val,
356 unsigned long ea, int nb,
357 struct pt_regs *regs)
363 err = __put_user(val, (unsigned char __user *) ea);
366 err = __put_user(val, (unsigned short __user *) ea);
369 err = __put_user(val, (unsigned int __user *) ea);
373 err = __put_user(val, (unsigned long __user *) ea);
383 * Copy from a buffer to userspace, using the largest possible
384 * aligned accesses, up to sizeof(long).
386 static int nokprobe_inline copy_mem_out(u8 *dest, unsigned long ea, int nb,
387 struct pt_regs *regs)
392 for (; nb > 0; nb -= c) {
398 err = __put_user(*dest, (unsigned char __user *) ea);
401 err = __put_user(*(u16 *)dest,
402 (unsigned short __user *) ea);
405 err = __put_user(*(u32 *)dest,
406 (unsigned int __user *) ea);
410 err = __put_user(*(unsigned long *)dest,
411 (unsigned long __user *) ea);
425 static nokprobe_inline int write_mem_unaligned(unsigned long val,
426 unsigned long ea, int nb,
427 struct pt_regs *regs)
431 u8 b[sizeof(unsigned long)];
436 i = IS_BE ? sizeof(unsigned long) - nb : 0;
437 return copy_mem_out(&u.b[i], ea, nb, regs);
441 * Write memory at address ea for nb bytes, return 0 for success
442 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
444 static int write_mem(unsigned long val, unsigned long ea, int nb,
445 struct pt_regs *regs)
447 if (!address_ok(regs, ea, nb))
449 if ((ea & (nb - 1)) == 0)
450 return write_mem_aligned(val, ea, nb, regs);
451 return write_mem_unaligned(val, ea, nb, regs);
453 NOKPROBE_SYMBOL(write_mem);
455 #ifdef CONFIG_PPC_FPU
457 * These access either the real FP register or the image in the
458 * thread_struct, depending on regs->msr & MSR_FP.
460 static int do_fp_load(struct instruction_op *op, unsigned long ea,
461 struct pt_regs *regs, bool cross_endian)
470 u8 b[2 * sizeof(double)];
473 nb = GETSIZE(op->type);
474 if (!address_ok(regs, ea, nb))
477 err = copy_mem_in(u.b, ea, nb, regs);
480 if (unlikely(cross_endian)) {
481 do_byte_reverse(u.b, min(nb, 8));
483 do_byte_reverse(&u.b[8], 8);
487 if (op->type & FPCONV)
488 conv_sp_to_dp(&u.f, &u.d[0]);
489 else if (op->type & SIGNEXT)
494 if (regs->msr & MSR_FP)
495 put_fpr(rn, &u.d[0]);
497 current->thread.TS_FPR(rn) = u.l[0];
501 if (regs->msr & MSR_FP)
502 put_fpr(rn, &u.d[1]);
504 current->thread.TS_FPR(rn) = u.l[1];
509 NOKPROBE_SYMBOL(do_fp_load);
511 static int do_fp_store(struct instruction_op *op, unsigned long ea,
512 struct pt_regs *regs, bool cross_endian)
520 u8 b[2 * sizeof(double)];
523 nb = GETSIZE(op->type);
524 if (!address_ok(regs, ea, nb))
528 if (regs->msr & MSR_FP)
529 get_fpr(rn, &u.d[0]);
531 u.l[0] = current->thread.TS_FPR(rn);
533 if (op->type & FPCONV)
534 conv_dp_to_sp(&u.d[0], &u.f);
540 if (regs->msr & MSR_FP)
541 get_fpr(rn, &u.d[1]);
543 u.l[1] = current->thread.TS_FPR(rn);
546 if (unlikely(cross_endian)) {
547 do_byte_reverse(u.b, min(nb, 8));
549 do_byte_reverse(&u.b[8], 8);
551 return copy_mem_out(u.b, ea, nb, regs);
553 NOKPROBE_SYMBOL(do_fp_store);
556 #ifdef CONFIG_ALTIVEC
557 /* For Altivec/VMX, no need to worry about alignment */
558 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
559 int size, struct pt_regs *regs,
565 u8 b[sizeof(__vector128)];
568 if (!address_ok(regs, ea & ~0xfUL, 16))
570 /* align to multiple of size */
572 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
575 if (unlikely(cross_endian))
576 do_byte_reverse(&u.b[ea & 0xf], size);
578 if (regs->msr & MSR_VEC)
581 current->thread.vr_state.vr[rn] = u.v;
586 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
587 int size, struct pt_regs *regs,
592 u8 b[sizeof(__vector128)];
595 if (!address_ok(regs, ea & ~0xfUL, 16))
597 /* align to multiple of size */
601 if (regs->msr & MSR_VEC)
604 u.v = current->thread.vr_state.vr[rn];
606 if (unlikely(cross_endian))
607 do_byte_reverse(&u.b[ea & 0xf], size);
608 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
610 #endif /* CONFIG_ALTIVEC */
613 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
614 int reg, bool cross_endian)
618 if (!address_ok(regs, ea, 16))
620 /* if aligned, should be atomic */
621 if ((ea & 0xf) == 0) {
622 err = do_lq(ea, ®s->gpr[reg]);
624 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs);
626 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs);
628 if (!err && unlikely(cross_endian))
629 do_byte_reverse(®s->gpr[reg], 16);
633 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
634 int reg, bool cross_endian)
637 unsigned long vals[2];
639 if (!address_ok(regs, ea, 16))
641 vals[0] = regs->gpr[reg];
642 vals[1] = regs->gpr[reg + 1];
643 if (unlikely(cross_endian))
644 do_byte_reverse(vals, 16);
646 /* if aligned, should be atomic */
648 return do_stq(ea, vals[0], vals[1]);
650 err = write_mem(vals[IS_LE], ea, 8, regs);
652 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
655 #endif /* __powerpc64 */
658 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
659 const void *mem, bool rev)
663 const unsigned int *wp;
664 const unsigned short *hp;
665 const unsigned char *bp;
667 size = GETSIZE(op->type);
668 reg->d[0] = reg->d[1] = 0;
670 switch (op->element_size) {
672 /* whole vector; lxv[x] or lxvl[l] */
675 memcpy(reg, mem, size);
676 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
679 do_byte_reverse(reg, 16);
682 /* scalar loads, lxvd2x, lxvdsx */
683 read_size = (size >= 8) ? 8 : size;
684 i = IS_LE ? 8 : 8 - read_size;
685 memcpy(®->b[i], mem, read_size);
687 do_byte_reverse(®->b[i], 8);
689 if (op->type & SIGNEXT) {
690 /* size == 4 is the only case here */
691 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
692 } else if (op->vsx_flags & VSX_FPCONV) {
694 conv_sp_to_dp(®->fp[1 + IS_LE],
700 unsigned long v = *(unsigned long *)(mem + 8);
701 reg->d[IS_BE] = !rev ? v : byterev_8(v);
702 } else if (op->vsx_flags & VSX_SPLAT)
703 reg->d[IS_BE] = reg->d[IS_LE];
709 for (j = 0; j < size / 4; ++j) {
710 i = IS_LE ? 3 - j : j;
711 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
713 if (op->vsx_flags & VSX_SPLAT) {
714 u32 val = reg->w[IS_LE ? 3 : 0];
716 i = IS_LE ? 3 - j : j;
724 for (j = 0; j < size / 2; ++j) {
725 i = IS_LE ? 7 - j : j;
726 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
732 for (j = 0; j < size; ++j) {
733 i = IS_LE ? 15 - j : j;
739 EXPORT_SYMBOL_GPL(emulate_vsx_load);
740 NOKPROBE_SYMBOL(emulate_vsx_load);
742 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
745 int size, write_size;
752 size = GETSIZE(op->type);
754 switch (op->element_size) {
756 /* stxv, stxvx, stxvl, stxvll */
759 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
762 /* reverse 16 bytes */
763 buf.d[0] = byterev_8(reg->d[1]);
764 buf.d[1] = byterev_8(reg->d[0]);
767 memcpy(mem, reg, size);
770 /* scalar stores, stxvd2x */
771 write_size = (size >= 8) ? 8 : size;
772 i = IS_LE ? 8 : 8 - write_size;
773 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
774 buf.d[0] = buf.d[1] = 0;
776 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]);
780 memcpy(mem, ®->b[i], write_size);
782 memcpy(mem + 8, ®->d[IS_BE], 8);
784 do_byte_reverse(mem, write_size);
786 do_byte_reverse(mem + 8, 8);
792 for (j = 0; j < size / 4; ++j) {
793 i = IS_LE ? 3 - j : j;
794 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
800 for (j = 0; j < size / 2; ++j) {
801 i = IS_LE ? 7 - j : j;
802 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
808 for (j = 0; j < size; ++j) {
809 i = IS_LE ? 15 - j : j;
815 EXPORT_SYMBOL_GPL(emulate_vsx_store);
816 NOKPROBE_SYMBOL(emulate_vsx_store);
818 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
819 unsigned long ea, struct pt_regs *regs,
825 int size = GETSIZE(op->type);
827 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
830 emulate_vsx_load(op, &buf, mem, cross_endian);
833 /* FP regs + extensions */
834 if (regs->msr & MSR_FP) {
835 load_vsrn(reg, &buf);
837 current->thread.fp_state.fpr[reg][0] = buf.d[0];
838 current->thread.fp_state.fpr[reg][1] = buf.d[1];
841 if (regs->msr & MSR_VEC)
842 load_vsrn(reg, &buf);
844 current->thread.vr_state.vr[reg - 32] = buf.v;
850 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
851 unsigned long ea, struct pt_regs *regs,
857 int size = GETSIZE(op->type);
859 if (!address_ok(regs, ea, size))
864 /* FP regs + extensions */
865 if (regs->msr & MSR_FP) {
866 store_vsrn(reg, &buf);
868 buf.d[0] = current->thread.fp_state.fpr[reg][0];
869 buf.d[1] = current->thread.fp_state.fpr[reg][1];
872 if (regs->msr & MSR_VEC)
873 store_vsrn(reg, &buf);
875 buf.v = current->thread.vr_state.vr[reg - 32];
878 emulate_vsx_store(op, &buf, mem, cross_endian);
879 return copy_mem_out(mem, ea, size, regs);
881 #endif /* CONFIG_VSX */
883 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
886 unsigned long i, size;
889 size = ppc64_caches.l1d.block_size;
890 if (!(regs->msr & MSR_64BIT))
893 size = L1_CACHE_BYTES;
896 if (!address_ok(regs, ea, size))
898 for (i = 0; i < size; i += sizeof(long)) {
899 err = __put_user(0, (unsigned long __user *) (ea + i));
907 NOKPROBE_SYMBOL(emulate_dcbz);
909 #define __put_user_asmx(x, addr, err, op, cr) \
910 __asm__ __volatile__( \
911 "1: " op " %2,0,%3\n" \
914 ".section .fixup,\"ax\"\n" \
919 : "=r" (err), "=r" (cr) \
920 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
922 #define __get_user_asmx(x, addr, err, op) \
923 __asm__ __volatile__( \
924 "1: "op" %1,0,%2\n" \
926 ".section .fixup,\"ax\"\n" \
931 : "=r" (err), "=r" (x) \
932 : "r" (addr), "i" (-EFAULT), "0" (err))
934 #define __cacheop_user_asmx(addr, err, op) \
935 __asm__ __volatile__( \
938 ".section .fixup,\"ax\"\n" \
944 : "r" (addr), "i" (-EFAULT), "0" (err))
946 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
947 struct instruction_op *op)
952 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
954 if (!(regs->msr & MSR_64BIT))
958 op->ccval |= 0x80000000;
960 op->ccval |= 0x40000000;
962 op->ccval |= 0x20000000;
965 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
966 struct instruction_op *op, int rd,
967 unsigned long val1, unsigned long val2,
968 unsigned long carry_in)
970 unsigned long val = val1 + val2;
974 op->type = COMPUTE + SETREG + SETXER;
978 if (!(regs->msr & MSR_64BIT)) {
979 val = (unsigned int) val;
980 val1 = (unsigned int) val1;
983 op->xerval = regs->xer;
984 if (val < val1 || (carry_in && val == val1))
985 op->xerval |= XER_CA;
987 op->xerval &= ~XER_CA;
990 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
991 struct instruction_op *op,
992 long v1, long v2, int crfld)
994 unsigned int crval, shift;
996 op->type = COMPUTE + SETCC;
997 crval = (regs->xer >> 31) & 1; /* get SO bit */
1004 shift = (7 - crfld) * 4;
1005 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1008 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1009 struct instruction_op *op,
1011 unsigned long v2, int crfld)
1013 unsigned int crval, shift;
1015 op->type = COMPUTE + SETCC;
1016 crval = (regs->xer >> 31) & 1; /* get SO bit */
1023 shift = (7 - crfld) * 4;
1024 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1027 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1028 struct instruction_op *op,
1029 unsigned long v1, unsigned long v2)
1031 unsigned long long out_val, mask;
1035 for (i = 0; i < 8; i++) {
1036 mask = 0xffUL << (i * 8);
1037 if ((v1 & mask) == (v2 & mask))
1044 * The size parameter is used to adjust the equivalent popcnt instruction.
1045 * popcntb = 8, popcntw = 32, popcntd = 64
1047 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1048 struct instruction_op *op,
1049 unsigned long v1, int size)
1051 unsigned long long out = v1;
1053 out -= (out >> 1) & 0x5555555555555555;
1054 out = (0x3333333333333333 & out) + (0x3333333333333333 & (out >> 2));
1055 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0f;
1057 if (size == 8) { /* popcntb */
1063 if (size == 32) { /* popcntw */
1064 op->val = out & 0x0000003f0000003f;
1068 out = (out + (out >> 32)) & 0x7f;
1069 op->val = out; /* popcntd */
1073 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1074 struct instruction_op *op,
1075 unsigned long v1, unsigned long v2)
1077 unsigned char perm, idx;
1081 for (i = 0; i < 8; i++) {
1082 idx = (v1 >> (i * 8)) & 0xff;
1084 if (v2 & PPC_BIT(idx))
1089 #endif /* CONFIG_PPC64 */
1091 * The size parameter adjusts the equivalent prty instruction.
1092 * prtyw = 32, prtyd = 64
1094 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1095 struct instruction_op *op,
1096 unsigned long v, int size)
1098 unsigned long long res = v ^ (v >> 8);
1101 if (size == 32) { /* prtyw */
1102 op->val = res & 0x0000000100000001;
1107 op->val = res & 1; /*prtyd */
1110 static nokprobe_inline int trap_compare(long v1, long v2)
1120 if ((unsigned long)v1 < (unsigned long)v2)
1122 else if ((unsigned long)v1 > (unsigned long)v2)
1128 * Elements of 32-bit rotate and mask instructions.
1130 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
1131 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1132 #ifdef __powerpc64__
1133 #define MASK64_L(mb) (~0UL >> (mb))
1134 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))
1135 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1136 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1138 #define DATA32(x) (x)
1140 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1143 * Decode an instruction, and return information about it in *op
1144 * without changing *regs.
1145 * Integer arithmetic and logical instructions, branches, and barrier
1146 * instructions can be emulated just using the information in *op.
1148 * Return value is 1 if the instruction can be emulated just by
1149 * updating *regs with the information in *op, -1 if we need the
1150 * GPRs but *regs doesn't contain the full register set, or 0
1153 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1156 unsigned int opcode, ra, rb, rd, spr, u;
1157 unsigned long int imm;
1158 unsigned long int val, val2;
1159 unsigned int mb, me, sh;
1164 opcode = instr >> 26;
1168 imm = (signed short)(instr & 0xfffc);
1169 if ((instr & 2) == 0)
1171 op->val = truncate_if_32bit(regs->msr, imm);
1174 if (branch_taken(instr, regs, op))
1175 op->type |= BRTAKEN;
1179 if ((instr & 0xfe2) == 2)
1186 op->type = BRANCH | BRTAKEN;
1187 imm = instr & 0x03fffffc;
1188 if (imm & 0x02000000)
1190 if ((instr & 2) == 0)
1192 op->val = truncate_if_32bit(regs->msr, imm);
1197 switch ((instr >> 1) & 0x3ff) {
1199 op->type = COMPUTE + SETCC;
1200 rd = 7 - ((instr >> 23) & 0x7);
1201 ra = 7 - ((instr >> 18) & 0x7);
1204 val = (regs->ccr >> ra) & 0xf;
1205 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1209 case 528: /* bcctr */
1211 imm = (instr & 0x400)? regs->ctr: regs->link;
1212 op->val = truncate_if_32bit(regs->msr, imm);
1215 if (branch_taken(instr, regs, op))
1216 op->type |= BRTAKEN;
1219 case 18: /* rfid, scary */
1220 if (regs->msr & MSR_PR)
1225 case 150: /* isync */
1226 op->type = BARRIER | BARRIER_ISYNC;
1229 case 33: /* crnor */
1230 case 129: /* crandc */
1231 case 193: /* crxor */
1232 case 225: /* crnand */
1233 case 257: /* crand */
1234 case 289: /* creqv */
1235 case 417: /* crorc */
1236 case 449: /* cror */
1237 op->type = COMPUTE + SETCC;
1238 ra = (instr >> 16) & 0x1f;
1239 rb = (instr >> 11) & 0x1f;
1240 rd = (instr >> 21) & 0x1f;
1241 ra = (regs->ccr >> (31 - ra)) & 1;
1242 rb = (regs->ccr >> (31 - rb)) & 1;
1243 val = (instr >> (6 + ra * 2 + rb)) & 1;
1244 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1250 switch ((instr >> 1) & 0x3ff) {
1251 case 598: /* sync */
1252 op->type = BARRIER + BARRIER_SYNC;
1253 #ifdef __powerpc64__
1254 switch ((instr >> 21) & 3) {
1255 case 1: /* lwsync */
1256 op->type = BARRIER + BARRIER_LWSYNC;
1258 case 2: /* ptesync */
1259 op->type = BARRIER + BARRIER_PTESYNC;
1265 case 854: /* eieio */
1266 op->type = BARRIER + BARRIER_EIEIO;
1272 /* Following cases refer to regs->gpr[], so we need all regs */
1273 if (!FULL_REGS(regs))
1276 rd = (instr >> 21) & 0x1f;
1277 ra = (instr >> 16) & 0x1f;
1278 rb = (instr >> 11) & 0x1f;
1281 #ifdef __powerpc64__
1283 if (rd & trap_compare(regs->gpr[ra], (short) instr))
1288 if (rd & trap_compare((int)regs->gpr[ra], (short) instr))
1293 op->val = regs->gpr[ra] * (short) instr;
1296 case 8: /* subfic */
1297 imm = (short) instr;
1298 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1301 case 10: /* cmpli */
1302 imm = (unsigned short) instr;
1303 val = regs->gpr[ra];
1304 #ifdef __powerpc64__
1306 val = (unsigned int) val;
1308 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1312 imm = (short) instr;
1313 val = regs->gpr[ra];
1314 #ifdef __powerpc64__
1318 do_cmp_signed(regs, op, val, imm, rd >> 2);
1321 case 12: /* addic */
1322 imm = (short) instr;
1323 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1326 case 13: /* addic. */
1327 imm = (short) instr;
1328 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1333 imm = (short) instr;
1335 imm += regs->gpr[ra];
1339 case 15: /* addis */
1340 imm = ((short) instr) << 16;
1342 imm += regs->gpr[ra];
1347 if (((instr >> 1) & 0x1f) == 2) {
1349 imm = (short) (instr & 0xffc1); /* d0 + d2 fields */
1350 imm |= (instr >> 15) & 0x3e; /* d1 field */
1351 op->val = regs->nip + (imm << 16) + 4;
1357 case 20: /* rlwimi */
1358 mb = (instr >> 6) & 0x1f;
1359 me = (instr >> 1) & 0x1f;
1360 val = DATA32(regs->gpr[rd]);
1361 imm = MASK32(mb, me);
1362 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1365 case 21: /* rlwinm */
1366 mb = (instr >> 6) & 0x1f;
1367 me = (instr >> 1) & 0x1f;
1368 val = DATA32(regs->gpr[rd]);
1369 op->val = ROTATE(val, rb) & MASK32(mb, me);
1372 case 23: /* rlwnm */
1373 mb = (instr >> 6) & 0x1f;
1374 me = (instr >> 1) & 0x1f;
1375 rb = regs->gpr[rb] & 0x1f;
1376 val = DATA32(regs->gpr[rd]);
1377 op->val = ROTATE(val, rb) & MASK32(mb, me);
1381 op->val = regs->gpr[rd] | (unsigned short) instr;
1382 goto logical_done_nocc;
1385 imm = (unsigned short) instr;
1386 op->val = regs->gpr[rd] | (imm << 16);
1387 goto logical_done_nocc;
1390 op->val = regs->gpr[rd] ^ (unsigned short) instr;
1391 goto logical_done_nocc;
1393 case 27: /* xoris */
1394 imm = (unsigned short) instr;
1395 op->val = regs->gpr[rd] ^ (imm << 16);
1396 goto logical_done_nocc;
1398 case 28: /* andi. */
1399 op->val = regs->gpr[rd] & (unsigned short) instr;
1401 goto logical_done_nocc;
1403 case 29: /* andis. */
1404 imm = (unsigned short) instr;
1405 op->val = regs->gpr[rd] & (imm << 16);
1407 goto logical_done_nocc;
1409 #ifdef __powerpc64__
1411 mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
1412 val = regs->gpr[rd];
1413 if ((instr & 0x10) == 0) {
1414 sh = rb | ((instr & 2) << 4);
1415 val = ROTATE(val, sh);
1416 switch ((instr >> 2) & 3) {
1417 case 0: /* rldicl */
1418 val &= MASK64_L(mb);
1420 case 1: /* rldicr */
1421 val &= MASK64_R(mb);
1424 val &= MASK64(mb, 63 - sh);
1426 case 3: /* rldimi */
1427 imm = MASK64(mb, 63 - sh);
1428 val = (regs->gpr[ra] & ~imm) |
1434 sh = regs->gpr[rb] & 0x3f;
1435 val = ROTATE(val, sh);
1436 switch ((instr >> 1) & 7) {
1438 op->val = val & MASK64_L(mb);
1441 op->val = val & MASK64_R(mb);
1446 op->type = UNKNOWN; /* illegal instruction */
1450 /* isel occupies 32 minor opcodes */
1451 if (((instr >> 1) & 0x1f) == 15) {
1452 mb = (instr >> 6) & 0x1f; /* bc field */
1453 val = (regs->ccr >> (31 - mb)) & 1;
1454 val2 = (ra) ? regs->gpr[ra] : 0;
1456 op->val = (val) ? val2 : regs->gpr[rb];
1460 switch ((instr >> 1) & 0x3ff) {
1463 (rd & trap_compare((int)regs->gpr[ra],
1464 (int)regs->gpr[rb])))
1467 #ifdef __powerpc64__
1469 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1473 case 83: /* mfmsr */
1474 if (regs->msr & MSR_PR)
1479 case 146: /* mtmsr */
1480 if (regs->msr & MSR_PR)
1484 op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1487 case 178: /* mtmsrd */
1488 if (regs->msr & MSR_PR)
1492 /* only MSR_EE and MSR_RI get changed if bit 15 set */
1493 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1494 imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1501 if ((instr >> 20) & 1) {
1503 for (sh = 0; sh < 8; ++sh) {
1504 if (instr & (0x80000 >> sh))
1509 op->val = regs->ccr & imm;
1512 case 144: /* mtcrf */
1513 op->type = COMPUTE + SETCC;
1515 val = regs->gpr[rd];
1516 op->ccval = regs->ccr;
1517 for (sh = 0; sh < 8; ++sh) {
1518 if (instr & (0x80000 >> sh))
1519 op->ccval = (op->ccval & ~imm) |
1525 case 339: /* mfspr */
1526 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1530 if (spr == SPRN_XER || spr == SPRN_LR ||
1535 case 467: /* mtspr */
1536 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1538 op->val = regs->gpr[rd];
1540 if (spr == SPRN_XER || spr == SPRN_LR ||
1546 * Compare instructions
1549 val = regs->gpr[ra];
1550 val2 = regs->gpr[rb];
1551 #ifdef __powerpc64__
1552 if ((rd & 1) == 0) {
1553 /* word (32-bit) compare */
1558 do_cmp_signed(regs, op, val, val2, rd >> 2);
1562 val = regs->gpr[ra];
1563 val2 = regs->gpr[rb];
1564 #ifdef __powerpc64__
1565 if ((rd & 1) == 0) {
1566 /* word (32-bit) compare */
1567 val = (unsigned int) val;
1568 val2 = (unsigned int) val2;
1571 do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1574 case 508: /* cmpb */
1575 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1576 goto logical_done_nocc;
1579 * Arithmetic instructions
1582 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1585 #ifdef __powerpc64__
1586 case 9: /* mulhdu */
1587 asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1588 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1592 add_with_carry(regs, op, rd, regs->gpr[ra],
1596 case 11: /* mulhwu */
1597 asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1598 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1602 op->val = regs->gpr[rb] - regs->gpr[ra];
1604 #ifdef __powerpc64__
1605 case 73: /* mulhd */
1606 asm("mulhd %0,%1,%2" : "=r" (op->val) :
1607 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1610 case 75: /* mulhw */
1611 asm("mulhw %0,%1,%2" : "=r" (op->val) :
1612 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1616 op->val = -regs->gpr[ra];
1619 case 136: /* subfe */
1620 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1621 regs->gpr[rb], regs->xer & XER_CA);
1624 case 138: /* adde */
1625 add_with_carry(regs, op, rd, regs->gpr[ra],
1626 regs->gpr[rb], regs->xer & XER_CA);
1629 case 200: /* subfze */
1630 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1631 regs->xer & XER_CA);
1634 case 202: /* addze */
1635 add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1636 regs->xer & XER_CA);
1639 case 232: /* subfme */
1640 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1641 regs->xer & XER_CA);
1643 #ifdef __powerpc64__
1644 case 233: /* mulld */
1645 op->val = regs->gpr[ra] * regs->gpr[rb];
1648 case 234: /* addme */
1649 add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1650 regs->xer & XER_CA);
1653 case 235: /* mullw */
1654 op->val = (long)(int) regs->gpr[ra] *
1655 (int) regs->gpr[rb];
1660 op->val = regs->gpr[ra] + regs->gpr[rb];
1662 #ifdef __powerpc64__
1663 case 457: /* divdu */
1664 op->val = regs->gpr[ra] / regs->gpr[rb];
1667 case 459: /* divwu */
1668 op->val = (unsigned int) regs->gpr[ra] /
1669 (unsigned int) regs->gpr[rb];
1671 #ifdef __powerpc64__
1672 case 489: /* divd */
1673 op->val = (long int) regs->gpr[ra] /
1674 (long int) regs->gpr[rb];
1677 case 491: /* divw */
1678 op->val = (int) regs->gpr[ra] /
1679 (int) regs->gpr[rb];
1684 * Logical instructions
1686 case 26: /* cntlzw */
1687 val = (unsigned int) regs->gpr[rd];
1688 op->val = ( val ? __builtin_clz(val) : 32 );
1690 #ifdef __powerpc64__
1691 case 58: /* cntlzd */
1692 val = regs->gpr[rd];
1693 op->val = ( val ? __builtin_clzl(val) : 64 );
1697 op->val = regs->gpr[rd] & regs->gpr[rb];
1701 op->val = regs->gpr[rd] & ~regs->gpr[rb];
1704 case 122: /* popcntb */
1705 do_popcnt(regs, op, regs->gpr[rd], 8);
1706 goto logical_done_nocc;
1709 op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1712 case 154: /* prtyw */
1713 do_prty(regs, op, regs->gpr[rd], 32);
1714 goto logical_done_nocc;
1716 case 186: /* prtyd */
1717 do_prty(regs, op, regs->gpr[rd], 64);
1718 goto logical_done_nocc;
1720 case 252: /* bpermd */
1721 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1722 goto logical_done_nocc;
1725 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1729 op->val = regs->gpr[rd] ^ regs->gpr[rb];
1732 case 378: /* popcntw */
1733 do_popcnt(regs, op, regs->gpr[rd], 32);
1734 goto logical_done_nocc;
1737 op->val = regs->gpr[rd] | ~regs->gpr[rb];
1741 op->val = regs->gpr[rd] | regs->gpr[rb];
1744 case 476: /* nand */
1745 op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1748 case 506: /* popcntd */
1749 do_popcnt(regs, op, regs->gpr[rd], 64);
1750 goto logical_done_nocc;
1752 case 922: /* extsh */
1753 op->val = (signed short) regs->gpr[rd];
1756 case 954: /* extsb */
1757 op->val = (signed char) regs->gpr[rd];
1759 #ifdef __powerpc64__
1760 case 986: /* extsw */
1761 op->val = (signed int) regs->gpr[rd];
1766 * Shift instructions
1769 sh = regs->gpr[rb] & 0x3f;
1771 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1777 sh = regs->gpr[rb] & 0x3f;
1779 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
1784 case 792: /* sraw */
1785 op->type = COMPUTE + SETREG + SETXER;
1786 sh = regs->gpr[rb] & 0x3f;
1787 ival = (signed int) regs->gpr[rd];
1788 op->val = ival >> (sh < 32 ? sh : 31);
1789 op->xerval = regs->xer;
1790 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
1791 op->xerval |= XER_CA;
1793 op->xerval &= ~XER_CA;
1796 case 824: /* srawi */
1797 op->type = COMPUTE + SETREG + SETXER;
1799 ival = (signed int) regs->gpr[rd];
1800 op->val = ival >> sh;
1801 op->xerval = regs->xer;
1802 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1803 op->xerval |= XER_CA;
1805 op->xerval &= ~XER_CA;
1808 #ifdef __powerpc64__
1810 sh = regs->gpr[rb] & 0x7f;
1812 op->val = regs->gpr[rd] << sh;
1818 sh = regs->gpr[rb] & 0x7f;
1820 op->val = regs->gpr[rd] >> sh;
1825 case 794: /* srad */
1826 op->type = COMPUTE + SETREG + SETXER;
1827 sh = regs->gpr[rb] & 0x7f;
1828 ival = (signed long int) regs->gpr[rd];
1829 op->val = ival >> (sh < 64 ? sh : 63);
1830 op->xerval = regs->xer;
1831 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
1832 op->xerval |= XER_CA;
1834 op->xerval &= ~XER_CA;
1837 case 826: /* sradi with sh_5 = 0 */
1838 case 827: /* sradi with sh_5 = 1 */
1839 op->type = COMPUTE + SETREG + SETXER;
1840 sh = rb | ((instr & 2) << 4);
1841 ival = (signed long int) regs->gpr[rd];
1842 op->val = ival >> sh;
1843 op->xerval = regs->xer;
1844 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1845 op->xerval |= XER_CA;
1847 op->xerval &= ~XER_CA;
1849 #endif /* __powerpc64__ */
1852 * Cache instructions
1854 case 54: /* dcbst */
1855 op->type = MKOP(CACHEOP, DCBST, 0);
1856 op->ea = xform_ea(instr, regs);
1860 op->type = MKOP(CACHEOP, DCBF, 0);
1861 op->ea = xform_ea(instr, regs);
1864 case 246: /* dcbtst */
1865 op->type = MKOP(CACHEOP, DCBTST, 0);
1866 op->ea = xform_ea(instr, regs);
1870 case 278: /* dcbt */
1871 op->type = MKOP(CACHEOP, DCBTST, 0);
1872 op->ea = xform_ea(instr, regs);
1876 case 982: /* icbi */
1877 op->type = MKOP(CACHEOP, ICBI, 0);
1878 op->ea = xform_ea(instr, regs);
1881 case 1014: /* dcbz */
1882 op->type = MKOP(CACHEOP, DCBZ, 0);
1883 op->ea = xform_ea(instr, regs);
1893 op->update_reg = ra;
1895 op->val = regs->gpr[rd];
1896 u = (instr >> 20) & UPDATE;
1902 op->ea = xform_ea(instr, regs);
1903 switch ((instr >> 1) & 0x3ff) {
1904 case 20: /* lwarx */
1905 op->type = MKOP(LARX, 0, 4);
1908 case 150: /* stwcx. */
1909 op->type = MKOP(STCX, 0, 4);
1912 #ifdef __powerpc64__
1913 case 84: /* ldarx */
1914 op->type = MKOP(LARX, 0, 8);
1917 case 214: /* stdcx. */
1918 op->type = MKOP(STCX, 0, 8);
1921 case 52: /* lbarx */
1922 op->type = MKOP(LARX, 0, 1);
1925 case 694: /* stbcx. */
1926 op->type = MKOP(STCX, 0, 1);
1929 case 116: /* lharx */
1930 op->type = MKOP(LARX, 0, 2);
1933 case 726: /* sthcx. */
1934 op->type = MKOP(STCX, 0, 2);
1937 case 276: /* lqarx */
1938 if (!((rd & 1) || rd == ra || rd == rb))
1939 op->type = MKOP(LARX, 0, 16);
1942 case 182: /* stqcx. */
1944 op->type = MKOP(STCX, 0, 16);
1949 case 55: /* lwzux */
1950 op->type = MKOP(LOAD, u, 4);
1954 case 119: /* lbzux */
1955 op->type = MKOP(LOAD, u, 1);
1958 #ifdef CONFIG_ALTIVEC
1960 * Note: for the load/store vector element instructions,
1961 * bits of the EA say which field of the VMX register to use.
1964 op->type = MKOP(LOAD_VMX, 0, 1);
1965 op->element_size = 1;
1968 case 39: /* lvehx */
1969 op->type = MKOP(LOAD_VMX, 0, 2);
1970 op->element_size = 2;
1973 case 71: /* lvewx */
1974 op->type = MKOP(LOAD_VMX, 0, 4);
1975 op->element_size = 4;
1979 case 359: /* lvxl */
1980 op->type = MKOP(LOAD_VMX, 0, 16);
1981 op->element_size = 16;
1984 case 135: /* stvebx */
1985 op->type = MKOP(STORE_VMX, 0, 1);
1986 op->element_size = 1;
1989 case 167: /* stvehx */
1990 op->type = MKOP(STORE_VMX, 0, 2);
1991 op->element_size = 2;
1994 case 199: /* stvewx */
1995 op->type = MKOP(STORE_VMX, 0, 4);
1996 op->element_size = 4;
1999 case 231: /* stvx */
2000 case 487: /* stvxl */
2001 op->type = MKOP(STORE_VMX, 0, 16);
2003 #endif /* CONFIG_ALTIVEC */
2005 #ifdef __powerpc64__
2008 op->type = MKOP(LOAD, u, 8);
2011 case 149: /* stdx */
2012 case 181: /* stdux */
2013 op->type = MKOP(STORE, u, 8);
2017 case 151: /* stwx */
2018 case 183: /* stwux */
2019 op->type = MKOP(STORE, u, 4);
2022 case 215: /* stbx */
2023 case 247: /* stbux */
2024 op->type = MKOP(STORE, u, 1);
2027 case 279: /* lhzx */
2028 case 311: /* lhzux */
2029 op->type = MKOP(LOAD, u, 2);
2032 #ifdef __powerpc64__
2033 case 341: /* lwax */
2034 case 373: /* lwaux */
2035 op->type = MKOP(LOAD, SIGNEXT | u, 4);
2039 case 343: /* lhax */
2040 case 375: /* lhaux */
2041 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2044 case 407: /* sthx */
2045 case 439: /* sthux */
2046 op->type = MKOP(STORE, u, 2);
2049 #ifdef __powerpc64__
2050 case 532: /* ldbrx */
2051 op->type = MKOP(LOAD, BYTEREV, 8);
2055 case 533: /* lswx */
2056 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2059 case 534: /* lwbrx */
2060 op->type = MKOP(LOAD, BYTEREV, 4);
2063 case 597: /* lswi */
2065 rb = 32; /* # bytes to load */
2066 op->type = MKOP(LOAD_MULTI, 0, rb);
2067 op->ea = ra ? regs->gpr[ra] : 0;
2070 #ifdef CONFIG_PPC_FPU
2071 case 535: /* lfsx */
2072 case 567: /* lfsux */
2073 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2076 case 599: /* lfdx */
2077 case 631: /* lfdux */
2078 op->type = MKOP(LOAD_FP, u, 8);
2081 case 663: /* stfsx */
2082 case 695: /* stfsux */
2083 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2086 case 727: /* stfdx */
2087 case 759: /* stfdux */
2088 op->type = MKOP(STORE_FP, u, 8);
2091 #ifdef __powerpc64__
2092 case 791: /* lfdpx */
2093 op->type = MKOP(LOAD_FP, 0, 16);
2096 case 855: /* lfiwax */
2097 op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2100 case 887: /* lfiwzx */
2101 op->type = MKOP(LOAD_FP, 0, 4);
2104 case 919: /* stfdpx */
2105 op->type = MKOP(STORE_FP, 0, 16);
2108 case 983: /* stfiwx */
2109 op->type = MKOP(STORE_FP, 0, 4);
2111 #endif /* __powerpc64 */
2112 #endif /* CONFIG_PPC_FPU */
2114 #ifdef __powerpc64__
2115 case 660: /* stdbrx */
2116 op->type = MKOP(STORE, BYTEREV, 8);
2117 op->val = byterev_8(regs->gpr[rd]);
2121 case 661: /* stswx */
2122 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2125 case 662: /* stwbrx */
2126 op->type = MKOP(STORE, BYTEREV, 4);
2127 op->val = byterev_4(regs->gpr[rd]);
2130 case 725: /* stswi */
2132 rb = 32; /* # bytes to store */
2133 op->type = MKOP(STORE_MULTI, 0, rb);
2134 op->ea = ra ? regs->gpr[ra] : 0;
2137 case 790: /* lhbrx */
2138 op->type = MKOP(LOAD, BYTEREV, 2);
2141 case 918: /* sthbrx */
2142 op->type = MKOP(STORE, BYTEREV, 2);
2143 op->val = byterev_2(regs->gpr[rd]);
2147 case 12: /* lxsiwzx */
2148 op->reg = rd | ((instr & 1) << 5);
2149 op->type = MKOP(LOAD_VSX, 0, 4);
2150 op->element_size = 8;
2153 case 76: /* lxsiwax */
2154 op->reg = rd | ((instr & 1) << 5);
2155 op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2156 op->element_size = 8;
2159 case 140: /* stxsiwx */
2160 op->reg = rd | ((instr & 1) << 5);
2161 op->type = MKOP(STORE_VSX, 0, 4);
2162 op->element_size = 8;
2165 case 268: /* lxvx */
2166 op->reg = rd | ((instr & 1) << 5);
2167 op->type = MKOP(LOAD_VSX, 0, 16);
2168 op->element_size = 16;
2169 op->vsx_flags = VSX_CHECK_VEC;
2172 case 269: /* lxvl */
2173 case 301: { /* lxvll */
2175 op->reg = rd | ((instr & 1) << 5);
2176 op->ea = ra ? regs->gpr[ra] : 0;
2177 nb = regs->gpr[rb] & 0xff;
2180 op->type = MKOP(LOAD_VSX, 0, nb);
2181 op->element_size = 16;
2182 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2186 case 332: /* lxvdsx */
2187 op->reg = rd | ((instr & 1) << 5);
2188 op->type = MKOP(LOAD_VSX, 0, 8);
2189 op->element_size = 8;
2190 op->vsx_flags = VSX_SPLAT;
2193 case 364: /* lxvwsx */
2194 op->reg = rd | ((instr & 1) << 5);
2195 op->type = MKOP(LOAD_VSX, 0, 4);
2196 op->element_size = 4;
2197 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2200 case 396: /* stxvx */
2201 op->reg = rd | ((instr & 1) << 5);
2202 op->type = MKOP(STORE_VSX, 0, 16);
2203 op->element_size = 16;
2204 op->vsx_flags = VSX_CHECK_VEC;
2207 case 397: /* stxvl */
2208 case 429: { /* stxvll */
2210 op->reg = rd | ((instr & 1) << 5);
2211 op->ea = ra ? regs->gpr[ra] : 0;
2212 nb = regs->gpr[rb] & 0xff;
2215 op->type = MKOP(STORE_VSX, 0, nb);
2216 op->element_size = 16;
2217 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2221 case 524: /* lxsspx */
2222 op->reg = rd | ((instr & 1) << 5);
2223 op->type = MKOP(LOAD_VSX, 0, 4);
2224 op->element_size = 8;
2225 op->vsx_flags = VSX_FPCONV;
2228 case 588: /* lxsdx */
2229 op->reg = rd | ((instr & 1) << 5);
2230 op->type = MKOP(LOAD_VSX, 0, 8);
2231 op->element_size = 8;
2234 case 652: /* stxsspx */
2235 op->reg = rd | ((instr & 1) << 5);
2236 op->type = MKOP(STORE_VSX, 0, 4);
2237 op->element_size = 8;
2238 op->vsx_flags = VSX_FPCONV;
2241 case 716: /* stxsdx */
2242 op->reg = rd | ((instr & 1) << 5);
2243 op->type = MKOP(STORE_VSX, 0, 8);
2244 op->element_size = 8;
2247 case 780: /* lxvw4x */
2248 op->reg = rd | ((instr & 1) << 5);
2249 op->type = MKOP(LOAD_VSX, 0, 16);
2250 op->element_size = 4;
2253 case 781: /* lxsibzx */
2254 op->reg = rd | ((instr & 1) << 5);
2255 op->type = MKOP(LOAD_VSX, 0, 1);
2256 op->element_size = 8;
2257 op->vsx_flags = VSX_CHECK_VEC;
2260 case 812: /* lxvh8x */
2261 op->reg = rd | ((instr & 1) << 5);
2262 op->type = MKOP(LOAD_VSX, 0, 16);
2263 op->element_size = 2;
2264 op->vsx_flags = VSX_CHECK_VEC;
2267 case 813: /* lxsihzx */
2268 op->reg = rd | ((instr & 1) << 5);
2269 op->type = MKOP(LOAD_VSX, 0, 2);
2270 op->element_size = 8;
2271 op->vsx_flags = VSX_CHECK_VEC;
2274 case 844: /* lxvd2x */
2275 op->reg = rd | ((instr & 1) << 5);
2276 op->type = MKOP(LOAD_VSX, 0, 16);
2277 op->element_size = 8;
2280 case 876: /* lxvb16x */
2281 op->reg = rd | ((instr & 1) << 5);
2282 op->type = MKOP(LOAD_VSX, 0, 16);
2283 op->element_size = 1;
2284 op->vsx_flags = VSX_CHECK_VEC;
2287 case 908: /* stxvw4x */
2288 op->reg = rd | ((instr & 1) << 5);
2289 op->type = MKOP(STORE_VSX, 0, 16);
2290 op->element_size = 4;
2293 case 909: /* stxsibx */
2294 op->reg = rd | ((instr & 1) << 5);
2295 op->type = MKOP(STORE_VSX, 0, 1);
2296 op->element_size = 8;
2297 op->vsx_flags = VSX_CHECK_VEC;
2300 case 940: /* stxvh8x */
2301 op->reg = rd | ((instr & 1) << 5);
2302 op->type = MKOP(STORE_VSX, 0, 16);
2303 op->element_size = 2;
2304 op->vsx_flags = VSX_CHECK_VEC;
2307 case 941: /* stxsihx */
2308 op->reg = rd | ((instr & 1) << 5);
2309 op->type = MKOP(STORE_VSX, 0, 2);
2310 op->element_size = 8;
2311 op->vsx_flags = VSX_CHECK_VEC;
2314 case 972: /* stxvd2x */
2315 op->reg = rd | ((instr & 1) << 5);
2316 op->type = MKOP(STORE_VSX, 0, 16);
2317 op->element_size = 8;
2320 case 1004: /* stxvb16x */
2321 op->reg = rd | ((instr & 1) << 5);
2322 op->type = MKOP(STORE_VSX, 0, 16);
2323 op->element_size = 1;
2324 op->vsx_flags = VSX_CHECK_VEC;
2327 #endif /* CONFIG_VSX */
2333 op->type = MKOP(LOAD, u, 4);
2334 op->ea = dform_ea(instr, regs);
2339 op->type = MKOP(LOAD, u, 1);
2340 op->ea = dform_ea(instr, regs);
2345 op->type = MKOP(STORE, u, 4);
2346 op->ea = dform_ea(instr, regs);
2351 op->type = MKOP(STORE, u, 1);
2352 op->ea = dform_ea(instr, regs);
2357 op->type = MKOP(LOAD, u, 2);
2358 op->ea = dform_ea(instr, regs);
2363 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2364 op->ea = dform_ea(instr, regs);
2369 op->type = MKOP(STORE, u, 2);
2370 op->ea = dform_ea(instr, regs);
2375 break; /* invalid form, ra in range to load */
2376 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2377 op->ea = dform_ea(instr, regs);
2381 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2382 op->ea = dform_ea(instr, regs);
2385 #ifdef CONFIG_PPC_FPU
2388 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2389 op->ea = dform_ea(instr, regs);
2394 op->type = MKOP(LOAD_FP, u, 8);
2395 op->ea = dform_ea(instr, regs);
2399 case 53: /* stfsu */
2400 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2401 op->ea = dform_ea(instr, regs);
2405 case 55: /* stfdu */
2406 op->type = MKOP(STORE_FP, u, 8);
2407 op->ea = dform_ea(instr, regs);
2411 #ifdef __powerpc64__
2413 if (!((rd & 1) || (rd == ra)))
2414 op->type = MKOP(LOAD, 0, 16);
2415 op->ea = dqform_ea(instr, regs);
2420 case 57: /* lfdp, lxsd, lxssp */
2421 op->ea = dsform_ea(instr, regs);
2422 switch (instr & 3) {
2425 break; /* reg must be even */
2426 op->type = MKOP(LOAD_FP, 0, 16);
2430 op->type = MKOP(LOAD_VSX, 0, 8);
2431 op->element_size = 8;
2432 op->vsx_flags = VSX_CHECK_VEC;
2436 op->type = MKOP(LOAD_VSX, 0, 4);
2437 op->element_size = 8;
2438 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2442 #endif /* CONFIG_VSX */
2444 #ifdef __powerpc64__
2445 case 58: /* ld[u], lwa */
2446 op->ea = dsform_ea(instr, regs);
2447 switch (instr & 3) {
2449 op->type = MKOP(LOAD, 0, 8);
2452 op->type = MKOP(LOAD, UPDATE, 8);
2455 op->type = MKOP(LOAD, SIGNEXT, 4);
2462 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */
2463 switch (instr & 7) {
2464 case 0: /* stfdp with LSB of DS field = 0 */
2465 case 4: /* stfdp with LSB of DS field = 1 */
2466 op->ea = dsform_ea(instr, regs);
2467 op->type = MKOP(STORE_FP, 0, 16);
2471 op->ea = dqform_ea(instr, regs);
2474 op->type = MKOP(LOAD_VSX, 0, 16);
2475 op->element_size = 16;
2476 op->vsx_flags = VSX_CHECK_VEC;
2479 case 2: /* stxsd with LSB of DS field = 0 */
2480 case 6: /* stxsd with LSB of DS field = 1 */
2481 op->ea = dsform_ea(instr, regs);
2483 op->type = MKOP(STORE_VSX, 0, 8);
2484 op->element_size = 8;
2485 op->vsx_flags = VSX_CHECK_VEC;
2488 case 3: /* stxssp with LSB of DS field = 0 */
2489 case 7: /* stxssp with LSB of DS field = 1 */
2490 op->ea = dsform_ea(instr, regs);
2492 op->type = MKOP(STORE_VSX, 0, 4);
2493 op->element_size = 8;
2494 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2498 op->ea = dqform_ea(instr, regs);
2501 op->type = MKOP(STORE_VSX, 0, 16);
2502 op->element_size = 16;
2503 op->vsx_flags = VSX_CHECK_VEC;
2507 #endif /* CONFIG_VSX */
2509 #ifdef __powerpc64__
2510 case 62: /* std[u] */
2511 op->ea = dsform_ea(instr, regs);
2512 switch (instr & 3) {
2514 op->type = MKOP(STORE, 0, 8);
2517 op->type = MKOP(STORE, UPDATE, 8);
2521 op->type = MKOP(STORE, 0, 16);
2525 #endif /* __powerpc64__ */
2547 op->type = INTERRUPT | 0x700;
2548 op->val = SRR1_PROGPRIV;
2552 op->type = INTERRUPT | 0x700;
2553 op->val = SRR1_PROGTRAP;
2556 EXPORT_SYMBOL_GPL(analyse_instr);
2557 NOKPROBE_SYMBOL(analyse_instr);
2560 * For PPC32 we always use stwu with r1 to change the stack pointer.
2561 * So this emulated store may corrupt the exception frame, now we
2562 * have to provide the exception frame trampoline, which is pushed
2563 * below the kprobed function stack. So we only update gpr[1] but
2564 * don't emulate the real store operation. We will do real store
2565 * operation safely in exception return code by checking this flag.
2567 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
2571 * Check if we will touch kernel stack overflow
2573 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
2574 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
2577 #endif /* CONFIG_PPC32 */
2579 * Check if we already set since that means we'll
2580 * lose the previous value.
2582 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
2583 set_thread_flag(TIF_EMULATE_STACK_STORE);
2587 static nokprobe_inline void do_signext(unsigned long *valp, int size)
2591 *valp = (signed short) *valp;
2594 *valp = (signed int) *valp;
2599 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
2603 *valp = byterev_2(*valp);
2606 *valp = byterev_4(*valp);
2608 #ifdef __powerpc64__
2610 *valp = byterev_8(*valp);
2617 * Emulate an instruction that can be executed just by updating
2620 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
2622 unsigned long next_pc;
2624 next_pc = truncate_if_32bit(regs->msr, regs->nip + 4);
2625 switch (op->type & INSTR_TYPE_MASK) {
2627 if (op->type & SETREG)
2628 regs->gpr[op->reg] = op->val;
2629 if (op->type & SETCC)
2630 regs->ccr = op->ccval;
2631 if (op->type & SETXER)
2632 regs->xer = op->xerval;
2636 if (op->type & SETLK)
2637 regs->link = next_pc;
2638 if (op->type & BRTAKEN)
2640 if (op->type & DECCTR)
2645 switch (op->type & BARRIER_MASK) {
2655 case BARRIER_LWSYNC:
2656 asm volatile("lwsync" : : : "memory");
2658 case BARRIER_PTESYNC:
2659 asm volatile("ptesync" : : : "memory");
2667 regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
2670 regs->gpr[op->reg] = regs->link;
2673 regs->gpr[op->reg] = regs->ctr;
2683 regs->xer = op->val & 0xffffffffUL;
2686 regs->link = op->val;
2689 regs->ctr = op->val;
2699 regs->nip = next_pc;
2703 * Emulate a previously-analysed load or store instruction.
2704 * Return values are:
2705 * 0 = instruction emulated successfully
2706 * -EFAULT = address out of range or access faulted (regs->dar
2707 * contains the faulting address)
2708 * -EACCES = misaligned access, instruction requires alignment
2709 * -EINVAL = unknown operation in *op
2711 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
2713 int err, size, type;
2721 size = GETSIZE(op->type);
2722 type = op->type & INSTR_TYPE_MASK;
2723 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
2724 ea = truncate_if_32bit(regs->msr, op->ea);
2728 if (ea & (size - 1))
2729 return -EACCES; /* can't handle misaligned */
2730 if (!address_ok(regs, ea, size))
2735 #ifdef __powerpc64__
2737 __get_user_asmx(val, ea, err, "lbarx");
2740 __get_user_asmx(val, ea, err, "lharx");
2744 __get_user_asmx(val, ea, err, "lwarx");
2746 #ifdef __powerpc64__
2748 __get_user_asmx(val, ea, err, "ldarx");
2751 err = do_lqarx(ea, ®s->gpr[op->reg]);
2762 regs->gpr[op->reg] = val;
2766 if (ea & (size - 1))
2767 return -EACCES; /* can't handle misaligned */
2768 if (!address_ok(regs, ea, size))
2772 #ifdef __powerpc64__
2774 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
2777 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
2781 __put_user_asmx(op->val, ea, err, "stwcx.", cr);
2783 #ifdef __powerpc64__
2785 __put_user_asmx(op->val, ea, err, "stdcx.", cr);
2788 err = do_stqcx(ea, regs->gpr[op->reg],
2789 regs->gpr[op->reg + 1], &cr);
2796 regs->ccr = (regs->ccr & 0x0fffffff) |
2798 ((regs->xer >> 3) & 0x10000000);
2804 #ifdef __powerpc64__
2806 err = emulate_lq(regs, ea, op->reg, cross_endian);
2810 err = read_mem(®s->gpr[op->reg], ea, size, regs);
2812 if (op->type & SIGNEXT)
2813 do_signext(®s->gpr[op->reg], size);
2814 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
2815 do_byterev(®s->gpr[op->reg], size);
2819 #ifdef CONFIG_PPC_FPU
2822 * If the instruction is in userspace, we can emulate it even
2823 * if the VMX state is not live, because we have the state
2824 * stored in the thread_struct. If the instruction is in
2825 * the kernel, we must not touch the state in the thread_struct.
2827 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2829 err = do_fp_load(op, ea, regs, cross_endian);
2832 #ifdef CONFIG_ALTIVEC
2834 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
2836 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
2841 unsigned long msrbit = MSR_VSX;
2844 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2845 * when the target of the instruction is a vector register.
2847 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
2849 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
2851 err = do_vsx_load(op, ea, regs, cross_endian);
2856 if (!address_ok(regs, ea, size))
2859 for (i = 0; i < size; i += 4) {
2860 unsigned int v32 = 0;
2865 err = copy_mem_in((u8 *) &v32, ea, nb, regs);
2868 if (unlikely(cross_endian))
2869 v32 = byterev_4(v32);
2870 regs->gpr[rd] = v32;
2872 /* reg number wraps from 31 to 0 for lsw[ix] */
2873 rd = (rd + 1) & 0x1f;
2878 #ifdef __powerpc64__
2880 err = emulate_stq(regs, ea, op->reg, cross_endian);
2884 if ((op->type & UPDATE) && size == sizeof(long) &&
2885 op->reg == 1 && op->update_reg == 1 &&
2886 !(regs->msr & MSR_PR) &&
2887 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
2888 err = handle_stack_update(ea, regs);
2891 if (unlikely(cross_endian))
2892 do_byterev(&op->val, size);
2893 err = write_mem(op->val, ea, size, regs);
2896 #ifdef CONFIG_PPC_FPU
2898 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2900 err = do_fp_store(op, ea, regs, cross_endian);
2903 #ifdef CONFIG_ALTIVEC
2905 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
2907 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
2912 unsigned long msrbit = MSR_VSX;
2915 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2916 * when the target of the instruction is a vector register.
2918 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
2920 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
2922 err = do_vsx_store(op, ea, regs, cross_endian);
2927 if (!address_ok(regs, ea, size))
2930 for (i = 0; i < size; i += 4) {
2931 unsigned int v32 = regs->gpr[rd];
2936 if (unlikely(cross_endian))
2937 v32 = byterev_4(v32);
2938 err = copy_mem_out((u8 *) &v32, ea, nb, regs);
2942 /* reg number wraps from 31 to 0 for stsw[ix] */
2943 rd = (rd + 1) & 0x1f;
2954 if (op->type & UPDATE)
2955 regs->gpr[op->update_reg] = op->ea;
2959 NOKPROBE_SYMBOL(emulate_loadstore);
2962 * Emulate instructions that cause a transfer of control,
2963 * loads and stores, and a few other instructions.
2964 * Returns 1 if the step was emulated, 0 if not,
2965 * or -1 if the instruction is one that should not be stepped,
2966 * such as an rfid, or a mtmsrd that would clear MSR_RI.
2968 int emulate_step(struct pt_regs *regs, unsigned int instr)
2970 struct instruction_op op;
2975 r = analyse_instr(&op, regs, instr);
2979 emulate_update_regs(regs, &op);
2984 type = op.type & INSTR_TYPE_MASK;
2986 if (OP_IS_LOAD_STORE(type)) {
2987 err = emulate_loadstore(regs, &op);
2995 ea = truncate_if_32bit(regs->msr, op.ea);
2996 if (!address_ok(regs, ea, 8))
2998 switch (op.type & CACHEOP_MASK) {
3000 __cacheop_user_asmx(ea, err, "dcbst");
3003 __cacheop_user_asmx(ea, err, "dcbf");
3007 prefetchw((void *) ea);
3011 prefetch((void *) ea);
3014 __cacheop_user_asmx(ea, err, "icbi");
3017 err = emulate_dcbz(ea, regs);
3027 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3031 val = regs->gpr[op.reg];
3032 if ((val & MSR_RI) == 0)
3033 /* can't step mtmsr[d] that would clear MSR_RI */
3035 /* here op.val is the mask of bits to change */
3036 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3040 case SYSCALL: /* sc */
3042 * N.B. this uses knowledge about how the syscall
3043 * entry code works. If that is changed, this will
3044 * need to be changed also.
3046 if (regs->gpr[0] == 0x1ebe &&
3047 cpu_has_feature(CPU_FTR_REAL_LE)) {
3048 regs->msr ^= MSR_LE;
3051 regs->gpr[9] = regs->gpr[13];
3052 regs->gpr[10] = MSR_KERNEL;
3053 regs->gpr[11] = regs->nip + 4;
3054 regs->gpr[12] = regs->msr & MSR_MASK;
3055 regs->gpr[13] = (unsigned long) get_paca();
3056 regs->nip = (unsigned long) &system_call_common;
3057 regs->msr = MSR_KERNEL;
3067 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
3070 NOKPROBE_SYMBOL(emulate_step);