1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
7 #include <linux/kernel.h>
8 #include <linux/kprobes.h>
9 #include <linux/ptrace.h>
10 #include <linux/prefetch.h>
11 #include <asm/sstep.h>
12 #include <asm/processor.h>
13 #include <linux/uaccess.h>
14 #include <asm/cpu_has_feature.h>
15 #include <asm/cputable.h>
16 #include <asm/disassemble.h>
19 /* Bits in SRR1 that are copied from MSR */
20 #define MSR_MASK 0xffffffff87c0ffffUL
22 #define MSR_MASK 0x87c0ffff
26 #define XER_SO 0x80000000U
27 #define XER_OV 0x40000000U
28 #define XER_CA 0x20000000U
29 #define XER_OV32 0x00080000U
30 #define XER_CA32 0x00040000U
33 #define VSX_REGISTER_XTP(rd) ((((rd) & 1) << 5) | ((rd) & 0xfe))
38 * Functions in ldstfp.S
40 extern void get_fpr(int rn, double *p);
41 extern void put_fpr(int rn, const double *p);
42 extern void get_vr(int rn, __vector128 *p);
43 extern void put_vr(int rn, __vector128 *p);
44 extern void load_vsrn(int vsr, const void *p);
45 extern void store_vsrn(int vsr, void *p);
46 extern void conv_sp_to_dp(const float *sp, double *dp);
47 extern void conv_dp_to_sp(const double *dp, float *sp);
54 extern int do_lq(unsigned long ea, unsigned long *regs);
55 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
56 extern int do_lqarx(unsigned long ea, unsigned long *regs);
57 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
61 #ifdef __LITTLE_ENDIAN__
70 * Emulate the truncation of 64 bit values in 32-bit mode.
72 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
75 if ((msr & MSR_64BIT) == 0)
81 * Determine whether a conditional branch instruction would branch.
83 static nokprobe_inline int branch_taken(unsigned int instr,
84 const struct pt_regs *regs,
85 struct instruction_op *op)
87 unsigned int bo = (instr >> 21) & 0x1f;
91 /* decrement counter */
93 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
96 if ((bo & 0x10) == 0) {
97 /* check bit from CR */
98 bi = (instr >> 16) & 0x1f;
99 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
105 static nokprobe_inline long address_ok(struct pt_regs *regs,
106 unsigned long ea, int nb)
108 if (!user_mode(regs))
110 if (access_ok((void __user *)ea, nb))
112 if (access_ok((void __user *)ea, 1))
113 /* Access overlaps the end of the user region */
114 regs->dar = TASK_SIZE_MAX - 1;
121 * Calculate effective address for a D-form instruction
123 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
124 const struct pt_regs *regs)
129 ra = (instr >> 16) & 0x1f;
130 ea = (signed short) instr; /* sign-extend */
139 * Calculate effective address for a DS-form instruction
141 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
142 const struct pt_regs *regs)
147 ra = (instr >> 16) & 0x1f;
148 ea = (signed short) (instr & ~3); /* sign-extend */
156 * Calculate effective address for a DQ-form instruction
158 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
159 const struct pt_regs *regs)
164 ra = (instr >> 16) & 0x1f;
165 ea = (signed short) (instr & ~0xf); /* sign-extend */
171 #endif /* __powerpc64 */
174 * Calculate effective address for an X-form instruction
176 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
177 const struct pt_regs *regs)
182 ra = (instr >> 16) & 0x1f;
183 rb = (instr >> 11) & 0x1f;
192 * Calculate effective address for a MLS:D-form / 8LS:D-form
193 * prefixed instruction
195 static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
197 const struct pt_regs *regs)
201 unsigned long ea, d0, d1, d;
203 prefix_r = GET_PREFIX_R(instr);
204 ra = GET_PREFIX_RA(suffix);
206 d0 = instr & 0x3ffff;
207 d1 = suffix & 0xffff;
211 * sign extend a 34 bit number
213 dd = (unsigned int)(d >> 2);
215 ea = (ea << 2) | (d & 0x3);
219 else if (!prefix_r && !ra)
220 ; /* Leave ea as is */
225 * (prefix_r && ra) is an invalid form. Should already be
226 * checked for by caller!
233 * Return the largest power of 2, not greater than sizeof(unsigned long),
234 * such that x is a multiple of it.
236 static nokprobe_inline unsigned long max_align(unsigned long x)
238 x |= sizeof(unsigned long);
239 return x & -x; /* isolates rightmost bit */
242 static nokprobe_inline unsigned long byterev_2(unsigned long x)
244 return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
247 static nokprobe_inline unsigned long byterev_4(unsigned long x)
249 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
250 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
254 static nokprobe_inline unsigned long byterev_8(unsigned long x)
256 return (byterev_4(x) << 32) | byterev_4(x >> 32);
260 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
264 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
267 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
271 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
274 unsigned long *up = (unsigned long *)ptr;
276 tmp = byterev_8(up[0]);
277 up[0] = byterev_8(up[1]);
282 unsigned long *up = (unsigned long *)ptr;
285 tmp = byterev_8(up[0]);
286 up[0] = byterev_8(up[3]);
288 tmp = byterev_8(up[2]);
289 up[2] = byterev_8(up[1]);
300 static __always_inline int
301 __read_mem_aligned(unsigned long *dest, unsigned long ea, int nb, struct pt_regs *regs)
307 unsafe_get_user(x, (unsigned char __user *)ea, Efault);
310 unsafe_get_user(x, (unsigned short __user *)ea, Efault);
313 unsafe_get_user(x, (unsigned int __user *)ea, Efault);
317 unsafe_get_user(x, (unsigned long __user *)ea, Efault);
329 static nokprobe_inline int
330 read_mem_aligned(unsigned long *dest, unsigned long ea, int nb, struct pt_regs *regs)
334 if (is_kernel_addr(ea))
335 return __read_mem_aligned(dest, ea, nb, regs);
337 if (user_read_access_begin((void __user *)ea, nb)) {
338 err = __read_mem_aligned(dest, ea, nb, regs);
339 user_read_access_end();
349 * Copy from userspace to a buffer, using the largest possible
350 * aligned accesses, up to sizeof(long).
352 static __always_inline int __copy_mem_in(u8 *dest, unsigned long ea, int nb, struct pt_regs *regs)
356 for (; nb > 0; nb -= c) {
362 unsafe_get_user(*dest, (u8 __user *)ea, Efault);
365 unsafe_get_user(*(u16 *)dest, (u16 __user *)ea, Efault);
368 unsafe_get_user(*(u32 *)dest, (u32 __user *)ea, Efault);
372 unsafe_get_user(*(u64 *)dest, (u64 __user *)ea, Efault);
386 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb, struct pt_regs *regs)
390 if (is_kernel_addr(ea))
391 return __copy_mem_in(dest, ea, nb, regs);
393 if (user_read_access_begin((void __user *)ea, nb)) {
394 err = __copy_mem_in(dest, ea, nb, regs);
395 user_read_access_end();
404 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
405 unsigned long ea, int nb,
406 struct pt_regs *regs)
410 u8 b[sizeof(unsigned long)];
416 i = IS_BE ? sizeof(unsigned long) - nb : 0;
417 err = copy_mem_in(&u.b[i], ea, nb, regs);
424 * Read memory at address ea for nb bytes, return 0 for success
425 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
426 * If nb < sizeof(long), the result is right-justified on BE systems.
428 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
429 struct pt_regs *regs)
431 if (!address_ok(regs, ea, nb))
433 if ((ea & (nb - 1)) == 0)
434 return read_mem_aligned(dest, ea, nb, regs);
435 return read_mem_unaligned(dest, ea, nb, regs);
437 NOKPROBE_SYMBOL(read_mem);
439 static __always_inline int
440 __write_mem_aligned(unsigned long val, unsigned long ea, int nb, struct pt_regs *regs)
444 unsafe_put_user(val, (unsigned char __user *)ea, Efault);
447 unsafe_put_user(val, (unsigned short __user *)ea, Efault);
450 unsafe_put_user(val, (unsigned int __user *)ea, Efault);
454 unsafe_put_user(val, (unsigned long __user *)ea, Efault);
465 static nokprobe_inline int
466 write_mem_aligned(unsigned long val, unsigned long ea, int nb, struct pt_regs *regs)
470 if (is_kernel_addr(ea))
471 return __write_mem_aligned(val, ea, nb, regs);
473 if (user_write_access_begin((void __user *)ea, nb)) {
474 err = __write_mem_aligned(val, ea, nb, regs);
475 user_write_access_end();
485 * Copy from a buffer to userspace, using the largest possible
486 * aligned accesses, up to sizeof(long).
488 static nokprobe_inline int __copy_mem_out(u8 *dest, unsigned long ea, int nb, struct pt_regs *regs)
492 for (; nb > 0; nb -= c) {
498 unsafe_put_user(*dest, (u8 __user *)ea, Efault);
501 unsafe_put_user(*(u16 *)dest, (u16 __user *)ea, Efault);
504 unsafe_put_user(*(u32 *)dest, (u32 __user *)ea, Efault);
508 unsafe_put_user(*(u64 *)dest, (u64 __user *)ea, Efault);
522 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb, struct pt_regs *regs)
526 if (is_kernel_addr(ea))
527 return __copy_mem_out(dest, ea, nb, regs);
529 if (user_write_access_begin((void __user *)ea, nb)) {
530 err = __copy_mem_out(dest, ea, nb, regs);
531 user_write_access_end();
540 static nokprobe_inline int write_mem_unaligned(unsigned long val,
541 unsigned long ea, int nb,
542 struct pt_regs *regs)
546 u8 b[sizeof(unsigned long)];
551 i = IS_BE ? sizeof(unsigned long) - nb : 0;
552 return copy_mem_out(&u.b[i], ea, nb, regs);
556 * Write memory at address ea for nb bytes, return 0 for success
557 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
559 static int write_mem(unsigned long val, unsigned long ea, int nb,
560 struct pt_regs *regs)
562 if (!address_ok(regs, ea, nb))
564 if ((ea & (nb - 1)) == 0)
565 return write_mem_aligned(val, ea, nb, regs);
566 return write_mem_unaligned(val, ea, nb, regs);
568 NOKPROBE_SYMBOL(write_mem);
570 #ifdef CONFIG_PPC_FPU
572 * These access either the real FP register or the image in the
573 * thread_struct, depending on regs->msr & MSR_FP.
575 static int do_fp_load(struct instruction_op *op, unsigned long ea,
576 struct pt_regs *regs, bool cross_endian)
585 u8 b[2 * sizeof(double)];
588 nb = GETSIZE(op->type);
591 if (!address_ok(regs, ea, nb))
594 err = copy_mem_in(u.b, ea, nb, regs);
597 if (unlikely(cross_endian)) {
598 do_byte_reverse(u.b, min(nb, 8));
600 do_byte_reverse(&u.b[8], 8);
604 if (op->type & FPCONV)
605 conv_sp_to_dp(&u.f, &u.d[0]);
606 else if (op->type & SIGNEXT)
611 if (regs->msr & MSR_FP)
612 put_fpr(rn, &u.d[0]);
614 current->thread.TS_FPR(rn) = u.l[0];
618 if (regs->msr & MSR_FP)
619 put_fpr(rn, &u.d[1]);
621 current->thread.TS_FPR(rn) = u.l[1];
626 NOKPROBE_SYMBOL(do_fp_load);
628 static int do_fp_store(struct instruction_op *op, unsigned long ea,
629 struct pt_regs *regs, bool cross_endian)
637 u8 b[2 * sizeof(double)];
640 nb = GETSIZE(op->type);
643 if (!address_ok(regs, ea, nb))
647 if (regs->msr & MSR_FP)
648 get_fpr(rn, &u.d[0]);
650 u.l[0] = current->thread.TS_FPR(rn);
652 if (op->type & FPCONV)
653 conv_dp_to_sp(&u.d[0], &u.f);
659 if (regs->msr & MSR_FP)
660 get_fpr(rn, &u.d[1]);
662 u.l[1] = current->thread.TS_FPR(rn);
665 if (unlikely(cross_endian)) {
666 do_byte_reverse(u.b, min(nb, 8));
668 do_byte_reverse(&u.b[8], 8);
670 return copy_mem_out(u.b, ea, nb, regs);
672 NOKPROBE_SYMBOL(do_fp_store);
675 #ifdef CONFIG_ALTIVEC
676 /* For Altivec/VMX, no need to worry about alignment */
677 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
678 int size, struct pt_regs *regs,
684 u8 b[sizeof(__vector128)];
687 if (size > sizeof(u))
690 if (!address_ok(regs, ea & ~0xfUL, 16))
692 /* align to multiple of size */
694 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
697 if (unlikely(cross_endian))
698 do_byte_reverse(&u.b[ea & 0xf], size);
700 if (regs->msr & MSR_VEC)
703 current->thread.vr_state.vr[rn] = u.v;
708 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
709 int size, struct pt_regs *regs,
714 u8 b[sizeof(__vector128)];
717 if (size > sizeof(u))
720 if (!address_ok(regs, ea & ~0xfUL, 16))
722 /* align to multiple of size */
726 if (regs->msr & MSR_VEC)
729 u.v = current->thread.vr_state.vr[rn];
731 if (unlikely(cross_endian))
732 do_byte_reverse(&u.b[ea & 0xf], size);
733 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
735 #endif /* CONFIG_ALTIVEC */
738 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
739 int reg, bool cross_endian)
743 if (!address_ok(regs, ea, 16))
745 /* if aligned, should be atomic */
746 if ((ea & 0xf) == 0) {
747 err = do_lq(ea, ®s->gpr[reg]);
749 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs);
751 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs);
753 if (!err && unlikely(cross_endian))
754 do_byte_reverse(®s->gpr[reg], 16);
758 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
759 int reg, bool cross_endian)
762 unsigned long vals[2];
764 if (!address_ok(regs, ea, 16))
766 vals[0] = regs->gpr[reg];
767 vals[1] = regs->gpr[reg + 1];
768 if (unlikely(cross_endian))
769 do_byte_reverse(vals, 16);
771 /* if aligned, should be atomic */
773 return do_stq(ea, vals[0], vals[1]);
775 err = write_mem(vals[IS_LE], ea, 8, regs);
777 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
780 #endif /* __powerpc64 */
783 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
784 const void *mem, bool rev)
788 const unsigned int *wp;
789 const unsigned short *hp;
790 const unsigned char *bp;
792 size = GETSIZE(op->type);
793 reg->d[0] = reg->d[1] = 0;
795 switch (op->element_size) {
799 /* whole vector; lxv[x] or lxvl[l] */
802 memcpy(reg, mem, size);
803 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
806 do_byte_reverse(reg, size);
809 /* scalar loads, lxvd2x, lxvdsx */
810 read_size = (size >= 8) ? 8 : size;
811 i = IS_LE ? 8 : 8 - read_size;
812 memcpy(®->b[i], mem, read_size);
814 do_byte_reverse(®->b[i], 8);
816 if (op->type & SIGNEXT) {
817 /* size == 4 is the only case here */
818 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
819 } else if (op->vsx_flags & VSX_FPCONV) {
821 conv_sp_to_dp(®->fp[1 + IS_LE],
827 unsigned long v = *(unsigned long *)(mem + 8);
828 reg->d[IS_BE] = !rev ? v : byterev_8(v);
829 } else if (op->vsx_flags & VSX_SPLAT)
830 reg->d[IS_BE] = reg->d[IS_LE];
836 for (j = 0; j < size / 4; ++j) {
837 i = IS_LE ? 3 - j : j;
838 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
840 if (op->vsx_flags & VSX_SPLAT) {
841 u32 val = reg->w[IS_LE ? 3 : 0];
843 i = IS_LE ? 3 - j : j;
851 for (j = 0; j < size / 2; ++j) {
852 i = IS_LE ? 7 - j : j;
853 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
859 for (j = 0; j < size; ++j) {
860 i = IS_LE ? 15 - j : j;
866 EXPORT_SYMBOL_GPL(emulate_vsx_load);
867 NOKPROBE_SYMBOL(emulate_vsx_load);
869 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
872 int size, write_size;
879 size = GETSIZE(op->type);
881 switch (op->element_size) {
887 /* reverse 32 bytes */
888 union vsx_reg buf32[2];
889 buf32[0].d[0] = byterev_8(reg[1].d[1]);
890 buf32[0].d[1] = byterev_8(reg[1].d[0]);
891 buf32[1].d[0] = byterev_8(reg[0].d[1]);
892 buf32[1].d[1] = byterev_8(reg[0].d[0]);
893 memcpy(mem, buf32, size);
895 memcpy(mem, reg, size);
899 /* stxv, stxvx, stxvl, stxvll */
902 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
905 /* reverse 16 bytes */
906 buf.d[0] = byterev_8(reg->d[1]);
907 buf.d[1] = byterev_8(reg->d[0]);
910 memcpy(mem, reg, size);
913 /* scalar stores, stxvd2x */
914 write_size = (size >= 8) ? 8 : size;
915 i = IS_LE ? 8 : 8 - write_size;
916 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
917 buf.d[0] = buf.d[1] = 0;
919 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]);
923 memcpy(mem, ®->b[i], write_size);
925 memcpy(mem + 8, ®->d[IS_BE], 8);
927 do_byte_reverse(mem, write_size);
929 do_byte_reverse(mem + 8, 8);
935 for (j = 0; j < size / 4; ++j) {
936 i = IS_LE ? 3 - j : j;
937 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
943 for (j = 0; j < size / 2; ++j) {
944 i = IS_LE ? 7 - j : j;
945 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
951 for (j = 0; j < size; ++j) {
952 i = IS_LE ? 15 - j : j;
958 EXPORT_SYMBOL_GPL(emulate_vsx_store);
959 NOKPROBE_SYMBOL(emulate_vsx_store);
961 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
962 unsigned long ea, struct pt_regs *regs,
966 int i, j, nr_vsx_regs;
968 union vsx_reg buf[2];
969 int size = GETSIZE(op->type);
971 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
974 nr_vsx_regs = max(1ul, size / sizeof(__vector128));
975 emulate_vsx_load(op, buf, mem, cross_endian);
978 /* FP regs + extensions */
979 if (regs->msr & MSR_FP) {
980 for (i = 0; i < nr_vsx_regs; i++) {
981 j = IS_LE ? nr_vsx_regs - i - 1 : i;
982 load_vsrn(reg + i, &buf[j].v);
985 for (i = 0; i < nr_vsx_regs; i++) {
986 j = IS_LE ? nr_vsx_regs - i - 1 : i;
987 current->thread.fp_state.fpr[reg + i][0] = buf[j].d[0];
988 current->thread.fp_state.fpr[reg + i][1] = buf[j].d[1];
992 if (regs->msr & MSR_VEC) {
993 for (i = 0; i < nr_vsx_regs; i++) {
994 j = IS_LE ? nr_vsx_regs - i - 1 : i;
995 load_vsrn(reg + i, &buf[j].v);
998 for (i = 0; i < nr_vsx_regs; i++) {
999 j = IS_LE ? nr_vsx_regs - i - 1 : i;
1000 current->thread.vr_state.vr[reg - 32 + i] = buf[j].v;
1008 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
1009 unsigned long ea, struct pt_regs *regs,
1013 int i, j, nr_vsx_regs;
1015 union vsx_reg buf[2];
1016 int size = GETSIZE(op->type);
1018 if (!address_ok(regs, ea, size))
1021 nr_vsx_regs = max(1ul, size / sizeof(__vector128));
1024 /* FP regs + extensions */
1025 if (regs->msr & MSR_FP) {
1026 for (i = 0; i < nr_vsx_regs; i++) {
1027 j = IS_LE ? nr_vsx_regs - i - 1 : i;
1028 store_vsrn(reg + i, &buf[j].v);
1031 for (i = 0; i < nr_vsx_regs; i++) {
1032 j = IS_LE ? nr_vsx_regs - i - 1 : i;
1033 buf[j].d[0] = current->thread.fp_state.fpr[reg + i][0];
1034 buf[j].d[1] = current->thread.fp_state.fpr[reg + i][1];
1038 if (regs->msr & MSR_VEC) {
1039 for (i = 0; i < nr_vsx_regs; i++) {
1040 j = IS_LE ? nr_vsx_regs - i - 1 : i;
1041 store_vsrn(reg + i, &buf[j].v);
1044 for (i = 0; i < nr_vsx_regs; i++) {
1045 j = IS_LE ? nr_vsx_regs - i - 1 : i;
1046 buf[j].v = current->thread.vr_state.vr[reg - 32 + i];
1051 emulate_vsx_store(op, buf, mem, cross_endian);
1052 return copy_mem_out(mem, ea, size, regs);
1054 #endif /* CONFIG_VSX */
1056 static int __emulate_dcbz(unsigned long ea)
1059 unsigned long size = l1_dcache_bytes();
1061 for (i = 0; i < size; i += sizeof(long))
1062 unsafe_put_user(0, (unsigned long __user *)(ea + i), Efault);
1070 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
1073 unsigned long size = l1_dcache_bytes();
1075 ea = truncate_if_32bit(regs->msr, ea);
1077 if (!address_ok(regs, ea, size))
1080 if (is_kernel_addr(ea)) {
1081 err = __emulate_dcbz(ea);
1082 } else if (user_write_access_begin((void __user *)ea, size)) {
1083 err = __emulate_dcbz(ea);
1084 user_write_access_end();
1095 NOKPROBE_SYMBOL(emulate_dcbz);
1097 #define __put_user_asmx(x, addr, err, op, cr) \
1098 __asm__ __volatile__( \
1100 ".machine power8\n" \
1101 "1: " op " %2,0,%3\n" \
1105 ".section .fixup,\"ax\"\n" \
1110 : "=r" (err), "=r" (cr) \
1111 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
1113 #define __get_user_asmx(x, addr, err, op) \
1114 __asm__ __volatile__( \
1116 ".machine power8\n" \
1117 "1: "op" %1,0,%2\n" \
1120 ".section .fixup,\"ax\"\n" \
1125 : "=r" (err), "=r" (x) \
1126 : "r" (addr), "i" (-EFAULT), "0" (err))
1128 #define __cacheop_user_asmx(addr, err, op) \
1129 __asm__ __volatile__( \
1132 ".section .fixup,\"ax\"\n" \
1138 : "r" (addr), "i" (-EFAULT), "0" (err))
1140 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
1141 struct instruction_op *op)
1146 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
1147 if (!(regs->msr & MSR_64BIT))
1150 op->ccval |= 0x80000000;
1152 op->ccval |= 0x40000000;
1154 op->ccval |= 0x20000000;
1157 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
1159 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1161 op->xerval |= XER_CA32;
1163 op->xerval &= ~XER_CA32;
1167 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
1168 struct instruction_op *op, int rd,
1169 unsigned long val1, unsigned long val2,
1170 unsigned long carry_in)
1172 unsigned long val = val1 + val2;
1176 op->type = COMPUTE | SETREG | SETXER;
1179 val = truncate_if_32bit(regs->msr, val);
1180 val1 = truncate_if_32bit(regs->msr, val1);
1181 op->xerval = regs->xer;
1182 if (val < val1 || (carry_in && val == val1))
1183 op->xerval |= XER_CA;
1185 op->xerval &= ~XER_CA;
1187 set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1188 (carry_in && (unsigned int)val == (unsigned int)val1));
1191 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1192 struct instruction_op *op,
1193 long v1, long v2, int crfld)
1195 unsigned int crval, shift;
1197 op->type = COMPUTE | SETCC;
1198 crval = (regs->xer >> 31) & 1; /* get SO bit */
1205 shift = (7 - crfld) * 4;
1206 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1209 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1210 struct instruction_op *op,
1212 unsigned long v2, int crfld)
1214 unsigned int crval, shift;
1216 op->type = COMPUTE | SETCC;
1217 crval = (regs->xer >> 31) & 1; /* get SO bit */
1224 shift = (7 - crfld) * 4;
1225 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1228 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1229 struct instruction_op *op,
1230 unsigned long v1, unsigned long v2)
1232 unsigned long long out_val, mask;
1236 for (i = 0; i < 8; i++) {
1237 mask = 0xffUL << (i * 8);
1238 if ((v1 & mask) == (v2 & mask))
1245 * The size parameter is used to adjust the equivalent popcnt instruction.
1246 * popcntb = 8, popcntw = 32, popcntd = 64
1248 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1249 struct instruction_op *op,
1250 unsigned long v1, int size)
1252 unsigned long long out = v1;
1254 out -= (out >> 1) & 0x5555555555555555ULL;
1255 out = (0x3333333333333333ULL & out) +
1256 (0x3333333333333333ULL & (out >> 2));
1257 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1259 if (size == 8) { /* popcntb */
1265 if (size == 32) { /* popcntw */
1266 op->val = out & 0x0000003f0000003fULL;
1270 out = (out + (out >> 32)) & 0x7f;
1271 op->val = out; /* popcntd */
1275 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1276 struct instruction_op *op,
1277 unsigned long v1, unsigned long v2)
1279 unsigned char perm, idx;
1283 for (i = 0; i < 8; i++) {
1284 idx = (v1 >> (i * 8)) & 0xff;
1286 if (v2 & PPC_BIT(idx))
1291 #endif /* CONFIG_PPC64 */
1293 * The size parameter adjusts the equivalent prty instruction.
1294 * prtyw = 32, prtyd = 64
1296 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1297 struct instruction_op *op,
1298 unsigned long v, int size)
1300 unsigned long long res = v ^ (v >> 8);
1303 if (size == 32) { /* prtyw */
1304 op->val = res & 0x0000000100000001ULL;
1309 op->val = res & 1; /*prtyd */
1312 static nokprobe_inline int trap_compare(long v1, long v2)
1322 if ((unsigned long)v1 < (unsigned long)v2)
1324 else if ((unsigned long)v1 > (unsigned long)v2)
1330 * Elements of 32-bit rotate and mask instructions.
1332 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
1333 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1334 #ifdef __powerpc64__
1335 #define MASK64_L(mb) (~0UL >> (mb))
1336 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))
1337 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1338 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1340 #define DATA32(x) (x)
1342 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1345 * Decode an instruction, and return information about it in *op
1346 * without changing *regs.
1347 * Integer arithmetic and logical instructions, branches, and barrier
1348 * instructions can be emulated just using the information in *op.
1350 * Return value is 1 if the instruction can be emulated just by
1351 * updating *regs with the information in *op, -1 if we need the
1352 * GPRs but *regs doesn't contain the full register set, or 0
1355 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1359 unsigned int suffixopcode, prefixtype, prefix_r;
1361 unsigned int opcode, ra, rb, rc, rd, spr, u;
1362 unsigned long int imm;
1363 unsigned long int val, val2;
1364 unsigned int mb, me, sh;
1365 unsigned int word, suffix;
1368 word = ppc_inst_val(instr);
1369 suffix = ppc_inst_suffix(instr);
1373 opcode = ppc_inst_primary_opcode(instr);
1377 imm = (signed short)(word & 0xfffc);
1378 if ((word & 2) == 0)
1380 op->val = truncate_if_32bit(regs->msr, imm);
1383 if (branch_taken(word, regs, op))
1384 op->type |= BRTAKEN;
1387 if ((word & 0xfe2) == 2)
1389 else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
1390 (word & 0xfe3) == 1) { /* scv */
1391 op->type = SYSCALL_VECTORED_0;
1392 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1393 goto unknown_opcode;
1398 op->type = BRANCH | BRTAKEN;
1399 imm = word & 0x03fffffc;
1400 if (imm & 0x02000000)
1402 if ((word & 2) == 0)
1404 op->val = truncate_if_32bit(regs->msr, imm);
1409 switch ((word >> 1) & 0x3ff) {
1411 op->type = COMPUTE + SETCC;
1412 rd = 7 - ((word >> 23) & 0x7);
1413 ra = 7 - ((word >> 18) & 0x7);
1416 val = (regs->ccr >> ra) & 0xf;
1417 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1421 case 528: /* bcctr */
1423 imm = (word & 0x400)? regs->ctr: regs->link;
1424 op->val = truncate_if_32bit(regs->msr, imm);
1427 if (branch_taken(word, regs, op))
1428 op->type |= BRTAKEN;
1431 case 18: /* rfid, scary */
1432 if (regs->msr & MSR_PR)
1437 case 150: /* isync */
1438 op->type = BARRIER | BARRIER_ISYNC;
1441 case 33: /* crnor */
1442 case 129: /* crandc */
1443 case 193: /* crxor */
1444 case 225: /* crnand */
1445 case 257: /* crand */
1446 case 289: /* creqv */
1447 case 417: /* crorc */
1448 case 449: /* cror */
1449 op->type = COMPUTE + SETCC;
1450 ra = (word >> 16) & 0x1f;
1451 rb = (word >> 11) & 0x1f;
1452 rd = (word >> 21) & 0x1f;
1453 ra = (regs->ccr >> (31 - ra)) & 1;
1454 rb = (regs->ccr >> (31 - rb)) & 1;
1455 val = (word >> (6 + ra * 2 + rb)) & 1;
1456 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1462 switch ((word >> 1) & 0x3ff) {
1463 case 598: /* sync */
1464 op->type = BARRIER + BARRIER_SYNC;
1465 #ifdef __powerpc64__
1466 switch ((word >> 21) & 3) {
1467 case 1: /* lwsync */
1468 op->type = BARRIER + BARRIER_LWSYNC;
1470 case 2: /* ptesync */
1471 op->type = BARRIER + BARRIER_PTESYNC;
1477 case 854: /* eieio */
1478 op->type = BARRIER + BARRIER_EIEIO;
1484 rd = (word >> 21) & 0x1f;
1485 ra = (word >> 16) & 0x1f;
1486 rb = (word >> 11) & 0x1f;
1487 rc = (word >> 6) & 0x1f;
1490 #ifdef __powerpc64__
1492 if (!cpu_has_feature(CPU_FTR_ARCH_31))
1493 goto unknown_opcode;
1495 prefix_r = GET_PREFIX_R(word);
1496 ra = GET_PREFIX_RA(suffix);
1497 rd = (suffix >> 21) & 0x1f;
1499 op->val = regs->gpr[rd];
1500 suffixopcode = get_op(suffix);
1501 prefixtype = (word >> 24) & 0x3;
1502 switch (prefixtype) {
1506 switch (suffixopcode) {
1507 case 14: /* paddi */
1508 op->type = COMPUTE | PREFIXED;
1509 op->val = mlsd_8lsd_ea(word, suffix, regs);
1515 if (rd & trap_compare(regs->gpr[ra], (short) word))
1520 if (rd & trap_compare((int)regs->gpr[ra], (short) word))
1524 #ifdef __powerpc64__
1527 * There are very many instructions with this primary opcode
1528 * introduced in the ISA as early as v2.03. However, the ones
1529 * we currently emulate were all introduced with ISA 3.0
1531 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1532 goto unknown_opcode;
1534 switch (word & 0x3f) {
1535 case 48: /* maddhd */
1536 asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1537 "=r" (op->val) : "r" (regs->gpr[ra]),
1538 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1541 case 49: /* maddhdu */
1542 asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1543 "=r" (op->val) : "r" (regs->gpr[ra]),
1544 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1547 case 51: /* maddld */
1548 asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1549 "=r" (op->val) : "r" (regs->gpr[ra]),
1550 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1555 * There are other instructions from ISA 3.0 with the same
1556 * primary opcode which do not have emulation support yet.
1558 goto unknown_opcode;
1562 op->val = regs->gpr[ra] * (short) word;
1565 case 8: /* subfic */
1567 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1570 case 10: /* cmpli */
1571 imm = (unsigned short) word;
1572 val = regs->gpr[ra];
1573 #ifdef __powerpc64__
1575 val = (unsigned int) val;
1577 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1582 val = regs->gpr[ra];
1583 #ifdef __powerpc64__
1587 do_cmp_signed(regs, op, val, imm, rd >> 2);
1590 case 12: /* addic */
1592 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1595 case 13: /* addic. */
1597 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1604 imm += regs->gpr[ra];
1608 case 15: /* addis */
1609 imm = ((short) word) << 16;
1611 imm += regs->gpr[ra];
1616 if (((word >> 1) & 0x1f) == 2) {
1618 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1619 goto unknown_opcode;
1620 imm = (short) (word & 0xffc1); /* d0 + d2 fields */
1621 imm |= (word >> 15) & 0x3e; /* d1 field */
1622 op->val = regs->nip + (imm << 16) + 4;
1628 case 20: /* rlwimi */
1629 mb = (word >> 6) & 0x1f;
1630 me = (word >> 1) & 0x1f;
1631 val = DATA32(regs->gpr[rd]);
1632 imm = MASK32(mb, me);
1633 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1636 case 21: /* rlwinm */
1637 mb = (word >> 6) & 0x1f;
1638 me = (word >> 1) & 0x1f;
1639 val = DATA32(regs->gpr[rd]);
1640 op->val = ROTATE(val, rb) & MASK32(mb, me);
1643 case 23: /* rlwnm */
1644 mb = (word >> 6) & 0x1f;
1645 me = (word >> 1) & 0x1f;
1646 rb = regs->gpr[rb] & 0x1f;
1647 val = DATA32(regs->gpr[rd]);
1648 op->val = ROTATE(val, rb) & MASK32(mb, me);
1652 op->val = regs->gpr[rd] | (unsigned short) word;
1653 goto logical_done_nocc;
1656 imm = (unsigned short) word;
1657 op->val = regs->gpr[rd] | (imm << 16);
1658 goto logical_done_nocc;
1661 op->val = regs->gpr[rd] ^ (unsigned short) word;
1662 goto logical_done_nocc;
1664 case 27: /* xoris */
1665 imm = (unsigned short) word;
1666 op->val = regs->gpr[rd] ^ (imm << 16);
1667 goto logical_done_nocc;
1669 case 28: /* andi. */
1670 op->val = regs->gpr[rd] & (unsigned short) word;
1672 goto logical_done_nocc;
1674 case 29: /* andis. */
1675 imm = (unsigned short) word;
1676 op->val = regs->gpr[rd] & (imm << 16);
1678 goto logical_done_nocc;
1680 #ifdef __powerpc64__
1682 mb = ((word >> 6) & 0x1f) | (word & 0x20);
1683 val = regs->gpr[rd];
1684 if ((word & 0x10) == 0) {
1685 sh = rb | ((word & 2) << 4);
1686 val = ROTATE(val, sh);
1687 switch ((word >> 2) & 3) {
1688 case 0: /* rldicl */
1689 val &= MASK64_L(mb);
1691 case 1: /* rldicr */
1692 val &= MASK64_R(mb);
1695 val &= MASK64(mb, 63 - sh);
1697 case 3: /* rldimi */
1698 imm = MASK64(mb, 63 - sh);
1699 val = (regs->gpr[ra] & ~imm) |
1705 sh = regs->gpr[rb] & 0x3f;
1706 val = ROTATE(val, sh);
1707 switch ((word >> 1) & 7) {
1709 op->val = val & MASK64_L(mb);
1712 op->val = val & MASK64_R(mb);
1717 op->type = UNKNOWN; /* illegal instruction */
1721 /* isel occupies 32 minor opcodes */
1722 if (((word >> 1) & 0x1f) == 15) {
1723 mb = (word >> 6) & 0x1f; /* bc field */
1724 val = (regs->ccr >> (31 - mb)) & 1;
1725 val2 = (ra) ? regs->gpr[ra] : 0;
1727 op->val = (val) ? val2 : regs->gpr[rb];
1731 switch ((word >> 1) & 0x3ff) {
1734 (rd & trap_compare((int)regs->gpr[ra],
1735 (int)regs->gpr[rb])))
1738 #ifdef __powerpc64__
1740 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1744 case 83: /* mfmsr */
1745 if (regs->msr & MSR_PR)
1750 case 146: /* mtmsr */
1751 if (regs->msr & MSR_PR)
1755 op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1758 case 178: /* mtmsrd */
1759 if (regs->msr & MSR_PR)
1763 /* only MSR_EE and MSR_RI get changed if bit 15 set */
1764 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1765 imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1772 if ((word >> 20) & 1) {
1774 for (sh = 0; sh < 8; ++sh) {
1775 if (word & (0x80000 >> sh))
1780 op->val = regs->ccr & imm;
1783 case 128: /* setb */
1784 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1785 goto unknown_opcode;
1787 * 'ra' encodes the CR field number (bfa) in the top 3 bits.
1788 * Since each CR field is 4 bits,
1789 * we can simply mask off the bottom two bits (bfa * 4)
1790 * to yield the first bit in the CR field.
1793 /* 'val' stores bits of the CR field (bfa) */
1794 val = regs->ccr >> (CR0_SHIFT - ra);
1795 /* checks if the LT bit of CR field (bfa) is set */
1798 /* checks if the GT bit of CR field (bfa) is set */
1805 case 144: /* mtcrf */
1806 op->type = COMPUTE + SETCC;
1808 val = regs->gpr[rd];
1809 op->ccval = regs->ccr;
1810 for (sh = 0; sh < 8; ++sh) {
1811 if (word & (0x80000 >> sh))
1812 op->ccval = (op->ccval & ~imm) |
1818 case 339: /* mfspr */
1819 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1823 if (spr == SPRN_XER || spr == SPRN_LR ||
1828 case 467: /* mtspr */
1829 spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1831 op->val = regs->gpr[rd];
1833 if (spr == SPRN_XER || spr == SPRN_LR ||
1839 * Compare instructions
1842 val = regs->gpr[ra];
1843 val2 = regs->gpr[rb];
1844 #ifdef __powerpc64__
1845 if ((rd & 1) == 0) {
1846 /* word (32-bit) compare */
1851 do_cmp_signed(regs, op, val, val2, rd >> 2);
1855 val = regs->gpr[ra];
1856 val2 = regs->gpr[rb];
1857 #ifdef __powerpc64__
1858 if ((rd & 1) == 0) {
1859 /* word (32-bit) compare */
1860 val = (unsigned int) val;
1861 val2 = (unsigned int) val2;
1864 do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1867 case 508: /* cmpb */
1868 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1869 goto logical_done_nocc;
1872 * Arithmetic instructions
1875 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1878 #ifdef __powerpc64__
1879 case 9: /* mulhdu */
1880 asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1881 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1885 add_with_carry(regs, op, rd, regs->gpr[ra],
1889 case 11: /* mulhwu */
1890 asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1891 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1895 op->val = regs->gpr[rb] - regs->gpr[ra];
1897 #ifdef __powerpc64__
1898 case 73: /* mulhd */
1899 asm("mulhd %0,%1,%2" : "=r" (op->val) :
1900 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1903 case 75: /* mulhw */
1904 asm("mulhw %0,%1,%2" : "=r" (op->val) :
1905 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1909 op->val = -regs->gpr[ra];
1912 case 136: /* subfe */
1913 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1914 regs->gpr[rb], regs->xer & XER_CA);
1917 case 138: /* adde */
1918 add_with_carry(regs, op, rd, regs->gpr[ra],
1919 regs->gpr[rb], regs->xer & XER_CA);
1922 case 200: /* subfze */
1923 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1924 regs->xer & XER_CA);
1927 case 202: /* addze */
1928 add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1929 regs->xer & XER_CA);
1932 case 232: /* subfme */
1933 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1934 regs->xer & XER_CA);
1936 #ifdef __powerpc64__
1937 case 233: /* mulld */
1938 op->val = regs->gpr[ra] * regs->gpr[rb];
1941 case 234: /* addme */
1942 add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1943 regs->xer & XER_CA);
1946 case 235: /* mullw */
1947 op->val = (long)(int) regs->gpr[ra] *
1948 (int) regs->gpr[rb];
1951 #ifdef __powerpc64__
1952 case 265: /* modud */
1953 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1954 goto unknown_opcode;
1955 op->val = regs->gpr[ra] % regs->gpr[rb];
1959 op->val = regs->gpr[ra] + regs->gpr[rb];
1962 case 267: /* moduw */
1963 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1964 goto unknown_opcode;
1965 op->val = (unsigned int) regs->gpr[ra] %
1966 (unsigned int) regs->gpr[rb];
1968 #ifdef __powerpc64__
1969 case 457: /* divdu */
1970 op->val = regs->gpr[ra] / regs->gpr[rb];
1973 case 459: /* divwu */
1974 op->val = (unsigned int) regs->gpr[ra] /
1975 (unsigned int) regs->gpr[rb];
1977 #ifdef __powerpc64__
1978 case 489: /* divd */
1979 op->val = (long int) regs->gpr[ra] /
1980 (long int) regs->gpr[rb];
1983 case 491: /* divw */
1984 op->val = (int) regs->gpr[ra] /
1985 (int) regs->gpr[rb];
1987 #ifdef __powerpc64__
1988 case 425: /* divde[.] */
1989 asm volatile(PPC_DIVDE(%0, %1, %2) :
1990 "=r" (op->val) : "r" (regs->gpr[ra]),
1991 "r" (regs->gpr[rb]));
1993 case 393: /* divdeu[.] */
1994 asm volatile(PPC_DIVDEU(%0, %1, %2) :
1995 "=r" (op->val) : "r" (regs->gpr[ra]),
1996 "r" (regs->gpr[rb]));
1999 case 755: /* darn */
2000 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2001 goto unknown_opcode;
2004 /* 32-bit conditioned */
2005 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
2009 /* 64-bit conditioned */
2010 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
2015 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
2019 goto unknown_opcode;
2020 #ifdef __powerpc64__
2021 case 777: /* modsd */
2022 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2023 goto unknown_opcode;
2024 op->val = (long int) regs->gpr[ra] %
2025 (long int) regs->gpr[rb];
2028 case 779: /* modsw */
2029 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2030 goto unknown_opcode;
2031 op->val = (int) regs->gpr[ra] %
2032 (int) regs->gpr[rb];
2037 * Logical instructions
2039 case 26: /* cntlzw */
2040 val = (unsigned int) regs->gpr[rd];
2041 op->val = ( val ? __builtin_clz(val) : 32 );
2043 #ifdef __powerpc64__
2044 case 58: /* cntlzd */
2045 val = regs->gpr[rd];
2046 op->val = ( val ? __builtin_clzl(val) : 64 );
2050 op->val = regs->gpr[rd] & regs->gpr[rb];
2054 op->val = regs->gpr[rd] & ~regs->gpr[rb];
2057 case 122: /* popcntb */
2058 do_popcnt(regs, op, regs->gpr[rd], 8);
2059 goto logical_done_nocc;
2062 op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
2065 case 154: /* prtyw */
2066 do_prty(regs, op, regs->gpr[rd], 32);
2067 goto logical_done_nocc;
2069 case 186: /* prtyd */
2070 do_prty(regs, op, regs->gpr[rd], 64);
2071 goto logical_done_nocc;
2073 case 252: /* bpermd */
2074 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
2075 goto logical_done_nocc;
2078 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
2082 op->val = regs->gpr[rd] ^ regs->gpr[rb];
2085 case 378: /* popcntw */
2086 do_popcnt(regs, op, regs->gpr[rd], 32);
2087 goto logical_done_nocc;
2090 op->val = regs->gpr[rd] | ~regs->gpr[rb];
2094 op->val = regs->gpr[rd] | regs->gpr[rb];
2097 case 476: /* nand */
2098 op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
2101 case 506: /* popcntd */
2102 do_popcnt(regs, op, regs->gpr[rd], 64);
2103 goto logical_done_nocc;
2105 case 538: /* cnttzw */
2106 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2107 goto unknown_opcode;
2108 val = (unsigned int) regs->gpr[rd];
2109 op->val = (val ? __builtin_ctz(val) : 32);
2111 #ifdef __powerpc64__
2112 case 570: /* cnttzd */
2113 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2114 goto unknown_opcode;
2115 val = regs->gpr[rd];
2116 op->val = (val ? __builtin_ctzl(val) : 64);
2119 case 922: /* extsh */
2120 op->val = (signed short) regs->gpr[rd];
2123 case 954: /* extsb */
2124 op->val = (signed char) regs->gpr[rd];
2126 #ifdef __powerpc64__
2127 case 986: /* extsw */
2128 op->val = (signed int) regs->gpr[rd];
2133 * Shift instructions
2136 sh = regs->gpr[rb] & 0x3f;
2138 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
2144 sh = regs->gpr[rb] & 0x3f;
2146 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
2151 case 792: /* sraw */
2152 op->type = COMPUTE + SETREG + SETXER;
2153 sh = regs->gpr[rb] & 0x3f;
2154 ival = (signed int) regs->gpr[rd];
2155 op->val = ival >> (sh < 32 ? sh : 31);
2156 op->xerval = regs->xer;
2157 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
2158 op->xerval |= XER_CA;
2160 op->xerval &= ~XER_CA;
2161 set_ca32(op, op->xerval & XER_CA);
2164 case 824: /* srawi */
2165 op->type = COMPUTE + SETREG + SETXER;
2167 ival = (signed int) regs->gpr[rd];
2168 op->val = ival >> sh;
2169 op->xerval = regs->xer;
2170 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2171 op->xerval |= XER_CA;
2173 op->xerval &= ~XER_CA;
2174 set_ca32(op, op->xerval & XER_CA);
2177 #ifdef __powerpc64__
2179 sh = regs->gpr[rb] & 0x7f;
2181 op->val = regs->gpr[rd] << sh;
2187 sh = regs->gpr[rb] & 0x7f;
2189 op->val = regs->gpr[rd] >> sh;
2194 case 794: /* srad */
2195 op->type = COMPUTE + SETREG + SETXER;
2196 sh = regs->gpr[rb] & 0x7f;
2197 ival = (signed long int) regs->gpr[rd];
2198 op->val = ival >> (sh < 64 ? sh : 63);
2199 op->xerval = regs->xer;
2200 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
2201 op->xerval |= XER_CA;
2203 op->xerval &= ~XER_CA;
2204 set_ca32(op, op->xerval & XER_CA);
2207 case 826: /* sradi with sh_5 = 0 */
2208 case 827: /* sradi with sh_5 = 1 */
2209 op->type = COMPUTE + SETREG + SETXER;
2210 sh = rb | ((word & 2) << 4);
2211 ival = (signed long int) regs->gpr[rd];
2212 op->val = ival >> sh;
2213 op->xerval = regs->xer;
2214 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2215 op->xerval |= XER_CA;
2217 op->xerval &= ~XER_CA;
2218 set_ca32(op, op->xerval & XER_CA);
2221 case 890: /* extswsli with sh_5 = 0 */
2222 case 891: /* extswsli with sh_5 = 1 */
2223 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2224 goto unknown_opcode;
2225 op->type = COMPUTE + SETREG;
2226 sh = rb | ((word & 2) << 4);
2227 val = (signed int) regs->gpr[rd];
2229 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2234 #endif /* __powerpc64__ */
2237 * Cache instructions
2239 case 54: /* dcbst */
2240 op->type = MKOP(CACHEOP, DCBST, 0);
2241 op->ea = xform_ea(word, regs);
2245 op->type = MKOP(CACHEOP, DCBF, 0);
2246 op->ea = xform_ea(word, regs);
2249 case 246: /* dcbtst */
2250 op->type = MKOP(CACHEOP, DCBTST, 0);
2251 op->ea = xform_ea(word, regs);
2255 case 278: /* dcbt */
2256 op->type = MKOP(CACHEOP, DCBTST, 0);
2257 op->ea = xform_ea(word, regs);
2261 case 982: /* icbi */
2262 op->type = MKOP(CACHEOP, ICBI, 0);
2263 op->ea = xform_ea(word, regs);
2266 case 1014: /* dcbz */
2267 op->type = MKOP(CACHEOP, DCBZ, 0);
2268 op->ea = xform_ea(word, regs);
2278 op->update_reg = ra;
2280 op->val = regs->gpr[rd];
2281 u = (word >> 20) & UPDATE;
2287 op->ea = xform_ea(word, regs);
2288 switch ((word >> 1) & 0x3ff) {
2289 case 20: /* lwarx */
2290 op->type = MKOP(LARX, 0, 4);
2293 case 150: /* stwcx. */
2294 op->type = MKOP(STCX, 0, 4);
2297 #ifdef __powerpc64__
2298 case 84: /* ldarx */
2299 op->type = MKOP(LARX, 0, 8);
2302 case 214: /* stdcx. */
2303 op->type = MKOP(STCX, 0, 8);
2306 case 52: /* lbarx */
2307 op->type = MKOP(LARX, 0, 1);
2310 case 694: /* stbcx. */
2311 op->type = MKOP(STCX, 0, 1);
2314 case 116: /* lharx */
2315 op->type = MKOP(LARX, 0, 2);
2318 case 726: /* sthcx. */
2319 op->type = MKOP(STCX, 0, 2);
2322 case 276: /* lqarx */
2323 if (!((rd & 1) || rd == ra || rd == rb))
2324 op->type = MKOP(LARX, 0, 16);
2327 case 182: /* stqcx. */
2329 op->type = MKOP(STCX, 0, 16);
2334 case 55: /* lwzux */
2335 op->type = MKOP(LOAD, u, 4);
2339 case 119: /* lbzux */
2340 op->type = MKOP(LOAD, u, 1);
2343 #ifdef CONFIG_ALTIVEC
2345 * Note: for the load/store vector element instructions,
2346 * bits of the EA say which field of the VMX register to use.
2349 op->type = MKOP(LOAD_VMX, 0, 1);
2350 op->element_size = 1;
2353 case 39: /* lvehx */
2354 op->type = MKOP(LOAD_VMX, 0, 2);
2355 op->element_size = 2;
2358 case 71: /* lvewx */
2359 op->type = MKOP(LOAD_VMX, 0, 4);
2360 op->element_size = 4;
2364 case 359: /* lvxl */
2365 op->type = MKOP(LOAD_VMX, 0, 16);
2366 op->element_size = 16;
2369 case 135: /* stvebx */
2370 op->type = MKOP(STORE_VMX, 0, 1);
2371 op->element_size = 1;
2374 case 167: /* stvehx */
2375 op->type = MKOP(STORE_VMX, 0, 2);
2376 op->element_size = 2;
2379 case 199: /* stvewx */
2380 op->type = MKOP(STORE_VMX, 0, 4);
2381 op->element_size = 4;
2384 case 231: /* stvx */
2385 case 487: /* stvxl */
2386 op->type = MKOP(STORE_VMX, 0, 16);
2388 #endif /* CONFIG_ALTIVEC */
2390 #ifdef __powerpc64__
2393 op->type = MKOP(LOAD, u, 8);
2396 case 149: /* stdx */
2397 case 181: /* stdux */
2398 op->type = MKOP(STORE, u, 8);
2402 case 151: /* stwx */
2403 case 183: /* stwux */
2404 op->type = MKOP(STORE, u, 4);
2407 case 215: /* stbx */
2408 case 247: /* stbux */
2409 op->type = MKOP(STORE, u, 1);
2412 case 279: /* lhzx */
2413 case 311: /* lhzux */
2414 op->type = MKOP(LOAD, u, 2);
2417 #ifdef __powerpc64__
2418 case 341: /* lwax */
2419 case 373: /* lwaux */
2420 op->type = MKOP(LOAD, SIGNEXT | u, 4);
2424 case 343: /* lhax */
2425 case 375: /* lhaux */
2426 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2429 case 407: /* sthx */
2430 case 439: /* sthux */
2431 op->type = MKOP(STORE, u, 2);
2434 #ifdef __powerpc64__
2435 case 532: /* ldbrx */
2436 op->type = MKOP(LOAD, BYTEREV, 8);
2440 case 533: /* lswx */
2441 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2444 case 534: /* lwbrx */
2445 op->type = MKOP(LOAD, BYTEREV, 4);
2448 case 597: /* lswi */
2450 rb = 32; /* # bytes to load */
2451 op->type = MKOP(LOAD_MULTI, 0, rb);
2452 op->ea = ra ? regs->gpr[ra] : 0;
2455 #ifdef CONFIG_PPC_FPU
2456 case 535: /* lfsx */
2457 case 567: /* lfsux */
2458 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2461 case 599: /* lfdx */
2462 case 631: /* lfdux */
2463 op->type = MKOP(LOAD_FP, u, 8);
2466 case 663: /* stfsx */
2467 case 695: /* stfsux */
2468 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2471 case 727: /* stfdx */
2472 case 759: /* stfdux */
2473 op->type = MKOP(STORE_FP, u, 8);
2476 #ifdef __powerpc64__
2477 case 791: /* lfdpx */
2478 op->type = MKOP(LOAD_FP, 0, 16);
2481 case 855: /* lfiwax */
2482 op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2485 case 887: /* lfiwzx */
2486 op->type = MKOP(LOAD_FP, 0, 4);
2489 case 919: /* stfdpx */
2490 op->type = MKOP(STORE_FP, 0, 16);
2493 case 983: /* stfiwx */
2494 op->type = MKOP(STORE_FP, 0, 4);
2496 #endif /* __powerpc64 */
2497 #endif /* CONFIG_PPC_FPU */
2499 #ifdef __powerpc64__
2500 case 660: /* stdbrx */
2501 op->type = MKOP(STORE, BYTEREV, 8);
2502 op->val = byterev_8(regs->gpr[rd]);
2506 case 661: /* stswx */
2507 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2510 case 662: /* stwbrx */
2511 op->type = MKOP(STORE, BYTEREV, 4);
2512 op->val = byterev_4(regs->gpr[rd]);
2515 case 725: /* stswi */
2517 rb = 32; /* # bytes to store */
2518 op->type = MKOP(STORE_MULTI, 0, rb);
2519 op->ea = ra ? regs->gpr[ra] : 0;
2522 case 790: /* lhbrx */
2523 op->type = MKOP(LOAD, BYTEREV, 2);
2526 case 918: /* sthbrx */
2527 op->type = MKOP(STORE, BYTEREV, 2);
2528 op->val = byterev_2(regs->gpr[rd]);
2532 case 12: /* lxsiwzx */
2533 op->reg = rd | ((word & 1) << 5);
2534 op->type = MKOP(LOAD_VSX, 0, 4);
2535 op->element_size = 8;
2538 case 76: /* lxsiwax */
2539 op->reg = rd | ((word & 1) << 5);
2540 op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2541 op->element_size = 8;
2544 case 140: /* stxsiwx */
2545 op->reg = rd | ((word & 1) << 5);
2546 op->type = MKOP(STORE_VSX, 0, 4);
2547 op->element_size = 8;
2550 case 268: /* lxvx */
2551 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2552 goto unknown_opcode;
2553 op->reg = rd | ((word & 1) << 5);
2554 op->type = MKOP(LOAD_VSX, 0, 16);
2555 op->element_size = 16;
2556 op->vsx_flags = VSX_CHECK_VEC;
2559 case 269: /* lxvl */
2560 case 301: { /* lxvll */
2562 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2563 goto unknown_opcode;
2564 op->reg = rd | ((word & 1) << 5);
2565 op->ea = ra ? regs->gpr[ra] : 0;
2566 nb = regs->gpr[rb] & 0xff;
2569 op->type = MKOP(LOAD_VSX, 0, nb);
2570 op->element_size = 16;
2571 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2575 case 332: /* lxvdsx */
2576 op->reg = rd | ((word & 1) << 5);
2577 op->type = MKOP(LOAD_VSX, 0, 8);
2578 op->element_size = 8;
2579 op->vsx_flags = VSX_SPLAT;
2582 case 333: /* lxvpx */
2583 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2584 goto unknown_opcode;
2585 op->reg = VSX_REGISTER_XTP(rd);
2586 op->type = MKOP(LOAD_VSX, 0, 32);
2587 op->element_size = 32;
2590 case 364: /* lxvwsx */
2591 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2592 goto unknown_opcode;
2593 op->reg = rd | ((word & 1) << 5);
2594 op->type = MKOP(LOAD_VSX, 0, 4);
2595 op->element_size = 4;
2596 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2599 case 396: /* stxvx */
2600 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2601 goto unknown_opcode;
2602 op->reg = rd | ((word & 1) << 5);
2603 op->type = MKOP(STORE_VSX, 0, 16);
2604 op->element_size = 16;
2605 op->vsx_flags = VSX_CHECK_VEC;
2608 case 397: /* stxvl */
2609 case 429: { /* stxvll */
2611 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2612 goto unknown_opcode;
2613 op->reg = rd | ((word & 1) << 5);
2614 op->ea = ra ? regs->gpr[ra] : 0;
2615 nb = regs->gpr[rb] & 0xff;
2618 op->type = MKOP(STORE_VSX, 0, nb);
2619 op->element_size = 16;
2620 op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2624 case 461: /* stxvpx */
2625 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2626 goto unknown_opcode;
2627 op->reg = VSX_REGISTER_XTP(rd);
2628 op->type = MKOP(STORE_VSX, 0, 32);
2629 op->element_size = 32;
2631 case 524: /* lxsspx */
2632 op->reg = rd | ((word & 1) << 5);
2633 op->type = MKOP(LOAD_VSX, 0, 4);
2634 op->element_size = 8;
2635 op->vsx_flags = VSX_FPCONV;
2638 case 588: /* lxsdx */
2639 op->reg = rd | ((word & 1) << 5);
2640 op->type = MKOP(LOAD_VSX, 0, 8);
2641 op->element_size = 8;
2644 case 652: /* stxsspx */
2645 op->reg = rd | ((word & 1) << 5);
2646 op->type = MKOP(STORE_VSX, 0, 4);
2647 op->element_size = 8;
2648 op->vsx_flags = VSX_FPCONV;
2651 case 716: /* stxsdx */
2652 op->reg = rd | ((word & 1) << 5);
2653 op->type = MKOP(STORE_VSX, 0, 8);
2654 op->element_size = 8;
2657 case 780: /* lxvw4x */
2658 op->reg = rd | ((word & 1) << 5);
2659 op->type = MKOP(LOAD_VSX, 0, 16);
2660 op->element_size = 4;
2663 case 781: /* lxsibzx */
2664 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2665 goto unknown_opcode;
2666 op->reg = rd | ((word & 1) << 5);
2667 op->type = MKOP(LOAD_VSX, 0, 1);
2668 op->element_size = 8;
2669 op->vsx_flags = VSX_CHECK_VEC;
2672 case 812: /* lxvh8x */
2673 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2674 goto unknown_opcode;
2675 op->reg = rd | ((word & 1) << 5);
2676 op->type = MKOP(LOAD_VSX, 0, 16);
2677 op->element_size = 2;
2678 op->vsx_flags = VSX_CHECK_VEC;
2681 case 813: /* lxsihzx */
2682 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2683 goto unknown_opcode;
2684 op->reg = rd | ((word & 1) << 5);
2685 op->type = MKOP(LOAD_VSX, 0, 2);
2686 op->element_size = 8;
2687 op->vsx_flags = VSX_CHECK_VEC;
2690 case 844: /* lxvd2x */
2691 op->reg = rd | ((word & 1) << 5);
2692 op->type = MKOP(LOAD_VSX, 0, 16);
2693 op->element_size = 8;
2696 case 876: /* lxvb16x */
2697 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2698 goto unknown_opcode;
2699 op->reg = rd | ((word & 1) << 5);
2700 op->type = MKOP(LOAD_VSX, 0, 16);
2701 op->element_size = 1;
2702 op->vsx_flags = VSX_CHECK_VEC;
2705 case 908: /* stxvw4x */
2706 op->reg = rd | ((word & 1) << 5);
2707 op->type = MKOP(STORE_VSX, 0, 16);
2708 op->element_size = 4;
2711 case 909: /* stxsibx */
2712 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2713 goto unknown_opcode;
2714 op->reg = rd | ((word & 1) << 5);
2715 op->type = MKOP(STORE_VSX, 0, 1);
2716 op->element_size = 8;
2717 op->vsx_flags = VSX_CHECK_VEC;
2720 case 940: /* stxvh8x */
2721 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2722 goto unknown_opcode;
2723 op->reg = rd | ((word & 1) << 5);
2724 op->type = MKOP(STORE_VSX, 0, 16);
2725 op->element_size = 2;
2726 op->vsx_flags = VSX_CHECK_VEC;
2729 case 941: /* stxsihx */
2730 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2731 goto unknown_opcode;
2732 op->reg = rd | ((word & 1) << 5);
2733 op->type = MKOP(STORE_VSX, 0, 2);
2734 op->element_size = 8;
2735 op->vsx_flags = VSX_CHECK_VEC;
2738 case 972: /* stxvd2x */
2739 op->reg = rd | ((word & 1) << 5);
2740 op->type = MKOP(STORE_VSX, 0, 16);
2741 op->element_size = 8;
2744 case 1004: /* stxvb16x */
2745 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2746 goto unknown_opcode;
2747 op->reg = rd | ((word & 1) << 5);
2748 op->type = MKOP(STORE_VSX, 0, 16);
2749 op->element_size = 1;
2750 op->vsx_flags = VSX_CHECK_VEC;
2753 #endif /* CONFIG_VSX */
2759 op->type = MKOP(LOAD, u, 4);
2760 op->ea = dform_ea(word, regs);
2765 op->type = MKOP(LOAD, u, 1);
2766 op->ea = dform_ea(word, regs);
2771 op->type = MKOP(STORE, u, 4);
2772 op->ea = dform_ea(word, regs);
2777 op->type = MKOP(STORE, u, 1);
2778 op->ea = dform_ea(word, regs);
2783 op->type = MKOP(LOAD, u, 2);
2784 op->ea = dform_ea(word, regs);
2789 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2790 op->ea = dform_ea(word, regs);
2795 op->type = MKOP(STORE, u, 2);
2796 op->ea = dform_ea(word, regs);
2801 break; /* invalid form, ra in range to load */
2802 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2803 op->ea = dform_ea(word, regs);
2807 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2808 op->ea = dform_ea(word, regs);
2811 #ifdef CONFIG_PPC_FPU
2814 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2815 op->ea = dform_ea(word, regs);
2820 op->type = MKOP(LOAD_FP, u, 8);
2821 op->ea = dform_ea(word, regs);
2825 case 53: /* stfsu */
2826 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2827 op->ea = dform_ea(word, regs);
2831 case 55: /* stfdu */
2832 op->type = MKOP(STORE_FP, u, 8);
2833 op->ea = dform_ea(word, regs);
2837 #ifdef __powerpc64__
2839 if (!((rd & 1) || (rd == ra)))
2840 op->type = MKOP(LOAD, 0, 16);
2841 op->ea = dqform_ea(word, regs);
2846 case 57: /* lfdp, lxsd, lxssp */
2847 op->ea = dsform_ea(word, regs);
2851 break; /* reg must be even */
2852 op->type = MKOP(LOAD_FP, 0, 16);
2855 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2856 goto unknown_opcode;
2858 op->type = MKOP(LOAD_VSX, 0, 8);
2859 op->element_size = 8;
2860 op->vsx_flags = VSX_CHECK_VEC;
2863 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2864 goto unknown_opcode;
2866 op->type = MKOP(LOAD_VSX, 0, 4);
2867 op->element_size = 8;
2868 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2872 #endif /* CONFIG_VSX */
2874 #ifdef __powerpc64__
2875 case 58: /* ld[u], lwa */
2876 op->ea = dsform_ea(word, regs);
2879 op->type = MKOP(LOAD, 0, 8);
2882 op->type = MKOP(LOAD, UPDATE, 8);
2885 op->type = MKOP(LOAD, SIGNEXT, 4);
2893 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2894 goto unknown_opcode;
2895 op->ea = dqform_ea(word, regs);
2896 op->reg = VSX_REGISTER_XTP(rd);
2897 op->element_size = 32;
2898 switch (word & 0xf) {
2900 op->type = MKOP(LOAD_VSX, 0, 32);
2903 op->type = MKOP(STORE_VSX, 0, 32);
2908 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */
2910 case 0: /* stfdp with LSB of DS field = 0 */
2911 case 4: /* stfdp with LSB of DS field = 1 */
2912 op->ea = dsform_ea(word, regs);
2913 op->type = MKOP(STORE_FP, 0, 16);
2917 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2918 goto unknown_opcode;
2919 op->ea = dqform_ea(word, regs);
2922 op->type = MKOP(LOAD_VSX, 0, 16);
2923 op->element_size = 16;
2924 op->vsx_flags = VSX_CHECK_VEC;
2927 case 2: /* stxsd with LSB of DS field = 0 */
2928 case 6: /* stxsd with LSB of DS field = 1 */
2929 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2930 goto unknown_opcode;
2931 op->ea = dsform_ea(word, regs);
2933 op->type = MKOP(STORE_VSX, 0, 8);
2934 op->element_size = 8;
2935 op->vsx_flags = VSX_CHECK_VEC;
2938 case 3: /* stxssp with LSB of DS field = 0 */
2939 case 7: /* stxssp with LSB of DS field = 1 */
2940 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2941 goto unknown_opcode;
2942 op->ea = dsform_ea(word, regs);
2944 op->type = MKOP(STORE_VSX, 0, 4);
2945 op->element_size = 8;
2946 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2950 if (!cpu_has_feature(CPU_FTR_ARCH_300))
2951 goto unknown_opcode;
2952 op->ea = dqform_ea(word, regs);
2955 op->type = MKOP(STORE_VSX, 0, 16);
2956 op->element_size = 16;
2957 op->vsx_flags = VSX_CHECK_VEC;
2961 #endif /* CONFIG_VSX */
2963 #ifdef __powerpc64__
2964 case 62: /* std[u] */
2965 op->ea = dsform_ea(word, regs);
2968 op->type = MKOP(STORE, 0, 8);
2971 op->type = MKOP(STORE, UPDATE, 8);
2975 op->type = MKOP(STORE, 0, 16);
2979 case 1: /* Prefixed instructions */
2980 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2981 goto unknown_opcode;
2983 prefix_r = GET_PREFIX_R(word);
2984 ra = GET_PREFIX_RA(suffix);
2985 op->update_reg = ra;
2986 rd = (suffix >> 21) & 0x1f;
2988 op->val = regs->gpr[rd];
2990 suffixopcode = get_op(suffix);
2991 prefixtype = (word >> 24) & 0x3;
2992 switch (prefixtype) {
2993 case 0: /* Type 00 Eight-Byte Load/Store */
2996 op->ea = mlsd_8lsd_ea(word, suffix, regs);
2997 switch (suffixopcode) {
2999 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
3002 case 42: /* plxsd */
3004 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
3005 op->element_size = 8;
3006 op->vsx_flags = VSX_CHECK_VEC;
3008 case 43: /* plxssp */
3010 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
3011 op->element_size = 8;
3012 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
3014 case 46: /* pstxsd */
3016 op->type = MKOP(STORE_VSX, PREFIXED, 8);
3017 op->element_size = 8;
3018 op->vsx_flags = VSX_CHECK_VEC;
3020 case 47: /* pstxssp */
3022 op->type = MKOP(STORE_VSX, PREFIXED, 4);
3023 op->element_size = 8;
3024 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
3026 case 51: /* plxv1 */
3029 case 50: /* plxv0 */
3030 op->type = MKOP(LOAD_VSX, PREFIXED, 16);
3031 op->element_size = 16;
3032 op->vsx_flags = VSX_CHECK_VEC;
3034 case 55: /* pstxv1 */
3037 case 54: /* pstxv0 */
3038 op->type = MKOP(STORE_VSX, PREFIXED, 16);
3039 op->element_size = 16;
3040 op->vsx_flags = VSX_CHECK_VEC;
3042 #endif /* CONFIG_VSX */
3044 op->type = MKOP(LOAD, PREFIXED, 16);
3047 op->type = MKOP(LOAD, PREFIXED, 8);
3050 case 58: /* plxvp */
3051 op->reg = VSX_REGISTER_XTP(rd);
3052 op->type = MKOP(LOAD_VSX, PREFIXED, 32);
3053 op->element_size = 32;
3055 #endif /* CONFIG_VSX */
3057 op->type = MKOP(STORE, PREFIXED, 16);
3060 op->type = MKOP(STORE, PREFIXED, 8);
3063 case 62: /* pstxvp */
3064 op->reg = VSX_REGISTER_XTP(rd);
3065 op->type = MKOP(STORE_VSX, PREFIXED, 32);
3066 op->element_size = 32;
3068 #endif /* CONFIG_VSX */
3071 case 1: /* Type 01 Eight-Byte Register-to-Register */
3073 case 2: /* Type 10 Modified Load/Store */
3076 op->ea = mlsd_8lsd_ea(word, suffix, regs);
3077 switch (suffixopcode) {
3079 op->type = MKOP(LOAD, PREFIXED, 4);
3082 op->type = MKOP(LOAD, PREFIXED, 1);
3085 op->type = MKOP(STORE, PREFIXED, 4);
3088 op->type = MKOP(STORE, PREFIXED, 1);
3091 op->type = MKOP(LOAD, PREFIXED, 2);
3094 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
3097 op->type = MKOP(STORE, PREFIXED, 2);
3100 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
3103 op->type = MKOP(LOAD_FP, PREFIXED, 8);
3105 case 52: /* pstfs */
3106 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
3108 case 54: /* pstfd */
3109 op->type = MKOP(STORE_FP, PREFIXED, 8);
3113 case 3: /* Type 11 Modified Register-to-Register */
3116 #endif /* __powerpc64__ */
3120 if (OP_IS_LOAD_STORE(op->type) && (op->type & UPDATE)) {
3121 switch (GETTYPE(op->type)) {
3124 goto unknown_opcode;
3130 goto unknown_opcode;
3135 if ((GETTYPE(op->type) == LOAD_VSX ||
3136 GETTYPE(op->type) == STORE_VSX) &&
3137 !cpu_has_feature(CPU_FTR_VSX)) {
3140 #endif /* CONFIG_VSX */
3165 op->type = INTERRUPT | 0x700;
3166 op->val = SRR1_PROGPRIV;
3170 op->type = INTERRUPT | 0x700;
3171 op->val = SRR1_PROGTRAP;
3174 EXPORT_SYMBOL_GPL(analyse_instr);
3175 NOKPROBE_SYMBOL(analyse_instr);
3178 * For PPC32 we always use stwu with r1 to change the stack pointer.
3179 * So this emulated store may corrupt the exception frame, now we
3180 * have to provide the exception frame trampoline, which is pushed
3181 * below the kprobed function stack. So we only update gpr[1] but
3182 * don't emulate the real store operation. We will do real store
3183 * operation safely in exception return code by checking this flag.
3185 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
3188 * Check if we already set since that means we'll
3189 * lose the previous value.
3191 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
3192 set_thread_flag(TIF_EMULATE_STACK_STORE);
3196 static nokprobe_inline void do_signext(unsigned long *valp, int size)
3200 *valp = (signed short) *valp;
3203 *valp = (signed int) *valp;
3208 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
3212 *valp = byterev_2(*valp);
3215 *valp = byterev_4(*valp);
3217 #ifdef __powerpc64__
3219 *valp = byterev_8(*valp);
3226 * Emulate an instruction that can be executed just by updating
3229 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
3231 unsigned long next_pc;
3233 next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
3234 switch (GETTYPE(op->type)) {
3236 if (op->type & SETREG)
3237 regs->gpr[op->reg] = op->val;
3238 if (op->type & SETCC)
3239 regs->ccr = op->ccval;
3240 if (op->type & SETXER)
3241 regs->xer = op->xerval;
3245 if (op->type & SETLK)
3246 regs->link = next_pc;
3247 if (op->type & BRTAKEN)
3249 if (op->type & DECCTR)
3254 switch (op->type & BARRIER_MASK) {
3265 case BARRIER_LWSYNC:
3266 asm volatile("lwsync" : : : "memory");
3268 case BARRIER_PTESYNC:
3269 asm volatile("ptesync" : : : "memory");
3278 regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
3281 regs->gpr[op->reg] = regs->link;
3284 regs->gpr[op->reg] = regs->ctr;
3294 regs->xer = op->val & 0xffffffffUL;
3297 regs->link = op->val;
3300 regs->ctr = op->val;
3310 regs_set_return_ip(regs, next_pc);
3312 NOKPROBE_SYMBOL(emulate_update_regs);
3315 * Emulate a previously-analysed load or store instruction.
3316 * Return values are:
3317 * 0 = instruction emulated successfully
3318 * -EFAULT = address out of range or access faulted (regs->dar
3319 * contains the faulting address)
3320 * -EACCES = misaligned access, instruction requires alignment
3321 * -EINVAL = unknown operation in *op
3323 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
3325 int err, size, type;
3333 size = GETSIZE(op->type);
3334 type = GETTYPE(op->type);
3335 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
3336 ea = truncate_if_32bit(regs->msr, op->ea);
3340 if (ea & (size - 1))
3341 return -EACCES; /* can't handle misaligned */
3342 if (!address_ok(regs, ea, size))
3347 #ifdef __powerpc64__
3349 __get_user_asmx(val, ea, err, "lbarx");
3352 __get_user_asmx(val, ea, err, "lharx");
3356 __get_user_asmx(val, ea, err, "lwarx");
3358 #ifdef __powerpc64__
3360 __get_user_asmx(val, ea, err, "ldarx");
3363 err = do_lqarx(ea, ®s->gpr[op->reg]);
3374 regs->gpr[op->reg] = val;
3378 if (ea & (size - 1))
3379 return -EACCES; /* can't handle misaligned */
3380 if (!address_ok(regs, ea, size))
3384 #ifdef __powerpc64__
3386 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3389 __put_user_asmx(op->val, ea, err, "sthcx.", cr);
3393 __put_user_asmx(op->val, ea, err, "stwcx.", cr);
3395 #ifdef __powerpc64__
3397 __put_user_asmx(op->val, ea, err, "stdcx.", cr);
3400 err = do_stqcx(ea, regs->gpr[op->reg],
3401 regs->gpr[op->reg + 1], &cr);
3408 regs->ccr = (regs->ccr & 0x0fffffff) |
3410 ((regs->xer >> 3) & 0x10000000);
3416 #ifdef __powerpc64__
3418 err = emulate_lq(regs, ea, op->reg, cross_endian);
3422 err = read_mem(®s->gpr[op->reg], ea, size, regs);
3424 if (op->type & SIGNEXT)
3425 do_signext(®s->gpr[op->reg], size);
3426 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
3427 do_byterev(®s->gpr[op->reg], size);
3431 #ifdef CONFIG_PPC_FPU
3434 * If the instruction is in userspace, we can emulate it even
3435 * if the VMX state is not live, because we have the state
3436 * stored in the thread_struct. If the instruction is in
3437 * the kernel, we must not touch the state in the thread_struct.
3439 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3441 err = do_fp_load(op, ea, regs, cross_endian);
3444 #ifdef CONFIG_ALTIVEC
3446 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3448 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3453 unsigned long msrbit = MSR_VSX;
3456 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3457 * when the target of the instruction is a vector register.
3459 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3461 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3463 err = do_vsx_load(op, ea, regs, cross_endian);
3468 if (!address_ok(regs, ea, size))
3471 for (i = 0; i < size; i += 4) {
3472 unsigned int v32 = 0;
3477 err = copy_mem_in((u8 *) &v32, ea, nb, regs);
3480 if (unlikely(cross_endian))
3481 v32 = byterev_4(v32);
3482 regs->gpr[rd] = v32;
3484 /* reg number wraps from 31 to 0 for lsw[ix] */
3485 rd = (rd + 1) & 0x1f;
3490 #ifdef __powerpc64__
3492 err = emulate_stq(regs, ea, op->reg, cross_endian);
3496 if ((op->type & UPDATE) && size == sizeof(long) &&
3497 op->reg == 1 && op->update_reg == 1 &&
3498 !(regs->msr & MSR_PR) &&
3499 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
3500 err = handle_stack_update(ea, regs);
3503 if (unlikely(cross_endian))
3504 do_byterev(&op->val, size);
3505 err = write_mem(op->val, ea, size, regs);
3508 #ifdef CONFIG_PPC_FPU
3510 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3512 err = do_fp_store(op, ea, regs, cross_endian);
3515 #ifdef CONFIG_ALTIVEC
3517 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3519 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3524 unsigned long msrbit = MSR_VSX;
3527 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3528 * when the target of the instruction is a vector register.
3530 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3532 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3534 err = do_vsx_store(op, ea, regs, cross_endian);
3539 if (!address_ok(regs, ea, size))
3542 for (i = 0; i < size; i += 4) {
3543 unsigned int v32 = regs->gpr[rd];
3548 if (unlikely(cross_endian))
3549 v32 = byterev_4(v32);
3550 err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3554 /* reg number wraps from 31 to 0 for stsw[ix] */
3555 rd = (rd + 1) & 0x1f;
3566 if (op->type & UPDATE)
3567 regs->gpr[op->update_reg] = op->ea;
3571 NOKPROBE_SYMBOL(emulate_loadstore);
3574 * Emulate instructions that cause a transfer of control,
3575 * loads and stores, and a few other instructions.
3576 * Returns 1 if the step was emulated, 0 if not,
3577 * or -1 if the instruction is one that should not be stepped,
3578 * such as an rfid, or a mtmsrd that would clear MSR_RI.
3580 int emulate_step(struct pt_regs *regs, ppc_inst_t instr)
3582 struct instruction_op op;
3587 r = analyse_instr(&op, regs, instr);
3591 emulate_update_regs(regs, &op);
3596 type = GETTYPE(op.type);
3598 if (OP_IS_LOAD_STORE(type)) {
3599 err = emulate_loadstore(regs, &op);
3607 ea = truncate_if_32bit(regs->msr, op.ea);
3608 if (!address_ok(regs, ea, 8))
3610 switch (op.type & CACHEOP_MASK) {
3612 __cacheop_user_asmx(ea, err, "dcbst");
3615 __cacheop_user_asmx(ea, err, "dcbf");
3619 prefetchw((void *) ea);
3623 prefetch((void *) ea);
3626 __cacheop_user_asmx(ea, err, "icbi");
3629 err = emulate_dcbz(ea, regs);
3639 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3643 val = regs->gpr[op.reg];
3644 if ((val & MSR_RI) == 0)
3645 /* can't step mtmsr[d] that would clear MSR_RI */
3647 /* here op.val is the mask of bits to change */
3648 regs_set_return_msr(regs, (regs->msr & ~op.val) | (val & op.val));
3651 case SYSCALL: /* sc */
3653 * Per ISA v3.1, section 7.5.15 'Trace Interrupt', we can't
3654 * single step a system call instruction:
3656 * Successful completion for an instruction means that the
3657 * instruction caused no other interrupt. Thus a Trace
3658 * interrupt never occurs for a System Call or System Call
3659 * Vectored instruction, or for a Trap instruction that
3663 case SYSCALL_VECTORED_0: /* scv 0 */
3671 regs_set_return_ip(regs,
3672 truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type)));
3675 NOKPROBE_SYMBOL(emulate_step);