arch/powerpc/lib/sstep.c

   1 /*
   2  * Single-step support.
   3  *
   4  * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version
   9  * 2 of the License, or (at your option) any later version.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/kprobes.h>
  13 #include <linux/ptrace.h>
  14 #include <linux/prefetch.h>
  15 #include <asm/sstep.h>
  16 #include <asm/processor.h>
  17 #include <linux/uaccess.h>
  18 #include <asm/cpu_has_feature.h>
  19 #include <asm/cputable.h>
  20
  21 extern char system_call_common[];
  22
  23 #ifdef CONFIG_PPC64
  24 /* Bits in SRR1 that are copied from MSR */
  25 #define MSR_MASK        0xffffffff87c0ffffUL
  26 #else
  27 #define MSR_MASK        0x87c0ffff
  28 #endif
  29
  30 /* Bits in XER */
  31 #define XER_SO          0x80000000U
  32 #define XER_OV          0x40000000U
  33 #define XER_CA          0x20000000U
  34
  35 #ifdef CONFIG_PPC_FPU
  36 /*
  37  * Functions in ldstfp.S
  38  */
  39 extern void get_fpr(int rn, double *p);
  40 extern void put_fpr(int rn, const double *p);
  41 extern void get_vr(int rn, __vector128 *p);
  42 extern void put_vr(int rn, __vector128 *p);
  43 extern void load_vsrn(int vsr, const void *p);
  44 extern void store_vsrn(int vsr, void *p);
  45 extern void conv_sp_to_dp(const float *sp, double *dp);
  46 extern void conv_dp_to_sp(const double *dp, float *sp);
  47 #endif
  48
  49 #ifdef __powerpc64__
  50 /*
  51  * Functions in quad.S
  52  */
  53 extern int do_lq(unsigned long ea, unsigned long *regs);
  54 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
  55 extern int do_lqarx(unsigned long ea, unsigned long *regs);
  56 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
  57                     unsigned int *crp);
  58 #endif
  59
  60 #ifdef __LITTLE_ENDIAN__
  61 #define IS_LE   1
  62 #define IS_BE   0
  63 #else
  64 #define IS_LE   0
  65 #define IS_BE   1
  66 #endif
  67
  68 /*
  69  * Emulate the truncation of 64 bit values in 32-bit mode.
  70  */
  71 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
  72                                                         unsigned long val)
  73 {
  74 #ifdef __powerpc64__
  75         if ((msr & MSR_64BIT) == 0)
  76                 val &= 0xffffffffUL;
  77 #endif
  78         return val;
  79 }
  80
  81 /*
  82  * Determine whether a conditional branch instruction would branch.
  83  */
  84 static nokprobe_inline int branch_taken(unsigned int instr,
  85                                         const struct pt_regs *regs,
  86                                         struct instruction_op *op)
  87 {
  88         unsigned int bo = (instr >> 21) & 0x1f;
  89         unsigned int bi;
  90
  91         if ((bo & 4) == 0) {
  92                 /* decrement counter */
  93                 op->type |= DECCTR;
  94                 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
  95                         return 0;
  96         }
  97         if ((bo & 0x10) == 0) {
  98                 /* check bit from CR */
  99                 bi = (instr >> 16) & 0x1f;
 100                 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
 101                         return 0;
 102         }
 103         return 1;
 104 }
 105
 106 static nokprobe_inline long address_ok(struct pt_regs *regs,
 107                                        unsigned long ea, int nb)
 108 {
 109         if (!user_mode(regs))
 110                 return 1;
 111         if (__access_ok(ea, nb, USER_DS))
 112                 return 1;
 113         if (__access_ok(ea, 1, USER_DS))
 114                 /* Access overlaps the end of the user region */
 115                 regs->dar = USER_DS.seg;
 116         else
 117                 regs->dar = ea;
 118         return 0;
 119 }
 120
 121 /*
 122  * Calculate effective address for a D-form instruction
 123  */
 124 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
 125                                               const struct pt_regs *regs)
 126 {
 127         int ra;
 128         unsigned long ea;
 129
 130         ra = (instr >> 16) & 0x1f;
 131         ea = (signed short) instr;              /* sign-extend */
 132         if (ra)
 133                 ea += regs->gpr[ra];
 134
 135         return ea;
 136 }
 137
 138 #ifdef __powerpc64__
 139 /*
 140  * Calculate effective address for a DS-form instruction
 141  */
 142 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
 143                                                const struct pt_regs *regs)
 144 {
 145         int ra;
 146         unsigned long ea;
 147
 148         ra = (instr >> 16) & 0x1f;
 149         ea = (signed short) (instr & ~3);       /* sign-extend */
 150         if (ra)
 151                 ea += regs->gpr[ra];
 152
 153         return ea;
 154 }
 155
 156 /*
 157  * Calculate effective address for a DQ-form instruction
 158  */
 159 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
 160                                                const struct pt_regs *regs)
 161 {
 162         int ra;
 163         unsigned long ea;
 164
 165         ra = (instr >> 16) & 0x1f;
 166         ea = (signed short) (instr & ~0xf);     /* sign-extend */
 167         if (ra)
 168                 ea += regs->gpr[ra];
 169
 170         return ea;
 171 }
 172 #endif /* __powerpc64 */
 173
 174 /*
 175  * Calculate effective address for an X-form instruction
 176  */
 177 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
 178                                               const struct pt_regs *regs)
 179 {
 180         int ra, rb;
 181         unsigned long ea;
 182
 183         ra = (instr >> 16) & 0x1f;
 184         rb = (instr >> 11) & 0x1f;
 185         ea = regs->gpr[rb];
 186         if (ra)
 187                 ea += regs->gpr[ra];
 188
 189         return ea;
 190 }
 191
 192 /*
 193  * Return the largest power of 2, not greater than sizeof(unsigned long),
 194  * such that x is a multiple of it.
 195  */
 196 static nokprobe_inline unsigned long max_align(unsigned long x)
 197 {
 198         x |= sizeof(unsigned long);
 199         return x & -x;          /* isolates rightmost bit */
 200 }
 201
 202 static nokprobe_inline unsigned long byterev_2(unsigned long x)
 203 {
 204         return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
 205 }
 206
 207 static nokprobe_inline unsigned long byterev_4(unsigned long x)
 208 {
 209         return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
 210                 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
 211 }
 212
 213 #ifdef __powerpc64__
 214 static nokprobe_inline unsigned long byterev_8(unsigned long x)
 215 {
 216         return (byterev_4(x) << 32) | byterev_4(x >> 32);
 217 }
 218 #endif
 219
 220 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
 221 {
 222         switch (nb) {
 223         case 2:
 224                 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
 225                 break;
 226         case 4:
 227                 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
 228                 break;
 229 #ifdef __powerpc64__
 230         case 8:
 231                 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
 232                 break;
 233         case 16: {
 234                 unsigned long *up = (unsigned long *)ptr;
 235                 unsigned long tmp;
 236                 tmp = byterev_8(up[0]);
 237                 up[0] = byterev_8(up[1]);
 238                 up[1] = tmp;
 239                 break;
 240         }
 241 #endif
 242         default:
 243                 WARN_ON_ONCE(1);
 244         }
 245 }
 246
 247 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
 248                                             unsigned long ea, int nb,
 249                                             struct pt_regs *regs)
 250 {
 251         int err = 0;
 252         unsigned long x = 0;
 253
 254         switch (nb) {
 255         case 1:
 256                 err = __get_user(x, (unsigned char __user *) ea);
 257                 break;
 258         case 2:
 259                 err = __get_user(x, (unsigned short __user *) ea);
 260                 break;
 261         case 4:
 262                 err = __get_user(x, (unsigned int __user *) ea);
 263                 break;
 264 #ifdef __powerpc64__
 265         case 8:
 266                 err = __get_user(x, (unsigned long __user *) ea);
 267                 break;
 268 #endif
 269         }
 270         if (!err)
 271                 *dest = x;
 272         else
 273                 regs->dar = ea;
 274         return err;
 275 }
 276
 277 /*
 278  * Copy from userspace to a buffer, using the largest possible
 279  * aligned accesses, up to sizeof(long).
 280  */
 281 static int nokprobe_inline copy_mem_in(u8 *dest, unsigned long ea, int nb,
 282                                        struct pt_regs *regs)
 283 {
 284         int err = 0;
 285         int c;
 286
 287         for (; nb > 0; nb -= c) {
 288                 c = max_align(ea);
 289                 if (c > nb)
 290                         c = max_align(nb);
 291                 switch (c) {
 292                 case 1:
 293                         err = __get_user(*dest, (unsigned char __user *) ea);
 294                         break;
 295                 case 2:
 296                         err = __get_user(*(u16 *)dest,
 297                                          (unsigned short __user *) ea);
 298                         break;
 299                 case 4:
 300                         err = __get_user(*(u32 *)dest,
 301                                          (unsigned int __user *) ea);
 302                         break;
 303 #ifdef __powerpc64__
 304                 case 8:
 305                         err = __get_user(*(unsigned long *)dest,
 306                                          (unsigned long __user *) ea);
 307                         break;
 308 #endif
 309                 }
 310                 if (err) {
 311                         regs->dar = ea;
 312                         return err;
 313                 }
 314                 dest += c;
 315                 ea += c;
 316         }
 317         return 0;
 318 }
 319
 320 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
 321                                               unsigned long ea, int nb,
 322                                               struct pt_regs *regs)
 323 {
 324         union {
 325                 unsigned long ul;
 326                 u8 b[sizeof(unsigned long)];
 327         } u;
 328         int i;
 329         int err;
 330
 331         u.ul = 0;
 332         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 333         err = copy_mem_in(&u.b[i], ea, nb, regs);
 334         if (!err)
 335                 *dest = u.ul;
 336         return err;
 337 }
 338
 339 /*
 340  * Read memory at address ea for nb bytes, return 0 for success
 341  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 342  * If nb < sizeof(long), the result is right-justified on BE systems.
 343  */
 344 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
 345                               struct pt_regs *regs)
 346 {
 347         if (!address_ok(regs, ea, nb))
 348                 return -EFAULT;
 349         if ((ea & (nb - 1)) == 0)
 350                 return read_mem_aligned(dest, ea, nb, regs);
 351         return read_mem_unaligned(dest, ea, nb, regs);
 352 }
 353 NOKPROBE_SYMBOL(read_mem);
 354
 355 static nokprobe_inline int write_mem_aligned(unsigned long val,
 356                                              unsigned long ea, int nb,
 357                                              struct pt_regs *regs)
 358 {
 359         int err = 0;
 360
 361         switch (nb) {
 362         case 1:
 363                 err = __put_user(val, (unsigned char __user *) ea);
 364                 break;
 365         case 2:
 366                 err = __put_user(val, (unsigned short __user *) ea);
 367                 break;
 368         case 4:
 369                 err = __put_user(val, (unsigned int __user *) ea);
 370                 break;
 371 #ifdef __powerpc64__
 372         case 8:
 373                 err = __put_user(val, (unsigned long __user *) ea);
 374                 break;
 375 #endif
 376         }
 377         if (err)
 378                 regs->dar = ea;
 379         return err;
 380 }
 381
 382 /*
 383  * Copy from a buffer to userspace, using the largest possible
 384  * aligned accesses, up to sizeof(long).
 385  */
 386 static int nokprobe_inline copy_mem_out(u8 *dest, unsigned long ea, int nb,
 387                                         struct pt_regs *regs)
 388 {
 389         int err = 0;
 390         int c;
 391
 392         for (; nb > 0; nb -= c) {
 393                 c = max_align(ea);
 394                 if (c > nb)
 395                         c = max_align(nb);
 396                 switch (c) {
 397                 case 1:
 398                         err = __put_user(*dest, (unsigned char __user *) ea);
 399                         break;
 400                 case 2:
 401                         err = __put_user(*(u16 *)dest,
 402                                          (unsigned short __user *) ea);
 403                         break;
 404                 case 4:
 405                         err = __put_user(*(u32 *)dest,
 406                                          (unsigned int __user *) ea);
 407                         break;
 408 #ifdef __powerpc64__
 409                 case 8:
 410                         err = __put_user(*(unsigned long *)dest,
 411                                          (unsigned long __user *) ea);
 412                         break;
 413 #endif
 414                 }
 415                 if (err) {
 416                         regs->dar = ea;
 417                         return err;
 418                 }
 419                 dest += c;
 420                 ea += c;
 421         }
 422         return 0;
 423 }
 424
 425 static nokprobe_inline int write_mem_unaligned(unsigned long val,
 426                                                unsigned long ea, int nb,
 427                                                struct pt_regs *regs)
 428 {
 429         union {
 430                 unsigned long ul;
 431                 u8 b[sizeof(unsigned long)];
 432         } u;
 433         int i;
 434
 435         u.ul = val;
 436         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 437         return copy_mem_out(&u.b[i], ea, nb, regs);
 438 }
 439
 440 /*
 441  * Write memory at address ea for nb bytes, return 0 for success
 442  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 443  */
 444 static int write_mem(unsigned long val, unsigned long ea, int nb,
 445                                struct pt_regs *regs)
 446 {
 447         if (!address_ok(regs, ea, nb))
 448                 return -EFAULT;
 449         if ((ea & (nb - 1)) == 0)
 450                 return write_mem_aligned(val, ea, nb, regs);
 451         return write_mem_unaligned(val, ea, nb, regs);
 452 }
 453 NOKPROBE_SYMBOL(write_mem);
 454
 455 #ifdef CONFIG_PPC_FPU
 456 /*
 457  * These access either the real FP register or the image in the
 458  * thread_struct, depending on regs->msr & MSR_FP.
 459  */
 460 static int do_fp_load(struct instruction_op *op, unsigned long ea,
 461                       struct pt_regs *regs, bool cross_endian)
 462 {
 463         int err, rn, nb;
 464         union {
 465                 int i;
 466                 unsigned int u;
 467                 float f;
 468                 double d[2];
 469                 unsigned long l[2];
 470                 u8 b[2 * sizeof(double)];
 471         } u;
 472
 473         nb = GETSIZE(op->type);
 474         if (!address_ok(regs, ea, nb))
 475                 return -EFAULT;
 476         rn = op->reg;
 477         err = copy_mem_in(u.b, ea, nb, regs);
 478         if (err)
 479                 return err;
 480         if (unlikely(cross_endian)) {
 481                 do_byte_reverse(u.b, min(nb, 8));
 482                 if (nb == 16)
 483                         do_byte_reverse(&u.b[8], 8);
 484         }
 485         preempt_disable();
 486         if (nb == 4) {
 487                 if (op->type & FPCONV)
 488                         conv_sp_to_dp(&u.f, &u.d[0]);
 489                 else if (op->type & SIGNEXT)
 490                         u.l[0] = u.i;
 491                 else
 492                         u.l[0] = u.u;
 493         }
 494         if (regs->msr & MSR_FP)
 495                 put_fpr(rn, &u.d[0]);
 496         else
 497                 current->thread.TS_FPR(rn) = u.l[0];
 498         if (nb == 16) {
 499                 /* lfdp */
 500                 rn |= 1;
 501                 if (regs->msr & MSR_FP)
 502                         put_fpr(rn, &u.d[1]);
 503                 else
 504                         current->thread.TS_FPR(rn) = u.l[1];
 505         }
 506         preempt_enable();
 507         return 0;
 508 }
 509 NOKPROBE_SYMBOL(do_fp_load);
 510
 511 static int do_fp_store(struct instruction_op *op, unsigned long ea,
 512                        struct pt_regs *regs, bool cross_endian)
 513 {
 514         int rn, nb;
 515         union {
 516                 unsigned int u;
 517                 float f;
 518                 double d[2];
 519                 unsigned long l[2];
 520                 u8 b[2 * sizeof(double)];
 521         } u;
 522
 523         nb = GETSIZE(op->type);
 524         if (!address_ok(regs, ea, nb))
 525                 return -EFAULT;
 526         rn = op->reg;
 527         preempt_disable();
 528         if (regs->msr & MSR_FP)
 529                 get_fpr(rn, &u.d[0]);
 530         else
 531                 u.l[0] = current->thread.TS_FPR(rn);
 532         if (nb == 4) {
 533                 if (op->type & FPCONV)
 534                         conv_dp_to_sp(&u.d[0], &u.f);
 535                 else
 536                         u.u = u.l[0];
 537         }
 538         if (nb == 16) {
 539                 rn |= 1;
 540                 if (regs->msr & MSR_FP)
 541                         get_fpr(rn, &u.d[1]);
 542                 else
 543                         u.l[1] = current->thread.TS_FPR(rn);
 544         }
 545         preempt_enable();
 546         if (unlikely(cross_endian)) {
 547                 do_byte_reverse(u.b, min(nb, 8));
 548                 if (nb == 16)
 549                         do_byte_reverse(&u.b[8], 8);
 550         }
 551         return copy_mem_out(u.b, ea, nb, regs);
 552 }
 553 NOKPROBE_SYMBOL(do_fp_store);
 554 #endif
 555
 556 #ifdef CONFIG_ALTIVEC
 557 /* For Altivec/VMX, no need to worry about alignment */
 558 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
 559                                        int size, struct pt_regs *regs,
 560                                        bool cross_endian)
 561 {
 562         int err;
 563         union {
 564                 __vector128 v;
 565                 u8 b[sizeof(__vector128)];
 566         } u = {};
 567
 568         if (!address_ok(regs, ea & ~0xfUL, 16))
 569                 return -EFAULT;
 570         /* align to multiple of size */
 571         ea &= ~(size - 1);
 572         err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
 573         if (err)
 574                 return err;
 575         if (unlikely(cross_endian))
 576                 do_byte_reverse(&u.b[ea & 0xf], size);
 577         preempt_disable();
 578         if (regs->msr & MSR_VEC)
 579                 put_vr(rn, &u.v);
 580         else
 581                 current->thread.vr_state.vr[rn] = u.v;
 582         preempt_enable();
 583         return 0;
 584 }
 585
 586 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
 587                                         int size, struct pt_regs *regs,
 588                                         bool cross_endian)
 589 {
 590         union {
 591                 __vector128 v;
 592                 u8 b[sizeof(__vector128)];
 593         } u;
 594
 595         if (!address_ok(regs, ea & ~0xfUL, 16))
 596                 return -EFAULT;
 597         /* align to multiple of size */
 598         ea &= ~(size - 1);
 599
 600         preempt_disable();
 601         if (regs->msr & MSR_VEC)
 602                 get_vr(rn, &u.v);
 603         else
 604                 u.v = current->thread.vr_state.vr[rn];
 605         preempt_enable();
 606         if (unlikely(cross_endian))
 607                 do_byte_reverse(&u.b[ea & 0xf], size);
 608         return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
 609 }
 610 #endif /* CONFIG_ALTIVEC */
 611
 612 #ifdef __powerpc64__
 613 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
 614                                       int reg, bool cross_endian)
 615 {
 616         int err;
 617
 618         if (!address_ok(regs, ea, 16))
 619                 return -EFAULT;
 620         /* if aligned, should be atomic */
 621         if ((ea & 0xf) == 0) {
 622                 err = do_lq(ea, &regs->gpr[reg]);
 623         } else {
 624                 err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);
 625                 if (!err)
 626                         err = read_mem(&regs->gpr[reg + IS_BE], ea + 8, 8, regs);
 627         }
 628         if (!err && unlikely(cross_endian))
 629                 do_byte_reverse(&regs->gpr[reg], 16);
 630         return err;
 631 }
 632
 633 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
 634                                        int reg, bool cross_endian)
 635 {
 636         int err;
 637         unsigned long vals[2];
 638
 639         if (!address_ok(regs, ea, 16))
 640                 return -EFAULT;
 641         vals[0] = regs->gpr[reg];
 642         vals[1] = regs->gpr[reg + 1];
 643         if (unlikely(cross_endian))
 644                 do_byte_reverse(vals, 16);
 645
 646         /* if aligned, should be atomic */
 647         if ((ea & 0xf) == 0)
 648                 return do_stq(ea, vals[0], vals[1]);
 649
 650         err = write_mem(vals[IS_LE], ea, 8, regs);
 651         if (!err)
 652                 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
 653         return err;
 654 }
 655 #endif /* __powerpc64 */
 656
 657 #ifdef CONFIG_VSX
 658 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
 659                       const void *mem, bool rev)
 660 {
 661         int size, read_size;
 662         int i, j;
 663         const unsigned int *wp;
 664         const unsigned short *hp;
 665         const unsigned char *bp;
 666
 667         size = GETSIZE(op->type);
 668         reg->d[0] = reg->d[1] = 0;
 669
 670         switch (op->element_size) {
 671         case 16:
 672                 /* whole vector; lxv[x] or lxvl[l] */
 673                 if (size == 0)
 674                         break;
 675                 memcpy(reg, mem, size);
 676                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 677                         rev = !rev;
 678                 if (rev)
 679                         do_byte_reverse(reg, 16);
 680                 break;
 681         case 8:
 682                 /* scalar loads, lxvd2x, lxvdsx */
 683                 read_size = (size >= 8) ? 8 : size;
 684                 i = IS_LE ? 8 : 8 - read_size;
 685                 memcpy(&reg->b[i], mem, read_size);
 686                 if (rev)
 687                         do_byte_reverse(&reg->b[i], 8);
 688                 if (size < 8) {
 689                         if (op->type & SIGNEXT) {
 690                                 /* size == 4 is the only case here */
 691                                 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
 692                         } else if (op->vsx_flags & VSX_FPCONV) {
 693                                 preempt_disable();
 694                                 conv_sp_to_dp(&reg->fp[1 + IS_LE],
 695                                               &reg->dp[IS_LE]);
 696                                 preempt_enable();
 697                         }
 698                 } else {
 699                         if (size == 16) {
 700                                 unsigned long v = *(unsigned long *)(mem + 8);
 701                                 reg->d[IS_BE] = !rev ? v : byterev_8(v);
 702                         } else if (op->vsx_flags & VSX_SPLAT)
 703                                 reg->d[IS_BE] = reg->d[IS_LE];
 704                 }
 705                 break;
 706         case 4:
 707                 /* lxvw4x, lxvwsx */
 708                 wp = mem;
 709                 for (j = 0; j < size / 4; ++j) {
 710                         i = IS_LE ? 3 - j : j;
 711                         reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
 712                 }
 713                 if (op->vsx_flags & VSX_SPLAT) {
 714                         u32 val = reg->w[IS_LE ? 3 : 0];
 715                         for (; j < 4; ++j) {
 716                                 i = IS_LE ? 3 - j : j;
 717                                 reg->w[i] = val;
 718                         }
 719                 }
 720                 break;
 721         case 2:
 722                 /* lxvh8x */
 723                 hp = mem;
 724                 for (j = 0; j < size / 2; ++j) {
 725                         i = IS_LE ? 7 - j : j;
 726                         reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
 727                 }
 728                 break;
 729         case 1:
 730                 /* lxvb16x */
 731                 bp = mem;
 732                 for (j = 0; j < size; ++j) {
 733                         i = IS_LE ? 15 - j : j;
 734                         reg->b[i] = *bp++;
 735                 }
 736                 break;
 737         }
 738 }
 739 EXPORT_SYMBOL_GPL(emulate_vsx_load);
 740 NOKPROBE_SYMBOL(emulate_vsx_load);
 741
 742 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
 743                        void *mem, bool rev)
 744 {
 745         int size, write_size;
 746         int i, j;
 747         union vsx_reg buf;
 748         unsigned int *wp;
 749         unsigned short *hp;
 750         unsigned char *bp;
 751
 752         size = GETSIZE(op->type);
 753
 754         switch (op->element_size) {
 755         case 16:
 756                 /* stxv, stxvx, stxvl, stxvll */
 757                 if (size == 0)
 758                         break;
 759                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 760                         rev = !rev;
 761                 if (rev) {
 762                         /* reverse 16 bytes */
 763                         buf.d[0] = byterev_8(reg->d[1]);
 764                         buf.d[1] = byterev_8(reg->d[0]);
 765                         reg = &buf;
 766                 }
 767                 memcpy(mem, reg, size);
 768                 break;
 769         case 8:
 770                 /* scalar stores, stxvd2x */
 771                 write_size = (size >= 8) ? 8 : size;
 772                 i = IS_LE ? 8 : 8 - write_size;
 773                 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
 774                         buf.d[0] = buf.d[1] = 0;
 775                         preempt_disable();
 776                         conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);
 777                         preempt_enable();
 778                         reg = &buf;
 779                 }
 780                 memcpy(mem, &reg->b[i], write_size);
 781                 if (size == 16)
 782                         memcpy(mem + 8, &reg->d[IS_BE], 8);
 783                 if (unlikely(rev)) {
 784                         do_byte_reverse(mem, write_size);
 785                         if (size == 16)
 786                                 do_byte_reverse(mem + 8, 8);
 787                 }
 788                 break;
 789         case 4:
 790                 /* stxvw4x */
 791                 wp = mem;
 792                 for (j = 0; j < size / 4; ++j) {
 793                         i = IS_LE ? 3 - j : j;
 794                         *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
 795                 }
 796                 break;
 797         case 2:
 798                 /* stxvh8x */
 799                 hp = mem;
 800                 for (j = 0; j < size / 2; ++j) {
 801                         i = IS_LE ? 7 - j : j;
 802                         *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
 803                 }
 804                 break;
 805         case 1:
 806                 /* stvxb16x */
 807                 bp = mem;
 808                 for (j = 0; j < size; ++j) {
 809                         i = IS_LE ? 15 - j : j;
 810                         *bp++ = reg->b[i];
 811                 }
 812                 break;
 813         }
 814 }
 815 EXPORT_SYMBOL_GPL(emulate_vsx_store);
 816 NOKPROBE_SYMBOL(emulate_vsx_store);
 817
 818 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
 819                                        unsigned long ea, struct pt_regs *regs,
 820                                        bool cross_endian)
 821 {
 822         int reg = op->reg;
 823         u8 mem[16];
 824         union vsx_reg buf;
 825         int size = GETSIZE(op->type);
 826
 827         if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
 828                 return -EFAULT;
 829
 830         emulate_vsx_load(op, &buf, mem, cross_endian);
 831         preempt_disable();
 832         if (reg < 32) {
 833                 /* FP regs + extensions */
 834                 if (regs->msr & MSR_FP) {
 835                         load_vsrn(reg, &buf);
 836                 } else {
 837                         current->thread.fp_state.fpr[reg][0] = buf.d[0];
 838                         current->thread.fp_state.fpr[reg][1] = buf.d[1];
 839                 }
 840         } else {
 841                 if (regs->msr & MSR_VEC)
 842                         load_vsrn(reg, &buf);
 843                 else
 844                         current->thread.vr_state.vr[reg - 32] = buf.v;
 845         }
 846         preempt_enable();
 847         return 0;
 848 }
 849
 850 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
 851                                         unsigned long ea, struct pt_regs *regs,
 852                                         bool cross_endian)
 853 {
 854         int reg = op->reg;
 855         u8 mem[16];
 856         union vsx_reg buf;
 857         int size = GETSIZE(op->type);
 858
 859         if (!address_ok(regs, ea, size))
 860                 return -EFAULT;
 861
 862         preempt_disable();
 863         if (reg < 32) {
 864                 /* FP regs + extensions */
 865                 if (regs->msr & MSR_FP) {
 866                         store_vsrn(reg, &buf);
 867                 } else {
 868                         buf.d[0] = current->thread.fp_state.fpr[reg][0];
 869                         buf.d[1] = current->thread.fp_state.fpr[reg][1];
 870                 }
 871         } else {
 872                 if (regs->msr & MSR_VEC)
 873                         store_vsrn(reg, &buf);
 874                 else
 875                         buf.v = current->thread.vr_state.vr[reg - 32];
 876         }
 877         preempt_enable();
 878         emulate_vsx_store(op, &buf, mem, cross_endian);
 879         return  copy_mem_out(mem, ea, size, regs);
 880 }
 881 #endif /* CONFIG_VSX */
 882
 883 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
 884 {
 885         int err;
 886         unsigned long i, size;
 887
 888 #ifdef __powerpc64__
 889         size = ppc64_caches.l1d.block_size;
 890         if (!(regs->msr & MSR_64BIT))
 891                 ea &= 0xffffffffUL;
 892 #else
 893         size = L1_CACHE_BYTES;
 894 #endif
 895         ea &= ~(size - 1);
 896         if (!address_ok(regs, ea, size))
 897                 return -EFAULT;
 898         for (i = 0; i < size; i += sizeof(long)) {
 899                 err = __put_user(0, (unsigned long __user *) (ea + i));
 900                 if (err) {
 901                         regs->dar = ea;
 902                         return err;
 903                 }
 904         }
 905         return 0;
 906 }
 907 NOKPROBE_SYMBOL(emulate_dcbz);
 908
 909 #define __put_user_asmx(x, addr, err, op, cr)           \
 910         __asm__ __volatile__(                           \
 911                 ".machine push\n"                       \
 912                 ".machine power8\n"                     \
 913                 "1:     " op " %2,0,%3\n"               \
 914                 ".machine pop\n"                        \
 915                 "       mfcr    %1\n"                   \
 916                 "2:\n"                                  \
 917                 ".section .fixup,\"ax\"\n"              \
 918                 "3:     li      %0,%4\n"                \
 919                 "       b       2b\n"                   \
 920                 ".previous\n"                           \
 921                 EX_TABLE(1b, 3b)                        \
 922                 : "=r" (err), "=r" (cr)                 \
 923                 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
 924
 925 #define __get_user_asmx(x, addr, err, op)               \
 926         __asm__ __volatile__(                           \
 927                 ".machine push\n"                       \
 928                 ".machine power8\n"                     \
 929                 "1:     "op" %1,0,%2\n"                 \
 930                 ".machine pop\n"                        \
 931                 "2:\n"                                  \
 932                 ".section .fixup,\"ax\"\n"              \
 933                 "3:     li      %0,%3\n"                \
 934                 "       b       2b\n"                   \
 935                 ".previous\n"                           \
 936                 EX_TABLE(1b, 3b)                        \
 937                 : "=r" (err), "=r" (x)                  \
 938                 : "r" (addr), "i" (-EFAULT), "0" (err))
 939
 940 #define __cacheop_user_asmx(addr, err, op)              \
 941         __asm__ __volatile__(                           \
 942                 "1:     "op" 0,%1\n"                    \
 943                 "2:\n"                                  \
 944                 ".section .fixup,\"ax\"\n"              \
 945                 "3:     li      %0,%3\n"                \
 946                 "       b       2b\n"                   \
 947                 ".previous\n"                           \
 948                 EX_TABLE(1b, 3b)                        \
 949                 : "=r" (err)                            \
 950                 : "r" (addr), "i" (-EFAULT), "0" (err))
 951
 952 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
 953                                     struct instruction_op *op)
 954 {
 955         long val = op->val;
 956
 957         op->type |= SETCC;
 958         op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
 959 #ifdef __powerpc64__
 960         if (!(regs->msr & MSR_64BIT))
 961                 val = (int) val;
 962 #endif
 963         if (val < 0)
 964                 op->ccval |= 0x80000000;
 965         else if (val > 0)
 966                 op->ccval |= 0x40000000;
 967         else
 968                 op->ccval |= 0x20000000;
 969 }
 970
 971 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
 972                                      struct instruction_op *op, int rd,
 973                                      unsigned long val1, unsigned long val2,
 974                                      unsigned long carry_in)
 975 {
 976         unsigned long val = val1 + val2;
 977
 978         if (carry_in)
 979                 ++val;
 980         op->type = COMPUTE + SETREG + SETXER;
 981         op->reg = rd;
 982         op->val = val;
 983 #ifdef __powerpc64__
 984         if (!(regs->msr & MSR_64BIT)) {
 985                 val = (unsigned int) val;
 986                 val1 = (unsigned int) val1;
 987         }
 988 #endif
 989         op->xerval = regs->xer;
 990         if (val < val1 || (carry_in && val == val1))
 991                 op->xerval |= XER_CA;
 992         else
 993                 op->xerval &= ~XER_CA;
 994 }
 995
 996 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
 997                                           struct instruction_op *op,
 998                                           long v1, long v2, int crfld)
 999 {
1000         unsigned int crval, shift;
1001
1002         op->type = COMPUTE + SETCC;
1003         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1004         if (v1 < v2)
1005                 crval |= 8;
1006         else if (v1 > v2)
1007                 crval |= 4;
1008         else
1009                 crval |= 2;
1010         shift = (7 - crfld) * 4;
1011         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1012 }
1013
1014 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1015                                             struct instruction_op *op,
1016                                             unsigned long v1,
1017                                             unsigned long v2, int crfld)
1018 {
1019         unsigned int crval, shift;
1020
1021         op->type = COMPUTE + SETCC;
1022         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1023         if (v1 < v2)
1024                 crval |= 8;
1025         else if (v1 > v2)
1026                 crval |= 4;
1027         else
1028                 crval |= 2;
1029         shift = (7 - crfld) * 4;
1030         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1031 }
1032
1033 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1034                                     struct instruction_op *op,
1035                                     unsigned long v1, unsigned long v2)
1036 {
1037         unsigned long long out_val, mask;
1038         int i;
1039
1040         out_val = 0;
1041         for (i = 0; i < 8; i++) {
1042                 mask = 0xffUL << (i * 8);
1043                 if ((v1 & mask) == (v2 & mask))
1044                         out_val |= mask;
1045         }
1046         op->val = out_val;
1047 }
1048
1049 /*
1050  * The size parameter is used to adjust the equivalent popcnt instruction.
1051  * popcntb = 8, popcntw = 32, popcntd = 64
1052  */
1053 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1054                                       struct instruction_op *op,
1055                                       unsigned long v1, int size)
1056 {
1057         unsigned long long out = v1;
1058
1059         out -= (out >> 1) & 0x5555555555555555;
1060         out = (0x3333333333333333 & out) + (0x3333333333333333 & (out >> 2));
1061         out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0f;
1062
1063         if (size == 8) {        /* popcntb */
1064                 op->val = out;
1065                 return;
1066         }
1067         out += out >> 8;
1068         out += out >> 16;
1069         if (size == 32) {       /* popcntw */
1070                 op->val = out & 0x0000003f0000003f;
1071                 return;
1072         }
1073
1074         out = (out + (out >> 32)) & 0x7f;
1075         op->val = out;  /* popcntd */
1076 }
1077
1078 #ifdef CONFIG_PPC64
1079 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1080                                       struct instruction_op *op,
1081                                       unsigned long v1, unsigned long v2)
1082 {
1083         unsigned char perm, idx;
1084         unsigned int i;
1085
1086         perm = 0;
1087         for (i = 0; i < 8; i++) {
1088                 idx = (v1 >> (i * 8)) & 0xff;
1089                 if (idx < 64)
1090                         if (v2 & PPC_BIT(idx))
1091                                 perm |= 1 << i;
1092         }
1093         op->val = perm;
1094 }
1095 #endif /* CONFIG_PPC64 */
1096 /*
1097  * The size parameter adjusts the equivalent prty instruction.
1098  * prtyw = 32, prtyd = 64
1099  */
1100 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1101                                     struct instruction_op *op,
1102                                     unsigned long v, int size)
1103 {
1104         unsigned long long res = v ^ (v >> 8);
1105
1106         res ^= res >> 16;
1107         if (size == 32) {               /* prtyw */
1108                 op->val = res & 0x0000000100000001;
1109                 return;
1110         }
1111
1112         res ^= res >> 32;
1113         op->val = res & 1;      /*prtyd */
1114 }
1115
1116 static nokprobe_inline int trap_compare(long v1, long v2)
1117 {
1118         int ret = 0;
1119
1120         if (v1 < v2)
1121                 ret |= 0x10;
1122         else if (v1 > v2)
1123                 ret |= 0x08;
1124         else
1125                 ret |= 0x04;
1126         if ((unsigned long)v1 < (unsigned long)v2)
1127                 ret |= 0x02;
1128         else if ((unsigned long)v1 > (unsigned long)v2)
1129                 ret |= 0x01;
1130         return ret;
1131 }
1132
1133 /*
1134  * Elements of 32-bit rotate and mask instructions.
1135  */
1136 #define MASK32(mb, me)  ((0xffffffffUL >> (mb)) + \
1137                          ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1138 #ifdef __powerpc64__
1139 #define MASK64_L(mb)    (~0UL >> (mb))
1140 #define MASK64_R(me)    ((signed long)-0x8000000000000000L >> (me))
1141 #define MASK64(mb, me)  (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1142 #define DATA32(x)       (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1143 #else
1144 #define DATA32(x)       (x)
1145 #endif
1146 #define ROTATE(x, n)    ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1147
1148 /*
1149  * Decode an instruction, and return information about it in *op
1150  * without changing *regs.
1151  * Integer arithmetic and logical instructions, branches, and barrier
1152  * instructions can be emulated just using the information in *op.
1153  *
1154  * Return value is 1 if the instruction can be emulated just by
1155  * updating *regs with the information in *op, -1 if we need the
1156  * GPRs but *regs doesn't contain the full register set, or 0
1157  * otherwise.
1158  */
1159 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1160                   unsigned int instr)
1161 {
1162         unsigned int opcode, ra, rb, rd, spr, u;
1163         unsigned long int imm;
1164         unsigned long int val, val2;
1165         unsigned int mb, me, sh;
1166         long ival;
1167
1168         op->type = COMPUTE;
1169
1170         opcode = instr >> 26;
1171         switch (opcode) {
1172         case 16:        /* bc */
1173                 op->type = BRANCH;
1174                 imm = (signed short)(instr & 0xfffc);
1175                 if ((instr & 2) == 0)
1176                         imm += regs->nip;
1177                 op->val = truncate_if_32bit(regs->msr, imm);
1178                 if (instr & 1)
1179                         op->type |= SETLK;
1180                 if (branch_taken(instr, regs, op))
1181                         op->type |= BRTAKEN;
1182                 return 1;
1183 #ifdef CONFIG_PPC64
1184         case 17:        /* sc */
1185                 if ((instr & 0xfe2) == 2)
1186                         op->type = SYSCALL;
1187                 else
1188                         op->type = UNKNOWN;
1189                 return 0;
1190 #endif
1191         case 18:        /* b */
1192                 op->type = BRANCH | BRTAKEN;
1193                 imm = instr & 0x03fffffc;
1194                 if (imm & 0x02000000)
1195                         imm -= 0x04000000;
1196                 if ((instr & 2) == 0)
1197                         imm += regs->nip;
1198                 op->val = truncate_if_32bit(regs->msr, imm);
1199                 if (instr & 1)
1200                         op->type |= SETLK;
1201                 return 1;
1202         case 19:
1203                 switch ((instr >> 1) & 0x3ff) {
1204                 case 0:         /* mcrf */
1205                         op->type = COMPUTE + SETCC;
1206                         rd = 7 - ((instr >> 23) & 0x7);
1207                         ra = 7 - ((instr >> 18) & 0x7);
1208                         rd *= 4;
1209                         ra *= 4;
1210                         val = (regs->ccr >> ra) & 0xf;
1211                         op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1212                         return 1;
1213
1214                 case 16:        /* bclr */
1215                 case 528:       /* bcctr */
1216                         op->type = BRANCH;
1217                         imm = (instr & 0x400)? regs->ctr: regs->link;
1218                         op->val = truncate_if_32bit(regs->msr, imm);
1219                         if (instr & 1)
1220                                 op->type |= SETLK;
1221                         if (branch_taken(instr, regs, op))
1222                                 op->type |= BRTAKEN;
1223                         return 1;
1224
1225                 case 18:        /* rfid, scary */
1226                         if (regs->msr & MSR_PR)
1227                                 goto priv;
1228                         op->type = RFI;
1229                         return 0;
1230
1231                 case 150:       /* isync */
1232                         op->type = BARRIER | BARRIER_ISYNC;
1233                         return 1;
1234
1235                 case 33:        /* crnor */
1236                 case 129:       /* crandc */
1237                 case 193:       /* crxor */
1238                 case 225:       /* crnand */
1239                 case 257:       /* crand */
1240                 case 289:       /* creqv */
1241                 case 417:       /* crorc */
1242                 case 449:       /* cror */
1243                         op->type = COMPUTE + SETCC;
1244                         ra = (instr >> 16) & 0x1f;
1245                         rb = (instr >> 11) & 0x1f;
1246                         rd = (instr >> 21) & 0x1f;
1247                         ra = (regs->ccr >> (31 - ra)) & 1;
1248                         rb = (regs->ccr >> (31 - rb)) & 1;
1249                         val = (instr >> (6 + ra * 2 + rb)) & 1;
1250                         op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1251                                 (val << (31 - rd));
1252                         return 1;
1253                 }
1254                 break;
1255         case 31:
1256                 switch ((instr >> 1) & 0x3ff) {
1257                 case 598:       /* sync */
1258                         op->type = BARRIER + BARRIER_SYNC;
1259 #ifdef __powerpc64__
1260                         switch ((instr >> 21) & 3) {
1261                         case 1:         /* lwsync */
1262                                 op->type = BARRIER + BARRIER_LWSYNC;
1263                                 break;
1264                         case 2:         /* ptesync */
1265                                 op->type = BARRIER + BARRIER_PTESYNC;
1266                                 break;
1267                         }
1268 #endif
1269                         return 1;
1270
1271                 case 854:       /* eieio */
1272                         op->type = BARRIER + BARRIER_EIEIO;
1273                         return 1;
1274                 }
1275                 break;
1276         }
1277
1278         /* Following cases refer to regs->gpr[], so we need all regs */
1279         if (!FULL_REGS(regs))
1280                 return -1;
1281
1282         rd = (instr >> 21) & 0x1f;
1283         ra = (instr >> 16) & 0x1f;
1284         rb = (instr >> 11) & 0x1f;
1285
1286         switch (opcode) {
1287 #ifdef __powerpc64__
1288         case 2:         /* tdi */
1289                 if (rd & trap_compare(regs->gpr[ra], (short) instr))
1290                         goto trap;
1291                 return 1;
1292 #endif
1293         case 3:         /* twi */
1294                 if (rd & trap_compare((int)regs->gpr[ra], (short) instr))
1295                         goto trap;
1296                 return 1;
1297
1298         case 7:         /* mulli */
1299                 op->val = regs->gpr[ra] * (short) instr;
1300                 goto compute_done;
1301
1302         case 8:         /* subfic */
1303                 imm = (short) instr;
1304                 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1305                 return 1;
1306
1307         case 10:        /* cmpli */
1308                 imm = (unsigned short) instr;
1309                 val = regs->gpr[ra];
1310 #ifdef __powerpc64__
1311                 if ((rd & 1) == 0)
1312                         val = (unsigned int) val;
1313 #endif
1314                 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1315                 return 1;
1316
1317         case 11:        /* cmpi */
1318                 imm = (short) instr;
1319                 val = regs->gpr[ra];
1320 #ifdef __powerpc64__
1321                 if ((rd & 1) == 0)
1322                         val = (int) val;
1323 #endif
1324                 do_cmp_signed(regs, op, val, imm, rd >> 2);
1325                 return 1;
1326
1327         case 12:        /* addic */
1328                 imm = (short) instr;
1329                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1330                 return 1;
1331
1332         case 13:        /* addic. */
1333                 imm = (short) instr;
1334                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1335                 set_cr0(regs, op);
1336                 return 1;
1337
1338         case 14:        /* addi */
1339                 imm = (short) instr;
1340                 if (ra)
1341                         imm += regs->gpr[ra];
1342                 op->val = imm;
1343                 goto compute_done;
1344
1345         case 15:        /* addis */
1346                 imm = ((short) instr) << 16;
1347                 if (ra)
1348                         imm += regs->gpr[ra];
1349                 op->val = imm;
1350                 goto compute_done;
1351
1352         case 19:
1353                 if (((instr >> 1) & 0x1f) == 2) {
1354                         /* addpcis */
1355                         imm = (short) (instr & 0xffc1); /* d0 + d2 fields */
1356                         imm |= (instr >> 15) & 0x3e;    /* d1 field */
1357                         op->val = regs->nip + (imm << 16) + 4;
1358                         goto compute_done;
1359                 }
1360                 op->type = UNKNOWN;
1361                 return 0;
1362
1363         case 20:        /* rlwimi */
1364                 mb = (instr >> 6) & 0x1f;
1365                 me = (instr >> 1) & 0x1f;
1366                 val = DATA32(regs->gpr[rd]);
1367                 imm = MASK32(mb, me);
1368                 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1369                 goto logical_done;
1370
1371         case 21:        /* rlwinm */
1372                 mb = (instr >> 6) & 0x1f;
1373                 me = (instr >> 1) & 0x1f;
1374                 val = DATA32(regs->gpr[rd]);
1375                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1376                 goto logical_done;
1377
1378         case 23:        /* rlwnm */
1379                 mb = (instr >> 6) & 0x1f;
1380                 me = (instr >> 1) & 0x1f;
1381                 rb = regs->gpr[rb] & 0x1f;
1382                 val = DATA32(regs->gpr[rd]);
1383                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1384                 goto logical_done;
1385
1386         case 24:        /* ori */
1387                 op->val = regs->gpr[rd] | (unsigned short) instr;
1388                 goto logical_done_nocc;
1389
1390         case 25:        /* oris */
1391                 imm = (unsigned short) instr;
1392                 op->val = regs->gpr[rd] | (imm << 16);
1393                 goto logical_done_nocc;
1394
1395         case 26:        /* xori */
1396                 op->val = regs->gpr[rd] ^ (unsigned short) instr;
1397                 goto logical_done_nocc;
1398
1399         case 27:        /* xoris */
1400                 imm = (unsigned short) instr;
1401                 op->val = regs->gpr[rd] ^ (imm << 16);
1402                 goto logical_done_nocc;
1403
1404         case 28:        /* andi. */
1405                 op->val = regs->gpr[rd] & (unsigned short) instr;
1406                 set_cr0(regs, op);
1407                 goto logical_done_nocc;
1408
1409         case 29:        /* andis. */
1410                 imm = (unsigned short) instr;
1411                 op->val = regs->gpr[rd] & (imm << 16);
1412                 set_cr0(regs, op);
1413                 goto logical_done_nocc;
1414
1415 #ifdef __powerpc64__
1416         case 30:        /* rld* */
1417                 mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
1418                 val = regs->gpr[rd];
1419                 if ((instr & 0x10) == 0) {
1420                         sh = rb | ((instr & 2) << 4);
1421                         val = ROTATE(val, sh);
1422                         switch ((instr >> 2) & 3) {
1423                         case 0:         /* rldicl */
1424                                 val &= MASK64_L(mb);
1425                                 break;
1426                         case 1:         /* rldicr */
1427                                 val &= MASK64_R(mb);
1428                                 break;
1429                         case 2:         /* rldic */
1430                                 val &= MASK64(mb, 63 - sh);
1431                                 break;
1432                         case 3:         /* rldimi */
1433                                 imm = MASK64(mb, 63 - sh);
1434                                 val = (regs->gpr[ra] & ~imm) |
1435                                         (val & imm);
1436                         }
1437                         op->val = val;
1438                         goto logical_done;
1439                 } else {
1440                         sh = regs->gpr[rb] & 0x3f;
1441                         val = ROTATE(val, sh);
1442                         switch ((instr >> 1) & 7) {
1443                         case 0:         /* rldcl */
1444                                 op->val = val & MASK64_L(mb);
1445                                 goto logical_done;
1446                         case 1:         /* rldcr */
1447                                 op->val = val & MASK64_R(mb);
1448                                 goto logical_done;
1449                         }
1450                 }
1451 #endif
1452                 op->type = UNKNOWN;     /* illegal instruction */
1453                 return 0;
1454
1455         case 31:
1456                 /* isel occupies 32 minor opcodes */
1457                 if (((instr >> 1) & 0x1f) == 15) {
1458                         mb = (instr >> 6) & 0x1f; /* bc field */
1459                         val = (regs->ccr >> (31 - mb)) & 1;
1460                         val2 = (ra) ? regs->gpr[ra] : 0;
1461
1462                         op->val = (val) ? val2 : regs->gpr[rb];
1463                         goto compute_done;
1464                 }
1465
1466                 switch ((instr >> 1) & 0x3ff) {
1467                 case 4:         /* tw */
1468                         if (rd == 0x1f ||
1469                             (rd & trap_compare((int)regs->gpr[ra],
1470                                                (int)regs->gpr[rb])))
1471                                 goto trap;
1472                         return 1;
1473 #ifdef __powerpc64__
1474                 case 68:        /* td */
1475                         if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1476                                 goto trap;
1477                         return 1;
1478 #endif
1479                 case 83:        /* mfmsr */
1480                         if (regs->msr & MSR_PR)
1481                                 goto priv;
1482                         op->type = MFMSR;
1483                         op->reg = rd;
1484                         return 0;
1485                 case 146:       /* mtmsr */
1486                         if (regs->msr & MSR_PR)
1487                                 goto priv;
1488                         op->type = MTMSR;
1489                         op->reg = rd;
1490                         op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1491                         return 0;
1492 #ifdef CONFIG_PPC64
1493                 case 178:       /* mtmsrd */
1494                         if (regs->msr & MSR_PR)
1495                                 goto priv;
1496                         op->type = MTMSR;
1497                         op->reg = rd;
1498                         /* only MSR_EE and MSR_RI get changed if bit 15 set */
1499                         /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1500                         imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1501                         op->val = imm;
1502                         return 0;
1503 #endif
1504
1505                 case 19:        /* mfcr */
1506                         imm = 0xffffffffUL;
1507                         if ((instr >> 20) & 1) {
1508                                 imm = 0xf0000000UL;
1509                                 for (sh = 0; sh < 8; ++sh) {
1510                                         if (instr & (0x80000 >> sh))
1511                                                 break;
1512                                         imm >>= 4;
1513                                 }
1514                         }
1515                         op->val = regs->ccr & imm;
1516                         goto compute_done;
1517
1518                 case 144:       /* mtcrf */
1519                         op->type = COMPUTE + SETCC;
1520                         imm = 0xf0000000UL;
1521                         val = regs->gpr[rd];
1522                         op->ccval = regs->ccr;
1523                         for (sh = 0; sh < 8; ++sh) {
1524                                 if (instr & (0x80000 >> sh))
1525                                         op->ccval = (op->ccval & ~imm) |
1526                                                 (val & imm);
1527                                 imm >>= 4;
1528                         }
1529                         return 1;
1530
1531                 case 339:       /* mfspr */
1532                         spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1533                         op->type = MFSPR;
1534                         op->reg = rd;
1535                         op->spr = spr;
1536                         if (spr == SPRN_XER || spr == SPRN_LR ||
1537                             spr == SPRN_CTR)
1538                                 return 1;
1539                         return 0;
1540
1541                 case 467:       /* mtspr */
1542                         spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1543                         op->type = MTSPR;
1544                         op->val = regs->gpr[rd];
1545                         op->spr = spr;
1546                         if (spr == SPRN_XER || spr == SPRN_LR ||
1547                             spr == SPRN_CTR)
1548                                 return 1;
1549                         return 0;
1550
1551 /*
1552  * Compare instructions
1553  */
1554                 case 0: /* cmp */
1555                         val = regs->gpr[ra];
1556                         val2 = regs->gpr[rb];
1557 #ifdef __powerpc64__
1558                         if ((rd & 1) == 0) {
1559                                 /* word (32-bit) compare */
1560                                 val = (int) val;
1561                                 val2 = (int) val2;
1562                         }
1563 #endif
1564                         do_cmp_signed(regs, op, val, val2, rd >> 2);
1565                         return 1;
1566
1567                 case 32:        /* cmpl */
1568                         val = regs->gpr[ra];
1569                         val2 = regs->gpr[rb];
1570 #ifdef __powerpc64__
1571                         if ((rd & 1) == 0) {
1572                                 /* word (32-bit) compare */
1573                                 val = (unsigned int) val;
1574                                 val2 = (unsigned int) val2;
1575                         }
1576 #endif
1577                         do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1578                         return 1;
1579
1580                 case 508: /* cmpb */
1581                         do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1582                         goto logical_done_nocc;
1583
1584 /*
1585  * Arithmetic instructions
1586  */
1587                 case 8: /* subfc */
1588                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1589                                        regs->gpr[rb], 1);
1590                         goto arith_done;
1591 #ifdef __powerpc64__
1592                 case 9: /* mulhdu */
1593                         asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1594                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1595                         goto arith_done;
1596 #endif
1597                 case 10:        /* addc */
1598                         add_with_carry(regs, op, rd, regs->gpr[ra],
1599                                        regs->gpr[rb], 0);
1600                         goto arith_done;
1601
1602                 case 11:        /* mulhwu */
1603                         asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1604                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1605                         goto arith_done;
1606
1607                 case 40:        /* subf */
1608                         op->val = regs->gpr[rb] - regs->gpr[ra];
1609                         goto arith_done;
1610 #ifdef __powerpc64__
1611                 case 73:        /* mulhd */
1612                         asm("mulhd %0,%1,%2" : "=r" (op->val) :
1613                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1614                         goto arith_done;
1615 #endif
1616                 case 75:        /* mulhw */
1617                         asm("mulhw %0,%1,%2" : "=r" (op->val) :
1618                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1619                         goto arith_done;
1620
1621                 case 104:       /* neg */
1622                         op->val = -regs->gpr[ra];
1623                         goto arith_done;
1624
1625                 case 136:       /* subfe */
1626                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1627                                        regs->gpr[rb], regs->xer & XER_CA);
1628                         goto arith_done;
1629
1630                 case 138:       /* adde */
1631                         add_with_carry(regs, op, rd, regs->gpr[ra],
1632                                        regs->gpr[rb], regs->xer & XER_CA);
1633                         goto arith_done;
1634
1635                 case 200:       /* subfze */
1636                         add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1637                                        regs->xer & XER_CA);
1638                         goto arith_done;
1639
1640                 case 202:       /* addze */
1641                         add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1642                                        regs->xer & XER_CA);
1643                         goto arith_done;
1644
1645                 case 232:       /* subfme */
1646                         add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1647                                        regs->xer & XER_CA);
1648                         goto arith_done;
1649 #ifdef __powerpc64__
1650                 case 233:       /* mulld */
1651                         op->val = regs->gpr[ra] * regs->gpr[rb];
1652                         goto arith_done;
1653 #endif
1654                 case 234:       /* addme */
1655                         add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1656                                        regs->xer & XER_CA);
1657                         goto arith_done;
1658
1659                 case 235:       /* mullw */
1660                         op->val = (long)(int) regs->gpr[ra] *
1661                                 (int) regs->gpr[rb];
1662
1663                         goto arith_done;
1664
1665                 case 266:       /* add */
1666                         op->val = regs->gpr[ra] + regs->gpr[rb];
1667                         goto arith_done;
1668 #ifdef __powerpc64__
1669                 case 457:       /* divdu */
1670                         op->val = regs->gpr[ra] / regs->gpr[rb];
1671                         goto arith_done;
1672 #endif
1673                 case 459:       /* divwu */
1674                         op->val = (unsigned int) regs->gpr[ra] /
1675                                 (unsigned int) regs->gpr[rb];
1676                         goto arith_done;
1677 #ifdef __powerpc64__
1678                 case 489:       /* divd */
1679                         op->val = (long int) regs->gpr[ra] /
1680                                 (long int) regs->gpr[rb];
1681                         goto arith_done;
1682 #endif
1683                 case 491:       /* divw */
1684                         op->val = (int) regs->gpr[ra] /
1685                                 (int) regs->gpr[rb];
1686                         goto arith_done;
1687
1688
1689 /*
1690  * Logical instructions
1691  */
1692                 case 26:        /* cntlzw */
1693                         val = (unsigned int) regs->gpr[rd];
1694                         op->val = ( val ? __builtin_clz(val) : 32 );
1695                         goto logical_done;
1696 #ifdef __powerpc64__
1697                 case 58:        /* cntlzd */
1698                         val = regs->gpr[rd];
1699                         op->val = ( val ? __builtin_clzl(val) : 64 );
1700                         goto logical_done;
1701 #endif
1702                 case 28:        /* and */
1703                         op->val = regs->gpr[rd] & regs->gpr[rb];
1704                         goto logical_done;
1705
1706                 case 60:        /* andc */
1707                         op->val = regs->gpr[rd] & ~regs->gpr[rb];
1708                         goto logical_done;
1709
1710                 case 122:       /* popcntb */
1711                         do_popcnt(regs, op, regs->gpr[rd], 8);
1712                         goto logical_done_nocc;
1713
1714                 case 124:       /* nor */
1715                         op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1716                         goto logical_done;
1717
1718                 case 154:       /* prtyw */
1719                         do_prty(regs, op, regs->gpr[rd], 32);
1720                         goto logical_done_nocc;
1721
1722                 case 186:       /* prtyd */
1723                         do_prty(regs, op, regs->gpr[rd], 64);
1724                         goto logical_done_nocc;
1725 #ifdef CONFIG_PPC64
1726                 case 252:       /* bpermd */
1727                         do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1728                         goto logical_done_nocc;
1729 #endif
1730                 case 284:       /* xor */
1731                         op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1732                         goto logical_done;
1733
1734                 case 316:       /* xor */
1735                         op->val = regs->gpr[rd] ^ regs->gpr[rb];
1736                         goto logical_done;
1737
1738                 case 378:       /* popcntw */
1739                         do_popcnt(regs, op, regs->gpr[rd], 32);
1740                         goto logical_done_nocc;
1741
1742                 case 412:       /* orc */
1743                         op->val = regs->gpr[rd] | ~regs->gpr[rb];
1744                         goto logical_done;
1745
1746                 case 444:       /* or */
1747                         op->val = regs->gpr[rd] | regs->gpr[rb];
1748                         goto logical_done;
1749
1750                 case 476:       /* nand */
1751                         op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1752                         goto logical_done;
1753 #ifdef CONFIG_PPC64
1754                 case 506:       /* popcntd */
1755                         do_popcnt(regs, op, regs->gpr[rd], 64);
1756                         goto logical_done_nocc;
1757 #endif
1758                 case 922:       /* extsh */
1759                         op->val = (signed short) regs->gpr[rd];
1760                         goto logical_done;
1761
1762                 case 954:       /* extsb */
1763                         op->val = (signed char) regs->gpr[rd];
1764                         goto logical_done;
1765 #ifdef __powerpc64__
1766                 case 986:       /* extsw */
1767                         op->val = (signed int) regs->gpr[rd];
1768                         goto logical_done;
1769 #endif
1770
1771 /*
1772  * Shift instructions
1773  */
1774                 case 24:        /* slw */
1775                         sh = regs->gpr[rb] & 0x3f;
1776                         if (sh < 32)
1777                                 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1778                         else
1779                                 op->val = 0;
1780                         goto logical_done;
1781
1782                 case 536:       /* srw */
1783                         sh = regs->gpr[rb] & 0x3f;
1784                         if (sh < 32)
1785                                 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
1786                         else
1787                                 op->val = 0;
1788                         goto logical_done;
1789
1790                 case 792:       /* sraw */
1791                         op->type = COMPUTE + SETREG + SETXER;
1792                         sh = regs->gpr[rb] & 0x3f;
1793                         ival = (signed int) regs->gpr[rd];
1794                         op->val = ival >> (sh < 32 ? sh : 31);
1795                         op->xerval = regs->xer;
1796                         if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
1797                                 op->xerval |= XER_CA;
1798                         else
1799                                 op->xerval &= ~XER_CA;
1800                         goto logical_done;
1801
1802                 case 824:       /* srawi */
1803                         op->type = COMPUTE + SETREG + SETXER;
1804                         sh = rb;
1805                         ival = (signed int) regs->gpr[rd];
1806                         op->val = ival >> sh;
1807                         op->xerval = regs->xer;
1808                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1809                                 op->xerval |= XER_CA;
1810                         else
1811                                 op->xerval &= ~XER_CA;
1812                         goto logical_done;
1813
1814 #ifdef __powerpc64__
1815                 case 27:        /* sld */
1816                         sh = regs->gpr[rb] & 0x7f;
1817                         if (sh < 64)
1818                                 op->val = regs->gpr[rd] << sh;
1819                         else
1820                                 op->val = 0;
1821                         goto logical_done;
1822
1823                 case 539:       /* srd */
1824                         sh = regs->gpr[rb] & 0x7f;
1825                         if (sh < 64)
1826                                 op->val = regs->gpr[rd] >> sh;
1827                         else
1828                                 op->val = 0;
1829                         goto logical_done;
1830
1831                 case 794:       /* srad */
1832                         op->type = COMPUTE + SETREG + SETXER;
1833                         sh = regs->gpr[rb] & 0x7f;
1834                         ival = (signed long int) regs->gpr[rd];
1835                         op->val = ival >> (sh < 64 ? sh : 63);
1836                         op->xerval = regs->xer;
1837                         if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
1838                                 op->xerval |= XER_CA;
1839                         else
1840                                 op->xerval &= ~XER_CA;
1841                         goto logical_done;
1842
1843                 case 826:       /* sradi with sh_5 = 0 */
1844                 case 827:       /* sradi with sh_5 = 1 */
1845                         op->type = COMPUTE + SETREG + SETXER;
1846                         sh = rb | ((instr & 2) << 4);
1847                         ival = (signed long int) regs->gpr[rd];
1848                         op->val = ival >> sh;
1849                         op->xerval = regs->xer;
1850                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1851                                 op->xerval |= XER_CA;
1852                         else
1853                                 op->xerval &= ~XER_CA;
1854                         goto logical_done;
1855 #endif /* __powerpc64__ */
1856
1857 /*
1858  * Cache instructions
1859  */
1860                 case 54:        /* dcbst */
1861                         op->type = MKOP(CACHEOP, DCBST, 0);
1862                         op->ea = xform_ea(instr, regs);
1863                         return 0;
1864
1865                 case 86:        /* dcbf */
1866                         op->type = MKOP(CACHEOP, DCBF, 0);
1867                         op->ea = xform_ea(instr, regs);
1868                         return 0;
1869
1870                 case 246:       /* dcbtst */
1871                         op->type = MKOP(CACHEOP, DCBTST, 0);
1872                         op->ea = xform_ea(instr, regs);
1873                         op->reg = rd;
1874                         return 0;
1875
1876                 case 278:       /* dcbt */
1877                         op->type = MKOP(CACHEOP, DCBTST, 0);
1878                         op->ea = xform_ea(instr, regs);
1879                         op->reg = rd;
1880                         return 0;
1881
1882                 case 982:       /* icbi */
1883                         op->type = MKOP(CACHEOP, ICBI, 0);
1884                         op->ea = xform_ea(instr, regs);
1885                         return 0;
1886
1887                 case 1014:      /* dcbz */
1888                         op->type = MKOP(CACHEOP, DCBZ, 0);
1889                         op->ea = xform_ea(instr, regs);
1890                         return 0;
1891                 }
1892                 break;
1893         }
1894
1895 /*
1896  * Loads and stores.
1897  */
1898         op->type = UNKNOWN;
1899         op->update_reg = ra;
1900         op->reg = rd;
1901         op->val = regs->gpr[rd];
1902         u = (instr >> 20) & UPDATE;
1903         op->vsx_flags = 0;
1904
1905         switch (opcode) {
1906         case 31:
1907                 u = instr & UPDATE;
1908                 op->ea = xform_ea(instr, regs);
1909                 switch ((instr >> 1) & 0x3ff) {
1910                 case 20:        /* lwarx */
1911                         op->type = MKOP(LARX, 0, 4);
1912                         break;
1913
1914                 case 150:       /* stwcx. */
1915                         op->type = MKOP(STCX, 0, 4);
1916                         break;
1917
1918 #ifdef __powerpc64__
1919                 case 84:        /* ldarx */
1920                         op->type = MKOP(LARX, 0, 8);
1921                         break;
1922
1923                 case 214:       /* stdcx. */
1924                         op->type = MKOP(STCX, 0, 8);
1925                         break;
1926
1927                 case 52:        /* lbarx */
1928                         op->type = MKOP(LARX, 0, 1);
1929                         break;
1930
1931                 case 694:       /* stbcx. */
1932                         op->type = MKOP(STCX, 0, 1);
1933                         break;
1934
1935                 case 116:       /* lharx */
1936                         op->type = MKOP(LARX, 0, 2);
1937                         break;
1938
1939                 case 726:       /* sthcx. */
1940                         op->type = MKOP(STCX, 0, 2);
1941                         break;
1942
1943                 case 276:       /* lqarx */
1944                         if (!((rd & 1) || rd == ra || rd == rb))
1945                                 op->type = MKOP(LARX, 0, 16);
1946                         break;
1947
1948                 case 182:       /* stqcx. */
1949                         if (!(rd & 1))
1950                                 op->type = MKOP(STCX, 0, 16);
1951                         break;
1952 #endif
1953
1954                 case 23:        /* lwzx */
1955                 case 55:        /* lwzux */
1956                         op->type = MKOP(LOAD, u, 4);
1957                         break;
1958
1959                 case 87:        /* lbzx */
1960                 case 119:       /* lbzux */
1961                         op->type = MKOP(LOAD, u, 1);
1962                         break;
1963
1964 #ifdef CONFIG_ALTIVEC
1965                 /*
1966                  * Note: for the load/store vector element instructions,
1967                  * bits of the EA say which field of the VMX register to use.
1968                  */
1969                 case 7:         /* lvebx */
1970                         op->type = MKOP(LOAD_VMX, 0, 1);
1971                         op->element_size = 1;
1972                         break;
1973
1974                 case 39:        /* lvehx */
1975                         op->type = MKOP(LOAD_VMX, 0, 2);
1976                         op->element_size = 2;
1977                         break;
1978
1979                 case 71:        /* lvewx */
1980                         op->type = MKOP(LOAD_VMX, 0, 4);
1981                         op->element_size = 4;
1982                         break;
1983
1984                 case 103:       /* lvx */
1985                 case 359:       /* lvxl */
1986                         op->type = MKOP(LOAD_VMX, 0, 16);
1987                         op->element_size = 16;
1988                         break;
1989
1990                 case 135:       /* stvebx */
1991                         op->type = MKOP(STORE_VMX, 0, 1);
1992                         op->element_size = 1;
1993                         break;
1994
1995                 case 167:       /* stvehx */
1996                         op->type = MKOP(STORE_VMX, 0, 2);
1997                         op->element_size = 2;
1998                         break;
1999
2000                 case 199:       /* stvewx */
2001                         op->type = MKOP(STORE_VMX, 0, 4);
2002                         op->element_size = 4;
2003                         break;
2004
2005                 case 231:       /* stvx */
2006                 case 487:       /* stvxl */
2007                         op->type = MKOP(STORE_VMX, 0, 16);
2008                         break;
2009 #endif /* CONFIG_ALTIVEC */
2010
2011 #ifdef __powerpc64__
2012                 case 21:        /* ldx */
2013                 case 53:        /* ldux */
2014                         op->type = MKOP(LOAD, u, 8);
2015                         break;
2016
2017                 case 149:       /* stdx */
2018                 case 181:       /* stdux */
2019                         op->type = MKOP(STORE, u, 8);
2020                         break;
2021 #endif
2022
2023                 case 151:       /* stwx */
2024                 case 183:       /* stwux */
2025                         op->type = MKOP(STORE, u, 4);
2026                         break;
2027
2028                 case 215:       /* stbx */
2029                 case 247:       /* stbux */
2030                         op->type = MKOP(STORE, u, 1);
2031                         break;
2032
2033                 case 279:       /* lhzx */
2034                 case 311:       /* lhzux */
2035                         op->type = MKOP(LOAD, u, 2);
2036                         break;
2037
2038 #ifdef __powerpc64__
2039                 case 341:       /* lwax */
2040                 case 373:       /* lwaux */
2041                         op->type = MKOP(LOAD, SIGNEXT | u, 4);
2042                         break;
2043 #endif
2044
2045                 case 343:       /* lhax */
2046                 case 375:       /* lhaux */
2047                         op->type = MKOP(LOAD, SIGNEXT | u, 2);
2048                         break;
2049
2050                 case 407:       /* sthx */
2051                 case 439:       /* sthux */
2052                         op->type = MKOP(STORE, u, 2);
2053                         break;
2054
2055 #ifdef __powerpc64__
2056                 case 532:       /* ldbrx */
2057                         op->type = MKOP(LOAD, BYTEREV, 8);
2058                         break;
2059
2060 #endif
2061                 case 533:       /* lswx */
2062                         op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2063                         break;
2064
2065                 case 534:       /* lwbrx */
2066                         op->type = MKOP(LOAD, BYTEREV, 4);
2067                         break;
2068
2069                 case 597:       /* lswi */
2070                         if (rb == 0)
2071                                 rb = 32;        /* # bytes to load */
2072                         op->type = MKOP(LOAD_MULTI, 0, rb);
2073                         op->ea = ra ? regs->gpr[ra] : 0;
2074                         break;
2075
2076 #ifdef CONFIG_PPC_FPU
2077                 case 535:       /* lfsx */
2078                 case 567:       /* lfsux */
2079                         op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2080                         break;
2081
2082                 case 599:       /* lfdx */
2083                 case 631:       /* lfdux */
2084                         op->type = MKOP(LOAD_FP, u, 8);
2085                         break;
2086
2087                 case 663:       /* stfsx */
2088                 case 695:       /* stfsux */
2089                         op->type = MKOP(STORE_FP, u | FPCONV, 4);
2090                         break;
2091
2092                 case 727:       /* stfdx */
2093                 case 759:       /* stfdux */
2094                         op->type = MKOP(STORE_FP, u, 8);
2095                         break;
2096
2097 #ifdef __powerpc64__
2098                 case 791:       /* lfdpx */
2099                         op->type = MKOP(LOAD_FP, 0, 16);
2100                         break;
2101
2102                 case 855:       /* lfiwax */
2103                         op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2104                         break;
2105
2106                 case 887:       /* lfiwzx */
2107                         op->type = MKOP(LOAD_FP, 0, 4);
2108                         break;
2109
2110                 case 919:       /* stfdpx */
2111                         op->type = MKOP(STORE_FP, 0, 16);
2112                         break;
2113
2114                 case 983:       /* stfiwx */
2115                         op->type = MKOP(STORE_FP, 0, 4);
2116                         break;
2117 #endif /* __powerpc64 */
2118 #endif /* CONFIG_PPC_FPU */
2119
2120 #ifdef __powerpc64__
2121                 case 660:       /* stdbrx */
2122                         op->type = MKOP(STORE, BYTEREV, 8);
2123                         op->val = byterev_8(regs->gpr[rd]);
2124                         break;
2125
2126 #endif
2127                 case 661:       /* stswx */
2128                         op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2129                         break;
2130
2131                 case 662:       /* stwbrx */
2132                         op->type = MKOP(STORE, BYTEREV, 4);
2133                         op->val = byterev_4(regs->gpr[rd]);
2134                         break;
2135
2136                 case 725:       /* stswi */
2137                         if (rb == 0)
2138                                 rb = 32;        /* # bytes to store */
2139                         op->type = MKOP(STORE_MULTI, 0, rb);
2140                         op->ea = ra ? regs->gpr[ra] : 0;
2141                         break;
2142
2143                 case 790:       /* lhbrx */
2144                         op->type = MKOP(LOAD, BYTEREV, 2);
2145                         break;
2146
2147                 case 918:       /* sthbrx */
2148                         op->type = MKOP(STORE, BYTEREV, 2);
2149                         op->val = byterev_2(regs->gpr[rd]);
2150                         break;
2151
2152 #ifdef CONFIG_VSX
2153                 case 12:        /* lxsiwzx */
2154                         op->reg = rd | ((instr & 1) << 5);
2155                         op->type = MKOP(LOAD_VSX, 0, 4);
2156                         op->element_size = 8;
2157                         break;
2158
2159                 case 76:        /* lxsiwax */
2160                         op->reg = rd | ((instr & 1) << 5);
2161                         op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2162                         op->element_size = 8;
2163                         break;
2164
2165                 case 140:       /* stxsiwx */
2166                         op->reg = rd | ((instr & 1) << 5);
2167                         op->type = MKOP(STORE_VSX, 0, 4);
2168                         op->element_size = 8;
2169                         break;
2170
2171                 case 268:       /* lxvx */
2172                         op->reg = rd | ((instr & 1) << 5);
2173                         op->type = MKOP(LOAD_VSX, 0, 16);
2174                         op->element_size = 16;
2175                         op->vsx_flags = VSX_CHECK_VEC;
2176                         break;
2177
2178                 case 269:       /* lxvl */
2179                 case 301: {     /* lxvll */
2180                         int nb;
2181                         op->reg = rd | ((instr & 1) << 5);
2182                         op->ea = ra ? regs->gpr[ra] : 0;
2183                         nb = regs->gpr[rb] & 0xff;
2184                         if (nb > 16)
2185                                 nb = 16;
2186                         op->type = MKOP(LOAD_VSX, 0, nb);
2187                         op->element_size = 16;
2188                         op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2189                                 VSX_CHECK_VEC;
2190                         break;
2191                 }
2192                 case 332:       /* lxvdsx */
2193                         op->reg = rd | ((instr & 1) << 5);
2194                         op->type = MKOP(LOAD_VSX, 0, 8);
2195                         op->element_size = 8;
2196                         op->vsx_flags = VSX_SPLAT;
2197                         break;
2198
2199                 case 364:       /* lxvwsx */
2200                         op->reg = rd | ((instr & 1) << 5);
2201                         op->type = MKOP(LOAD_VSX, 0, 4);
2202                         op->element_size = 4;
2203                         op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2204                         break;
2205
2206                 case 396:       /* stxvx */
2207                         op->reg = rd | ((instr & 1) << 5);
2208                         op->type = MKOP(STORE_VSX, 0, 16);
2209                         op->element_size = 16;
2210                         op->vsx_flags = VSX_CHECK_VEC;
2211                         break;
2212
2213                 case 397:       /* stxvl */
2214                 case 429: {     /* stxvll */
2215                         int nb;
2216                         op->reg = rd | ((instr & 1) << 5);
2217                         op->ea = ra ? regs->gpr[ra] : 0;
2218                         nb = regs->gpr[rb] & 0xff;
2219                         if (nb > 16)
2220                                 nb = 16;
2221                         op->type = MKOP(STORE_VSX, 0, nb);
2222                         op->element_size = 16;
2223                         op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2224                                 VSX_CHECK_VEC;
2225                         break;
2226                 }
2227                 case 524:       /* lxsspx */
2228                         op->reg = rd | ((instr & 1) << 5);
2229                         op->type = MKOP(LOAD_VSX, 0, 4);
2230                         op->element_size = 8;
2231                         op->vsx_flags = VSX_FPCONV;
2232                         break;
2233
2234                 case 588:       /* lxsdx */
2235                         op->reg = rd | ((instr & 1) << 5);
2236                         op->type = MKOP(LOAD_VSX, 0, 8);
2237                         op->element_size = 8;
2238                         break;
2239
2240                 case 652:       /* stxsspx */
2241                         op->reg = rd | ((instr & 1) << 5);
2242                         op->type = MKOP(STORE_VSX, 0, 4);
2243                         op->element_size = 8;
2244                         op->vsx_flags = VSX_FPCONV;
2245                         break;
2246
2247                 case 716:       /* stxsdx */
2248                         op->reg = rd | ((instr & 1) << 5);
2249                         op->type = MKOP(STORE_VSX, 0, 8);
2250                         op->element_size = 8;
2251                         break;
2252
2253                 case 780:       /* lxvw4x */
2254                         op->reg = rd | ((instr & 1) << 5);
2255                         op->type = MKOP(LOAD_VSX, 0, 16);
2256                         op->element_size = 4;
2257                         break;
2258
2259                 case 781:       /* lxsibzx */
2260                         op->reg = rd | ((instr & 1) << 5);
2261                         op->type = MKOP(LOAD_VSX, 0, 1);
2262                         op->element_size = 8;
2263                         op->vsx_flags = VSX_CHECK_VEC;
2264                         break;
2265
2266                 case 812:       /* lxvh8x */
2267                         op->reg = rd | ((instr & 1) << 5);
2268                         op->type = MKOP(LOAD_VSX, 0, 16);
2269                         op->element_size = 2;
2270                         op->vsx_flags = VSX_CHECK_VEC;
2271                         break;
2272
2273                 case 813:       /* lxsihzx */
2274                         op->reg = rd | ((instr & 1) << 5);
2275                         op->type = MKOP(LOAD_VSX, 0, 2);
2276                         op->element_size = 8;
2277                         op->vsx_flags = VSX_CHECK_VEC;
2278                         break;
2279
2280                 case 844:       /* lxvd2x */
2281                         op->reg = rd | ((instr & 1) << 5);
2282                         op->type = MKOP(LOAD_VSX, 0, 16);
2283                         op->element_size = 8;
2284                         break;
2285
2286                 case 876:       /* lxvb16x */
2287                         op->reg = rd | ((instr & 1) << 5);
2288                         op->type = MKOP(LOAD_VSX, 0, 16);
2289                         op->element_size = 1;
2290                         op->vsx_flags = VSX_CHECK_VEC;
2291                         break;
2292
2293                 case 908:       /* stxvw4x */
2294                         op->reg = rd | ((instr & 1) << 5);
2295                         op->type = MKOP(STORE_VSX, 0, 16);
2296                         op->element_size = 4;
2297                         break;
2298
2299                 case 909:       /* stxsibx */
2300                         op->reg = rd | ((instr & 1) << 5);
2301                         op->type = MKOP(STORE_VSX, 0, 1);
2302                         op->element_size = 8;
2303                         op->vsx_flags = VSX_CHECK_VEC;
2304                         break;
2305
2306                 case 940:       /* stxvh8x */
2307                         op->reg = rd | ((instr & 1) << 5);
2308                         op->type = MKOP(STORE_VSX, 0, 16);
2309                         op->element_size = 2;
2310                         op->vsx_flags = VSX_CHECK_VEC;
2311                         break;
2312
2313                 case 941:       /* stxsihx */
2314                         op->reg = rd | ((instr & 1) << 5);
2315                         op->type = MKOP(STORE_VSX, 0, 2);
2316                         op->element_size = 8;
2317                         op->vsx_flags = VSX_CHECK_VEC;
2318                         break;
2319
2320                 case 972:       /* stxvd2x */
2321                         op->reg = rd | ((instr & 1) << 5);
2322                         op->type = MKOP(STORE_VSX, 0, 16);
2323                         op->element_size = 8;
2324                         break;
2325
2326                 case 1004:      /* stxvb16x */
2327                         op->reg = rd | ((instr & 1) << 5);
2328                         op->type = MKOP(STORE_VSX, 0, 16);
2329                         op->element_size = 1;
2330                         op->vsx_flags = VSX_CHECK_VEC;
2331                         break;
2332
2333 #endif /* CONFIG_VSX */
2334                 }
2335                 break;
2336
2337         case 32:        /* lwz */
2338         case 33:        /* lwzu */
2339                 op->type = MKOP(LOAD, u, 4);
2340                 op->ea = dform_ea(instr, regs);
2341                 break;
2342
2343         case 34:        /* lbz */
2344         case 35:        /* lbzu */
2345                 op->type = MKOP(LOAD, u, 1);
2346                 op->ea = dform_ea(instr, regs);
2347                 break;
2348
2349         case 36:        /* stw */
2350         case 37:        /* stwu */
2351                 op->type = MKOP(STORE, u, 4);
2352                 op->ea = dform_ea(instr, regs);
2353                 break;
2354
2355         case 38:        /* stb */
2356         case 39:        /* stbu */
2357                 op->type = MKOP(STORE, u, 1);
2358                 op->ea = dform_ea(instr, regs);
2359                 break;
2360
2361         case 40:        /* lhz */
2362         case 41:        /* lhzu */
2363                 op->type = MKOP(LOAD, u, 2);
2364                 op->ea = dform_ea(instr, regs);
2365                 break;
2366
2367         case 42:        /* lha */
2368         case 43:        /* lhau */
2369                 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2370                 op->ea = dform_ea(instr, regs);
2371                 break;
2372
2373         case 44:        /* sth */
2374         case 45:        /* sthu */
2375                 op->type = MKOP(STORE, u, 2);
2376                 op->ea = dform_ea(instr, regs);
2377                 break;
2378
2379         case 46:        /* lmw */
2380                 if (ra >= rd)
2381                         break;          /* invalid form, ra in range to load */
2382                 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2383                 op->ea = dform_ea(instr, regs);
2384                 break;
2385
2386         case 47:        /* stmw */
2387                 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2388                 op->ea = dform_ea(instr, regs);
2389                 break;
2390
2391 #ifdef CONFIG_PPC_FPU
2392         case 48:        /* lfs */
2393         case 49:        /* lfsu */
2394                 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2395                 op->ea = dform_ea(instr, regs);
2396                 break;
2397
2398         case 50:        /* lfd */
2399         case 51:        /* lfdu */
2400                 op->type = MKOP(LOAD_FP, u, 8);
2401                 op->ea = dform_ea(instr, regs);
2402                 break;
2403
2404         case 52:        /* stfs */
2405         case 53:        /* stfsu */
2406                 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2407                 op->ea = dform_ea(instr, regs);
2408                 break;
2409
2410         case 54:        /* stfd */
2411         case 55:        /* stfdu */
2412                 op->type = MKOP(STORE_FP, u, 8);
2413                 op->ea = dform_ea(instr, regs);
2414                 break;
2415 #endif
2416
2417 #ifdef __powerpc64__
2418         case 56:        /* lq */
2419                 if (!((rd & 1) || (rd == ra)))
2420                         op->type = MKOP(LOAD, 0, 16);
2421                 op->ea = dqform_ea(instr, regs);
2422                 break;
2423 #endif
2424
2425 #ifdef CONFIG_VSX
2426         case 57:        /* lfdp, lxsd, lxssp */
2427                 op->ea = dsform_ea(instr, regs);
2428                 switch (instr & 3) {
2429                 case 0:         /* lfdp */
2430                         if (rd & 1)
2431                                 break;          /* reg must be even */
2432                         op->type = MKOP(LOAD_FP, 0, 16);
2433                         break;
2434                 case 2:         /* lxsd */
2435                         op->reg = rd + 32;
2436                         op->type = MKOP(LOAD_VSX, 0, 8);
2437                         op->element_size = 8;
2438                         op->vsx_flags = VSX_CHECK_VEC;
2439                         break;
2440                 case 3:         /* lxssp */
2441                         op->reg = rd + 32;
2442                         op->type = MKOP(LOAD_VSX, 0, 4);
2443                         op->element_size = 8;
2444                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2445                         break;
2446                 }
2447                 break;
2448 #endif /* CONFIG_VSX */
2449
2450 #ifdef __powerpc64__
2451         case 58:        /* ld[u], lwa */
2452                 op->ea = dsform_ea(instr, regs);
2453                 switch (instr & 3) {
2454                 case 0:         /* ld */
2455                         op->type = MKOP(LOAD, 0, 8);
2456                         break;
2457                 case 1:         /* ldu */
2458                         op->type = MKOP(LOAD, UPDATE, 8);
2459                         break;
2460                 case 2:         /* lwa */
2461                         op->type = MKOP(LOAD, SIGNEXT, 4);
2462                         break;
2463                 }
2464                 break;
2465 #endif
2466
2467 #ifdef CONFIG_VSX
2468         case 61:        /* stfdp, lxv, stxsd, stxssp, stxv */
2469                 switch (instr & 7) {
2470                 case 0:         /* stfdp with LSB of DS field = 0 */
2471                 case 4:         /* stfdp with LSB of DS field = 1 */
2472                         op->ea = dsform_ea(instr, regs);
2473                         op->type = MKOP(STORE_FP, 0, 16);
2474                         break;
2475
2476                 case 1:         /* lxv */
2477                         op->ea = dqform_ea(instr, regs);
2478                         if (instr & 8)
2479                                 op->reg = rd + 32;
2480                         op->type = MKOP(LOAD_VSX, 0, 16);
2481                         op->element_size = 16;
2482                         op->vsx_flags = VSX_CHECK_VEC;
2483                         break;
2484
2485                 case 2:         /* stxsd with LSB of DS field = 0 */
2486                 case 6:         /* stxsd with LSB of DS field = 1 */
2487                         op->ea = dsform_ea(instr, regs);
2488                         op->reg = rd + 32;
2489                         op->type = MKOP(STORE_VSX, 0, 8);
2490                         op->element_size = 8;
2491                         op->vsx_flags = VSX_CHECK_VEC;
2492                         break;
2493
2494                 case 3:         /* stxssp with LSB of DS field = 0 */
2495                 case 7:         /* stxssp with LSB of DS field = 1 */
2496                         op->ea = dsform_ea(instr, regs);
2497                         op->reg = rd + 32;
2498                         op->type = MKOP(STORE_VSX, 0, 4);
2499                         op->element_size = 8;
2500                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2501                         break;
2502
2503                 case 5:         /* stxv */
2504                         op->ea = dqform_ea(instr, regs);
2505                         if (instr & 8)
2506                                 op->reg = rd + 32;
2507                         op->type = MKOP(STORE_VSX, 0, 16);
2508                         op->element_size = 16;
2509                         op->vsx_flags = VSX_CHECK_VEC;
2510                         break;
2511                 }
2512                 break;
2513 #endif /* CONFIG_VSX */
2514
2515 #ifdef __powerpc64__
2516         case 62:        /* std[u] */
2517                 op->ea = dsform_ea(instr, regs);
2518                 switch (instr & 3) {
2519                 case 0:         /* std */
2520                         op->type = MKOP(STORE, 0, 8);
2521                         break;
2522                 case 1:         /* stdu */
2523                         op->type = MKOP(STORE, UPDATE, 8);
2524                         break;
2525                 case 2:         /* stq */
2526                         if (!(rd & 1))
2527                                 op->type = MKOP(STORE, 0, 16);
2528                         break;
2529                 }
2530                 break;
2531 #endif /* __powerpc64__ */
2532
2533         }
2534         return 0;
2535
2536  logical_done:
2537         if (instr & 1)
2538                 set_cr0(regs, op);
2539  logical_done_nocc:
2540         op->reg = ra;
2541         op->type |= SETREG;
2542         return 1;
2543
2544  arith_done:
2545         if (instr & 1)
2546                 set_cr0(regs, op);
2547  compute_done:
2548         op->reg = rd;
2549         op->type |= SETREG;
2550         return 1;
2551
2552  priv:
2553         op->type = INTERRUPT | 0x700;
2554         op->val = SRR1_PROGPRIV;
2555         return 0;
2556
2557  trap:
2558         op->type = INTERRUPT | 0x700;
2559         op->val = SRR1_PROGTRAP;
2560         return 0;
2561 }
2562 EXPORT_SYMBOL_GPL(analyse_instr);
2563 NOKPROBE_SYMBOL(analyse_instr);
2564
2565 /*
2566  * For PPC32 we always use stwu with r1 to change the stack pointer.
2567  * So this emulated store may corrupt the exception frame, now we
2568  * have to provide the exception frame trampoline, which is pushed
2569  * below the kprobed function stack. So we only update gpr[1] but
2570  * don't emulate the real store operation. We will do real store
2571  * operation safely in exception return code by checking this flag.
2572  */
2573 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
2574 {
2575 #ifdef CONFIG_PPC32
2576         /*
2577          * Check if we will touch kernel stack overflow
2578          */
2579         if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
2580                 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
2581                 return -EINVAL;
2582         }
2583 #endif /* CONFIG_PPC32 */
2584         /*
2585          * Check if we already set since that means we'll
2586          * lose the previous value.
2587          */
2588         WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
2589         set_thread_flag(TIF_EMULATE_STACK_STORE);
2590         return 0;
2591 }
2592
2593 static nokprobe_inline void do_signext(unsigned long *valp, int size)
2594 {
2595         switch (size) {
2596         case 2:
2597                 *valp = (signed short) *valp;
2598                 break;
2599         case 4:
2600                 *valp = (signed int) *valp;
2601                 break;
2602         }
2603 }
2604
2605 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
2606 {
2607         switch (size) {
2608         case 2:
2609                 *valp = byterev_2(*valp);
2610                 break;
2611         case 4:
2612                 *valp = byterev_4(*valp);
2613                 break;
2614 #ifdef __powerpc64__
2615         case 8:
2616                 *valp = byterev_8(*valp);
2617                 break;
2618 #endif
2619         }
2620 }
2621
2622 /*
2623  * Emulate an instruction that can be executed just by updating
2624  * fields in *regs.
2625  */
2626 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
2627 {
2628         unsigned long next_pc;
2629
2630         next_pc = truncate_if_32bit(regs->msr, regs->nip + 4);
2631         switch (op->type & INSTR_TYPE_MASK) {
2632         case COMPUTE:
2633                 if (op->type & SETREG)
2634                         regs->gpr[op->reg] = op->val;
2635                 if (op->type & SETCC)
2636                         regs->ccr = op->ccval;
2637                 if (op->type & SETXER)
2638                         regs->xer = op->xerval;
2639                 break;
2640
2641         case BRANCH:
2642                 if (op->type & SETLK)
2643                         regs->link = next_pc;
2644                 if (op->type & BRTAKEN)
2645                         next_pc = op->val;
2646                 if (op->type & DECCTR)
2647                         --regs->ctr;
2648                 break;
2649
2650         case BARRIER:
2651                 switch (op->type & BARRIER_MASK) {
2652                 case BARRIER_SYNC:
2653                         mb();
2654                         break;
2655                 case BARRIER_ISYNC:
2656                         isync();
2657                         break;
2658                 case BARRIER_EIEIO:
2659                         eieio();
2660                         break;
2661 #ifdef CONFIG_PPC64
2662                 case BARRIER_LWSYNC:
2663                         asm volatile("lwsync" : : : "memory");
2664                         break;
2665                 case BARRIER_PTESYNC:
2666                         asm volatile("ptesync" : : : "memory");
2667                         break;
2668 #endif
2669                 }
2670                 break;
2671
2672         case MFSPR:
2673                 switch (op->spr) {
2674                 case SPRN_XER:
2675                         regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
2676                         break;
2677                 case SPRN_LR:
2678                         regs->gpr[op->reg] = regs->link;
2679                         break;
2680                 case SPRN_CTR:
2681                         regs->gpr[op->reg] = regs->ctr;
2682                         break;
2683                 default:
2684                         WARN_ON_ONCE(1);
2685                 }
2686                 break;
2687
2688         case MTSPR:
2689                 switch (op->spr) {
2690                 case SPRN_XER:
2691                         regs->xer = op->val & 0xffffffffUL;
2692                         break;
2693                 case SPRN_LR:
2694                         regs->link = op->val;
2695                         break;
2696                 case SPRN_CTR:
2697                         regs->ctr = op->val;
2698                         break;
2699                 default:
2700                         WARN_ON_ONCE(1);
2701                 }
2702                 break;
2703
2704         default:
2705                 WARN_ON_ONCE(1);
2706         }
2707         regs->nip = next_pc;
2708 }
2709
2710 /*
2711  * Emulate a previously-analysed load or store instruction.
2712  * Return values are:
2713  * 0 = instruction emulated successfully
2714  * -EFAULT = address out of range or access faulted (regs->dar
2715  *           contains the faulting address)
2716  * -EACCES = misaligned access, instruction requires alignment
2717  * -EINVAL = unknown operation in *op
2718  */
2719 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
2720 {
2721         int err, size, type;
2722         int i, rd, nb;
2723         unsigned int cr;
2724         unsigned long val;
2725         unsigned long ea;
2726         bool cross_endian;
2727
2728         err = 0;
2729         size = GETSIZE(op->type);
2730         type = op->type & INSTR_TYPE_MASK;
2731         cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
2732         ea = truncate_if_32bit(regs->msr, op->ea);
2733
2734         switch (type) {
2735         case LARX:
2736                 if (ea & (size - 1))
2737                         return -EACCES;         /* can't handle misaligned */
2738                 if (!address_ok(regs, ea, size))
2739                         return -EFAULT;
2740                 err = 0;
2741                 val = 0;
2742                 switch (size) {
2743 #ifdef __powerpc64__
2744                 case 1:
2745                         __get_user_asmx(val, ea, err, "lbarx");
2746                         break;
2747                 case 2:
2748                         __get_user_asmx(val, ea, err, "lharx");
2749                         break;
2750 #endif
2751                 case 4:
2752                         __get_user_asmx(val, ea, err, "lwarx");
2753                         break;
2754 #ifdef __powerpc64__
2755                 case 8:
2756                         __get_user_asmx(val, ea, err, "ldarx");
2757                         break;
2758                 case 16:
2759                         err = do_lqarx(ea, &regs->gpr[op->reg]);
2760                         break;
2761 #endif
2762                 default:
2763                         return -EINVAL;
2764                 }
2765                 if (err) {
2766                         regs->dar = ea;
2767                         break;
2768                 }
2769                 if (size < 16)
2770                         regs->gpr[op->reg] = val;
2771                 break;
2772
2773         case STCX:
2774                 if (ea & (size - 1))
2775                         return -EACCES;         /* can't handle misaligned */
2776                 if (!address_ok(regs, ea, size))
2777                         return -EFAULT;
2778                 err = 0;
2779                 switch (size) {
2780 #ifdef __powerpc64__
2781                 case 1:
2782                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
2783                         break;
2784                 case 2:
2785                         __put_user_asmx(op->val, ea, err, "sthcx.", cr);
2786                         break;
2787 #endif
2788                 case 4:
2789                         __put_user_asmx(op->val, ea, err, "stwcx.", cr);
2790                         break;
2791 #ifdef __powerpc64__
2792                 case 8:
2793                         __put_user_asmx(op->val, ea, err, "stdcx.", cr);
2794                         break;
2795                 case 16:
2796                         err = do_stqcx(ea, regs->gpr[op->reg],
2797                                        regs->gpr[op->reg + 1], &cr);
2798                         break;
2799 #endif
2800                 default:
2801                         return -EINVAL;
2802                 }
2803                 if (!err)
2804                         regs->ccr = (regs->ccr & 0x0fffffff) |
2805                                 (cr & 0xe0000000) |
2806                                 ((regs->xer >> 3) & 0x10000000);
2807                 else
2808                         regs->dar = ea;
2809                 break;
2810
2811         case LOAD:
2812 #ifdef __powerpc64__
2813                 if (size == 16) {
2814                         err = emulate_lq(regs, ea, op->reg, cross_endian);
2815                         break;
2816                 }
2817 #endif
2818                 err = read_mem(&regs->gpr[op->reg], ea, size, regs);
2819                 if (!err) {
2820                         if (op->type & SIGNEXT)
2821                                 do_signext(&regs->gpr[op->reg], size);
2822                         if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
2823                                 do_byterev(&regs->gpr[op->reg], size);
2824                 }
2825                 break;
2826
2827 #ifdef CONFIG_PPC_FPU
2828         case LOAD_FP:
2829                 /*
2830                  * If the instruction is in userspace, we can emulate it even
2831                  * if the VMX state is not live, because we have the state
2832                  * stored in the thread_struct.  If the instruction is in
2833                  * the kernel, we must not touch the state in the thread_struct.
2834                  */
2835                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2836                         return 0;
2837                 err = do_fp_load(op, ea, regs, cross_endian);
2838                 break;
2839 #endif
2840 #ifdef CONFIG_ALTIVEC
2841         case LOAD_VMX:
2842                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
2843                         return 0;
2844                 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
2845                 break;
2846 #endif
2847 #ifdef CONFIG_VSX
2848         case LOAD_VSX: {
2849                 unsigned long msrbit = MSR_VSX;
2850
2851                 /*
2852                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2853                  * when the target of the instruction is a vector register.
2854                  */
2855                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
2856                         msrbit = MSR_VEC;
2857                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
2858                         return 0;
2859                 err = do_vsx_load(op, ea, regs, cross_endian);
2860                 break;
2861         }
2862 #endif
2863         case LOAD_MULTI:
2864                 if (!address_ok(regs, ea, size))
2865                         return -EFAULT;
2866                 rd = op->reg;
2867                 for (i = 0; i < size; i += 4) {
2868                         unsigned int v32 = 0;
2869
2870                         nb = size - i;
2871                         if (nb > 4)
2872                                 nb = 4;
2873                         err = copy_mem_in((u8 *) &v32, ea, nb, regs);
2874                         if (err)
2875                                 break;
2876                         if (unlikely(cross_endian))
2877                                 v32 = byterev_4(v32);
2878                         regs->gpr[rd] = v32;
2879                         ea += 4;
2880                         /* reg number wraps from 31 to 0 for lsw[ix] */
2881                         rd = (rd + 1) & 0x1f;
2882                 }
2883                 break;
2884
2885         case STORE:
2886 #ifdef __powerpc64__
2887                 if (size == 16) {
2888                         err = emulate_stq(regs, ea, op->reg, cross_endian);
2889                         break;
2890                 }
2891 #endif
2892                 if ((op->type & UPDATE) && size == sizeof(long) &&
2893                     op->reg == 1 && op->update_reg == 1 &&
2894                     !(regs->msr & MSR_PR) &&
2895                     ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
2896                         err = handle_stack_update(ea, regs);
2897                         break;
2898                 }
2899                 if (unlikely(cross_endian))
2900                         do_byterev(&op->val, size);
2901                 err = write_mem(op->val, ea, size, regs);
2902                 break;
2903
2904 #ifdef CONFIG_PPC_FPU
2905         case STORE_FP:
2906                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2907                         return 0;
2908                 err = do_fp_store(op, ea, regs, cross_endian);
2909                 break;
2910 #endif
2911 #ifdef CONFIG_ALTIVEC
2912         case STORE_VMX:
2913                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
2914                         return 0;
2915                 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
2916                 break;
2917 #endif
2918 #ifdef CONFIG_VSX
2919         case STORE_VSX: {
2920                 unsigned long msrbit = MSR_VSX;
2921
2922                 /*
2923                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2924                  * when the target of the instruction is a vector register.
2925                  */
2926                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
2927                         msrbit = MSR_VEC;
2928                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
2929                         return 0;
2930                 err = do_vsx_store(op, ea, regs, cross_endian);
2931                 break;
2932         }
2933 #endif
2934         case STORE_MULTI:
2935                 if (!address_ok(regs, ea, size))
2936                         return -EFAULT;
2937                 rd = op->reg;
2938                 for (i = 0; i < size; i += 4) {
2939                         unsigned int v32 = regs->gpr[rd];
2940
2941                         nb = size - i;
2942                         if (nb > 4)
2943                                 nb = 4;
2944                         if (unlikely(cross_endian))
2945                                 v32 = byterev_4(v32);
2946                         err = copy_mem_out((u8 *) &v32, ea, nb, regs);
2947                         if (err)
2948                                 break;
2949                         ea += 4;
2950                         /* reg number wraps from 31 to 0 for stsw[ix] */
2951                         rd = (rd + 1) & 0x1f;
2952                 }
2953                 break;
2954
2955         default:
2956                 return -EINVAL;
2957         }
2958
2959         if (err)
2960                 return err;
2961
2962         if (op->type & UPDATE)
2963                 regs->gpr[op->update_reg] = op->ea;
2964
2965         return 0;
2966 }
2967 NOKPROBE_SYMBOL(emulate_loadstore);
2968
2969 /*
2970  * Emulate instructions that cause a transfer of control,
2971  * loads and stores, and a few other instructions.
2972  * Returns 1 if the step was emulated, 0 if not,
2973  * or -1 if the instruction is one that should not be stepped,
2974  * such as an rfid, or a mtmsrd that would clear MSR_RI.
2975  */
2976 int emulate_step(struct pt_regs *regs, unsigned int instr)
2977 {
2978         struct instruction_op op;
2979         int r, err, type;
2980         unsigned long val;
2981         unsigned long ea;
2982
2983         r = analyse_instr(&op, regs, instr);
2984         if (r < 0)
2985                 return r;
2986         if (r > 0) {
2987                 emulate_update_regs(regs, &op);
2988                 return 1;
2989         }
2990
2991         err = 0;
2992         type = op.type & INSTR_TYPE_MASK;
2993
2994         if (OP_IS_LOAD_STORE(type)) {
2995                 err = emulate_loadstore(regs, &op);
2996                 if (err)
2997                         return 0;
2998                 goto instr_done;
2999         }
3000
3001         switch (type) {
3002         case CACHEOP:
3003                 ea = truncate_if_32bit(regs->msr, op.ea);
3004                 if (!address_ok(regs, ea, 8))
3005                         return 0;
3006                 switch (op.type & CACHEOP_MASK) {
3007                 case DCBST:
3008                         __cacheop_user_asmx(ea, err, "dcbst");
3009                         break;
3010                 case DCBF:
3011                         __cacheop_user_asmx(ea, err, "dcbf");
3012                         break;
3013                 case DCBTST:
3014                         if (op.reg == 0)
3015                                 prefetchw((void *) ea);
3016                         break;
3017                 case DCBT:
3018                         if (op.reg == 0)
3019                                 prefetch((void *) ea);
3020                         break;
3021                 case ICBI:
3022                         __cacheop_user_asmx(ea, err, "icbi");
3023                         break;
3024                 case DCBZ:
3025                         err = emulate_dcbz(ea, regs);
3026                         break;
3027                 }
3028                 if (err) {
3029                         regs->dar = ea;
3030                         return 0;
3031                 }
3032                 goto instr_done;
3033
3034         case MFMSR:
3035                 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3036                 goto instr_done;
3037
3038         case MTMSR:
3039                 val = regs->gpr[op.reg];
3040                 if ((val & MSR_RI) == 0)
3041                         /* can't step mtmsr[d] that would clear MSR_RI */
3042                         return -1;
3043                 /* here op.val is the mask of bits to change */
3044                 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3045                 goto instr_done;
3046
3047 #ifdef CONFIG_PPC64
3048         case SYSCALL:   /* sc */
3049                 /*
3050                  * N.B. this uses knowledge about how the syscall
3051                  * entry code works.  If that is changed, this will
3052                  * need to be changed also.
3053                  */
3054                 if (regs->gpr[0] == 0x1ebe &&
3055                     cpu_has_feature(CPU_FTR_REAL_LE)) {
3056                         regs->msr ^= MSR_LE;
3057                         goto instr_done;
3058                 }
3059                 regs->gpr[9] = regs->gpr[13];
3060                 regs->gpr[10] = MSR_KERNEL;
3061                 regs->gpr[11] = regs->nip + 4;
3062                 regs->gpr[12] = regs->msr & MSR_MASK;
3063                 regs->gpr[13] = (unsigned long) get_paca();
3064                 regs->nip = (unsigned long) &system_call_common;
3065                 regs->msr = MSR_KERNEL;
3066                 return 1;
3067
3068         case RFI:
3069                 return -1;
3070 #endif
3071         }
3072         return 0;
3073
3074  instr_done:
3075         regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
3076         return 1;
3077 }
3078 NOKPROBE_SYMBOL(emulate_step);