4 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
11 #include <linux/kernel.h>
12 #include <linux/kprobes.h>
13 #include <linux/ptrace.h>
14 #include <linux/prefetch.h>
15 #include <asm/sstep.h>
16 #include <asm/processor.h>
17 #include <linux/uaccess.h>
18 #include <asm/cpu_has_feature.h>
19 #include <asm/cputable.h>
21 extern char system_call_common[];
24 /* Bits in SRR1 that are copied from MSR */
25 #define MSR_MASK 0xffffffff87c0ffffUL
27 #define MSR_MASK 0x87c0ffff
31 #define XER_SO 0x80000000U
32 #define XER_OV 0x40000000U
33 #define XER_CA 0x20000000U
37 * Functions in ldstfp.S
39 extern void get_fpr(int rn, double *p);
40 extern void put_fpr(int rn, const double *p);
41 extern void get_vr(int rn, __vector128 *p);
42 extern void put_vr(int rn, __vector128 *p);
43 extern void load_vsrn(int vsr, const void *p);
44 extern void store_vsrn(int vsr, void *p);
45 extern void conv_sp_to_dp(const float *sp, double *dp);
46 extern void conv_dp_to_sp(const double *dp, float *sp);
53 extern int do_lq(unsigned long ea, unsigned long *regs);
54 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
55 extern int do_lqarx(unsigned long ea, unsigned long *regs);
56 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
60 #ifdef __LITTLE_ENDIAN__
69 * Emulate the truncation of 64 bit values in 32-bit mode.
71 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
75 if ((msr & MSR_64BIT) == 0)
82 * Determine whether a conditional branch instruction would branch.
84 static nokprobe_inline int branch_taken(unsigned int instr,
85 const struct pt_regs *regs,
86 struct instruction_op *op)
88 unsigned int bo = (instr >> 21) & 0x1f;
92 /* decrement counter */
94 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
97 if ((bo & 0x10) == 0) {
98 /* check bit from CR */
99 bi = (instr >> 16) & 0x1f;
100 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
106 static nokprobe_inline long address_ok(struct pt_regs *regs,
107 unsigned long ea, int nb)
109 if (!user_mode(regs))
111 if (__access_ok(ea, nb, USER_DS))
113 if (__access_ok(ea, 1, USER_DS))
114 /* Access overlaps the end of the user region */
115 regs->dar = USER_DS.seg;
122 * Calculate effective address for a D-form instruction
124 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
125 const struct pt_regs *regs)
130 ra = (instr >> 16) & 0x1f;
131 ea = (signed short) instr; /* sign-extend */
140 * Calculate effective address for a DS-form instruction
142 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
143 const struct pt_regs *regs)
148 ra = (instr >> 16) & 0x1f;
149 ea = (signed short) (instr & ~3); /* sign-extend */
157 * Calculate effective address for a DQ-form instruction
159 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
160 const struct pt_regs *regs)
165 ra = (instr >> 16) & 0x1f;
166 ea = (signed short) (instr & ~0xf); /* sign-extend */
172 #endif /* __powerpc64 */
175 * Calculate effective address for an X-form instruction
177 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
178 const struct pt_regs *regs)
183 ra = (instr >> 16) & 0x1f;
184 rb = (instr >> 11) & 0x1f;
193 * Return the largest power of 2, not greater than sizeof(unsigned long),
194 * such that x is a multiple of it.
196 static nokprobe_inline unsigned long max_align(unsigned long x)
198 x |= sizeof(unsigned long);
199 return x & -x; /* isolates rightmost bit */
202 static nokprobe_inline unsigned long byterev_2(unsigned long x)
204 return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
207 static nokprobe_inline unsigned long byterev_4(unsigned long x)
209 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
210 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
214 static nokprobe_inline unsigned long byterev_8(unsigned long x)
216 return (byterev_4(x) << 32) | byterev_4(x >> 32);
220 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
224 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
227 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
231 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
234 unsigned long *up = (unsigned long *)ptr;
236 tmp = byterev_8(up[0]);
237 up[0] = byterev_8(up[1]);
247 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
248 unsigned long ea, int nb,
249 struct pt_regs *regs)
256 err = __get_user(x, (unsigned char __user *) ea);
259 err = __get_user(x, (unsigned short __user *) ea);
262 err = __get_user(x, (unsigned int __user *) ea);
266 err = __get_user(x, (unsigned long __user *) ea);
278 * Copy from userspace to a buffer, using the largest possible
279 * aligned accesses, up to sizeof(long).
281 static int nokprobe_inline copy_mem_in(u8 *dest, unsigned long ea, int nb,
282 struct pt_regs *regs)
287 for (; nb > 0; nb -= c) {
293 err = __get_user(*dest, (unsigned char __user *) ea);
296 err = __get_user(*(u16 *)dest,
297 (unsigned short __user *) ea);
300 err = __get_user(*(u32 *)dest,
301 (unsigned int __user *) ea);
305 err = __get_user(*(unsigned long *)dest,
306 (unsigned long __user *) ea);
320 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
321 unsigned long ea, int nb,
322 struct pt_regs *regs)
326 u8 b[sizeof(unsigned long)];
332 i = IS_BE ? sizeof(unsigned long) - nb : 0;
333 err = copy_mem_in(&u.b[i], ea, nb, regs);
340 * Read memory at address ea for nb bytes, return 0 for success
341 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
342 * If nb < sizeof(long), the result is right-justified on BE systems.
344 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
345 struct pt_regs *regs)
347 if (!address_ok(regs, ea, nb))
349 if ((ea & (nb - 1)) == 0)
350 return read_mem_aligned(dest, ea, nb, regs);
351 return read_mem_unaligned(dest, ea, nb, regs);
353 NOKPROBE_SYMBOL(read_mem);
355 static nokprobe_inline int write_mem_aligned(unsigned long val,
356 unsigned long ea, int nb,
357 struct pt_regs *regs)
363 err = __put_user(val, (unsigned char __user *) ea);
366 err = __put_user(val, (unsigned short __user *) ea);
369 err = __put_user(val, (unsigned int __user *) ea);
373 err = __put_user(val, (unsigned long __user *) ea);
383 * Copy from a buffer to userspace, using the largest possible
384 * aligned accesses, up to sizeof(long).
386 static int nokprobe_inline copy_mem_out(u8 *dest, unsigned long ea, int nb,
387 struct pt_regs *regs)
392 for (; nb > 0; nb -= c) {
398 err = __put_user(*dest, (unsigned char __user *) ea);
401 err = __put_user(*(u16 *)dest,
402 (unsigned short __user *) ea);
405 err = __put_user(*(u32 *)dest,
406 (unsigned int __user *) ea);
410 err = __put_user(*(unsigned long *)dest,
411 (unsigned long __user *) ea);
425 static nokprobe_inline int write_mem_unaligned(unsigned long val,
426 unsigned long ea, int nb,
427 struct pt_regs *regs)
431 u8 b[sizeof(unsigned long)];
436 i = IS_BE ? sizeof(unsigned long) - nb : 0;
437 return copy_mem_out(&u.b[i], ea, nb, regs);
441 * Write memory at address ea for nb bytes, return 0 for success
442 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
444 static int write_mem(unsigned long val, unsigned long ea, int nb,
445 struct pt_regs *regs)
447 if (!address_ok(regs, ea, nb))
449 if ((ea & (nb - 1)) == 0)
450 return write_mem_aligned(val, ea, nb, regs);
451 return write_mem_unaligned(val, ea, nb, regs);
453 NOKPROBE_SYMBOL(write_mem);
455 #ifdef CONFIG_PPC_FPU
457 * These access either the real FP register or the image in the
458 * thread_struct, depending on regs->msr & MSR_FP.
460 static int do_fp_load(struct instruction_op *op, unsigned long ea,
461 struct pt_regs *regs, bool cross_endian)
470 u8 b[2 * sizeof(double)];
473 nb = GETSIZE(op->type);
474 if (!address_ok(regs, ea, nb))
477 err = copy_mem_in(u.b, ea, nb, regs);
480 if (unlikely(cross_endian)) {
481 do_byte_reverse(u.b, min(nb, 8));
483 do_byte_reverse(&u.b[8], 8);
487 if (op->type & FPCONV)
488 conv_sp_to_dp(&u.f, &u.d[0]);
489 else if (op->type & SIGNEXT)
494 if (regs->msr & MSR_FP)
495 put_fpr(rn, &u.d[0]);
497 current->thread.TS_FPR(rn) = u.l[0];
501 if (regs->msr & MSR_FP)
502 put_fpr(rn, &u.d[1]);
504 current->thread.TS_FPR(rn) = u.l[1];
509 NOKPROBE_SYMBOL(do_fp_load);
511 static int do_fp_store(struct instruction_op *op, unsigned long ea,
512 struct pt_regs *regs, bool cross_endian)
520 u8 b[2 * sizeof(double)];
523 nb = GETSIZE(op->type);
524 if (!address_ok(regs, ea, nb))
528 if (regs->msr & MSR_FP)
529 get_fpr(rn, &u.d[0]);
531 u.l[0] = current->thread.TS_FPR(rn);
533 if (op->type & FPCONV)
534 conv_dp_to_sp(&u.d[0], &u.f);
540 if (regs->msr & MSR_FP)
541 get_fpr(rn, &u.d[1]);
543 u.l[1] = current->thread.TS_FPR(rn);
546 if (unlikely(cross_endian)) {
547 do_byte_reverse(u.b, min(nb, 8));
549 do_byte_reverse(&u.b[8], 8);
551 return copy_mem_out(u.b, ea, nb, regs);
553 NOKPROBE_SYMBOL(do_fp_store);
556 #ifdef CONFIG_ALTIVEC
557 /* For Altivec/VMX, no need to worry about alignment */
558 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
559 int size, struct pt_regs *regs,
565 u8 b[sizeof(__vector128)];
568 if (!address_ok(regs, ea & ~0xfUL, 16))
570 /* align to multiple of size */
572 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
575 if (unlikely(cross_endian))
576 do_byte_reverse(&u.b[ea & 0xf], size);
578 if (regs->msr & MSR_VEC)
581 current->thread.vr_state.vr[rn] = u.v;
586 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
587 int size, struct pt_regs *regs,
592 u8 b[sizeof(__vector128)];
595 if (!address_ok(regs, ea & ~0xfUL, 16))
597 /* align to multiple of size */
601 if (regs->msr & MSR_VEC)
604 u.v = current->thread.vr_state.vr[rn];
606 if (unlikely(cross_endian))
607 do_byte_reverse(&u.b[ea & 0xf], size);
608 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
610 #endif /* CONFIG_ALTIVEC */
613 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
614 int reg, bool cross_endian)
618 if (!address_ok(regs, ea, 16))
620 /* if aligned, should be atomic */
621 if ((ea & 0xf) == 0) {
622 err = do_lq(ea, ®s->gpr[reg]);
624 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs);
626 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs);
628 if (!err && unlikely(cross_endian))
629 do_byte_reverse(®s->gpr[reg], 16);
633 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
634 int reg, bool cross_endian)
637 unsigned long vals[2];
639 if (!address_ok(regs, ea, 16))
641 vals[0] = regs->gpr[reg];
642 vals[1] = regs->gpr[reg + 1];
643 if (unlikely(cross_endian))
644 do_byte_reverse(vals, 16);
646 /* if aligned, should be atomic */
648 return do_stq(ea, vals[0], vals[1]);
650 err = write_mem(vals[IS_LE], ea, 8, regs);
652 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
655 #endif /* __powerpc64 */
658 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
659 const void *mem, bool rev)
663 const unsigned int *wp;
664 const unsigned short *hp;
665 const unsigned char *bp;
667 size = GETSIZE(op->type);
668 reg->d[0] = reg->d[1] = 0;
670 switch (op->element_size) {
672 /* whole vector; lxv[x] or lxvl[l] */
675 memcpy(reg, mem, size);
676 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
679 do_byte_reverse(reg, 16);
682 /* scalar loads, lxvd2x, lxvdsx */
683 read_size = (size >= 8) ? 8 : size;
684 i = IS_LE ? 8 : 8 - read_size;
685 memcpy(®->b[i], mem, read_size);
687 do_byte_reverse(®->b[i], 8);
689 if (op->type & SIGNEXT) {
690 /* size == 4 is the only case here */
691 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
692 } else if (op->vsx_flags & VSX_FPCONV) {
694 conv_sp_to_dp(®->fp[1 + IS_LE],
700 unsigned long v = *(unsigned long *)(mem + 8);
701 reg->d[IS_BE] = !rev ? v : byterev_8(v);
702 } else if (op->vsx_flags & VSX_SPLAT)
703 reg->d[IS_BE] = reg->d[IS_LE];
709 for (j = 0; j < size / 4; ++j) {
710 i = IS_LE ? 3 - j : j;
711 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
713 if (op->vsx_flags & VSX_SPLAT) {
714 u32 val = reg->w[IS_LE ? 3 : 0];
716 i = IS_LE ? 3 - j : j;
724 for (j = 0; j < size / 2; ++j) {
725 i = IS_LE ? 7 - j : j;
726 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
732 for (j = 0; j < size; ++j) {
733 i = IS_LE ? 15 - j : j;
739 EXPORT_SYMBOL_GPL(emulate_vsx_load);
740 NOKPROBE_SYMBOL(emulate_vsx_load);
742 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
745 int size, write_size;
752 size = GETSIZE(op->type);
754 switch (op->element_size) {
756 /* stxv, stxvx, stxvl, stxvll */
759 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
762 /* reverse 16 bytes */
763 buf.d[0] = byterev_8(reg->d[1]);
764 buf.d[1] = byterev_8(reg->d[0]);
767 memcpy(mem, reg, size);
770 /* scalar stores, stxvd2x */
771 write_size = (size >= 8) ? 8 : size;
772 i = IS_LE ? 8 : 8 - write_size;
773 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
774 buf.d[0] = buf.d[1] = 0;
776 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]);
780 memcpy(mem, ®->b[i], write_size);
782 memcpy(mem + 8, ®->d[IS_BE], 8);
784 do_byte_reverse(mem, write_size);
786 do_byte_reverse(mem + 8, 8);
792 for (j = 0; j < size / 4; ++j) {
793 i = IS_LE ? 3 - j : j;
794 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
800 for (j = 0; j < size / 2; ++j) {
801 i = IS_LE ? 7 - j : j;
802 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
808 for (j = 0; j < size; ++j) {
809 i = IS_LE ? 15 - j : j;
815 EXPORT_SYMBOL_GPL(emulate_vsx_store);
816 NOKPROBE_SYMBOL(emulate_vsx_store);
818 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
819 unsigned long ea, struct pt_regs *regs,
825 int size = GETSIZE(op->type);
827 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
830 emulate_vsx_load(op, &buf, mem, cross_endian);
833 /* FP regs + extensions */
834 if (regs->msr & MSR_FP) {
835 load_vsrn(reg, &buf);
837 current->thread.fp_state.fpr[reg][0] = buf.d[0];
838 current->thread.fp_state.fpr[reg][1] = buf.d[1];
841 if (regs->msr & MSR_VEC)
842 load_vsrn(reg, &buf);
844 current->thread.vr_state.vr[reg - 32] = buf.v;
850 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
851 unsigned long ea, struct pt_regs *regs,
857 int size = GETSIZE(op->type);
859 if (!address_ok(regs, ea, size))
864 /* FP regs + extensions */
865 if (regs->msr & MSR_FP) {
866 store_vsrn(reg, &buf);
868 buf.d[0] = current->thread.fp_state.fpr[reg][0];
869 buf.d[1] = current->thread.fp_state.fpr[reg][1];
872 if (regs->msr & MSR_VEC)
873 store_vsrn(reg, &buf);
875 buf.v = current->thread.vr_state.vr[reg - 32];
878 emulate_vsx_store(op, &buf, mem, cross_endian);
879 return copy_mem_out(mem, ea, size, regs);
881 #endif /* CONFIG_VSX */
883 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
886 unsigned long i, size;
889 size = ppc64_caches.l1d.block_size;
890 if (!(regs->msr & MSR_64BIT))
893 size = L1_CACHE_BYTES;
896 if (!address_ok(regs, ea, size))
898 for (i = 0; i < size; i += sizeof(long)) {
899 err = __put_user(0, (unsigned long __user *) (ea + i));
907 NOKPROBE_SYMBOL(emulate_dcbz);
909 #define __put_user_asmx(x, addr, err, op, cr) \
910 __asm__ __volatile__( \
912 ".machine power8\n" \
913 "1: " op " %2,0,%3\n" \
917 ".section .fixup,\"ax\"\n" \
922 : "=r" (err), "=r" (cr) \
923 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
925 #define __get_user_asmx(x, addr, err, op) \
926 __asm__ __volatile__( \
928 ".machine power8\n" \
929 "1: "op" %1,0,%2\n" \
932 ".section .fixup,\"ax\"\n" \
937 : "=r" (err), "=r" (x) \
938 : "r" (addr), "i" (-EFAULT), "0" (err))
940 #define __cacheop_user_asmx(addr, err, op) \
941 __asm__ __volatile__( \
944 ".section .fixup,\"ax\"\n" \
950 : "r" (addr), "i" (-EFAULT), "0" (err))
952 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
953 struct instruction_op *op)
958 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
960 if (!(regs->msr & MSR_64BIT))
964 op->ccval |= 0x80000000;
966 op->ccval |= 0x40000000;
968 op->ccval |= 0x20000000;
971 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
972 struct instruction_op *op, int rd,
973 unsigned long val1, unsigned long val2,
974 unsigned long carry_in)
976 unsigned long val = val1 + val2;
980 op->type = COMPUTE + SETREG + SETXER;
984 if (!(regs->msr & MSR_64BIT)) {
985 val = (unsigned int) val;
986 val1 = (unsigned int) val1;
989 op->xerval = regs->xer;
990 if (val < val1 || (carry_in && val == val1))
991 op->xerval |= XER_CA;
993 op->xerval &= ~XER_CA;
996 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
997 struct instruction_op *op,
998 long v1, long v2, int crfld)
1000 unsigned int crval, shift;
1002 op->type = COMPUTE + SETCC;
1003 crval = (regs->xer >> 31) & 1; /* get SO bit */
1010 shift = (7 - crfld) * 4;
1011 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1014 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1015 struct instruction_op *op,
1017 unsigned long v2, int crfld)
1019 unsigned int crval, shift;
1021 op->type = COMPUTE + SETCC;
1022 crval = (regs->xer >> 31) & 1; /* get SO bit */
1029 shift = (7 - crfld) * 4;
1030 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1033 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1034 struct instruction_op *op,
1035 unsigned long v1, unsigned long v2)
1037 unsigned long long out_val, mask;
1041 for (i = 0; i < 8; i++) {
1042 mask = 0xffUL << (i * 8);
1043 if ((v1 & mask) == (v2 & mask))
1050 * The size parameter is used to adjust the equivalent popcnt instruction.
1051 * popcntb = 8, popcntw = 32, popcntd = 64
1053 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1054 struct instruction_op *op,
1055 unsigned long v1, int size)
1057 unsigned long long out = v1;
1059 out -= (out >> 1) & 0x5555555555555555;
1060 out = (0x3333333333333333 & out) + (0x3333333333333333 & (out >> 2));
1061 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0f;
1063 if (size == 8) { /* popcntb */
1069 if (size == 32) { /* popcntw */
1070 op->val = out & 0x0000003f0000003f;
1074 out = (out + (out >> 32)) & 0x7f;
1075 op->val = out; /* popcntd */
1079 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1080 struct instruction_op *op,
1081 unsigned long v1, unsigned long v2)
1083 unsigned char perm, idx;
1087 for (i = 0; i < 8; i++) {
1088 idx = (v1 >> (i * 8)) & 0xff;
1090 if (v2 & PPC_BIT(idx))
1095 #endif /* CONFIG_PPC64 */
1097 * The size parameter adjusts the equivalent prty instruction.
1098 * prtyw = 32, prtyd = 64
1100 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1101 struct instruction_op *op,
1102 unsigned long v, int size)
1104 unsigned long long res = v ^ (v >> 8);
1107 if (size == 32) { /* prtyw */
1108 op->val = res & 0x0000000100000001;
1113 op->val = res & 1; /*prtyd */
1116 static nokprobe_inline int trap_compare(long v1, long v2)
1126 if ((unsigned long)v1 < (unsigned long)v2)
1128 else if ((unsigned long)v1 > (unsigned long)v2)
1134 * Elements of 32-bit rotate and mask instructions.
1136 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
1137 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1138 #ifdef __powerpc64__
1139 #define MASK64_L(mb) (~0UL >> (mb))
1140 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))
1141 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1142 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1144 #define DATA32(x) (x)
1146 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1149 * Decode an instruction, and return information about it in *op
1150 * without changing *regs.
1151 * Integer arithmetic and logical instructions, branches, and barrier
1152 * instructions can be emulated just using the information in *op.
1154 * Return value is 1 if the instruction can be emulated just by
1155 * updating *regs with the information in *op, -1 if we need the
1156 * GPRs but *regs doesn't contain the full register set, or 0
1159 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1162 unsigned int opcode, ra, rb, rd, spr, u;
1163 unsigned long int imm;
1164 unsigned long int val, val2;
1165 unsigned int mb, me, sh;
1170 opcode = instr >> 26;
1174 imm = (signed short)(instr & 0xfffc);
1175 if ((instr & 2) == 0)
1177 op->val = truncate_if_32bit(regs->msr, imm);
1180 if (branch_taken(instr, regs, op))
1181 op->type |= BRTAKEN;
1185 if ((instr & 0xfe2) == 2)
1192 op->type = BRANCH | BRTAKEN;
1193 imm = instr & 0x03fffffc;
1194 if (imm & 0x02000000)
1196 if ((instr & 2) == 0)
1198 op->val = truncate_if_32bit(regs->msr, imm);
1203 switch ((instr >> 1) & 0x3ff) {
1205 op->type = COMPUTE + SETCC;
1206 rd = 7 - ((instr >> 23) & 0x7);
1207 ra = 7 - ((instr >> 18) & 0x7);
1210 val = (regs->ccr >> ra) & 0xf;
1211 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1215 case 528: /* bcctr */
1217 imm = (instr & 0x400)? regs->ctr: regs->link;
1218 op->val = truncate_if_32bit(regs->msr, imm);
1221 if (branch_taken(instr, regs, op))
1222 op->type |= BRTAKEN;
1225 case 18: /* rfid, scary */
1226 if (regs->msr & MSR_PR)
1231 case 150: /* isync */
1232 op->type = BARRIER | BARRIER_ISYNC;
1235 case 33: /* crnor */
1236 case 129: /* crandc */
1237 case 193: /* crxor */
1238 case 225: /* crnand */
1239 case 257: /* crand */
1240 case 289: /* creqv */
1241 case 417: /* crorc */
1242 case 449: /* cror */
1243 op->type = COMPUTE + SETCC;
1244 ra = (instr >> 16) & 0x1f;
1245 rb = (instr >> 11) & 0x1f;
1246 rd = (instr >> 21) & 0x1f;
1247 ra = (regs->ccr >> (31 - ra)) & 1;
1248 rb = (regs->ccr >> (31 - rb)) & 1;
1249 val = (instr >> (6 + ra * 2 + rb)) & 1;
1250 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1256 switch ((instr >> 1) & 0x3ff) {
1257 case 598: /* sync */
1258 op->type = BARRIER + BARRIER_SYNC;
1259 #ifdef __powerpc64__
1260 switch ((instr >> 21) & 3) {
1261 case 1: /* lwsync */
1262 op->type = BARRIER + BARRIER_LWSYNC;
1264 case 2: /* ptesync */
1265 op->type = BARRIER + BARRIER_PTESYNC;
1271 case 854: /* eieio */
1272 op->type = BARRIER + BARRIER_EIEIO;
1278 /* Following cases refer to regs->gpr[], so we need all regs */
1279 if (!FULL_REGS(regs))
1282 rd = (instr >> 21) & 0x1f;
1283 ra = (instr >> 16) & 0x1f;
1284 rb = (instr >> 11) & 0x1f;
1287 #ifdef __powerpc64__
1289 if (rd & trap_compare(regs->gpr[ra], (short) instr))
1294 if (rd & trap_compare((int)regs->gpr[ra], (short) instr))
1299 op->val = regs->gpr[ra] * (short) instr;
1302 case 8: /* subfic */
1303 imm = (short) instr;
1304 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1307 case 10: /* cmpli */
1308 imm = (unsigned short) instr;
1309 val = regs->gpr[ra];
1310 #ifdef __powerpc64__
1312 val = (unsigned int) val;
1314 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1318 imm = (short) instr;
1319 val = regs->gpr[ra];
1320 #ifdef __powerpc64__
1324 do_cmp_signed(regs, op, val, imm, rd >> 2);
1327 case 12: /* addic */
1328 imm = (short) instr;
1329 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1332 case 13: /* addic. */
1333 imm = (short) instr;
1334 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1339 imm = (short) instr;
1341 imm += regs->gpr[ra];
1345 case 15: /* addis */
1346 imm = ((short) instr) << 16;
1348 imm += regs->gpr[ra];
1353 if (((instr >> 1) & 0x1f) == 2) {
1355 imm = (short) (instr & 0xffc1); /* d0 + d2 fields */
1356 imm |= (instr >> 15) & 0x3e; /* d1 field */
1357 op->val = regs->nip + (imm << 16) + 4;
1363 case 20: /* rlwimi */
1364 mb = (instr >> 6) & 0x1f;
1365 me = (instr >> 1) & 0x1f;
1366 val = DATA32(regs->gpr[rd]);
1367 imm = MASK32(mb, me);
1368 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1371 case 21: /* rlwinm */
1372 mb = (instr >> 6) & 0x1f;
1373 me = (instr >> 1) & 0x1f;
1374 val = DATA32(regs->gpr[rd]);
1375 op->val = ROTATE(val, rb) & MASK32(mb, me);
1378 case 23: /* rlwnm */
1379 mb = (instr >> 6) & 0x1f;
1380 me = (instr >> 1) & 0x1f;
1381 rb = regs->gpr[rb] & 0x1f;
1382 val = DATA32(regs->gpr[rd]);
1383 op->val = ROTATE(val, rb) & MASK32(mb, me);
1387 op->val = regs->gpr[rd] | (unsigned short) instr;
1388 goto logical_done_nocc;
1391 imm = (unsigned short) instr;
1392 op->val = regs->gpr[rd] | (imm << 16);
1393 goto logical_done_nocc;
1396 op->val = regs->gpr[rd] ^ (unsigned short) instr;
1397 goto logical_done_nocc;
1399 case 27: /* xoris */
1400 imm = (unsigned short) instr;
1401 op->val = regs->gpr[rd] ^ (imm << 16);
1402 goto logical_done_nocc;
1404 case 28: /* andi. */
1405 op->val = regs->gpr[rd] & (unsigned short) instr;
1407 goto logical_done_nocc;
1409 case 29: /* andis. */
1410 imm = (unsigned short) instr;
1411 op->val = regs->gpr[rd] & (imm << 16);
1413 goto logical_done_nocc;
1415 #ifdef __powerpc64__
1417 mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
1418 val = regs->gpr[rd];
1419 if ((instr & 0x10) == 0) {
1420 sh = rb | ((instr & 2) << 4);
1421 val = ROTATE(val, sh);
1422 switch ((instr >> 2) & 3) {
1423 case 0: /* rldicl */
1424 val &= MASK64_L(mb);
1426 case 1: /* rldicr */
1427 val &= MASK64_R(mb);
1430 val &= MASK64(mb, 63 - sh);
1432 case 3: /* rldimi */
1433 imm = MASK64(mb, 63 - sh);
1434 val = (regs->gpr[ra] & ~imm) |
1440 sh = regs->gpr[rb] & 0x3f;
1441 val = ROTATE(val, sh);
1442 switch ((instr >> 1) & 7) {
1444 op->val = val & MASK64_L(mb);
1447 op->val = val & MASK64_R(mb);
1452 op->type = UNKNOWN; /* illegal instruction */
1456 /* isel occupies 32 minor opcodes */
1457 if (((instr >> 1) & 0x1f) == 15) {
1458 mb = (instr >> 6) & 0x1f; /* bc field */
1459 val = (regs->ccr >> (31 - mb)) & 1;
1460 val2 = (ra) ? regs->gpr[ra] : 0;
1462 op->val = (val) ? val2 : regs->gpr[rb];
1466 switch ((instr >> 1) & 0x3ff) {
1469 (rd & trap_compare((int)regs->gpr[ra],
1470 (int)regs->gpr[rb])))
1473 #ifdef __powerpc64__
1475 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1479 case 83: /* mfmsr */
1480 if (regs->msr & MSR_PR)
1485 case 146: /* mtmsr */
1486 if (regs->msr & MSR_PR)
1490 op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1493 case 178: /* mtmsrd */
1494 if (regs->msr & MSR_PR)
1498 /* only MSR_EE and MSR_RI get changed if bit 15 set */
1499 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1500 imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1507 if ((instr >> 20) & 1) {
1509 for (sh = 0; sh < 8; ++sh) {
1510 if (instr & (0x80000 >> sh))
1515 op->val = regs->ccr & imm;
1518 case 144: /* mtcrf */
1519 op->type = COMPUTE + SETCC;
1521 val = regs->gpr[rd];
1522 op->ccval = regs->ccr;
1523 for (sh = 0; sh < 8; ++sh) {
1524 if (instr & (0x80000 >> sh))
1525 op->ccval = (op->ccval & ~imm) |
1531 case 339: /* mfspr */
1532 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1536 if (spr == SPRN_XER || spr == SPRN_LR ||
1541 case 467: /* mtspr */
1542 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1544 op->val = regs->gpr[rd];
1546 if (spr == SPRN_XER || spr == SPRN_LR ||
1552 * Compare instructions
1555 val = regs->gpr[ra];
1556 val2 = regs->gpr[rb];
1557 #ifdef __powerpc64__
1558 if ((rd & 1) == 0) {
1559 /* word (32-bit) compare */
1564 do_cmp_signed(regs, op, val, val2, rd >> 2);
1568 val = regs->gpr[ra];
1569 val2 = regs->gpr[rb];
1570 #ifdef __powerpc64__
1571 if ((rd & 1) == 0) {
1572 /* word (32-bit) compare */
1573 val = (unsigned int) val;
1574 val2 = (unsigned int) val2;
1577 do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1580 case 508: /* cmpb */
1581 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1582 goto logical_done_nocc;
1585 * Arithmetic instructions
1588 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1591 #ifdef __powerpc64__
1592 case 9: /* mulhdu */
1593 asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1594 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1598 add_with_carry(regs, op, rd, regs->gpr[ra],
1602 case 11: /* mulhwu */
1603 asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1604 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1608 op->val = regs->gpr[rb] - regs->gpr[ra];
1610 #ifdef __powerpc64__
1611 case 73: /* mulhd */
1612 asm("mulhd %0,%1,%2" : "=r" (op->val) :
1613 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1616 case 75: /* mulhw */
1617 asm("mulhw %0,%1,%2" : "=r" (op->val) :
1618 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1622 op->val = -regs->gpr[ra];
1625 case 136: /* subfe */
1626 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1627 regs->gpr[rb], regs->xer & XER_CA);
1630 case 138: /* adde */
1631 add_with_carry(regs, op, rd, regs->gpr[ra],
1632 regs->gpr[rb], regs->xer & XER_CA);
1635 case 200: /* subfze */
1636 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1637 regs->xer & XER_CA);
1640 case 202: /* addze */
1641 add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1642 regs->xer & XER_CA);
1645 case 232: /* subfme */
1646 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1647 regs->xer & XER_CA);
1649 #ifdef __powerpc64__
1650 case 233: /* mulld */
1651 op->val = regs->gpr[ra] * regs->gpr[rb];
1654 case 234: /* addme */
1655 add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1656 regs->xer & XER_CA);
1659 case 235: /* mullw */
1660 op->val = (long)(int) regs->gpr[ra] *
1661 (int) regs->gpr[rb];
1666 op->val = regs->gpr[ra] + regs->gpr[rb];
1668 #ifdef __powerpc64__
1669 case 457: /* divdu */
1670 op->val = regs->gpr[ra] / regs->gpr[rb];
1673 case 459: /* divwu */
1674 op->val = (unsigned int) regs->gpr[ra] /
1675 (unsigned int) regs->gpr[rb];
1677 #ifdef __powerpc64__
1678 case 489: /* divd */
1679 op->val = (long int) regs->gpr[ra] /
1680 (long int) regs->gpr[rb];
1683 case 491: /* divw */
1684 op->val = (int) regs->gpr[ra] /
1685 (int) regs->gpr[rb];
1690 * Logical instructions
1692 case 26: /* cntlzw */
1693 val = (unsigned int) regs->gpr[rd];
1694 op->val = ( val ? __builtin_clz(val) : 32 );
1696 #ifdef __powerpc64__
1697 case 58: /* cntlzd */
1698 val = regs->gpr[rd];
1699 op->val = ( val ? __builtin_clzl(val) : 64 );
1703 op->val = regs->gpr[rd] & regs->gpr[rb];
1707 op->val = regs->gpr[rd] & ~regs->gpr[rb];
1710 case 122: /* popcntb */
1711 do_popcnt(regs, op, regs->gpr[rd], 8);
1712 goto logical_done_nocc;
1715 op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1718 case 154: /* prtyw */
1719 do_prty(regs, op, regs->gpr[rd], 32);
1720 goto logical_done_nocc;
1722 case 186: /* prtyd */
1723 do_prty(regs, op, regs->gpr[rd], 64);
1724 goto logical_done_nocc;
1726 case 252: /* bpermd */
1727 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1728 goto logical_done_nocc;
1731 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1735 op->val = regs->gpr[rd] ^ regs->gpr[rb];
1738 case 378: /* popcntw */
1739 do_popcnt(regs, op, regs->gpr[rd], 32);
1740 goto logical_done_nocc;
1743 op->val = regs->gpr[rd] | ~regs->gpr[rb];
1747 op->val = regs->gpr[rd] | regs->gpr[rb];
1750 case 476: /* nand */
1751 op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1754 case 506: /* popcntd */
1755 do_popcnt(regs, op, regs->gpr[rd], 64);
1756 goto logical_done_nocc;
1758 case 922: /* extsh */
1759 op->val = (signed short) regs->gpr[rd];
1762 case 954: /* extsb */
1763 op->val = (signed char) regs->gpr[rd];
1765 #ifdef __powerpc64__
1766 case 986: /* extsw */
1767 op->val = (signed int) regs->gpr[rd];
1772 * Shift instructions
1775 sh = regs->gpr[rb] & 0x3f;
1777 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1783 sh = regs->gpr[rb] & 0x3f;
1785 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
1790 case 792: /* sraw */
1791 op->type = COMPUTE + SETREG + SETXER;
1792 sh = regs->gpr[rb] & 0x3f;
1793 ival = (signed int) regs->gpr[rd];
1794 op->val = ival >> (sh < 32 ? sh : 31);
1795 op->xerval = regs->xer;
1796 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
1797 op->xerval |= XER_CA;
1799 op->xerval &= ~XER_CA;
1802 case 824: /* srawi */
1803 op->type = COMPUTE + SETREG + SETXER;
1805 ival = (signed int) regs->gpr[rd];
1806 op->val = ival >> sh;
1807 op->xerval = regs->xer;
1808 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1809 op->xerval |= XER_CA;
1811 op->xerval &= ~XER_CA;
1814 #ifdef __powerpc64__
1816 sh = regs->gpr[rb] & 0x7f;
1818 op->val = regs->gpr[rd] << sh;
1824 sh = regs->gpr[rb] & 0x7f;
1826 op->val = regs->gpr[rd] >> sh;
1831 case 794: /* srad */
1832 op->type = COMPUTE + SETREG + SETXER;
1833 sh = regs->gpr[rb] & 0x7f;
1834 ival = (signed long int) regs->gpr[rd];
1835 op->val = ival >> (sh < 64 ? sh : 63);
1836 op->xerval = regs->xer;
1837 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
1838 op->xerval |= XER_CA;
1840 op->xerval &= ~XER_CA;
1843 case 826: /* sradi with sh_5 = 0 */
1844 case 827: /* sradi with sh_5 = 1 */
1845 op->type = COMPUTE + SETREG + SETXER;
1846 sh = rb | ((instr & 2) << 4);
1847 ival = (signed long int) regs->gpr[rd];
1848 op->val = ival >> sh;
1849 op->xerval = regs->xer;
1850 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1851 op->xerval |= XER_CA;
1853 op->xerval &= ~XER_CA;
1855 #endif /* __powerpc64__ */
1858 * Cache instructions
1860 case 54: /* dcbst */
1861 op->type = MKOP(CACHEOP, DCBST, 0);
1862 op->ea = xform_ea(instr, regs);
1866 op->type = MKOP(CACHEOP, DCBF, 0);
1867 op->ea = xform_ea(instr, regs);
1870 case 246: /* dcbtst */
1871 op->type = MKOP(CACHEOP, DCBTST, 0);
1872 op->ea = xform_ea(instr, regs);
1876 case 278: /* dcbt */
1877 op->type = MKOP(CACHEOP, DCBTST, 0);
1878 op->ea = xform_ea(instr, regs);
1882 case 982: /* icbi */
1883 op->type = MKOP(CACHEOP, ICBI, 0);
1884 op->ea = xform_ea(instr, regs);
1887 case 1014: /* dcbz */
1888 op->type = MKOP(CACHEOP, DCBZ, 0);
1889 op->ea = xform_ea(instr, regs);
1899 op->update_reg = ra;
1901 op->val = regs->gpr[rd];
1902 u = (instr >> 20) & UPDATE;
1908 op->ea = xform_ea(instr, regs);
1909 switch ((instr >> 1) & 0x3ff) {
1910 case 20: /* lwarx */
1911 op->type = MKOP(LARX, 0, 4);
1914 case 150: /* stwcx. */
1915 op->type = MKOP(STCX, 0, 4);
1918 #ifdef __powerpc64__
1919 case 84: /* ldarx */
1920 op->type = MKOP(LARX, 0, 8);
1923 case 214: /* stdcx. */
1924 op->type = MKOP(STCX, 0, 8);
1927 case 52: /* lbarx */
1928 op->type = MKOP(LARX, 0, 1);
1931 case 694: /* stbcx. */
1932 op->type = MKOP(STCX, 0, 1);
1935 case 116: /* lharx */
1936 op->type = MKOP(LARX, 0, 2);
1939 case 726: /* sthcx. */
1940 op->type = MKOP(STCX, 0, 2);
1943 case 276: /* lqarx */
1944 if (!((rd & 1) || rd == ra || rd == rb))
1945 op->type = MKOP(LARX, 0, 16);
1948 case 182: /* stqcx. */
1950 op->type = MKOP(STCX, 0, 16);
1955 case 55: /* lwzux */
1956 op->type = MKOP(LOAD, u, 4);
1960 case 119: /* lbzux */
1961 op->type = MKOP(LOAD, u, 1);
1964 #ifdef CONFIG_ALTIVEC
1966 * Note: for the load/store vector element instructions,
1967 * bits of the EA say which field of the VMX register to use.
1970 op->type = MKOP(LOAD_VMX, 0, 1);
1971 op->element_size = 1;
1974 case 39: /* lvehx */
1975 op->type = MKOP(LOAD_VMX, 0, 2);
1976 op->element_size = 2;
1979 case 71: /* lvewx */
1980 op->type = MKOP(LOAD_VMX, 0, 4);
1981 op->element_size = 4;
1985 case 359: /* lvxl */
1986 op->type = MKOP(LOAD_VMX, 0, 16);
1987 op->element_size = 16;
1990 case 135: /* stvebx */
1991 op->type = MKOP(STORE_VMX, 0, 1);
1992 op->element_size = 1;
1995 case 167: /* stvehx */
1996 op->type = MKOP(STORE_VMX, 0, 2);
1997 op->element_size = 2;
2000 case 199: /* stvewx */
2001 op->type = MKOP(STORE_VMX, 0, 4);
2002 op->element_size = 4;
2005 case 231: /* stvx */
2006 case 487: /* stvxl */
2007 op->type = MKOP(STORE_VMX, 0, 16);
2009 #endif /* CONFIG_ALTIVEC */
2011 #ifdef __powerpc64__
2014 op->type = MKOP(LOAD, u, 8);
2017 case 149: /* stdx */
2018 case 181: /* stdux */
2019 op->type = MKOP(STORE, u, 8);
2023 case 151: /* stwx */
2024 case 183: /* stwux */
2025 op->type = MKOP(STORE, u, 4);
2028 case 215: /* stbx */
2029 case 247: /* stbux */
2030 op->type = MKOP(STORE, u, 1);
2033 case 279: /* lhzx */
2034 case 311: /* lhzux */
2035 op->type = MKOP(LOAD, u, 2);
2038 #ifdef __powerpc64__
2039 case 341: /* lwax */
2040 case 373: /* lwaux */
2041 op->type = MKOP(LOAD, SIGNEXT | u, 4);
2045 case 343: /* lhax */
2046 case 375: /* lhaux */
2047 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2050 case 407: /* sthx */
2051 case 439: /* sthux */
2052 op->type = MKOP(STORE, u, 2);
2055 #ifdef __powerpc64__
2056 case 532: /* ldbrx */
2057 op->type = MKOP(LOAD, BYTEREV, 8);
2061 case 533: /* lswx */
2062 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2065 case 534: /* lwbrx */
2066 op->type = MKOP(LOAD, BYTEREV, 4);
2069 case 597: /* lswi */
2071 rb = 32; /* # bytes to load */
2072 op->type = MKOP(LOAD_MULTI, 0, rb);
2073 op->ea = ra ? regs->gpr[ra] : 0;
2076 #ifdef CONFIG_PPC_FPU
2077 case 535: /* lfsx */
2078 case 567: /* lfsux */
2079 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2082 case 599: /* lfdx */
2083 case 631: /* lfdux */
2084 op->type = MKOP(LOAD_FP, u, 8);
2087 case 663: /* stfsx */
2088 case 695: /* stfsux */
2089 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2092 case 727: /* stfdx */
2093 case 759: /* stfdux */
2094 op->type = MKOP(STORE_FP, u, 8);
2097 #ifdef __powerpc64__
2098 case 791: /* lfdpx */
2099 op->type = MKOP(LOAD_FP, 0, 16);
2102 case 855: /* lfiwax */
2103 op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2106 case 887: /* lfiwzx */
2107 op->type = MKOP(LOAD_FP, 0, 4);
2110 case 919: /* stfdpx */
2111 op->type = MKOP(STORE_FP, 0, 16);
2114 case 983: /* stfiwx */
2115 op->type = MKOP(STORE_FP, 0, 4);
2117 #endif /* __powerpc64 */
2118 #endif /* CONFIG_PPC_FPU */
2120 #ifdef __powerpc64__
2121 case 660: /* stdbrx */
2122 op->type = MKOP(STORE, BYTEREV, 8);
2123 op->val = byterev_8(regs->gpr[rd]);
2127 case 661: /* stswx */
2128 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2131 case 662: /* stwbrx */
2132 op->type = MKOP(STORE, BYTEREV, 4);
2133 op->val = byterev_4(regs->gpr[rd]);
2136 case 725: /* stswi */
2138 rb = 32; /* # bytes to store */
2139 op->type = MKOP(STORE_MULTI, 0, rb);
2140 op->ea = ra ? regs->gpr[ra] : 0;
2143 case 790: /* lhbrx */
2144 op->type = MKOP(LOAD, BYTEREV, 2);
2147 case 918: /* sthbrx */
2148 op->type = MKOP(STORE, BYTEREV, 2);
2149 op->val = byterev_2(regs->gpr[rd]);
2153 case 12: /* lxsiwzx */
2154 op->reg = rd | ((instr & 1) << 5);
2155 op->type = MKOP(LOAD_VSX, 0, 4);
2156 op->element_size = 8;
2159 case 76: /* lxsiwax */
2160 op->reg = rd | ((instr & 1) << 5);
2161 op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2162 op->element_size = 8;
2165 case 140: /* stxsiwx */
2166 op->reg = rd | ((instr & 1) << 5);
2167 op->type = MKOP(STORE_VSX, 0, 4);
2168 op->element_size = 8;
2171 case 268: /* lxvx */
2172 op->reg = rd | ((instr & 1) << 5);
2173 op->type = MKOP(LOAD_VSX, 0, 16);
2174 op->element_size = 16;
2175 op->vsx_flags = VSX_CHECK_VEC;
2178 case 269: /* lxvl */
2179 case 301: { /* lxvll */
2181 op->reg = rd | ((instr & 1) << 5);
2182 op->ea = ra ? regs->gpr[ra] : 0;
2183 nb = regs->gpr[rb] & 0xff;
2186 op->type = MKOP(LOAD_VSX, 0, nb);
2187 op->element_size = 16;
2188 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2192 case 332: /* lxvdsx */
2193 op->reg = rd | ((instr & 1) << 5);
2194 op->type = MKOP(LOAD_VSX, 0, 8);
2195 op->element_size = 8;
2196 op->vsx_flags = VSX_SPLAT;
2199 case 364: /* lxvwsx */
2200 op->reg = rd | ((instr & 1) << 5);
2201 op->type = MKOP(LOAD_VSX, 0, 4);
2202 op->element_size = 4;
2203 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2206 case 396: /* stxvx */
2207 op->reg = rd | ((instr & 1) << 5);
2208 op->type = MKOP(STORE_VSX, 0, 16);
2209 op->element_size = 16;
2210 op->vsx_flags = VSX_CHECK_VEC;
2213 case 397: /* stxvl */
2214 case 429: { /* stxvll */
2216 op->reg = rd | ((instr & 1) << 5);
2217 op->ea = ra ? regs->gpr[ra] : 0;
2218 nb = regs->gpr[rb] & 0xff;
2221 op->type = MKOP(STORE_VSX, 0, nb);
2222 op->element_size = 16;
2223 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2227 case 524: /* lxsspx */
2228 op->reg = rd | ((instr & 1) << 5);
2229 op->type = MKOP(LOAD_VSX, 0, 4);
2230 op->element_size = 8;
2231 op->vsx_flags = VSX_FPCONV;
2234 case 588: /* lxsdx */
2235 op->reg = rd | ((instr & 1) << 5);
2236 op->type = MKOP(LOAD_VSX, 0, 8);
2237 op->element_size = 8;
2240 case 652: /* stxsspx */
2241 op->reg = rd | ((instr & 1) << 5);
2242 op->type = MKOP(STORE_VSX, 0, 4);
2243 op->element_size = 8;
2244 op->vsx_flags = VSX_FPCONV;
2247 case 716: /* stxsdx */
2248 op->reg = rd | ((instr & 1) << 5);
2249 op->type = MKOP(STORE_VSX, 0, 8);
2250 op->element_size = 8;
2253 case 780: /* lxvw4x */
2254 op->reg = rd | ((instr & 1) << 5);
2255 op->type = MKOP(LOAD_VSX, 0, 16);
2256 op->element_size = 4;
2259 case 781: /* lxsibzx */
2260 op->reg = rd | ((instr & 1) << 5);
2261 op->type = MKOP(LOAD_VSX, 0, 1);
2262 op->element_size = 8;
2263 op->vsx_flags = VSX_CHECK_VEC;
2266 case 812: /* lxvh8x */
2267 op->reg = rd | ((instr & 1) << 5);
2268 op->type = MKOP(LOAD_VSX, 0, 16);
2269 op->element_size = 2;
2270 op->vsx_flags = VSX_CHECK_VEC;
2273 case 813: /* lxsihzx */
2274 op->reg = rd | ((instr & 1) << 5);
2275 op->type = MKOP(LOAD_VSX, 0, 2);
2276 op->element_size = 8;
2277 op->vsx_flags = VSX_CHECK_VEC;
2280 case 844: /* lxvd2x */
2281 op->reg = rd | ((instr & 1) << 5);
2282 op->type = MKOP(LOAD_VSX, 0, 16);
2283 op->element_size = 8;
2286 case 876: /* lxvb16x */
2287 op->reg = rd | ((instr & 1) << 5);
2288 op->type = MKOP(LOAD_VSX, 0, 16);
2289 op->element_size = 1;
2290 op->vsx_flags = VSX_CHECK_VEC;
2293 case 908: /* stxvw4x */
2294 op->reg = rd | ((instr & 1) << 5);
2295 op->type = MKOP(STORE_VSX, 0, 16);
2296 op->element_size = 4;
2299 case 909: /* stxsibx */
2300 op->reg = rd | ((instr & 1) << 5);
2301 op->type = MKOP(STORE_VSX, 0, 1);
2302 op->element_size = 8;
2303 op->vsx_flags = VSX_CHECK_VEC;
2306 case 940: /* stxvh8x */
2307 op->reg = rd | ((instr & 1) << 5);
2308 op->type = MKOP(STORE_VSX, 0, 16);
2309 op->element_size = 2;
2310 op->vsx_flags = VSX_CHECK_VEC;
2313 case 941: /* stxsihx */
2314 op->reg = rd | ((instr & 1) << 5);
2315 op->type = MKOP(STORE_VSX, 0, 2);
2316 op->element_size = 8;
2317 op->vsx_flags = VSX_CHECK_VEC;
2320 case 972: /* stxvd2x */
2321 op->reg = rd | ((instr & 1) << 5);
2322 op->type = MKOP(STORE_VSX, 0, 16);
2323 op->element_size = 8;
2326 case 1004: /* stxvb16x */
2327 op->reg = rd | ((instr & 1) << 5);
2328 op->type = MKOP(STORE_VSX, 0, 16);
2329 op->element_size = 1;
2330 op->vsx_flags = VSX_CHECK_VEC;
2333 #endif /* CONFIG_VSX */
2339 op->type = MKOP(LOAD, u, 4);
2340 op->ea = dform_ea(instr, regs);
2345 op->type = MKOP(LOAD, u, 1);
2346 op->ea = dform_ea(instr, regs);
2351 op->type = MKOP(STORE, u, 4);
2352 op->ea = dform_ea(instr, regs);
2357 op->type = MKOP(STORE, u, 1);
2358 op->ea = dform_ea(instr, regs);
2363 op->type = MKOP(LOAD, u, 2);
2364 op->ea = dform_ea(instr, regs);
2369 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2370 op->ea = dform_ea(instr, regs);
2375 op->type = MKOP(STORE, u, 2);
2376 op->ea = dform_ea(instr, regs);
2381 break; /* invalid form, ra in range to load */
2382 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2383 op->ea = dform_ea(instr, regs);
2387 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2388 op->ea = dform_ea(instr, regs);
2391 #ifdef CONFIG_PPC_FPU
2394 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2395 op->ea = dform_ea(instr, regs);
2400 op->type = MKOP(LOAD_FP, u, 8);
2401 op->ea = dform_ea(instr, regs);
2405 case 53: /* stfsu */
2406 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2407 op->ea = dform_ea(instr, regs);
2411 case 55: /* stfdu */
2412 op->type = MKOP(STORE_FP, u, 8);
2413 op->ea = dform_ea(instr, regs);
2417 #ifdef __powerpc64__
2419 if (!((rd & 1) || (rd == ra)))
2420 op->type = MKOP(LOAD, 0, 16);
2421 op->ea = dqform_ea(instr, regs);
2426 case 57: /* lfdp, lxsd, lxssp */
2427 op->ea = dsform_ea(instr, regs);
2428 switch (instr & 3) {
2431 break; /* reg must be even */
2432 op->type = MKOP(LOAD_FP, 0, 16);
2436 op->type = MKOP(LOAD_VSX, 0, 8);
2437 op->element_size = 8;
2438 op->vsx_flags = VSX_CHECK_VEC;
2442 op->type = MKOP(LOAD_VSX, 0, 4);
2443 op->element_size = 8;
2444 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2448 #endif /* CONFIG_VSX */
2450 #ifdef __powerpc64__
2451 case 58: /* ld[u], lwa */
2452 op->ea = dsform_ea(instr, regs);
2453 switch (instr & 3) {
2455 op->type = MKOP(LOAD, 0, 8);
2458 op->type = MKOP(LOAD, UPDATE, 8);
2461 op->type = MKOP(LOAD, SIGNEXT, 4);
2468 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */
2469 switch (instr & 7) {
2470 case 0: /* stfdp with LSB of DS field = 0 */
2471 case 4: /* stfdp with LSB of DS field = 1 */
2472 op->ea = dsform_ea(instr, regs);
2473 op->type = MKOP(STORE_FP, 0, 16);
2477 op->ea = dqform_ea(instr, regs);
2480 op->type = MKOP(LOAD_VSX, 0, 16);
2481 op->element_size = 16;
2482 op->vsx_flags = VSX_CHECK_VEC;
2485 case 2: /* stxsd with LSB of DS field = 0 */
2486 case 6: /* stxsd with LSB of DS field = 1 */
2487 op->ea = dsform_ea(instr, regs);
2489 op->type = MKOP(STORE_VSX, 0, 8);
2490 op->element_size = 8;
2491 op->vsx_flags = VSX_CHECK_VEC;
2494 case 3: /* stxssp with LSB of DS field = 0 */
2495 case 7: /* stxssp with LSB of DS field = 1 */
2496 op->ea = dsform_ea(instr, regs);
2498 op->type = MKOP(STORE_VSX, 0, 4);
2499 op->element_size = 8;
2500 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2504 op->ea = dqform_ea(instr, regs);
2507 op->type = MKOP(STORE_VSX, 0, 16);
2508 op->element_size = 16;
2509 op->vsx_flags = VSX_CHECK_VEC;
2513 #endif /* CONFIG_VSX */
2515 #ifdef __powerpc64__
2516 case 62: /* std[u] */
2517 op->ea = dsform_ea(instr, regs);
2518 switch (instr & 3) {
2520 op->type = MKOP(STORE, 0, 8);
2523 op->type = MKOP(STORE, UPDATE, 8);
2527 op->type = MKOP(STORE, 0, 16);
2531 #endif /* __powerpc64__ */
2553 op->type = INTERRUPT | 0x700;
2554 op->val = SRR1_PROGPRIV;
2558 op->type = INTERRUPT | 0x700;
2559 op->val = SRR1_PROGTRAP;
2562 EXPORT_SYMBOL_GPL(analyse_instr);
2563 NOKPROBE_SYMBOL(analyse_instr);
2566 * For PPC32 we always use stwu with r1 to change the stack pointer.
2567 * So this emulated store may corrupt the exception frame, now we
2568 * have to provide the exception frame trampoline, which is pushed
2569 * below the kprobed function stack. So we only update gpr[1] but
2570 * don't emulate the real store operation. We will do real store
2571 * operation safely in exception return code by checking this flag.
2573 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
2577 * Check if we will touch kernel stack overflow
2579 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
2580 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
2583 #endif /* CONFIG_PPC32 */
2585 * Check if we already set since that means we'll
2586 * lose the previous value.
2588 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
2589 set_thread_flag(TIF_EMULATE_STACK_STORE);
2593 static nokprobe_inline void do_signext(unsigned long *valp, int size)
2597 *valp = (signed short) *valp;
2600 *valp = (signed int) *valp;
2605 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
2609 *valp = byterev_2(*valp);
2612 *valp = byterev_4(*valp);
2614 #ifdef __powerpc64__
2616 *valp = byterev_8(*valp);
2623 * Emulate an instruction that can be executed just by updating
2626 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
2628 unsigned long next_pc;
2630 next_pc = truncate_if_32bit(regs->msr, regs->nip + 4);
2631 switch (op->type & INSTR_TYPE_MASK) {
2633 if (op->type & SETREG)
2634 regs->gpr[op->reg] = op->val;
2635 if (op->type & SETCC)
2636 regs->ccr = op->ccval;
2637 if (op->type & SETXER)
2638 regs->xer = op->xerval;
2642 if (op->type & SETLK)
2643 regs->link = next_pc;
2644 if (op->type & BRTAKEN)
2646 if (op->type & DECCTR)
2651 switch (op->type & BARRIER_MASK) {
2662 case BARRIER_LWSYNC:
2663 asm volatile("lwsync" : : : "memory");
2665 case BARRIER_PTESYNC:
2666 asm volatile("ptesync" : : : "memory");
2675 regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
2678 regs->gpr[op->reg] = regs->link;
2681 regs->gpr[op->reg] = regs->ctr;
2691 regs->xer = op->val & 0xffffffffUL;
2694 regs->link = op->val;
2697 regs->ctr = op->val;
2707 regs->nip = next_pc;
2711 * Emulate a previously-analysed load or store instruction.
2712 * Return values are:
2713 * 0 = instruction emulated successfully
2714 * -EFAULT = address out of range or access faulted (regs->dar
2715 * contains the faulting address)
2716 * -EACCES = misaligned access, instruction requires alignment
2717 * -EINVAL = unknown operation in *op
2719 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
2721 int err, size, type;
2729 size = GETSIZE(op->type);
2730 type = op->type & INSTR_TYPE_MASK;
2731 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
2732 ea = truncate_if_32bit(regs->msr, op->ea);
2736 if (ea & (size - 1))
2737 return -EACCES; /* can't handle misaligned */
2738 if (!address_ok(regs, ea, size))
2743 #ifdef __powerpc64__
2745 __get_user_asmx(val, ea, err, "lbarx");
2748 __get_user_asmx(val, ea, err, "lharx");
2752 __get_user_asmx(val, ea, err, "lwarx");
2754 #ifdef __powerpc64__
2756 __get_user_asmx(val, ea, err, "ldarx");
2759 err = do_lqarx(ea, ®s->gpr[op->reg]);
2770 regs->gpr[op->reg] = val;
2774 if (ea & (size - 1))
2775 return -EACCES; /* can't handle misaligned */
2776 if (!address_ok(regs, ea, size))
2780 #ifdef __powerpc64__
2782 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
2785 __put_user_asmx(op->val, ea, err, "sthcx.", cr);
2789 __put_user_asmx(op->val, ea, err, "stwcx.", cr);
2791 #ifdef __powerpc64__
2793 __put_user_asmx(op->val, ea, err, "stdcx.", cr);
2796 err = do_stqcx(ea, regs->gpr[op->reg],
2797 regs->gpr[op->reg + 1], &cr);
2804 regs->ccr = (regs->ccr & 0x0fffffff) |
2806 ((regs->xer >> 3) & 0x10000000);
2812 #ifdef __powerpc64__
2814 err = emulate_lq(regs, ea, op->reg, cross_endian);
2818 err = read_mem(®s->gpr[op->reg], ea, size, regs);
2820 if (op->type & SIGNEXT)
2821 do_signext(®s->gpr[op->reg], size);
2822 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
2823 do_byterev(®s->gpr[op->reg], size);
2827 #ifdef CONFIG_PPC_FPU
2830 * If the instruction is in userspace, we can emulate it even
2831 * if the VMX state is not live, because we have the state
2832 * stored in the thread_struct. If the instruction is in
2833 * the kernel, we must not touch the state in the thread_struct.
2835 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2837 err = do_fp_load(op, ea, regs, cross_endian);
2840 #ifdef CONFIG_ALTIVEC
2842 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
2844 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
2849 unsigned long msrbit = MSR_VSX;
2852 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2853 * when the target of the instruction is a vector register.
2855 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
2857 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
2859 err = do_vsx_load(op, ea, regs, cross_endian);
2864 if (!address_ok(regs, ea, size))
2867 for (i = 0; i < size; i += 4) {
2868 unsigned int v32 = 0;
2873 err = copy_mem_in((u8 *) &v32, ea, nb, regs);
2876 if (unlikely(cross_endian))
2877 v32 = byterev_4(v32);
2878 regs->gpr[rd] = v32;
2880 /* reg number wraps from 31 to 0 for lsw[ix] */
2881 rd = (rd + 1) & 0x1f;
2886 #ifdef __powerpc64__
2888 err = emulate_stq(regs, ea, op->reg, cross_endian);
2892 if ((op->type & UPDATE) && size == sizeof(long) &&
2893 op->reg == 1 && op->update_reg == 1 &&
2894 !(regs->msr & MSR_PR) &&
2895 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
2896 err = handle_stack_update(ea, regs);
2899 if (unlikely(cross_endian))
2900 do_byterev(&op->val, size);
2901 err = write_mem(op->val, ea, size, regs);
2904 #ifdef CONFIG_PPC_FPU
2906 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2908 err = do_fp_store(op, ea, regs, cross_endian);
2911 #ifdef CONFIG_ALTIVEC
2913 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
2915 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
2920 unsigned long msrbit = MSR_VSX;
2923 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2924 * when the target of the instruction is a vector register.
2926 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
2928 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
2930 err = do_vsx_store(op, ea, regs, cross_endian);
2935 if (!address_ok(regs, ea, size))
2938 for (i = 0; i < size; i += 4) {
2939 unsigned int v32 = regs->gpr[rd];
2944 if (unlikely(cross_endian))
2945 v32 = byterev_4(v32);
2946 err = copy_mem_out((u8 *) &v32, ea, nb, regs);
2950 /* reg number wraps from 31 to 0 for stsw[ix] */
2951 rd = (rd + 1) & 0x1f;
2962 if (op->type & UPDATE)
2963 regs->gpr[op->update_reg] = op->ea;
2967 NOKPROBE_SYMBOL(emulate_loadstore);
2970 * Emulate instructions that cause a transfer of control,
2971 * loads and stores, and a few other instructions.
2972 * Returns 1 if the step was emulated, 0 if not,
2973 * or -1 if the instruction is one that should not be stepped,
2974 * such as an rfid, or a mtmsrd that would clear MSR_RI.
2976 int emulate_step(struct pt_regs *regs, unsigned int instr)
2978 struct instruction_op op;
2983 r = analyse_instr(&op, regs, instr);
2987 emulate_update_regs(regs, &op);
2992 type = op.type & INSTR_TYPE_MASK;
2994 if (OP_IS_LOAD_STORE(type)) {
2995 err = emulate_loadstore(regs, &op);
3003 ea = truncate_if_32bit(regs->msr, op.ea);
3004 if (!address_ok(regs, ea, 8))
3006 switch (op.type & CACHEOP_MASK) {
3008 __cacheop_user_asmx(ea, err, "dcbst");
3011 __cacheop_user_asmx(ea, err, "dcbf");
3015 prefetchw((void *) ea);
3019 prefetch((void *) ea);
3022 __cacheop_user_asmx(ea, err, "icbi");
3025 err = emulate_dcbz(ea, regs);
3035 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3039 val = regs->gpr[op.reg];
3040 if ((val & MSR_RI) == 0)
3041 /* can't step mtmsr[d] that would clear MSR_RI */
3043 /* here op.val is the mask of bits to change */
3044 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3048 case SYSCALL: /* sc */
3050 * N.B. this uses knowledge about how the syscall
3051 * entry code works. If that is changed, this will
3052 * need to be changed also.
3054 if (regs->gpr[0] == 0x1ebe &&
3055 cpu_has_feature(CPU_FTR_REAL_LE)) {
3056 regs->msr ^= MSR_LE;
3059 regs->gpr[9] = regs->gpr[13];
3060 regs->gpr[10] = MSR_KERNEL;
3061 regs->gpr[11] = regs->nip + 4;
3062 regs->gpr[12] = regs->msr & MSR_MASK;
3063 regs->gpr[13] = (unsigned long) get_paca();
3064 regs->nip = (unsigned long) &system_call_common;
3065 regs->msr = MSR_KERNEL;
3075 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
3078 NOKPROBE_SYMBOL(emulate_step);