1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
7 #include <linux/kernel.h>
8 #include <linux/kprobes.h>
9 #include <linux/ptrace.h>
10 #include <linux/prefetch.h>
11 #include <asm/sstep.h>
12 #include <asm/processor.h>
13 #include <linux/uaccess.h>
14 #include <asm/cpu_has_feature.h>
15 #include <asm/cputable.h>
17 extern char system_call_common[];
20 /* Bits in SRR1 that are copied from MSR */
21 #define MSR_MASK 0xffffffff87c0ffffUL
23 #define MSR_MASK 0x87c0ffff
27 #define XER_SO 0x80000000U
28 #define XER_OV 0x40000000U
29 #define XER_CA 0x20000000U
30 #define XER_OV32 0x00080000U
31 #define XER_CA32 0x00040000U
35 * Functions in ldstfp.S
37 extern void get_fpr(int rn, double *p);
38 extern void put_fpr(int rn, const double *p);
39 extern void get_vr(int rn, __vector128 *p);
40 extern void put_vr(int rn, __vector128 *p);
41 extern void load_vsrn(int vsr, const void *p);
42 extern void store_vsrn(int vsr, void *p);
43 extern void conv_sp_to_dp(const float *sp, double *dp);
44 extern void conv_dp_to_sp(const double *dp, float *sp);
51 extern int do_lq(unsigned long ea, unsigned long *regs);
52 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
53 extern int do_lqarx(unsigned long ea, unsigned long *regs);
54 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
58 #ifdef __LITTLE_ENDIAN__
67 * Emulate the truncation of 64 bit values in 32-bit mode.
69 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
73 if ((msr & MSR_64BIT) == 0)
80 * Determine whether a conditional branch instruction would branch.
82 static nokprobe_inline int branch_taken(unsigned int instr,
83 const struct pt_regs *regs,
84 struct instruction_op *op)
86 unsigned int bo = (instr >> 21) & 0x1f;
90 /* decrement counter */
92 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
95 if ((bo & 0x10) == 0) {
96 /* check bit from CR */
97 bi = (instr >> 16) & 0x1f;
98 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
104 static nokprobe_inline long address_ok(struct pt_regs *regs,
105 unsigned long ea, int nb)
107 if (!user_mode(regs))
109 if (__access_ok(ea, nb, USER_DS))
111 if (__access_ok(ea, 1, USER_DS))
112 /* Access overlaps the end of the user region */
113 regs->dar = USER_DS.seg;
120 * Calculate effective address for a D-form instruction
122 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
123 const struct pt_regs *regs)
128 ra = (instr >> 16) & 0x1f;
129 ea = (signed short) instr; /* sign-extend */
138 * Calculate effective address for a DS-form instruction
140 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
141 const struct pt_regs *regs)
146 ra = (instr >> 16) & 0x1f;
147 ea = (signed short) (instr & ~3); /* sign-extend */
155 * Calculate effective address for a DQ-form instruction
157 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
158 const struct pt_regs *regs)
163 ra = (instr >> 16) & 0x1f;
164 ea = (signed short) (instr & ~0xf); /* sign-extend */
170 #endif /* __powerpc64 */
173 * Calculate effective address for an X-form instruction
175 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
176 const struct pt_regs *regs)
181 ra = (instr >> 16) & 0x1f;
182 rb = (instr >> 11) & 0x1f;
191 * Return the largest power of 2, not greater than sizeof(unsigned long),
192 * such that x is a multiple of it.
194 static nokprobe_inline unsigned long max_align(unsigned long x)
196 x |= sizeof(unsigned long);
197 return x & -x; /* isolates rightmost bit */
200 static nokprobe_inline unsigned long byterev_2(unsigned long x)
202 return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
205 static nokprobe_inline unsigned long byterev_4(unsigned long x)
207 return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
208 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
212 static nokprobe_inline unsigned long byterev_8(unsigned long x)
214 return (byterev_4(x) << 32) | byterev_4(x >> 32);
218 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
222 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
225 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
229 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
232 unsigned long *up = (unsigned long *)ptr;
234 tmp = byterev_8(up[0]);
235 up[0] = byterev_8(up[1]);
245 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
246 unsigned long ea, int nb,
247 struct pt_regs *regs)
254 err = __get_user(x, (unsigned char __user *) ea);
257 err = __get_user(x, (unsigned short __user *) ea);
260 err = __get_user(x, (unsigned int __user *) ea);
264 err = __get_user(x, (unsigned long __user *) ea);
276 * Copy from userspace to a buffer, using the largest possible
277 * aligned accesses, up to sizeof(long).
279 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
280 struct pt_regs *regs)
285 for (; nb > 0; nb -= c) {
291 err = __get_user(*dest, (unsigned char __user *) ea);
294 err = __get_user(*(u16 *)dest,
295 (unsigned short __user *) ea);
298 err = __get_user(*(u32 *)dest,
299 (unsigned int __user *) ea);
303 err = __get_user(*(unsigned long *)dest,
304 (unsigned long __user *) ea);
318 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
319 unsigned long ea, int nb,
320 struct pt_regs *regs)
324 u8 b[sizeof(unsigned long)];
330 i = IS_BE ? sizeof(unsigned long) - nb : 0;
331 err = copy_mem_in(&u.b[i], ea, nb, regs);
338 * Read memory at address ea for nb bytes, return 0 for success
339 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
340 * If nb < sizeof(long), the result is right-justified on BE systems.
342 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
343 struct pt_regs *regs)
345 if (!address_ok(regs, ea, nb))
347 if ((ea & (nb - 1)) == 0)
348 return read_mem_aligned(dest, ea, nb, regs);
349 return read_mem_unaligned(dest, ea, nb, regs);
351 NOKPROBE_SYMBOL(read_mem);
353 static nokprobe_inline int write_mem_aligned(unsigned long val,
354 unsigned long ea, int nb,
355 struct pt_regs *regs)
361 err = __put_user(val, (unsigned char __user *) ea);
364 err = __put_user(val, (unsigned short __user *) ea);
367 err = __put_user(val, (unsigned int __user *) ea);
371 err = __put_user(val, (unsigned long __user *) ea);
381 * Copy from a buffer to userspace, using the largest possible
382 * aligned accesses, up to sizeof(long).
384 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
385 struct pt_regs *regs)
390 for (; nb > 0; nb -= c) {
396 err = __put_user(*dest, (unsigned char __user *) ea);
399 err = __put_user(*(u16 *)dest,
400 (unsigned short __user *) ea);
403 err = __put_user(*(u32 *)dest,
404 (unsigned int __user *) ea);
408 err = __put_user(*(unsigned long *)dest,
409 (unsigned long __user *) ea);
423 static nokprobe_inline int write_mem_unaligned(unsigned long val,
424 unsigned long ea, int nb,
425 struct pt_regs *regs)
429 u8 b[sizeof(unsigned long)];
434 i = IS_BE ? sizeof(unsigned long) - nb : 0;
435 return copy_mem_out(&u.b[i], ea, nb, regs);
439 * Write memory at address ea for nb bytes, return 0 for success
440 * or -EFAULT if an error occurred. N.B. nb must be 1, 2, 4 or 8.
442 static int write_mem(unsigned long val, unsigned long ea, int nb,
443 struct pt_regs *regs)
445 if (!address_ok(regs, ea, nb))
447 if ((ea & (nb - 1)) == 0)
448 return write_mem_aligned(val, ea, nb, regs);
449 return write_mem_unaligned(val, ea, nb, regs);
451 NOKPROBE_SYMBOL(write_mem);
453 #ifdef CONFIG_PPC_FPU
455 * These access either the real FP register or the image in the
456 * thread_struct, depending on regs->msr & MSR_FP.
458 static int do_fp_load(struct instruction_op *op, unsigned long ea,
459 struct pt_regs *regs, bool cross_endian)
468 u8 b[2 * sizeof(double)];
471 nb = GETSIZE(op->type);
474 if (!address_ok(regs, ea, nb))
477 err = copy_mem_in(u.b, ea, nb, regs);
480 if (unlikely(cross_endian)) {
481 do_byte_reverse(u.b, min(nb, 8));
483 do_byte_reverse(&u.b[8], 8);
487 if (op->type & FPCONV)
488 conv_sp_to_dp(&u.f, &u.d[0]);
489 else if (op->type & SIGNEXT)
494 if (regs->msr & MSR_FP)
495 put_fpr(rn, &u.d[0]);
497 current->thread.TS_FPR(rn) = u.l[0];
501 if (regs->msr & MSR_FP)
502 put_fpr(rn, &u.d[1]);
504 current->thread.TS_FPR(rn) = u.l[1];
509 NOKPROBE_SYMBOL(do_fp_load);
511 static int do_fp_store(struct instruction_op *op, unsigned long ea,
512 struct pt_regs *regs, bool cross_endian)
520 u8 b[2 * sizeof(double)];
523 nb = GETSIZE(op->type);
526 if (!address_ok(regs, ea, nb))
530 if (regs->msr & MSR_FP)
531 get_fpr(rn, &u.d[0]);
533 u.l[0] = current->thread.TS_FPR(rn);
535 if (op->type & FPCONV)
536 conv_dp_to_sp(&u.d[0], &u.f);
542 if (regs->msr & MSR_FP)
543 get_fpr(rn, &u.d[1]);
545 u.l[1] = current->thread.TS_FPR(rn);
548 if (unlikely(cross_endian)) {
549 do_byte_reverse(u.b, min(nb, 8));
551 do_byte_reverse(&u.b[8], 8);
553 return copy_mem_out(u.b, ea, nb, regs);
555 NOKPROBE_SYMBOL(do_fp_store);
558 #ifdef CONFIG_ALTIVEC
559 /* For Altivec/VMX, no need to worry about alignment */
560 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
561 int size, struct pt_regs *regs,
567 u8 b[sizeof(__vector128)];
570 if (size > sizeof(u))
573 if (!address_ok(regs, ea & ~0xfUL, 16))
575 /* align to multiple of size */
577 err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
580 if (unlikely(cross_endian))
581 do_byte_reverse(&u.b[ea & 0xf], size);
583 if (regs->msr & MSR_VEC)
586 current->thread.vr_state.vr[rn] = u.v;
591 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
592 int size, struct pt_regs *regs,
597 u8 b[sizeof(__vector128)];
600 if (size > sizeof(u))
603 if (!address_ok(regs, ea & ~0xfUL, 16))
605 /* align to multiple of size */
609 if (regs->msr & MSR_VEC)
612 u.v = current->thread.vr_state.vr[rn];
614 if (unlikely(cross_endian))
615 do_byte_reverse(&u.b[ea & 0xf], size);
616 return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
618 #endif /* CONFIG_ALTIVEC */
621 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
622 int reg, bool cross_endian)
626 if (!address_ok(regs, ea, 16))
628 /* if aligned, should be atomic */
629 if ((ea & 0xf) == 0) {
630 err = do_lq(ea, ®s->gpr[reg]);
632 err = read_mem(®s->gpr[reg + IS_LE], ea, 8, regs);
634 err = read_mem(®s->gpr[reg + IS_BE], ea + 8, 8, regs);
636 if (!err && unlikely(cross_endian))
637 do_byte_reverse(®s->gpr[reg], 16);
641 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
642 int reg, bool cross_endian)
645 unsigned long vals[2];
647 if (!address_ok(regs, ea, 16))
649 vals[0] = regs->gpr[reg];
650 vals[1] = regs->gpr[reg + 1];
651 if (unlikely(cross_endian))
652 do_byte_reverse(vals, 16);
654 /* if aligned, should be atomic */
656 return do_stq(ea, vals[0], vals[1]);
658 err = write_mem(vals[IS_LE], ea, 8, regs);
660 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
663 #endif /* __powerpc64 */
666 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
667 const void *mem, bool rev)
671 const unsigned int *wp;
672 const unsigned short *hp;
673 const unsigned char *bp;
675 size = GETSIZE(op->type);
676 reg->d[0] = reg->d[1] = 0;
678 switch (op->element_size) {
680 /* whole vector; lxv[x] or lxvl[l] */
683 memcpy(reg, mem, size);
684 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
687 do_byte_reverse(reg, 16);
690 /* scalar loads, lxvd2x, lxvdsx */
691 read_size = (size >= 8) ? 8 : size;
692 i = IS_LE ? 8 : 8 - read_size;
693 memcpy(®->b[i], mem, read_size);
695 do_byte_reverse(®->b[i], 8);
697 if (op->type & SIGNEXT) {
698 /* size == 4 is the only case here */
699 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
700 } else if (op->vsx_flags & VSX_FPCONV) {
702 conv_sp_to_dp(®->fp[1 + IS_LE],
708 unsigned long v = *(unsigned long *)(mem + 8);
709 reg->d[IS_BE] = !rev ? v : byterev_8(v);
710 } else if (op->vsx_flags & VSX_SPLAT)
711 reg->d[IS_BE] = reg->d[IS_LE];
717 for (j = 0; j < size / 4; ++j) {
718 i = IS_LE ? 3 - j : j;
719 reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
721 if (op->vsx_flags & VSX_SPLAT) {
722 u32 val = reg->w[IS_LE ? 3 : 0];
724 i = IS_LE ? 3 - j : j;
732 for (j = 0; j < size / 2; ++j) {
733 i = IS_LE ? 7 - j : j;
734 reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
740 for (j = 0; j < size; ++j) {
741 i = IS_LE ? 15 - j : j;
747 EXPORT_SYMBOL_GPL(emulate_vsx_load);
748 NOKPROBE_SYMBOL(emulate_vsx_load);
750 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
753 int size, write_size;
760 size = GETSIZE(op->type);
762 switch (op->element_size) {
764 /* stxv, stxvx, stxvl, stxvll */
767 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
770 /* reverse 16 bytes */
771 buf.d[0] = byterev_8(reg->d[1]);
772 buf.d[1] = byterev_8(reg->d[0]);
775 memcpy(mem, reg, size);
778 /* scalar stores, stxvd2x */
779 write_size = (size >= 8) ? 8 : size;
780 i = IS_LE ? 8 : 8 - write_size;
781 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
782 buf.d[0] = buf.d[1] = 0;
784 conv_dp_to_sp(®->dp[IS_LE], &buf.fp[1 + IS_LE]);
788 memcpy(mem, ®->b[i], write_size);
790 memcpy(mem + 8, ®->d[IS_BE], 8);
792 do_byte_reverse(mem, write_size);
794 do_byte_reverse(mem + 8, 8);
800 for (j = 0; j < size / 4; ++j) {
801 i = IS_LE ? 3 - j : j;
802 *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
808 for (j = 0; j < size / 2; ++j) {
809 i = IS_LE ? 7 - j : j;
810 *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
816 for (j = 0; j < size; ++j) {
817 i = IS_LE ? 15 - j : j;
823 EXPORT_SYMBOL_GPL(emulate_vsx_store);
824 NOKPROBE_SYMBOL(emulate_vsx_store);
826 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
827 unsigned long ea, struct pt_regs *regs,
833 int size = GETSIZE(op->type);
835 if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
838 emulate_vsx_load(op, &buf, mem, cross_endian);
841 /* FP regs + extensions */
842 if (regs->msr & MSR_FP) {
843 load_vsrn(reg, &buf);
845 current->thread.fp_state.fpr[reg][0] = buf.d[0];
846 current->thread.fp_state.fpr[reg][1] = buf.d[1];
849 if (regs->msr & MSR_VEC)
850 load_vsrn(reg, &buf);
852 current->thread.vr_state.vr[reg - 32] = buf.v;
858 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
859 unsigned long ea, struct pt_regs *regs,
865 int size = GETSIZE(op->type);
867 if (!address_ok(regs, ea, size))
872 /* FP regs + extensions */
873 if (regs->msr & MSR_FP) {
874 store_vsrn(reg, &buf);
876 buf.d[0] = current->thread.fp_state.fpr[reg][0];
877 buf.d[1] = current->thread.fp_state.fpr[reg][1];
880 if (regs->msr & MSR_VEC)
881 store_vsrn(reg, &buf);
883 buf.v = current->thread.vr_state.vr[reg - 32];
886 emulate_vsx_store(op, &buf, mem, cross_endian);
887 return copy_mem_out(mem, ea, size, regs);
889 #endif /* CONFIG_VSX */
891 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
894 unsigned long i, size;
897 size = ppc64_caches.l1d.block_size;
898 if (!(regs->msr & MSR_64BIT))
901 size = L1_CACHE_BYTES;
904 if (!address_ok(regs, ea, size))
906 for (i = 0; i < size; i += sizeof(long)) {
907 err = __put_user(0, (unsigned long __user *) (ea + i));
915 NOKPROBE_SYMBOL(emulate_dcbz);
917 #define __put_user_asmx(x, addr, err, op, cr) \
918 __asm__ __volatile__( \
920 ".machine power8\n" \
921 "1: " op " %2,0,%3\n" \
925 ".section .fixup,\"ax\"\n" \
930 : "=r" (err), "=r" (cr) \
931 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
933 #define __get_user_asmx(x, addr, err, op) \
934 __asm__ __volatile__( \
936 ".machine power8\n" \
937 "1: "op" %1,0,%2\n" \
940 ".section .fixup,\"ax\"\n" \
945 : "=r" (err), "=r" (x) \
946 : "r" (addr), "i" (-EFAULT), "0" (err))
948 #define __cacheop_user_asmx(addr, err, op) \
949 __asm__ __volatile__( \
952 ".section .fixup,\"ax\"\n" \
958 : "r" (addr), "i" (-EFAULT), "0" (err))
960 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
961 struct instruction_op *op)
966 op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
968 if (!(regs->msr & MSR_64BIT))
972 op->ccval |= 0x80000000;
974 op->ccval |= 0x40000000;
976 op->ccval |= 0x20000000;
979 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
981 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
983 op->xerval |= XER_CA32;
985 op->xerval &= ~XER_CA32;
989 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
990 struct instruction_op *op, int rd,
991 unsigned long val1, unsigned long val2,
992 unsigned long carry_in)
994 unsigned long val = val1 + val2;
998 op->type = COMPUTE + SETREG + SETXER;
1001 #ifdef __powerpc64__
1002 if (!(regs->msr & MSR_64BIT)) {
1003 val = (unsigned int) val;
1004 val1 = (unsigned int) val1;
1007 op->xerval = regs->xer;
1008 if (val < val1 || (carry_in && val == val1))
1009 op->xerval |= XER_CA;
1011 op->xerval &= ~XER_CA;
1013 set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1014 (carry_in && (unsigned int)val == (unsigned int)val1));
1017 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1018 struct instruction_op *op,
1019 long v1, long v2, int crfld)
1021 unsigned int crval, shift;
1023 op->type = COMPUTE + SETCC;
1024 crval = (regs->xer >> 31) & 1; /* get SO bit */
1031 shift = (7 - crfld) * 4;
1032 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1035 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1036 struct instruction_op *op,
1038 unsigned long v2, int crfld)
1040 unsigned int crval, shift;
1042 op->type = COMPUTE + SETCC;
1043 crval = (regs->xer >> 31) & 1; /* get SO bit */
1050 shift = (7 - crfld) * 4;
1051 op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1054 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1055 struct instruction_op *op,
1056 unsigned long v1, unsigned long v2)
1058 unsigned long long out_val, mask;
1062 for (i = 0; i < 8; i++) {
1063 mask = 0xffUL << (i * 8);
1064 if ((v1 & mask) == (v2 & mask))
1071 * The size parameter is used to adjust the equivalent popcnt instruction.
1072 * popcntb = 8, popcntw = 32, popcntd = 64
1074 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1075 struct instruction_op *op,
1076 unsigned long v1, int size)
1078 unsigned long long out = v1;
1080 out -= (out >> 1) & 0x5555555555555555ULL;
1081 out = (0x3333333333333333ULL & out) +
1082 (0x3333333333333333ULL & (out >> 2));
1083 out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1085 if (size == 8) { /* popcntb */
1091 if (size == 32) { /* popcntw */
1092 op->val = out & 0x0000003f0000003fULL;
1096 out = (out + (out >> 32)) & 0x7f;
1097 op->val = out; /* popcntd */
1101 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1102 struct instruction_op *op,
1103 unsigned long v1, unsigned long v2)
1105 unsigned char perm, idx;
1109 for (i = 0; i < 8; i++) {
1110 idx = (v1 >> (i * 8)) & 0xff;
1112 if (v2 & PPC_BIT(idx))
1117 #endif /* CONFIG_PPC64 */
1119 * The size parameter adjusts the equivalent prty instruction.
1120 * prtyw = 32, prtyd = 64
1122 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1123 struct instruction_op *op,
1124 unsigned long v, int size)
1126 unsigned long long res = v ^ (v >> 8);
1129 if (size == 32) { /* prtyw */
1130 op->val = res & 0x0000000100000001ULL;
1135 op->val = res & 1; /*prtyd */
1138 static nokprobe_inline int trap_compare(long v1, long v2)
1148 if ((unsigned long)v1 < (unsigned long)v2)
1150 else if ((unsigned long)v1 > (unsigned long)v2)
1156 * Elements of 32-bit rotate and mask instructions.
1158 #define MASK32(mb, me) ((0xffffffffUL >> (mb)) + \
1159 ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1160 #ifdef __powerpc64__
1161 #define MASK64_L(mb) (~0UL >> (mb))
1162 #define MASK64_R(me) ((signed long)-0x8000000000000000L >> (me))
1163 #define MASK64(mb, me) (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1164 #define DATA32(x) (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1166 #define DATA32(x) (x)
1168 #define ROTATE(x, n) ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1171 * Decode an instruction, and return information about it in *op
1172 * without changing *regs.
1173 * Integer arithmetic and logical instructions, branches, and barrier
1174 * instructions can be emulated just using the information in *op.
1176 * Return value is 1 if the instruction can be emulated just by
1177 * updating *regs with the information in *op, -1 if we need the
1178 * GPRs but *regs doesn't contain the full register set, or 0
1181 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1184 unsigned int opcode, ra, rb, rc, rd, spr, u;
1185 unsigned long int imm;
1186 unsigned long int val, val2;
1187 unsigned int mb, me, sh;
1192 opcode = instr >> 26;
1196 imm = (signed short)(instr & 0xfffc);
1197 if ((instr & 2) == 0)
1199 op->val = truncate_if_32bit(regs->msr, imm);
1202 if (branch_taken(instr, regs, op))
1203 op->type |= BRTAKEN;
1207 if ((instr & 0xfe2) == 2)
1214 op->type = BRANCH | BRTAKEN;
1215 imm = instr & 0x03fffffc;
1216 if (imm & 0x02000000)
1218 if ((instr & 2) == 0)
1220 op->val = truncate_if_32bit(regs->msr, imm);
1225 switch ((instr >> 1) & 0x3ff) {
1227 op->type = COMPUTE + SETCC;
1228 rd = 7 - ((instr >> 23) & 0x7);
1229 ra = 7 - ((instr >> 18) & 0x7);
1232 val = (regs->ccr >> ra) & 0xf;
1233 op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1237 case 528: /* bcctr */
1239 imm = (instr & 0x400)? regs->ctr: regs->link;
1240 op->val = truncate_if_32bit(regs->msr, imm);
1243 if (branch_taken(instr, regs, op))
1244 op->type |= BRTAKEN;
1247 case 18: /* rfid, scary */
1248 if (regs->msr & MSR_PR)
1253 case 150: /* isync */
1254 op->type = BARRIER | BARRIER_ISYNC;
1257 case 33: /* crnor */
1258 case 129: /* crandc */
1259 case 193: /* crxor */
1260 case 225: /* crnand */
1261 case 257: /* crand */
1262 case 289: /* creqv */
1263 case 417: /* crorc */
1264 case 449: /* cror */
1265 op->type = COMPUTE + SETCC;
1266 ra = (instr >> 16) & 0x1f;
1267 rb = (instr >> 11) & 0x1f;
1268 rd = (instr >> 21) & 0x1f;
1269 ra = (regs->ccr >> (31 - ra)) & 1;
1270 rb = (regs->ccr >> (31 - rb)) & 1;
1271 val = (instr >> (6 + ra * 2 + rb)) & 1;
1272 op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1278 switch ((instr >> 1) & 0x3ff) {
1279 case 598: /* sync */
1280 op->type = BARRIER + BARRIER_SYNC;
1281 #ifdef __powerpc64__
1282 switch ((instr >> 21) & 3) {
1283 case 1: /* lwsync */
1284 op->type = BARRIER + BARRIER_LWSYNC;
1286 case 2: /* ptesync */
1287 op->type = BARRIER + BARRIER_PTESYNC;
1293 case 854: /* eieio */
1294 op->type = BARRIER + BARRIER_EIEIO;
1300 /* Following cases refer to regs->gpr[], so we need all regs */
1301 if (!FULL_REGS(regs))
1304 rd = (instr >> 21) & 0x1f;
1305 ra = (instr >> 16) & 0x1f;
1306 rb = (instr >> 11) & 0x1f;
1307 rc = (instr >> 6) & 0x1f;
1310 #ifdef __powerpc64__
1312 if (rd & trap_compare(regs->gpr[ra], (short) instr))
1317 if (rd & trap_compare((int)regs->gpr[ra], (short) instr))
1321 #ifdef __powerpc64__
1323 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1326 switch (instr & 0x3f) {
1327 case 48: /* maddhd */
1328 asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1329 "=r" (op->val) : "r" (regs->gpr[ra]),
1330 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1333 case 49: /* maddhdu */
1334 asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1335 "=r" (op->val) : "r" (regs->gpr[ra]),
1336 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1339 case 51: /* maddld */
1340 asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1341 "=r" (op->val) : "r" (regs->gpr[ra]),
1342 "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1347 * There are other instructions from ISA 3.0 with the same
1348 * primary opcode which do not have emulation support yet.
1354 op->val = regs->gpr[ra] * (short) instr;
1357 case 8: /* subfic */
1358 imm = (short) instr;
1359 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1362 case 10: /* cmpli */
1363 imm = (unsigned short) instr;
1364 val = regs->gpr[ra];
1365 #ifdef __powerpc64__
1367 val = (unsigned int) val;
1369 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1373 imm = (short) instr;
1374 val = regs->gpr[ra];
1375 #ifdef __powerpc64__
1379 do_cmp_signed(regs, op, val, imm, rd >> 2);
1382 case 12: /* addic */
1383 imm = (short) instr;
1384 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1387 case 13: /* addic. */
1388 imm = (short) instr;
1389 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1394 imm = (short) instr;
1396 imm += regs->gpr[ra];
1400 case 15: /* addis */
1401 imm = ((short) instr) << 16;
1403 imm += regs->gpr[ra];
1408 if (((instr >> 1) & 0x1f) == 2) {
1410 imm = (short) (instr & 0xffc1); /* d0 + d2 fields */
1411 imm |= (instr >> 15) & 0x3e; /* d1 field */
1412 op->val = regs->nip + (imm << 16) + 4;
1418 case 20: /* rlwimi */
1419 mb = (instr >> 6) & 0x1f;
1420 me = (instr >> 1) & 0x1f;
1421 val = DATA32(regs->gpr[rd]);
1422 imm = MASK32(mb, me);
1423 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1426 case 21: /* rlwinm */
1427 mb = (instr >> 6) & 0x1f;
1428 me = (instr >> 1) & 0x1f;
1429 val = DATA32(regs->gpr[rd]);
1430 op->val = ROTATE(val, rb) & MASK32(mb, me);
1433 case 23: /* rlwnm */
1434 mb = (instr >> 6) & 0x1f;
1435 me = (instr >> 1) & 0x1f;
1436 rb = regs->gpr[rb] & 0x1f;
1437 val = DATA32(regs->gpr[rd]);
1438 op->val = ROTATE(val, rb) & MASK32(mb, me);
1442 op->val = regs->gpr[rd] | (unsigned short) instr;
1443 goto logical_done_nocc;
1446 imm = (unsigned short) instr;
1447 op->val = regs->gpr[rd] | (imm << 16);
1448 goto logical_done_nocc;
1451 op->val = regs->gpr[rd] ^ (unsigned short) instr;
1452 goto logical_done_nocc;
1454 case 27: /* xoris */
1455 imm = (unsigned short) instr;
1456 op->val = regs->gpr[rd] ^ (imm << 16);
1457 goto logical_done_nocc;
1459 case 28: /* andi. */
1460 op->val = regs->gpr[rd] & (unsigned short) instr;
1462 goto logical_done_nocc;
1464 case 29: /* andis. */
1465 imm = (unsigned short) instr;
1466 op->val = regs->gpr[rd] & (imm << 16);
1468 goto logical_done_nocc;
1470 #ifdef __powerpc64__
1472 mb = ((instr >> 6) & 0x1f) | (instr & 0x20);
1473 val = regs->gpr[rd];
1474 if ((instr & 0x10) == 0) {
1475 sh = rb | ((instr & 2) << 4);
1476 val = ROTATE(val, sh);
1477 switch ((instr >> 2) & 3) {
1478 case 0: /* rldicl */
1479 val &= MASK64_L(mb);
1481 case 1: /* rldicr */
1482 val &= MASK64_R(mb);
1485 val &= MASK64(mb, 63 - sh);
1487 case 3: /* rldimi */
1488 imm = MASK64(mb, 63 - sh);
1489 val = (regs->gpr[ra] & ~imm) |
1495 sh = regs->gpr[rb] & 0x3f;
1496 val = ROTATE(val, sh);
1497 switch ((instr >> 1) & 7) {
1499 op->val = val & MASK64_L(mb);
1502 op->val = val & MASK64_R(mb);
1507 op->type = UNKNOWN; /* illegal instruction */
1511 /* isel occupies 32 minor opcodes */
1512 if (((instr >> 1) & 0x1f) == 15) {
1513 mb = (instr >> 6) & 0x1f; /* bc field */
1514 val = (regs->ccr >> (31 - mb)) & 1;
1515 val2 = (ra) ? regs->gpr[ra] : 0;
1517 op->val = (val) ? val2 : regs->gpr[rb];
1521 switch ((instr >> 1) & 0x3ff) {
1524 (rd & trap_compare((int)regs->gpr[ra],
1525 (int)regs->gpr[rb])))
1528 #ifdef __powerpc64__
1530 if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1534 case 83: /* mfmsr */
1535 if (regs->msr & MSR_PR)
1540 case 146: /* mtmsr */
1541 if (regs->msr & MSR_PR)
1545 op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1548 case 178: /* mtmsrd */
1549 if (regs->msr & MSR_PR)
1553 /* only MSR_EE and MSR_RI get changed if bit 15 set */
1554 /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1555 imm = (instr & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1562 if ((instr >> 20) & 1) {
1564 for (sh = 0; sh < 8; ++sh) {
1565 if (instr & (0x80000 >> sh))
1570 op->val = regs->ccr & imm;
1573 case 144: /* mtcrf */
1574 op->type = COMPUTE + SETCC;
1576 val = regs->gpr[rd];
1577 op->ccval = regs->ccr;
1578 for (sh = 0; sh < 8; ++sh) {
1579 if (instr & (0x80000 >> sh))
1580 op->ccval = (op->ccval & ~imm) |
1586 case 339: /* mfspr */
1587 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1591 if (spr == SPRN_XER || spr == SPRN_LR ||
1596 case 467: /* mtspr */
1597 spr = ((instr >> 16) & 0x1f) | ((instr >> 6) & 0x3e0);
1599 op->val = regs->gpr[rd];
1601 if (spr == SPRN_XER || spr == SPRN_LR ||
1607 * Compare instructions
1610 val = regs->gpr[ra];
1611 val2 = regs->gpr[rb];
1612 #ifdef __powerpc64__
1613 if ((rd & 1) == 0) {
1614 /* word (32-bit) compare */
1619 do_cmp_signed(regs, op, val, val2, rd >> 2);
1623 val = regs->gpr[ra];
1624 val2 = regs->gpr[rb];
1625 #ifdef __powerpc64__
1626 if ((rd & 1) == 0) {
1627 /* word (32-bit) compare */
1628 val = (unsigned int) val;
1629 val2 = (unsigned int) val2;
1632 do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1635 case 508: /* cmpb */
1636 do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1637 goto logical_done_nocc;
1640 * Arithmetic instructions
1643 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1646 #ifdef __powerpc64__
1647 case 9: /* mulhdu */
1648 asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1649 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1653 add_with_carry(regs, op, rd, regs->gpr[ra],
1657 case 11: /* mulhwu */
1658 asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1659 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1663 op->val = regs->gpr[rb] - regs->gpr[ra];
1665 #ifdef __powerpc64__
1666 case 73: /* mulhd */
1667 asm("mulhd %0,%1,%2" : "=r" (op->val) :
1668 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1671 case 75: /* mulhw */
1672 asm("mulhw %0,%1,%2" : "=r" (op->val) :
1673 "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1677 op->val = -regs->gpr[ra];
1680 case 136: /* subfe */
1681 add_with_carry(regs, op, rd, ~regs->gpr[ra],
1682 regs->gpr[rb], regs->xer & XER_CA);
1685 case 138: /* adde */
1686 add_with_carry(regs, op, rd, regs->gpr[ra],
1687 regs->gpr[rb], regs->xer & XER_CA);
1690 case 200: /* subfze */
1691 add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1692 regs->xer & XER_CA);
1695 case 202: /* addze */
1696 add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1697 regs->xer & XER_CA);
1700 case 232: /* subfme */
1701 add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1702 regs->xer & XER_CA);
1704 #ifdef __powerpc64__
1705 case 233: /* mulld */
1706 op->val = regs->gpr[ra] * regs->gpr[rb];
1709 case 234: /* addme */
1710 add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1711 regs->xer & XER_CA);
1714 case 235: /* mullw */
1715 op->val = (long)(int) regs->gpr[ra] *
1716 (int) regs->gpr[rb];
1719 #ifdef __powerpc64__
1720 case 265: /* modud */
1721 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1723 op->val = regs->gpr[ra] % regs->gpr[rb];
1727 op->val = regs->gpr[ra] + regs->gpr[rb];
1730 case 267: /* moduw */
1731 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1733 op->val = (unsigned int) regs->gpr[ra] %
1734 (unsigned int) regs->gpr[rb];
1736 #ifdef __powerpc64__
1737 case 457: /* divdu */
1738 op->val = regs->gpr[ra] / regs->gpr[rb];
1741 case 459: /* divwu */
1742 op->val = (unsigned int) regs->gpr[ra] /
1743 (unsigned int) regs->gpr[rb];
1745 #ifdef __powerpc64__
1746 case 489: /* divd */
1747 op->val = (long int) regs->gpr[ra] /
1748 (long int) regs->gpr[rb];
1751 case 491: /* divw */
1752 op->val = (int) regs->gpr[ra] /
1753 (int) regs->gpr[rb];
1756 case 755: /* darn */
1757 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1761 /* 32-bit conditioned */
1762 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1766 /* 64-bit conditioned */
1767 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1772 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1777 #ifdef __powerpc64__
1778 case 777: /* modsd */
1779 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1781 op->val = (long int) regs->gpr[ra] %
1782 (long int) regs->gpr[rb];
1785 case 779: /* modsw */
1786 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1788 op->val = (int) regs->gpr[ra] %
1789 (int) regs->gpr[rb];
1794 * Logical instructions
1796 case 26: /* cntlzw */
1797 val = (unsigned int) regs->gpr[rd];
1798 op->val = ( val ? __builtin_clz(val) : 32 );
1800 #ifdef __powerpc64__
1801 case 58: /* cntlzd */
1802 val = regs->gpr[rd];
1803 op->val = ( val ? __builtin_clzl(val) : 64 );
1807 op->val = regs->gpr[rd] & regs->gpr[rb];
1811 op->val = regs->gpr[rd] & ~regs->gpr[rb];
1814 case 122: /* popcntb */
1815 do_popcnt(regs, op, regs->gpr[rd], 8);
1816 goto logical_done_nocc;
1819 op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1822 case 154: /* prtyw */
1823 do_prty(regs, op, regs->gpr[rd], 32);
1824 goto logical_done_nocc;
1826 case 186: /* prtyd */
1827 do_prty(regs, op, regs->gpr[rd], 64);
1828 goto logical_done_nocc;
1830 case 252: /* bpermd */
1831 do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
1832 goto logical_done_nocc;
1835 op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
1839 op->val = regs->gpr[rd] ^ regs->gpr[rb];
1842 case 378: /* popcntw */
1843 do_popcnt(regs, op, regs->gpr[rd], 32);
1844 goto logical_done_nocc;
1847 op->val = regs->gpr[rd] | ~regs->gpr[rb];
1851 op->val = regs->gpr[rd] | regs->gpr[rb];
1854 case 476: /* nand */
1855 op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
1858 case 506: /* popcntd */
1859 do_popcnt(regs, op, regs->gpr[rd], 64);
1860 goto logical_done_nocc;
1862 case 538: /* cnttzw */
1863 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1865 val = (unsigned int) regs->gpr[rd];
1866 op->val = (val ? __builtin_ctz(val) : 32);
1868 #ifdef __powerpc64__
1869 case 570: /* cnttzd */
1870 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1872 val = regs->gpr[rd];
1873 op->val = (val ? __builtin_ctzl(val) : 64);
1876 case 922: /* extsh */
1877 op->val = (signed short) regs->gpr[rd];
1880 case 954: /* extsb */
1881 op->val = (signed char) regs->gpr[rd];
1883 #ifdef __powerpc64__
1884 case 986: /* extsw */
1885 op->val = (signed int) regs->gpr[rd];
1890 * Shift instructions
1893 sh = regs->gpr[rb] & 0x3f;
1895 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
1901 sh = regs->gpr[rb] & 0x3f;
1903 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
1908 case 792: /* sraw */
1909 op->type = COMPUTE + SETREG + SETXER;
1910 sh = regs->gpr[rb] & 0x3f;
1911 ival = (signed int) regs->gpr[rd];
1912 op->val = ival >> (sh < 32 ? sh : 31);
1913 op->xerval = regs->xer;
1914 if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
1915 op->xerval |= XER_CA;
1917 op->xerval &= ~XER_CA;
1918 set_ca32(op, op->xerval & XER_CA);
1921 case 824: /* srawi */
1922 op->type = COMPUTE + SETREG + SETXER;
1924 ival = (signed int) regs->gpr[rd];
1925 op->val = ival >> sh;
1926 op->xerval = regs->xer;
1927 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1928 op->xerval |= XER_CA;
1930 op->xerval &= ~XER_CA;
1931 set_ca32(op, op->xerval & XER_CA);
1934 #ifdef __powerpc64__
1936 sh = regs->gpr[rb] & 0x7f;
1938 op->val = regs->gpr[rd] << sh;
1944 sh = regs->gpr[rb] & 0x7f;
1946 op->val = regs->gpr[rd] >> sh;
1951 case 794: /* srad */
1952 op->type = COMPUTE + SETREG + SETXER;
1953 sh = regs->gpr[rb] & 0x7f;
1954 ival = (signed long int) regs->gpr[rd];
1955 op->val = ival >> (sh < 64 ? sh : 63);
1956 op->xerval = regs->xer;
1957 if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
1958 op->xerval |= XER_CA;
1960 op->xerval &= ~XER_CA;
1961 set_ca32(op, op->xerval & XER_CA);
1964 case 826: /* sradi with sh_5 = 0 */
1965 case 827: /* sradi with sh_5 = 1 */
1966 op->type = COMPUTE + SETREG + SETXER;
1967 sh = rb | ((instr & 2) << 4);
1968 ival = (signed long int) regs->gpr[rd];
1969 op->val = ival >> sh;
1970 op->xerval = regs->xer;
1971 if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
1972 op->xerval |= XER_CA;
1974 op->xerval &= ~XER_CA;
1975 set_ca32(op, op->xerval & XER_CA);
1978 case 890: /* extswsli with sh_5 = 0 */
1979 case 891: /* extswsli with sh_5 = 1 */
1980 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1982 op->type = COMPUTE + SETREG;
1983 sh = rb | ((instr & 2) << 4);
1984 val = (signed int) regs->gpr[rd];
1986 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
1991 #endif /* __powerpc64__ */
1994 * Cache instructions
1996 case 54: /* dcbst */
1997 op->type = MKOP(CACHEOP, DCBST, 0);
1998 op->ea = xform_ea(instr, regs);
2002 op->type = MKOP(CACHEOP, DCBF, 0);
2003 op->ea = xform_ea(instr, regs);
2006 case 246: /* dcbtst */
2007 op->type = MKOP(CACHEOP, DCBTST, 0);
2008 op->ea = xform_ea(instr, regs);
2012 case 278: /* dcbt */
2013 op->type = MKOP(CACHEOP, DCBTST, 0);
2014 op->ea = xform_ea(instr, regs);
2018 case 982: /* icbi */
2019 op->type = MKOP(CACHEOP, ICBI, 0);
2020 op->ea = xform_ea(instr, regs);
2023 case 1014: /* dcbz */
2024 op->type = MKOP(CACHEOP, DCBZ, 0);
2025 op->ea = xform_ea(instr, regs);
2035 op->update_reg = ra;
2037 op->val = regs->gpr[rd];
2038 u = (instr >> 20) & UPDATE;
2044 op->ea = xform_ea(instr, regs);
2045 switch ((instr >> 1) & 0x3ff) {
2046 case 20: /* lwarx */
2047 op->type = MKOP(LARX, 0, 4);
2050 case 150: /* stwcx. */
2051 op->type = MKOP(STCX, 0, 4);
2054 #ifdef __powerpc64__
2055 case 84: /* ldarx */
2056 op->type = MKOP(LARX, 0, 8);
2059 case 214: /* stdcx. */
2060 op->type = MKOP(STCX, 0, 8);
2063 case 52: /* lbarx */
2064 op->type = MKOP(LARX, 0, 1);
2067 case 694: /* stbcx. */
2068 op->type = MKOP(STCX, 0, 1);
2071 case 116: /* lharx */
2072 op->type = MKOP(LARX, 0, 2);
2075 case 726: /* sthcx. */
2076 op->type = MKOP(STCX, 0, 2);
2079 case 276: /* lqarx */
2080 if (!((rd & 1) || rd == ra || rd == rb))
2081 op->type = MKOP(LARX, 0, 16);
2084 case 182: /* stqcx. */
2086 op->type = MKOP(STCX, 0, 16);
2091 case 55: /* lwzux */
2092 op->type = MKOP(LOAD, u, 4);
2096 case 119: /* lbzux */
2097 op->type = MKOP(LOAD, u, 1);
2100 #ifdef CONFIG_ALTIVEC
2102 * Note: for the load/store vector element instructions,
2103 * bits of the EA say which field of the VMX register to use.
2106 op->type = MKOP(LOAD_VMX, 0, 1);
2107 op->element_size = 1;
2110 case 39: /* lvehx */
2111 op->type = MKOP(LOAD_VMX, 0, 2);
2112 op->element_size = 2;
2115 case 71: /* lvewx */
2116 op->type = MKOP(LOAD_VMX, 0, 4);
2117 op->element_size = 4;
2121 case 359: /* lvxl */
2122 op->type = MKOP(LOAD_VMX, 0, 16);
2123 op->element_size = 16;
2126 case 135: /* stvebx */
2127 op->type = MKOP(STORE_VMX, 0, 1);
2128 op->element_size = 1;
2131 case 167: /* stvehx */
2132 op->type = MKOP(STORE_VMX, 0, 2);
2133 op->element_size = 2;
2136 case 199: /* stvewx */
2137 op->type = MKOP(STORE_VMX, 0, 4);
2138 op->element_size = 4;
2141 case 231: /* stvx */
2142 case 487: /* stvxl */
2143 op->type = MKOP(STORE_VMX, 0, 16);
2145 #endif /* CONFIG_ALTIVEC */
2147 #ifdef __powerpc64__
2150 op->type = MKOP(LOAD, u, 8);
2153 case 149: /* stdx */
2154 case 181: /* stdux */
2155 op->type = MKOP(STORE, u, 8);
2159 case 151: /* stwx */
2160 case 183: /* stwux */
2161 op->type = MKOP(STORE, u, 4);
2164 case 215: /* stbx */
2165 case 247: /* stbux */
2166 op->type = MKOP(STORE, u, 1);
2169 case 279: /* lhzx */
2170 case 311: /* lhzux */
2171 op->type = MKOP(LOAD, u, 2);
2174 #ifdef __powerpc64__
2175 case 341: /* lwax */
2176 case 373: /* lwaux */
2177 op->type = MKOP(LOAD, SIGNEXT | u, 4);
2181 case 343: /* lhax */
2182 case 375: /* lhaux */
2183 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2186 case 407: /* sthx */
2187 case 439: /* sthux */
2188 op->type = MKOP(STORE, u, 2);
2191 #ifdef __powerpc64__
2192 case 532: /* ldbrx */
2193 op->type = MKOP(LOAD, BYTEREV, 8);
2197 case 533: /* lswx */
2198 op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2201 case 534: /* lwbrx */
2202 op->type = MKOP(LOAD, BYTEREV, 4);
2205 case 597: /* lswi */
2207 rb = 32; /* # bytes to load */
2208 op->type = MKOP(LOAD_MULTI, 0, rb);
2209 op->ea = ra ? regs->gpr[ra] : 0;
2212 #ifdef CONFIG_PPC_FPU
2213 case 535: /* lfsx */
2214 case 567: /* lfsux */
2215 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2218 case 599: /* lfdx */
2219 case 631: /* lfdux */
2220 op->type = MKOP(LOAD_FP, u, 8);
2223 case 663: /* stfsx */
2224 case 695: /* stfsux */
2225 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2228 case 727: /* stfdx */
2229 case 759: /* stfdux */
2230 op->type = MKOP(STORE_FP, u, 8);
2233 #ifdef __powerpc64__
2234 case 791: /* lfdpx */
2235 op->type = MKOP(LOAD_FP, 0, 16);
2238 case 855: /* lfiwax */
2239 op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2242 case 887: /* lfiwzx */
2243 op->type = MKOP(LOAD_FP, 0, 4);
2246 case 919: /* stfdpx */
2247 op->type = MKOP(STORE_FP, 0, 16);
2250 case 983: /* stfiwx */
2251 op->type = MKOP(STORE_FP, 0, 4);
2253 #endif /* __powerpc64 */
2254 #endif /* CONFIG_PPC_FPU */
2256 #ifdef __powerpc64__
2257 case 660: /* stdbrx */
2258 op->type = MKOP(STORE, BYTEREV, 8);
2259 op->val = byterev_8(regs->gpr[rd]);
2263 case 661: /* stswx */
2264 op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2267 case 662: /* stwbrx */
2268 op->type = MKOP(STORE, BYTEREV, 4);
2269 op->val = byterev_4(regs->gpr[rd]);
2272 case 725: /* stswi */
2274 rb = 32; /* # bytes to store */
2275 op->type = MKOP(STORE_MULTI, 0, rb);
2276 op->ea = ra ? regs->gpr[ra] : 0;
2279 case 790: /* lhbrx */
2280 op->type = MKOP(LOAD, BYTEREV, 2);
2283 case 918: /* sthbrx */
2284 op->type = MKOP(STORE, BYTEREV, 2);
2285 op->val = byterev_2(regs->gpr[rd]);
2289 case 12: /* lxsiwzx */
2290 op->reg = rd | ((instr & 1) << 5);
2291 op->type = MKOP(LOAD_VSX, 0, 4);
2292 op->element_size = 8;
2295 case 76: /* lxsiwax */
2296 op->reg = rd | ((instr & 1) << 5);
2297 op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2298 op->element_size = 8;
2301 case 140: /* stxsiwx */
2302 op->reg = rd | ((instr & 1) << 5);
2303 op->type = MKOP(STORE_VSX, 0, 4);
2304 op->element_size = 8;
2307 case 268: /* lxvx */
2308 op->reg = rd | ((instr & 1) << 5);
2309 op->type = MKOP(LOAD_VSX, 0, 16);
2310 op->element_size = 16;
2311 op->vsx_flags = VSX_CHECK_VEC;
2314 case 269: /* lxvl */
2315 case 301: { /* lxvll */
2317 op->reg = rd | ((instr & 1) << 5);
2318 op->ea = ra ? regs->gpr[ra] : 0;
2319 nb = regs->gpr[rb] & 0xff;
2322 op->type = MKOP(LOAD_VSX, 0, nb);
2323 op->element_size = 16;
2324 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2328 case 332: /* lxvdsx */
2329 op->reg = rd | ((instr & 1) << 5);
2330 op->type = MKOP(LOAD_VSX, 0, 8);
2331 op->element_size = 8;
2332 op->vsx_flags = VSX_SPLAT;
2335 case 364: /* lxvwsx */
2336 op->reg = rd | ((instr & 1) << 5);
2337 op->type = MKOP(LOAD_VSX, 0, 4);
2338 op->element_size = 4;
2339 op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2342 case 396: /* stxvx */
2343 op->reg = rd | ((instr & 1) << 5);
2344 op->type = MKOP(STORE_VSX, 0, 16);
2345 op->element_size = 16;
2346 op->vsx_flags = VSX_CHECK_VEC;
2349 case 397: /* stxvl */
2350 case 429: { /* stxvll */
2352 op->reg = rd | ((instr & 1) << 5);
2353 op->ea = ra ? regs->gpr[ra] : 0;
2354 nb = regs->gpr[rb] & 0xff;
2357 op->type = MKOP(STORE_VSX, 0, nb);
2358 op->element_size = 16;
2359 op->vsx_flags = ((instr & 0x20) ? VSX_LDLEFT : 0) |
2363 case 524: /* lxsspx */
2364 op->reg = rd | ((instr & 1) << 5);
2365 op->type = MKOP(LOAD_VSX, 0, 4);
2366 op->element_size = 8;
2367 op->vsx_flags = VSX_FPCONV;
2370 case 588: /* lxsdx */
2371 op->reg = rd | ((instr & 1) << 5);
2372 op->type = MKOP(LOAD_VSX, 0, 8);
2373 op->element_size = 8;
2376 case 652: /* stxsspx */
2377 op->reg = rd | ((instr & 1) << 5);
2378 op->type = MKOP(STORE_VSX, 0, 4);
2379 op->element_size = 8;
2380 op->vsx_flags = VSX_FPCONV;
2383 case 716: /* stxsdx */
2384 op->reg = rd | ((instr & 1) << 5);
2385 op->type = MKOP(STORE_VSX, 0, 8);
2386 op->element_size = 8;
2389 case 780: /* lxvw4x */
2390 op->reg = rd | ((instr & 1) << 5);
2391 op->type = MKOP(LOAD_VSX, 0, 16);
2392 op->element_size = 4;
2395 case 781: /* lxsibzx */
2396 op->reg = rd | ((instr & 1) << 5);
2397 op->type = MKOP(LOAD_VSX, 0, 1);
2398 op->element_size = 8;
2399 op->vsx_flags = VSX_CHECK_VEC;
2402 case 812: /* lxvh8x */
2403 op->reg = rd | ((instr & 1) << 5);
2404 op->type = MKOP(LOAD_VSX, 0, 16);
2405 op->element_size = 2;
2406 op->vsx_flags = VSX_CHECK_VEC;
2409 case 813: /* lxsihzx */
2410 op->reg = rd | ((instr & 1) << 5);
2411 op->type = MKOP(LOAD_VSX, 0, 2);
2412 op->element_size = 8;
2413 op->vsx_flags = VSX_CHECK_VEC;
2416 case 844: /* lxvd2x */
2417 op->reg = rd | ((instr & 1) << 5);
2418 op->type = MKOP(LOAD_VSX, 0, 16);
2419 op->element_size = 8;
2422 case 876: /* lxvb16x */
2423 op->reg = rd | ((instr & 1) << 5);
2424 op->type = MKOP(LOAD_VSX, 0, 16);
2425 op->element_size = 1;
2426 op->vsx_flags = VSX_CHECK_VEC;
2429 case 908: /* stxvw4x */
2430 op->reg = rd | ((instr & 1) << 5);
2431 op->type = MKOP(STORE_VSX, 0, 16);
2432 op->element_size = 4;
2435 case 909: /* stxsibx */
2436 op->reg = rd | ((instr & 1) << 5);
2437 op->type = MKOP(STORE_VSX, 0, 1);
2438 op->element_size = 8;
2439 op->vsx_flags = VSX_CHECK_VEC;
2442 case 940: /* stxvh8x */
2443 op->reg = rd | ((instr & 1) << 5);
2444 op->type = MKOP(STORE_VSX, 0, 16);
2445 op->element_size = 2;
2446 op->vsx_flags = VSX_CHECK_VEC;
2449 case 941: /* stxsihx */
2450 op->reg = rd | ((instr & 1) << 5);
2451 op->type = MKOP(STORE_VSX, 0, 2);
2452 op->element_size = 8;
2453 op->vsx_flags = VSX_CHECK_VEC;
2456 case 972: /* stxvd2x */
2457 op->reg = rd | ((instr & 1) << 5);
2458 op->type = MKOP(STORE_VSX, 0, 16);
2459 op->element_size = 8;
2462 case 1004: /* stxvb16x */
2463 op->reg = rd | ((instr & 1) << 5);
2464 op->type = MKOP(STORE_VSX, 0, 16);
2465 op->element_size = 1;
2466 op->vsx_flags = VSX_CHECK_VEC;
2469 #endif /* CONFIG_VSX */
2475 op->type = MKOP(LOAD, u, 4);
2476 op->ea = dform_ea(instr, regs);
2481 op->type = MKOP(LOAD, u, 1);
2482 op->ea = dform_ea(instr, regs);
2487 op->type = MKOP(STORE, u, 4);
2488 op->ea = dform_ea(instr, regs);
2493 op->type = MKOP(STORE, u, 1);
2494 op->ea = dform_ea(instr, regs);
2499 op->type = MKOP(LOAD, u, 2);
2500 op->ea = dform_ea(instr, regs);
2505 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2506 op->ea = dform_ea(instr, regs);
2511 op->type = MKOP(STORE, u, 2);
2512 op->ea = dform_ea(instr, regs);
2517 break; /* invalid form, ra in range to load */
2518 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2519 op->ea = dform_ea(instr, regs);
2523 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2524 op->ea = dform_ea(instr, regs);
2527 #ifdef CONFIG_PPC_FPU
2530 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2531 op->ea = dform_ea(instr, regs);
2536 op->type = MKOP(LOAD_FP, u, 8);
2537 op->ea = dform_ea(instr, regs);
2541 case 53: /* stfsu */
2542 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2543 op->ea = dform_ea(instr, regs);
2547 case 55: /* stfdu */
2548 op->type = MKOP(STORE_FP, u, 8);
2549 op->ea = dform_ea(instr, regs);
2553 #ifdef __powerpc64__
2555 if (!((rd & 1) || (rd == ra)))
2556 op->type = MKOP(LOAD, 0, 16);
2557 op->ea = dqform_ea(instr, regs);
2562 case 57: /* lfdp, lxsd, lxssp */
2563 op->ea = dsform_ea(instr, regs);
2564 switch (instr & 3) {
2567 break; /* reg must be even */
2568 op->type = MKOP(LOAD_FP, 0, 16);
2572 op->type = MKOP(LOAD_VSX, 0, 8);
2573 op->element_size = 8;
2574 op->vsx_flags = VSX_CHECK_VEC;
2578 op->type = MKOP(LOAD_VSX, 0, 4);
2579 op->element_size = 8;
2580 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2584 #endif /* CONFIG_VSX */
2586 #ifdef __powerpc64__
2587 case 58: /* ld[u], lwa */
2588 op->ea = dsform_ea(instr, regs);
2589 switch (instr & 3) {
2591 op->type = MKOP(LOAD, 0, 8);
2594 op->type = MKOP(LOAD, UPDATE, 8);
2597 op->type = MKOP(LOAD, SIGNEXT, 4);
2604 case 61: /* stfdp, lxv, stxsd, stxssp, stxv */
2605 switch (instr & 7) {
2606 case 0: /* stfdp with LSB of DS field = 0 */
2607 case 4: /* stfdp with LSB of DS field = 1 */
2608 op->ea = dsform_ea(instr, regs);
2609 op->type = MKOP(STORE_FP, 0, 16);
2613 op->ea = dqform_ea(instr, regs);
2616 op->type = MKOP(LOAD_VSX, 0, 16);
2617 op->element_size = 16;
2618 op->vsx_flags = VSX_CHECK_VEC;
2621 case 2: /* stxsd with LSB of DS field = 0 */
2622 case 6: /* stxsd with LSB of DS field = 1 */
2623 op->ea = dsform_ea(instr, regs);
2625 op->type = MKOP(STORE_VSX, 0, 8);
2626 op->element_size = 8;
2627 op->vsx_flags = VSX_CHECK_VEC;
2630 case 3: /* stxssp with LSB of DS field = 0 */
2631 case 7: /* stxssp with LSB of DS field = 1 */
2632 op->ea = dsform_ea(instr, regs);
2634 op->type = MKOP(STORE_VSX, 0, 4);
2635 op->element_size = 8;
2636 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2640 op->ea = dqform_ea(instr, regs);
2643 op->type = MKOP(STORE_VSX, 0, 16);
2644 op->element_size = 16;
2645 op->vsx_flags = VSX_CHECK_VEC;
2649 #endif /* CONFIG_VSX */
2651 #ifdef __powerpc64__
2652 case 62: /* std[u] */
2653 op->ea = dsform_ea(instr, regs);
2654 switch (instr & 3) {
2656 op->type = MKOP(STORE, 0, 8);
2659 op->type = MKOP(STORE, UPDATE, 8);
2663 op->type = MKOP(STORE, 0, 16);
2667 #endif /* __powerpc64__ */
2672 if ((GETTYPE(op->type) == LOAD_VSX ||
2673 GETTYPE(op->type) == STORE_VSX) &&
2674 !cpu_has_feature(CPU_FTR_VSX)) {
2677 #endif /* CONFIG_VSX */
2698 op->type = INTERRUPT | 0x700;
2699 op->val = SRR1_PROGPRIV;
2703 op->type = INTERRUPT | 0x700;
2704 op->val = SRR1_PROGTRAP;
2707 EXPORT_SYMBOL_GPL(analyse_instr);
2708 NOKPROBE_SYMBOL(analyse_instr);
2711 * For PPC32 we always use stwu with r1 to change the stack pointer.
2712 * So this emulated store may corrupt the exception frame, now we
2713 * have to provide the exception frame trampoline, which is pushed
2714 * below the kprobed function stack. So we only update gpr[1] but
2715 * don't emulate the real store operation. We will do real store
2716 * operation safely in exception return code by checking this flag.
2718 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
2722 * Check if we will touch kernel stack overflow
2724 if (ea - STACK_INT_FRAME_SIZE <= current->thread.ksp_limit) {
2725 printk(KERN_CRIT "Can't kprobe this since kernel stack would overflow.\n");
2728 #endif /* CONFIG_PPC32 */
2730 * Check if we already set since that means we'll
2731 * lose the previous value.
2733 WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
2734 set_thread_flag(TIF_EMULATE_STACK_STORE);
2738 static nokprobe_inline void do_signext(unsigned long *valp, int size)
2742 *valp = (signed short) *valp;
2745 *valp = (signed int) *valp;
2750 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
2754 *valp = byterev_2(*valp);
2757 *valp = byterev_4(*valp);
2759 #ifdef __powerpc64__
2761 *valp = byterev_8(*valp);
2768 * Emulate an instruction that can be executed just by updating
2771 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
2773 unsigned long next_pc;
2775 next_pc = truncate_if_32bit(regs->msr, regs->nip + 4);
2776 switch (GETTYPE(op->type)) {
2778 if (op->type & SETREG)
2779 regs->gpr[op->reg] = op->val;
2780 if (op->type & SETCC)
2781 regs->ccr = op->ccval;
2782 if (op->type & SETXER)
2783 regs->xer = op->xerval;
2787 if (op->type & SETLK)
2788 regs->link = next_pc;
2789 if (op->type & BRTAKEN)
2791 if (op->type & DECCTR)
2796 switch (op->type & BARRIER_MASK) {
2807 case BARRIER_LWSYNC:
2808 asm volatile("lwsync" : : : "memory");
2810 case BARRIER_PTESYNC:
2811 asm volatile("ptesync" : : : "memory");
2820 regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
2823 regs->gpr[op->reg] = regs->link;
2826 regs->gpr[op->reg] = regs->ctr;
2836 regs->xer = op->val & 0xffffffffUL;
2839 regs->link = op->val;
2842 regs->ctr = op->val;
2852 regs->nip = next_pc;
2854 NOKPROBE_SYMBOL(emulate_update_regs);
2857 * Emulate a previously-analysed load or store instruction.
2858 * Return values are:
2859 * 0 = instruction emulated successfully
2860 * -EFAULT = address out of range or access faulted (regs->dar
2861 * contains the faulting address)
2862 * -EACCES = misaligned access, instruction requires alignment
2863 * -EINVAL = unknown operation in *op
2865 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
2867 int err, size, type;
2875 size = GETSIZE(op->type);
2876 type = GETTYPE(op->type);
2877 cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
2878 ea = truncate_if_32bit(regs->msr, op->ea);
2882 if (ea & (size - 1))
2883 return -EACCES; /* can't handle misaligned */
2884 if (!address_ok(regs, ea, size))
2889 #ifdef __powerpc64__
2891 __get_user_asmx(val, ea, err, "lbarx");
2894 __get_user_asmx(val, ea, err, "lharx");
2898 __get_user_asmx(val, ea, err, "lwarx");
2900 #ifdef __powerpc64__
2902 __get_user_asmx(val, ea, err, "ldarx");
2905 err = do_lqarx(ea, ®s->gpr[op->reg]);
2916 regs->gpr[op->reg] = val;
2920 if (ea & (size - 1))
2921 return -EACCES; /* can't handle misaligned */
2922 if (!address_ok(regs, ea, size))
2926 #ifdef __powerpc64__
2928 __put_user_asmx(op->val, ea, err, "stbcx.", cr);
2931 __put_user_asmx(op->val, ea, err, "sthcx.", cr);
2935 __put_user_asmx(op->val, ea, err, "stwcx.", cr);
2937 #ifdef __powerpc64__
2939 __put_user_asmx(op->val, ea, err, "stdcx.", cr);
2942 err = do_stqcx(ea, regs->gpr[op->reg],
2943 regs->gpr[op->reg + 1], &cr);
2950 regs->ccr = (regs->ccr & 0x0fffffff) |
2952 ((regs->xer >> 3) & 0x10000000);
2958 #ifdef __powerpc64__
2960 err = emulate_lq(regs, ea, op->reg, cross_endian);
2964 err = read_mem(®s->gpr[op->reg], ea, size, regs);
2966 if (op->type & SIGNEXT)
2967 do_signext(®s->gpr[op->reg], size);
2968 if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
2969 do_byterev(®s->gpr[op->reg], size);
2973 #ifdef CONFIG_PPC_FPU
2976 * If the instruction is in userspace, we can emulate it even
2977 * if the VMX state is not live, because we have the state
2978 * stored in the thread_struct. If the instruction is in
2979 * the kernel, we must not touch the state in the thread_struct.
2981 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
2983 err = do_fp_load(op, ea, regs, cross_endian);
2986 #ifdef CONFIG_ALTIVEC
2988 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
2990 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
2995 unsigned long msrbit = MSR_VSX;
2998 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
2999 * when the target of the instruction is a vector register.
3001 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3003 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3005 err = do_vsx_load(op, ea, regs, cross_endian);
3010 if (!address_ok(regs, ea, size))
3013 for (i = 0; i < size; i += 4) {
3014 unsigned int v32 = 0;
3019 err = copy_mem_in((u8 *) &v32, ea, nb, regs);
3022 if (unlikely(cross_endian))
3023 v32 = byterev_4(v32);
3024 regs->gpr[rd] = v32;
3026 /* reg number wraps from 31 to 0 for lsw[ix] */
3027 rd = (rd + 1) & 0x1f;
3032 #ifdef __powerpc64__
3034 err = emulate_stq(regs, ea, op->reg, cross_endian);
3038 if ((op->type & UPDATE) && size == sizeof(long) &&
3039 op->reg == 1 && op->update_reg == 1 &&
3040 !(regs->msr & MSR_PR) &&
3041 ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
3042 err = handle_stack_update(ea, regs);
3045 if (unlikely(cross_endian))
3046 do_byterev(&op->val, size);
3047 err = write_mem(op->val, ea, size, regs);
3050 #ifdef CONFIG_PPC_FPU
3052 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3054 err = do_fp_store(op, ea, regs, cross_endian);
3057 #ifdef CONFIG_ALTIVEC
3059 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3061 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3066 unsigned long msrbit = MSR_VSX;
3069 * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3070 * when the target of the instruction is a vector register.
3072 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3074 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3076 err = do_vsx_store(op, ea, regs, cross_endian);
3081 if (!address_ok(regs, ea, size))
3084 for (i = 0; i < size; i += 4) {
3085 unsigned int v32 = regs->gpr[rd];
3090 if (unlikely(cross_endian))
3091 v32 = byterev_4(v32);
3092 err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3096 /* reg number wraps from 31 to 0 for stsw[ix] */
3097 rd = (rd + 1) & 0x1f;
3108 if (op->type & UPDATE)
3109 regs->gpr[op->update_reg] = op->ea;
3113 NOKPROBE_SYMBOL(emulate_loadstore);
3116 * Emulate instructions that cause a transfer of control,
3117 * loads and stores, and a few other instructions.
3118 * Returns 1 if the step was emulated, 0 if not,
3119 * or -1 if the instruction is one that should not be stepped,
3120 * such as an rfid, or a mtmsrd that would clear MSR_RI.
3122 int emulate_step(struct pt_regs *regs, unsigned int instr)
3124 struct instruction_op op;
3129 r = analyse_instr(&op, regs, instr);
3133 emulate_update_regs(regs, &op);
3138 type = GETTYPE(op.type);
3140 if (OP_IS_LOAD_STORE(type)) {
3141 err = emulate_loadstore(regs, &op);
3149 ea = truncate_if_32bit(regs->msr, op.ea);
3150 if (!address_ok(regs, ea, 8))
3152 switch (op.type & CACHEOP_MASK) {
3154 __cacheop_user_asmx(ea, err, "dcbst");
3157 __cacheop_user_asmx(ea, err, "dcbf");
3161 prefetchw((void *) ea);
3165 prefetch((void *) ea);
3168 __cacheop_user_asmx(ea, err, "icbi");
3171 err = emulate_dcbz(ea, regs);
3181 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3185 val = regs->gpr[op.reg];
3186 if ((val & MSR_RI) == 0)
3187 /* can't step mtmsr[d] that would clear MSR_RI */
3189 /* here op.val is the mask of bits to change */
3190 regs->msr = (regs->msr & ~op.val) | (val & op.val);
3194 case SYSCALL: /* sc */
3196 * N.B. this uses knowledge about how the syscall
3197 * entry code works. If that is changed, this will
3198 * need to be changed also.
3200 if (regs->gpr[0] == 0x1ebe &&
3201 cpu_has_feature(CPU_FTR_REAL_LE)) {
3202 regs->msr ^= MSR_LE;
3205 regs->gpr[9] = regs->gpr[13];
3206 regs->gpr[10] = MSR_KERNEL;
3207 regs->gpr[11] = regs->nip + 4;
3208 regs->gpr[12] = regs->msr & MSR_MASK;
3209 regs->gpr[13] = (unsigned long) get_paca();
3210 regs->nip = (unsigned long) &system_call_common;
3211 regs->msr = MSR_KERNEL;
3221 regs->nip = truncate_if_32bit(regs->msr, regs->nip + 4);
3224 NOKPROBE_SYMBOL(emulate_step);