arch/powerpc/lib/sstep.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * Single-step support.
   4  *
   5  * Copyright (C) 2004 Paul Mackerras <paulus@au.ibm.com>, IBM
   6  */
   7 #include <linux/kernel.h>
   8 #include <linux/kprobes.h>
   9 #include <linux/ptrace.h>
  10 #include <linux/prefetch.h>
  11 #include <asm/sstep.h>
  12 #include <asm/processor.h>
  13 #include <linux/uaccess.h>
  14 #include <asm/cpu_has_feature.h>
  15 #include <asm/cputable.h>
  16 #include <asm/disassemble.h>
  17
  18 extern char system_call_common[];
  19 extern char system_call_vectored_emulate[];
  20
  21 #ifdef CONFIG_PPC64
  22 /* Bits in SRR1 that are copied from MSR */
  23 #define MSR_MASK        0xffffffff87c0ffffUL
  24 #else
  25 #define MSR_MASK        0x87c0ffff
  26 #endif
  27
  28 /* Bits in XER */
  29 #define XER_SO          0x80000000U
  30 #define XER_OV          0x40000000U
  31 #define XER_CA          0x20000000U
  32 #define XER_OV32        0x00080000U
  33 #define XER_CA32        0x00040000U
  34
  35 #ifdef CONFIG_VSX
  36 #define VSX_REGISTER_XTP(rd)   ((((rd) & 1) << 5) | ((rd) & 0xfe))
  37 #endif
  38
  39 #ifdef CONFIG_PPC_FPU
  40 /*
  41  * Functions in ldstfp.S
  42  */
  43 extern void get_fpr(int rn, double *p);
  44 extern void put_fpr(int rn, const double *p);
  45 extern void get_vr(int rn, __vector128 *p);
  46 extern void put_vr(int rn, __vector128 *p);
  47 extern void load_vsrn(int vsr, const void *p);
  48 extern void store_vsrn(int vsr, void *p);
  49 extern void conv_sp_to_dp(const float *sp, double *dp);
  50 extern void conv_dp_to_sp(const double *dp, float *sp);
  51 #endif
  52
  53 #ifdef __powerpc64__
  54 /*
  55  * Functions in quad.S
  56  */
  57 extern int do_lq(unsigned long ea, unsigned long *regs);
  58 extern int do_stq(unsigned long ea, unsigned long val0, unsigned long val1);
  59 extern int do_lqarx(unsigned long ea, unsigned long *regs);
  60 extern int do_stqcx(unsigned long ea, unsigned long val0, unsigned long val1,
  61                     unsigned int *crp);
  62 #endif
  63
  64 #ifdef __LITTLE_ENDIAN__
  65 #define IS_LE   1
  66 #define IS_BE   0
  67 #else
  68 #define IS_LE   0
  69 #define IS_BE   1
  70 #endif
  71
  72 /*
  73  * Emulate the truncation of 64 bit values in 32-bit mode.
  74  */
  75 static nokprobe_inline unsigned long truncate_if_32bit(unsigned long msr,
  76                                                         unsigned long val)
  77 {
  78 #ifdef __powerpc64__
  79         if ((msr & MSR_64BIT) == 0)
  80                 val &= 0xffffffffUL;
  81 #endif
  82         return val;
  83 }
  84
  85 /*
  86  * Determine whether a conditional branch instruction would branch.
  87  */
  88 static nokprobe_inline int branch_taken(unsigned int instr,
  89                                         const struct pt_regs *regs,
  90                                         struct instruction_op *op)
  91 {
  92         unsigned int bo = (instr >> 21) & 0x1f;
  93         unsigned int bi;
  94
  95         if ((bo & 4) == 0) {
  96                 /* decrement counter */
  97                 op->type |= DECCTR;
  98                 if (((bo >> 1) & 1) ^ (regs->ctr == 1))
  99                         return 0;
 100         }
 101         if ((bo & 0x10) == 0) {
 102                 /* check bit from CR */
 103                 bi = (instr >> 16) & 0x1f;
 104                 if (((regs->ccr >> (31 - bi)) & 1) != ((bo >> 3) & 1))
 105                         return 0;
 106         }
 107         return 1;
 108 }
 109
 110 static nokprobe_inline long address_ok(struct pt_regs *regs,
 111                                        unsigned long ea, int nb)
 112 {
 113         if (!user_mode(regs))
 114                 return 1;
 115         if (access_ok((void __user *)ea, nb))
 116                 return 1;
 117         if (access_ok((void __user *)ea, 1))
 118                 /* Access overlaps the end of the user region */
 119                 regs->dar = TASK_SIZE_MAX - 1;
 120         else
 121                 regs->dar = ea;
 122         return 0;
 123 }
 124
 125 /*
 126  * Calculate effective address for a D-form instruction
 127  */
 128 static nokprobe_inline unsigned long dform_ea(unsigned int instr,
 129                                               const struct pt_regs *regs)
 130 {
 131         int ra;
 132         unsigned long ea;
 133
 134         ra = (instr >> 16) & 0x1f;
 135         ea = (signed short) instr;              /* sign-extend */
 136         if (ra)
 137                 ea += regs->gpr[ra];
 138
 139         return ea;
 140 }
 141
 142 #ifdef __powerpc64__
 143 /*
 144  * Calculate effective address for a DS-form instruction
 145  */
 146 static nokprobe_inline unsigned long dsform_ea(unsigned int instr,
 147                                                const struct pt_regs *regs)
 148 {
 149         int ra;
 150         unsigned long ea;
 151
 152         ra = (instr >> 16) & 0x1f;
 153         ea = (signed short) (instr & ~3);       /* sign-extend */
 154         if (ra)
 155                 ea += regs->gpr[ra];
 156
 157         return ea;
 158 }
 159
 160 /*
 161  * Calculate effective address for a DQ-form instruction
 162  */
 163 static nokprobe_inline unsigned long dqform_ea(unsigned int instr,
 164                                                const struct pt_regs *regs)
 165 {
 166         int ra;
 167         unsigned long ea;
 168
 169         ra = (instr >> 16) & 0x1f;
 170         ea = (signed short) (instr & ~0xf);     /* sign-extend */
 171         if (ra)
 172                 ea += regs->gpr[ra];
 173
 174         return ea;
 175 }
 176 #endif /* __powerpc64 */
 177
 178 /*
 179  * Calculate effective address for an X-form instruction
 180  */
 181 static nokprobe_inline unsigned long xform_ea(unsigned int instr,
 182                                               const struct pt_regs *regs)
 183 {
 184         int ra, rb;
 185         unsigned long ea;
 186
 187         ra = (instr >> 16) & 0x1f;
 188         rb = (instr >> 11) & 0x1f;
 189         ea = regs->gpr[rb];
 190         if (ra)
 191                 ea += regs->gpr[ra];
 192
 193         return ea;
 194 }
 195
 196 /*
 197  * Calculate effective address for a MLS:D-form / 8LS:D-form
 198  * prefixed instruction
 199  */
 200 static nokprobe_inline unsigned long mlsd_8lsd_ea(unsigned int instr,
 201                                                   unsigned int suffix,
 202                                                   const struct pt_regs *regs)
 203 {
 204         int ra, prefix_r;
 205         unsigned int  dd;
 206         unsigned long ea, d0, d1, d;
 207
 208         prefix_r = GET_PREFIX_R(instr);
 209         ra = GET_PREFIX_RA(suffix);
 210
 211         d0 = instr & 0x3ffff;
 212         d1 = suffix & 0xffff;
 213         d = (d0 << 16) | d1;
 214
 215         /*
 216          * sign extend a 34 bit number
 217          */
 218         dd = (unsigned int)(d >> 2);
 219         ea = (signed int)dd;
 220         ea = (ea << 2) | (d & 0x3);
 221
 222         if (!prefix_r && ra)
 223                 ea += regs->gpr[ra];
 224         else if (!prefix_r && !ra)
 225                 ; /* Leave ea as is */
 226         else if (prefix_r)
 227                 ea += regs->nip;
 228
 229         /*
 230          * (prefix_r && ra) is an invalid form. Should already be
 231          * checked for by caller!
 232          */
 233
 234         return ea;
 235 }
 236
 237 /*
 238  * Return the largest power of 2, not greater than sizeof(unsigned long),
 239  * such that x is a multiple of it.
 240  */
 241 static nokprobe_inline unsigned long max_align(unsigned long x)
 242 {
 243         x |= sizeof(unsigned long);
 244         return x & -x;          /* isolates rightmost bit */
 245 }
 246
 247 static nokprobe_inline unsigned long byterev_2(unsigned long x)
 248 {
 249         return ((x >> 8) & 0xff) | ((x & 0xff) << 8);
 250 }
 251
 252 static nokprobe_inline unsigned long byterev_4(unsigned long x)
 253 {
 254         return ((x >> 24) & 0xff) | ((x >> 8) & 0xff00) |
 255                 ((x & 0xff00) << 8) | ((x & 0xff) << 24);
 256 }
 257
 258 #ifdef __powerpc64__
 259 static nokprobe_inline unsigned long byterev_8(unsigned long x)
 260 {
 261         return (byterev_4(x) << 32) | byterev_4(x >> 32);
 262 }
 263 #endif
 264
 265 static nokprobe_inline void do_byte_reverse(void *ptr, int nb)
 266 {
 267         switch (nb) {
 268         case 2:
 269                 *(u16 *)ptr = byterev_2(*(u16 *)ptr);
 270                 break;
 271         case 4:
 272                 *(u32 *)ptr = byterev_4(*(u32 *)ptr);
 273                 break;
 274 #ifdef __powerpc64__
 275         case 8:
 276                 *(unsigned long *)ptr = byterev_8(*(unsigned long *)ptr);
 277                 break;
 278         case 16: {
 279                 unsigned long *up = (unsigned long *)ptr;
 280                 unsigned long tmp;
 281                 tmp = byterev_8(up[0]);
 282                 up[0] = byterev_8(up[1]);
 283                 up[1] = tmp;
 284                 break;
 285         }
 286         case 32: {
 287                 unsigned long *up = (unsigned long *)ptr;
 288                 unsigned long tmp;
 289
 290                 tmp = byterev_8(up[0]);
 291                 up[0] = byterev_8(up[3]);
 292                 up[3] = tmp;
 293                 tmp = byterev_8(up[2]);
 294                 up[2] = byterev_8(up[1]);
 295                 up[1] = tmp;
 296                 break;
 297         }
 298
 299 #endif
 300         default:
 301                 WARN_ON_ONCE(1);
 302         }
 303 }
 304
 305 static nokprobe_inline int read_mem_aligned(unsigned long *dest,
 306                                             unsigned long ea, int nb,
 307                                             struct pt_regs *regs)
 308 {
 309         int err = 0;
 310         unsigned long x = 0;
 311
 312         switch (nb) {
 313         case 1:
 314                 err = __get_user(x, (unsigned char __user *) ea);
 315                 break;
 316         case 2:
 317                 err = __get_user(x, (unsigned short __user *) ea);
 318                 break;
 319         case 4:
 320                 err = __get_user(x, (unsigned int __user *) ea);
 321                 break;
 322 #ifdef __powerpc64__
 323         case 8:
 324                 err = __get_user(x, (unsigned long __user *) ea);
 325                 break;
 326 #endif
 327         }
 328         if (!err)
 329                 *dest = x;
 330         else
 331                 regs->dar = ea;
 332         return err;
 333 }
 334
 335 /*
 336  * Copy from userspace to a buffer, using the largest possible
 337  * aligned accesses, up to sizeof(long).
 338  */
 339 static nokprobe_inline int copy_mem_in(u8 *dest, unsigned long ea, int nb,
 340                                        struct pt_regs *regs)
 341 {
 342         int err = 0;
 343         int c;
 344
 345         for (; nb > 0; nb -= c) {
 346                 c = max_align(ea);
 347                 if (c > nb)
 348                         c = max_align(nb);
 349                 switch (c) {
 350                 case 1:
 351                         err = __get_user(*dest, (unsigned char __user *) ea);
 352                         break;
 353                 case 2:
 354                         err = __get_user(*(u16 *)dest,
 355                                          (unsigned short __user *) ea);
 356                         break;
 357                 case 4:
 358                         err = __get_user(*(u32 *)dest,
 359                                          (unsigned int __user *) ea);
 360                         break;
 361 #ifdef __powerpc64__
 362                 case 8:
 363                         err = __get_user(*(unsigned long *)dest,
 364                                          (unsigned long __user *) ea);
 365                         break;
 366 #endif
 367                 }
 368                 if (err) {
 369                         regs->dar = ea;
 370                         return err;
 371                 }
 372                 dest += c;
 373                 ea += c;
 374         }
 375         return 0;
 376 }
 377
 378 static nokprobe_inline int read_mem_unaligned(unsigned long *dest,
 379                                               unsigned long ea, int nb,
 380                                               struct pt_regs *regs)
 381 {
 382         union {
 383                 unsigned long ul;
 384                 u8 b[sizeof(unsigned long)];
 385         } u;
 386         int i;
 387         int err;
 388
 389         u.ul = 0;
 390         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 391         err = copy_mem_in(&u.b[i], ea, nb, regs);
 392         if (!err)
 393                 *dest = u.ul;
 394         return err;
 395 }
 396
 397 /*
 398  * Read memory at address ea for nb bytes, return 0 for success
 399  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 400  * If nb < sizeof(long), the result is right-justified on BE systems.
 401  */
 402 static int read_mem(unsigned long *dest, unsigned long ea, int nb,
 403                               struct pt_regs *regs)
 404 {
 405         if (!address_ok(regs, ea, nb))
 406                 return -EFAULT;
 407         if ((ea & (nb - 1)) == 0)
 408                 return read_mem_aligned(dest, ea, nb, regs);
 409         return read_mem_unaligned(dest, ea, nb, regs);
 410 }
 411 NOKPROBE_SYMBOL(read_mem);
 412
 413 static nokprobe_inline int write_mem_aligned(unsigned long val,
 414                                              unsigned long ea, int nb,
 415                                              struct pt_regs *regs)
 416 {
 417         int err = 0;
 418
 419         switch (nb) {
 420         case 1:
 421                 err = __put_user(val, (unsigned char __user *) ea);
 422                 break;
 423         case 2:
 424                 err = __put_user(val, (unsigned short __user *) ea);
 425                 break;
 426         case 4:
 427                 err = __put_user(val, (unsigned int __user *) ea);
 428                 break;
 429 #ifdef __powerpc64__
 430         case 8:
 431                 err = __put_user(val, (unsigned long __user *) ea);
 432                 break;
 433 #endif
 434         }
 435         if (err)
 436                 regs->dar = ea;
 437         return err;
 438 }
 439
 440 /*
 441  * Copy from a buffer to userspace, using the largest possible
 442  * aligned accesses, up to sizeof(long).
 443  */
 444 static nokprobe_inline int copy_mem_out(u8 *dest, unsigned long ea, int nb,
 445                                         struct pt_regs *regs)
 446 {
 447         int err = 0;
 448         int c;
 449
 450         for (; nb > 0; nb -= c) {
 451                 c = max_align(ea);
 452                 if (c > nb)
 453                         c = max_align(nb);
 454                 switch (c) {
 455                 case 1:
 456                         err = __put_user(*dest, (unsigned char __user *) ea);
 457                         break;
 458                 case 2:
 459                         err = __put_user(*(u16 *)dest,
 460                                          (unsigned short __user *) ea);
 461                         break;
 462                 case 4:
 463                         err = __put_user(*(u32 *)dest,
 464                                          (unsigned int __user *) ea);
 465                         break;
 466 #ifdef __powerpc64__
 467                 case 8:
 468                         err = __put_user(*(unsigned long *)dest,
 469                                          (unsigned long __user *) ea);
 470                         break;
 471 #endif
 472                 }
 473                 if (err) {
 474                         regs->dar = ea;
 475                         return err;
 476                 }
 477                 dest += c;
 478                 ea += c;
 479         }
 480         return 0;
 481 }
 482
 483 static nokprobe_inline int write_mem_unaligned(unsigned long val,
 484                                                unsigned long ea, int nb,
 485                                                struct pt_regs *regs)
 486 {
 487         union {
 488                 unsigned long ul;
 489                 u8 b[sizeof(unsigned long)];
 490         } u;
 491         int i;
 492
 493         u.ul = val;
 494         i = IS_BE ? sizeof(unsigned long) - nb : 0;
 495         return copy_mem_out(&u.b[i], ea, nb, regs);
 496 }
 497
 498 /*
 499  * Write memory at address ea for nb bytes, return 0 for success
 500  * or -EFAULT if an error occurred.  N.B. nb must be 1, 2, 4 or 8.
 501  */
 502 static int write_mem(unsigned long val, unsigned long ea, int nb,
 503                                struct pt_regs *regs)
 504 {
 505         if (!address_ok(regs, ea, nb))
 506                 return -EFAULT;
 507         if ((ea & (nb - 1)) == 0)
 508                 return write_mem_aligned(val, ea, nb, regs);
 509         return write_mem_unaligned(val, ea, nb, regs);
 510 }
 511 NOKPROBE_SYMBOL(write_mem);
 512
 513 #ifdef CONFIG_PPC_FPU
 514 /*
 515  * These access either the real FP register or the image in the
 516  * thread_struct, depending on regs->msr & MSR_FP.
 517  */
 518 static int do_fp_load(struct instruction_op *op, unsigned long ea,
 519                       struct pt_regs *regs, bool cross_endian)
 520 {
 521         int err, rn, nb;
 522         union {
 523                 int i;
 524                 unsigned int u;
 525                 float f;
 526                 double d[2];
 527                 unsigned long l[2];
 528                 u8 b[2 * sizeof(double)];
 529         } u;
 530
 531         nb = GETSIZE(op->type);
 532         if (!address_ok(regs, ea, nb))
 533                 return -EFAULT;
 534         rn = op->reg;
 535         err = copy_mem_in(u.b, ea, nb, regs);
 536         if (err)
 537                 return err;
 538         if (unlikely(cross_endian)) {
 539                 do_byte_reverse(u.b, min(nb, 8));
 540                 if (nb == 16)
 541                         do_byte_reverse(&u.b[8], 8);
 542         }
 543         preempt_disable();
 544         if (nb == 4) {
 545                 if (op->type & FPCONV)
 546                         conv_sp_to_dp(&u.f, &u.d[0]);
 547                 else if (op->type & SIGNEXT)
 548                         u.l[0] = u.i;
 549                 else
 550                         u.l[0] = u.u;
 551         }
 552         if (regs->msr & MSR_FP)
 553                 put_fpr(rn, &u.d[0]);
 554         else
 555                 current->thread.TS_FPR(rn) = u.l[0];
 556         if (nb == 16) {
 557                 /* lfdp */
 558                 rn |= 1;
 559                 if (regs->msr & MSR_FP)
 560                         put_fpr(rn, &u.d[1]);
 561                 else
 562                         current->thread.TS_FPR(rn) = u.l[1];
 563         }
 564         preempt_enable();
 565         return 0;
 566 }
 567 NOKPROBE_SYMBOL(do_fp_load);
 568
 569 static int do_fp_store(struct instruction_op *op, unsigned long ea,
 570                        struct pt_regs *regs, bool cross_endian)
 571 {
 572         int rn, nb;
 573         union {
 574                 unsigned int u;
 575                 float f;
 576                 double d[2];
 577                 unsigned long l[2];
 578                 u8 b[2 * sizeof(double)];
 579         } u;
 580
 581         nb = GETSIZE(op->type);
 582         if (!address_ok(regs, ea, nb))
 583                 return -EFAULT;
 584         rn = op->reg;
 585         preempt_disable();
 586         if (regs->msr & MSR_FP)
 587                 get_fpr(rn, &u.d[0]);
 588         else
 589                 u.l[0] = current->thread.TS_FPR(rn);
 590         if (nb == 4) {
 591                 if (op->type & FPCONV)
 592                         conv_dp_to_sp(&u.d[0], &u.f);
 593                 else
 594                         u.u = u.l[0];
 595         }
 596         if (nb == 16) {
 597                 rn |= 1;
 598                 if (regs->msr & MSR_FP)
 599                         get_fpr(rn, &u.d[1]);
 600                 else
 601                         u.l[1] = current->thread.TS_FPR(rn);
 602         }
 603         preempt_enable();
 604         if (unlikely(cross_endian)) {
 605                 do_byte_reverse(u.b, min(nb, 8));
 606                 if (nb == 16)
 607                         do_byte_reverse(&u.b[8], 8);
 608         }
 609         return copy_mem_out(u.b, ea, nb, regs);
 610 }
 611 NOKPROBE_SYMBOL(do_fp_store);
 612 #endif
 613
 614 #ifdef CONFIG_ALTIVEC
 615 /* For Altivec/VMX, no need to worry about alignment */
 616 static nokprobe_inline int do_vec_load(int rn, unsigned long ea,
 617                                        int size, struct pt_regs *regs,
 618                                        bool cross_endian)
 619 {
 620         int err;
 621         union {
 622                 __vector128 v;
 623                 u8 b[sizeof(__vector128)];
 624         } u = {};
 625
 626         if (!address_ok(regs, ea & ~0xfUL, 16))
 627                 return -EFAULT;
 628         /* align to multiple of size */
 629         ea &= ~(size - 1);
 630         err = copy_mem_in(&u.b[ea & 0xf], ea, size, regs);
 631         if (err)
 632                 return err;
 633         if (unlikely(cross_endian))
 634                 do_byte_reverse(&u.b[ea & 0xf], size);
 635         preempt_disable();
 636         if (regs->msr & MSR_VEC)
 637                 put_vr(rn, &u.v);
 638         else
 639                 current->thread.vr_state.vr[rn] = u.v;
 640         preempt_enable();
 641         return 0;
 642 }
 643
 644 static nokprobe_inline int do_vec_store(int rn, unsigned long ea,
 645                                         int size, struct pt_regs *regs,
 646                                         bool cross_endian)
 647 {
 648         union {
 649                 __vector128 v;
 650                 u8 b[sizeof(__vector128)];
 651         } u;
 652
 653         if (!address_ok(regs, ea & ~0xfUL, 16))
 654                 return -EFAULT;
 655         /* align to multiple of size */
 656         ea &= ~(size - 1);
 657
 658         preempt_disable();
 659         if (regs->msr & MSR_VEC)
 660                 get_vr(rn, &u.v);
 661         else
 662                 u.v = current->thread.vr_state.vr[rn];
 663         preempt_enable();
 664         if (unlikely(cross_endian))
 665                 do_byte_reverse(&u.b[ea & 0xf], size);
 666         return copy_mem_out(&u.b[ea & 0xf], ea, size, regs);
 667 }
 668 #endif /* CONFIG_ALTIVEC */
 669
 670 #ifdef __powerpc64__
 671 static nokprobe_inline int emulate_lq(struct pt_regs *regs, unsigned long ea,
 672                                       int reg, bool cross_endian)
 673 {
 674         int err;
 675
 676         if (!address_ok(regs, ea, 16))
 677                 return -EFAULT;
 678         /* if aligned, should be atomic */
 679         if ((ea & 0xf) == 0) {
 680                 err = do_lq(ea, &regs->gpr[reg]);
 681         } else {
 682                 err = read_mem(&regs->gpr[reg + IS_LE], ea, 8, regs);
 683                 if (!err)
 684                         err = read_mem(&regs->gpr[reg + IS_BE], ea + 8, 8, regs);
 685         }
 686         if (!err && unlikely(cross_endian))
 687                 do_byte_reverse(&regs->gpr[reg], 16);
 688         return err;
 689 }
 690
 691 static nokprobe_inline int emulate_stq(struct pt_regs *regs, unsigned long ea,
 692                                        int reg, bool cross_endian)
 693 {
 694         int err;
 695         unsigned long vals[2];
 696
 697         if (!address_ok(regs, ea, 16))
 698                 return -EFAULT;
 699         vals[0] = regs->gpr[reg];
 700         vals[1] = regs->gpr[reg + 1];
 701         if (unlikely(cross_endian))
 702                 do_byte_reverse(vals, 16);
 703
 704         /* if aligned, should be atomic */
 705         if ((ea & 0xf) == 0)
 706                 return do_stq(ea, vals[0], vals[1]);
 707
 708         err = write_mem(vals[IS_LE], ea, 8, regs);
 709         if (!err)
 710                 err = write_mem(vals[IS_BE], ea + 8, 8, regs);
 711         return err;
 712 }
 713 #endif /* __powerpc64 */
 714
 715 #ifdef CONFIG_VSX
 716 void emulate_vsx_load(struct instruction_op *op, union vsx_reg *reg,
 717                       const void *mem, bool rev)
 718 {
 719         int size, read_size;
 720         int i, j;
 721         const unsigned int *wp;
 722         const unsigned short *hp;
 723         const unsigned char *bp;
 724
 725         size = GETSIZE(op->type);
 726         reg->d[0] = reg->d[1] = 0;
 727
 728         switch (op->element_size) {
 729         case 32:
 730                 /* [p]lxvp[x] */
 731         case 16:
 732                 /* whole vector; lxv[x] or lxvl[l] */
 733                 if (size == 0)
 734                         break;
 735                 memcpy(reg, mem, size);
 736                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 737                         rev = !rev;
 738                 if (rev)
 739                         do_byte_reverse(reg, size);
 740                 break;
 741         case 8:
 742                 /* scalar loads, lxvd2x, lxvdsx */
 743                 read_size = (size >= 8) ? 8 : size;
 744                 i = IS_LE ? 8 : 8 - read_size;
 745                 memcpy(&reg->b[i], mem, read_size);
 746                 if (rev)
 747                         do_byte_reverse(&reg->b[i], 8);
 748                 if (size < 8) {
 749                         if (op->type & SIGNEXT) {
 750                                 /* size == 4 is the only case here */
 751                                 reg->d[IS_LE] = (signed int) reg->d[IS_LE];
 752                         } else if (op->vsx_flags & VSX_FPCONV) {
 753                                 preempt_disable();
 754                                 conv_sp_to_dp(&reg->fp[1 + IS_LE],
 755                                               &reg->dp[IS_LE]);
 756                                 preempt_enable();
 757                         }
 758                 } else {
 759                         if (size == 16) {
 760                                 unsigned long v = *(unsigned long *)(mem + 8);
 761                                 reg->d[IS_BE] = !rev ? v : byterev_8(v);
 762                         } else if (op->vsx_flags & VSX_SPLAT)
 763                                 reg->d[IS_BE] = reg->d[IS_LE];
 764                 }
 765                 break;
 766         case 4:
 767                 /* lxvw4x, lxvwsx */
 768                 wp = mem;
 769                 for (j = 0; j < size / 4; ++j) {
 770                         i = IS_LE ? 3 - j : j;
 771                         reg->w[i] = !rev ? *wp++ : byterev_4(*wp++);
 772                 }
 773                 if (op->vsx_flags & VSX_SPLAT) {
 774                         u32 val = reg->w[IS_LE ? 3 : 0];
 775                         for (; j < 4; ++j) {
 776                                 i = IS_LE ? 3 - j : j;
 777                                 reg->w[i] = val;
 778                         }
 779                 }
 780                 break;
 781         case 2:
 782                 /* lxvh8x */
 783                 hp = mem;
 784                 for (j = 0; j < size / 2; ++j) {
 785                         i = IS_LE ? 7 - j : j;
 786                         reg->h[i] = !rev ? *hp++ : byterev_2(*hp++);
 787                 }
 788                 break;
 789         case 1:
 790                 /* lxvb16x */
 791                 bp = mem;
 792                 for (j = 0; j < size; ++j) {
 793                         i = IS_LE ? 15 - j : j;
 794                         reg->b[i] = *bp++;
 795                 }
 796                 break;
 797         }
 798 }
 799 EXPORT_SYMBOL_GPL(emulate_vsx_load);
 800 NOKPROBE_SYMBOL(emulate_vsx_load);
 801
 802 void emulate_vsx_store(struct instruction_op *op, const union vsx_reg *reg,
 803                        void *mem, bool rev)
 804 {
 805         int size, write_size;
 806         int i, j;
 807         union vsx_reg buf;
 808         unsigned int *wp;
 809         unsigned short *hp;
 810         unsigned char *bp;
 811
 812         size = GETSIZE(op->type);
 813
 814         switch (op->element_size) {
 815         case 32:
 816                 /* [p]stxvp[x] */
 817                 if (size == 0)
 818                         break;
 819                 if (rev) {
 820                         /* reverse 32 bytes */
 821                         union vsx_reg buf32[2];
 822                         buf32[0].d[0] = byterev_8(reg[1].d[1]);
 823                         buf32[0].d[1] = byterev_8(reg[1].d[0]);
 824                         buf32[1].d[0] = byterev_8(reg[0].d[1]);
 825                         buf32[1].d[1] = byterev_8(reg[0].d[0]);
 826                         memcpy(mem, buf32, size);
 827                 } else {
 828                         memcpy(mem, reg, size);
 829                 }
 830                 break;
 831         case 16:
 832                 /* stxv, stxvx, stxvl, stxvll */
 833                 if (size == 0)
 834                         break;
 835                 if (IS_LE && (op->vsx_flags & VSX_LDLEFT))
 836                         rev = !rev;
 837                 if (rev) {
 838                         /* reverse 16 bytes */
 839                         buf.d[0] = byterev_8(reg->d[1]);
 840                         buf.d[1] = byterev_8(reg->d[0]);
 841                         reg = &buf;
 842                 }
 843                 memcpy(mem, reg, size);
 844                 break;
 845         case 8:
 846                 /* scalar stores, stxvd2x */
 847                 write_size = (size >= 8) ? 8 : size;
 848                 i = IS_LE ? 8 : 8 - write_size;
 849                 if (size < 8 && op->vsx_flags & VSX_FPCONV) {
 850                         buf.d[0] = buf.d[1] = 0;
 851                         preempt_disable();
 852                         conv_dp_to_sp(&reg->dp[IS_LE], &buf.fp[1 + IS_LE]);
 853                         preempt_enable();
 854                         reg = &buf;
 855                 }
 856                 memcpy(mem, &reg->b[i], write_size);
 857                 if (size == 16)
 858                         memcpy(mem + 8, &reg->d[IS_BE], 8);
 859                 if (unlikely(rev)) {
 860                         do_byte_reverse(mem, write_size);
 861                         if (size == 16)
 862                                 do_byte_reverse(mem + 8, 8);
 863                 }
 864                 break;
 865         case 4:
 866                 /* stxvw4x */
 867                 wp = mem;
 868                 for (j = 0; j < size / 4; ++j) {
 869                         i = IS_LE ? 3 - j : j;
 870                         *wp++ = !rev ? reg->w[i] : byterev_4(reg->w[i]);
 871                 }
 872                 break;
 873         case 2:
 874                 /* stxvh8x */
 875                 hp = mem;
 876                 for (j = 0; j < size / 2; ++j) {
 877                         i = IS_LE ? 7 - j : j;
 878                         *hp++ = !rev ? reg->h[i] : byterev_2(reg->h[i]);
 879                 }
 880                 break;
 881         case 1:
 882                 /* stvxb16x */
 883                 bp = mem;
 884                 for (j = 0; j < size; ++j) {
 885                         i = IS_LE ? 15 - j : j;
 886                         *bp++ = reg->b[i];
 887                 }
 888                 break;
 889         }
 890 }
 891 EXPORT_SYMBOL_GPL(emulate_vsx_store);
 892 NOKPROBE_SYMBOL(emulate_vsx_store);
 893
 894 static nokprobe_inline int do_vsx_load(struct instruction_op *op,
 895                                        unsigned long ea, struct pt_regs *regs,
 896                                        bool cross_endian)
 897 {
 898         int reg = op->reg;
 899         int i, j, nr_vsx_regs;
 900         u8 mem[32];
 901         union vsx_reg buf[2];
 902         int size = GETSIZE(op->type);
 903
 904         if (!address_ok(regs, ea, size) || copy_mem_in(mem, ea, size, regs))
 905                 return -EFAULT;
 906
 907         nr_vsx_regs = max(1ul, size / sizeof(__vector128));
 908         emulate_vsx_load(op, buf, mem, cross_endian);
 909         preempt_disable();
 910         if (reg < 32) {
 911                 /* FP regs + extensions */
 912                 if (regs->msr & MSR_FP) {
 913                         for (i = 0; i < nr_vsx_regs; i++) {
 914                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 915                                 load_vsrn(reg + i, &buf[j].v);
 916                         }
 917                 } else {
 918                         for (i = 0; i < nr_vsx_regs; i++) {
 919                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 920                                 current->thread.fp_state.fpr[reg + i][0] = buf[j].d[0];
 921                                 current->thread.fp_state.fpr[reg + i][1] = buf[j].d[1];
 922                         }
 923                 }
 924         } else {
 925                 if (regs->msr & MSR_VEC) {
 926                         for (i = 0; i < nr_vsx_regs; i++) {
 927                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 928                                 load_vsrn(reg + i, &buf[j].v);
 929                         }
 930                 } else {
 931                         for (i = 0; i < nr_vsx_regs; i++) {
 932                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 933                                 current->thread.vr_state.vr[reg - 32 + i] = buf[j].v;
 934                         }
 935                 }
 936         }
 937         preempt_enable();
 938         return 0;
 939 }
 940
 941 static nokprobe_inline int do_vsx_store(struct instruction_op *op,
 942                                         unsigned long ea, struct pt_regs *regs,
 943                                         bool cross_endian)
 944 {
 945         int reg = op->reg;
 946         int i, j, nr_vsx_regs;
 947         u8 mem[32];
 948         union vsx_reg buf[2];
 949         int size = GETSIZE(op->type);
 950
 951         if (!address_ok(regs, ea, size))
 952                 return -EFAULT;
 953
 954         nr_vsx_regs = max(1ul, size / sizeof(__vector128));
 955         preempt_disable();
 956         if (reg < 32) {
 957                 /* FP regs + extensions */
 958                 if (regs->msr & MSR_FP) {
 959                         for (i = 0; i < nr_vsx_regs; i++) {
 960                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 961                                 store_vsrn(reg + i, &buf[j].v);
 962                         }
 963                 } else {
 964                         for (i = 0; i < nr_vsx_regs; i++) {
 965                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 966                                 buf[j].d[0] = current->thread.fp_state.fpr[reg + i][0];
 967                                 buf[j].d[1] = current->thread.fp_state.fpr[reg + i][1];
 968                         }
 969                 }
 970         } else {
 971                 if (regs->msr & MSR_VEC) {
 972                         for (i = 0; i < nr_vsx_regs; i++) {
 973                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 974                                 store_vsrn(reg + i, &buf[j].v);
 975                         }
 976                 } else {
 977                         for (i = 0; i < nr_vsx_regs; i++) {
 978                                 j = IS_LE ? nr_vsx_regs - i - 1 : i;
 979                                 buf[j].v = current->thread.vr_state.vr[reg - 32 + i];
 980                         }
 981                 }
 982         }
 983         preempt_enable();
 984         emulate_vsx_store(op, buf, mem, cross_endian);
 985         return  copy_mem_out(mem, ea, size, regs);
 986 }
 987 #endif /* CONFIG_VSX */
 988
 989 int emulate_dcbz(unsigned long ea, struct pt_regs *regs)
 990 {
 991         int err;
 992         unsigned long i, size;
 993
 994 #ifdef __powerpc64__
 995         size = ppc64_caches.l1d.block_size;
 996         if (!(regs->msr & MSR_64BIT))
 997                 ea &= 0xffffffffUL;
 998 #else
 999         size = L1_CACHE_BYTES;
1000 #endif
1001         ea &= ~(size - 1);
1002         if (!address_ok(regs, ea, size))
1003                 return -EFAULT;
1004         for (i = 0; i < size; i += sizeof(long)) {
1005                 err = __put_user(0, (unsigned long __user *) (ea + i));
1006                 if (err) {
1007                         regs->dar = ea;
1008                         return err;
1009                 }
1010         }
1011         return 0;
1012 }
1013 NOKPROBE_SYMBOL(emulate_dcbz);
1014
1015 #define __put_user_asmx(x, addr, err, op, cr)           \
1016         __asm__ __volatile__(                           \
1017                 ".machine push\n"                       \
1018                 ".machine power8\n"                     \
1019                 "1:     " op " %2,0,%3\n"               \
1020                 ".machine pop\n"                        \
1021                 "       mfcr    %1\n"                   \
1022                 "2:\n"                                  \
1023                 ".section .fixup,\"ax\"\n"              \
1024                 "3:     li      %0,%4\n"                \
1025                 "       b       2b\n"                   \
1026                 ".previous\n"                           \
1027                 EX_TABLE(1b, 3b)                        \
1028                 : "=r" (err), "=r" (cr)                 \
1029                 : "r" (x), "r" (addr), "i" (-EFAULT), "0" (err))
1030
1031 #define __get_user_asmx(x, addr, err, op)               \
1032         __asm__ __volatile__(                           \
1033                 ".machine push\n"                       \
1034                 ".machine power8\n"                     \
1035                 "1:     "op" %1,0,%2\n"                 \
1036                 ".machine pop\n"                        \
1037                 "2:\n"                                  \
1038                 ".section .fixup,\"ax\"\n"              \
1039                 "3:     li      %0,%3\n"                \
1040                 "       b       2b\n"                   \
1041                 ".previous\n"                           \
1042                 EX_TABLE(1b, 3b)                        \
1043                 : "=r" (err), "=r" (x)                  \
1044                 : "r" (addr), "i" (-EFAULT), "0" (err))
1045
1046 #define __cacheop_user_asmx(addr, err, op)              \
1047         __asm__ __volatile__(                           \
1048                 "1:     "op" 0,%1\n"                    \
1049                 "2:\n"                                  \
1050                 ".section .fixup,\"ax\"\n"              \
1051                 "3:     li      %0,%3\n"                \
1052                 "       b       2b\n"                   \
1053                 ".previous\n"                           \
1054                 EX_TABLE(1b, 3b)                        \
1055                 : "=r" (err)                            \
1056                 : "r" (addr), "i" (-EFAULT), "0" (err))
1057
1058 static nokprobe_inline void set_cr0(const struct pt_regs *regs,
1059                                     struct instruction_op *op)
1060 {
1061         long val = op->val;
1062
1063         op->type |= SETCC;
1064         op->ccval = (regs->ccr & 0x0fffffff) | ((regs->xer >> 3) & 0x10000000);
1065 #ifdef __powerpc64__
1066         if (!(regs->msr & MSR_64BIT))
1067                 val = (int) val;
1068 #endif
1069         if (val < 0)
1070                 op->ccval |= 0x80000000;
1071         else if (val > 0)
1072                 op->ccval |= 0x40000000;
1073         else
1074                 op->ccval |= 0x20000000;
1075 }
1076
1077 static nokprobe_inline void set_ca32(struct instruction_op *op, bool val)
1078 {
1079         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1080                 if (val)
1081                         op->xerval |= XER_CA32;
1082                 else
1083                         op->xerval &= ~XER_CA32;
1084         }
1085 }
1086
1087 static nokprobe_inline void add_with_carry(const struct pt_regs *regs,
1088                                      struct instruction_op *op, int rd,
1089                                      unsigned long val1, unsigned long val2,
1090                                      unsigned long carry_in)
1091 {
1092         unsigned long val = val1 + val2;
1093
1094         if (carry_in)
1095                 ++val;
1096         op->type = COMPUTE + SETREG + SETXER;
1097         op->reg = rd;
1098         op->val = val;
1099 #ifdef __powerpc64__
1100         if (!(regs->msr & MSR_64BIT)) {
1101                 val = (unsigned int) val;
1102                 val1 = (unsigned int) val1;
1103         }
1104 #endif
1105         op->xerval = regs->xer;
1106         if (val < val1 || (carry_in && val == val1))
1107                 op->xerval |= XER_CA;
1108         else
1109                 op->xerval &= ~XER_CA;
1110
1111         set_ca32(op, (unsigned int)val < (unsigned int)val1 ||
1112                         (carry_in && (unsigned int)val == (unsigned int)val1));
1113 }
1114
1115 static nokprobe_inline void do_cmp_signed(const struct pt_regs *regs,
1116                                           struct instruction_op *op,
1117                                           long v1, long v2, int crfld)
1118 {
1119         unsigned int crval, shift;
1120
1121         op->type = COMPUTE + SETCC;
1122         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1123         if (v1 < v2)
1124                 crval |= 8;
1125         else if (v1 > v2)
1126                 crval |= 4;
1127         else
1128                 crval |= 2;
1129         shift = (7 - crfld) * 4;
1130         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1131 }
1132
1133 static nokprobe_inline void do_cmp_unsigned(const struct pt_regs *regs,
1134                                             struct instruction_op *op,
1135                                             unsigned long v1,
1136                                             unsigned long v2, int crfld)
1137 {
1138         unsigned int crval, shift;
1139
1140         op->type = COMPUTE + SETCC;
1141         crval = (regs->xer >> 31) & 1;          /* get SO bit */
1142         if (v1 < v2)
1143                 crval |= 8;
1144         else if (v1 > v2)
1145                 crval |= 4;
1146         else
1147                 crval |= 2;
1148         shift = (7 - crfld) * 4;
1149         op->ccval = (regs->ccr & ~(0xf << shift)) | (crval << shift);
1150 }
1151
1152 static nokprobe_inline void do_cmpb(const struct pt_regs *regs,
1153                                     struct instruction_op *op,
1154                                     unsigned long v1, unsigned long v2)
1155 {
1156         unsigned long long out_val, mask;
1157         int i;
1158
1159         out_val = 0;
1160         for (i = 0; i < 8; i++) {
1161                 mask = 0xffUL << (i * 8);
1162                 if ((v1 & mask) == (v2 & mask))
1163                         out_val |= mask;
1164         }
1165         op->val = out_val;
1166 }
1167
1168 /*
1169  * The size parameter is used to adjust the equivalent popcnt instruction.
1170  * popcntb = 8, popcntw = 32, popcntd = 64
1171  */
1172 static nokprobe_inline void do_popcnt(const struct pt_regs *regs,
1173                                       struct instruction_op *op,
1174                                       unsigned long v1, int size)
1175 {
1176         unsigned long long out = v1;
1177
1178         out -= (out >> 1) & 0x5555555555555555ULL;
1179         out = (0x3333333333333333ULL & out) +
1180               (0x3333333333333333ULL & (out >> 2));
1181         out = (out + (out >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1182
1183         if (size == 8) {        /* popcntb */
1184                 op->val = out;
1185                 return;
1186         }
1187         out += out >> 8;
1188         out += out >> 16;
1189         if (size == 32) {       /* popcntw */
1190                 op->val = out & 0x0000003f0000003fULL;
1191                 return;
1192         }
1193
1194         out = (out + (out >> 32)) & 0x7f;
1195         op->val = out;  /* popcntd */
1196 }
1197
1198 #ifdef CONFIG_PPC64
1199 static nokprobe_inline void do_bpermd(const struct pt_regs *regs,
1200                                       struct instruction_op *op,
1201                                       unsigned long v1, unsigned long v2)
1202 {
1203         unsigned char perm, idx;
1204         unsigned int i;
1205
1206         perm = 0;
1207         for (i = 0; i < 8; i++) {
1208                 idx = (v1 >> (i * 8)) & 0xff;
1209                 if (idx < 64)
1210                         if (v2 & PPC_BIT(idx))
1211                                 perm |= 1 << i;
1212         }
1213         op->val = perm;
1214 }
1215 #endif /* CONFIG_PPC64 */
1216 /*
1217  * The size parameter adjusts the equivalent prty instruction.
1218  * prtyw = 32, prtyd = 64
1219  */
1220 static nokprobe_inline void do_prty(const struct pt_regs *regs,
1221                                     struct instruction_op *op,
1222                                     unsigned long v, int size)
1223 {
1224         unsigned long long res = v ^ (v >> 8);
1225
1226         res ^= res >> 16;
1227         if (size == 32) {               /* prtyw */
1228                 op->val = res & 0x0000000100000001ULL;
1229                 return;
1230         }
1231
1232         res ^= res >> 32;
1233         op->val = res & 1;      /*prtyd */
1234 }
1235
1236 static nokprobe_inline int trap_compare(long v1, long v2)
1237 {
1238         int ret = 0;
1239
1240         if (v1 < v2)
1241                 ret |= 0x10;
1242         else if (v1 > v2)
1243                 ret |= 0x08;
1244         else
1245                 ret |= 0x04;
1246         if ((unsigned long)v1 < (unsigned long)v2)
1247                 ret |= 0x02;
1248         else if ((unsigned long)v1 > (unsigned long)v2)
1249                 ret |= 0x01;
1250         return ret;
1251 }
1252
1253 /*
1254  * Elements of 32-bit rotate and mask instructions.
1255  */
1256 #define MASK32(mb, me)  ((0xffffffffUL >> (mb)) + \
1257                          ((signed long)-0x80000000L >> (me)) + ((me) >= (mb)))
1258 #ifdef __powerpc64__
1259 #define MASK64_L(mb)    (~0UL >> (mb))
1260 #define MASK64_R(me)    ((signed long)-0x8000000000000000L >> (me))
1261 #define MASK64(mb, me)  (MASK64_L(mb) + MASK64_R(me) + ((me) >= (mb)))
1262 #define DATA32(x)       (((x) & 0xffffffffUL) | (((x) & 0xffffffffUL) << 32))
1263 #else
1264 #define DATA32(x)       (x)
1265 #endif
1266 #define ROTATE(x, n)    ((n) ? (((x) << (n)) | ((x) >> (8 * sizeof(long) - (n)))) : (x))
1267
1268 /*
1269  * Decode an instruction, and return information about it in *op
1270  * without changing *regs.
1271  * Integer arithmetic and logical instructions, branches, and barrier
1272  * instructions can be emulated just using the information in *op.
1273  *
1274  * Return value is 1 if the instruction can be emulated just by
1275  * updating *regs with the information in *op, -1 if we need the
1276  * GPRs but *regs doesn't contain the full register set, or 0
1277  * otherwise.
1278  */
1279 int analyse_instr(struct instruction_op *op, const struct pt_regs *regs,
1280                   struct ppc_inst instr)
1281 {
1282 #ifdef CONFIG_PPC64
1283         unsigned int suffixopcode, prefixtype, prefix_r;
1284 #endif
1285         unsigned int opcode, ra, rb, rc, rd, spr, u;
1286         unsigned long int imm;
1287         unsigned long int val, val2;
1288         unsigned int mb, me, sh;
1289         unsigned int word, suffix;
1290         long ival;
1291
1292         word = ppc_inst_val(instr);
1293         suffix = ppc_inst_suffix(instr);
1294
1295         op->type = COMPUTE;
1296
1297         opcode = ppc_inst_primary_opcode(instr);
1298         switch (opcode) {
1299         case 16:        /* bc */
1300                 op->type = BRANCH;
1301                 imm = (signed short)(word & 0xfffc);
1302                 if ((word & 2) == 0)
1303                         imm += regs->nip;
1304                 op->val = truncate_if_32bit(regs->msr, imm);
1305                 if (word & 1)
1306                         op->type |= SETLK;
1307                 if (branch_taken(word, regs, op))
1308                         op->type |= BRTAKEN;
1309                 return 1;
1310 #ifdef CONFIG_PPC64
1311         case 17:        /* sc */
1312                 if ((word & 0xfe2) == 2)
1313                         op->type = SYSCALL;
1314                 else if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) &&
1315                                 (word & 0xfe3) == 1) {  /* scv */
1316                         op->type = SYSCALL_VECTORED_0;
1317                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1318                                 goto unknown_opcode;
1319                 } else
1320                         op->type = UNKNOWN;
1321                 return 0;
1322 #endif
1323         case 18:        /* b */
1324                 op->type = BRANCH | BRTAKEN;
1325                 imm = word & 0x03fffffc;
1326                 if (imm & 0x02000000)
1327                         imm -= 0x04000000;
1328                 if ((word & 2) == 0)
1329                         imm += regs->nip;
1330                 op->val = truncate_if_32bit(regs->msr, imm);
1331                 if (word & 1)
1332                         op->type |= SETLK;
1333                 return 1;
1334         case 19:
1335                 switch ((word >> 1) & 0x3ff) {
1336                 case 0:         /* mcrf */
1337                         op->type = COMPUTE + SETCC;
1338                         rd = 7 - ((word >> 23) & 0x7);
1339                         ra = 7 - ((word >> 18) & 0x7);
1340                         rd *= 4;
1341                         ra *= 4;
1342                         val = (regs->ccr >> ra) & 0xf;
1343                         op->ccval = (regs->ccr & ~(0xfUL << rd)) | (val << rd);
1344                         return 1;
1345
1346                 case 16:        /* bclr */
1347                 case 528:       /* bcctr */
1348                         op->type = BRANCH;
1349                         imm = (word & 0x400)? regs->ctr: regs->link;
1350                         op->val = truncate_if_32bit(regs->msr, imm);
1351                         if (word & 1)
1352                                 op->type |= SETLK;
1353                         if (branch_taken(word, regs, op))
1354                                 op->type |= BRTAKEN;
1355                         return 1;
1356
1357                 case 18:        /* rfid, scary */
1358                         if (regs->msr & MSR_PR)
1359                                 goto priv;
1360                         op->type = RFI;
1361                         return 0;
1362
1363                 case 150:       /* isync */
1364                         op->type = BARRIER | BARRIER_ISYNC;
1365                         return 1;
1366
1367                 case 33:        /* crnor */
1368                 case 129:       /* crandc */
1369                 case 193:       /* crxor */
1370                 case 225:       /* crnand */
1371                 case 257:       /* crand */
1372                 case 289:       /* creqv */
1373                 case 417:       /* crorc */
1374                 case 449:       /* cror */
1375                         op->type = COMPUTE + SETCC;
1376                         ra = (word >> 16) & 0x1f;
1377                         rb = (word >> 11) & 0x1f;
1378                         rd = (word >> 21) & 0x1f;
1379                         ra = (regs->ccr >> (31 - ra)) & 1;
1380                         rb = (regs->ccr >> (31 - rb)) & 1;
1381                         val = (word >> (6 + ra * 2 + rb)) & 1;
1382                         op->ccval = (regs->ccr & ~(1UL << (31 - rd))) |
1383                                 (val << (31 - rd));
1384                         return 1;
1385                 }
1386                 break;
1387         case 31:
1388                 switch ((word >> 1) & 0x3ff) {
1389                 case 598:       /* sync */
1390                         op->type = BARRIER + BARRIER_SYNC;
1391 #ifdef __powerpc64__
1392                         switch ((word >> 21) & 3) {
1393                         case 1:         /* lwsync */
1394                                 op->type = BARRIER + BARRIER_LWSYNC;
1395                                 break;
1396                         case 2:         /* ptesync */
1397                                 op->type = BARRIER + BARRIER_PTESYNC;
1398                                 break;
1399                         }
1400 #endif
1401                         return 1;
1402
1403                 case 854:       /* eieio */
1404                         op->type = BARRIER + BARRIER_EIEIO;
1405                         return 1;
1406                 }
1407                 break;
1408         }
1409
1410         rd = (word >> 21) & 0x1f;
1411         ra = (word >> 16) & 0x1f;
1412         rb = (word >> 11) & 0x1f;
1413         rc = (word >> 6) & 0x1f;
1414
1415         switch (opcode) {
1416 #ifdef __powerpc64__
1417         case 1:
1418                 if (!cpu_has_feature(CPU_FTR_ARCH_31))
1419                         goto unknown_opcode;
1420
1421                 prefix_r = GET_PREFIX_R(word);
1422                 ra = GET_PREFIX_RA(suffix);
1423                 rd = (suffix >> 21) & 0x1f;
1424                 op->reg = rd;
1425                 op->val = regs->gpr[rd];
1426                 suffixopcode = get_op(suffix);
1427                 prefixtype = (word >> 24) & 0x3;
1428                 switch (prefixtype) {
1429                 case 2:
1430                         if (prefix_r && ra)
1431                                 return 0;
1432                         switch (suffixopcode) {
1433                         case 14:        /* paddi */
1434                                 op->type = COMPUTE | PREFIXED;
1435                                 op->val = mlsd_8lsd_ea(word, suffix, regs);
1436                                 goto compute_done;
1437                         }
1438                 }
1439                 break;
1440         case 2:         /* tdi */
1441                 if (rd & trap_compare(regs->gpr[ra], (short) word))
1442                         goto trap;
1443                 return 1;
1444 #endif
1445         case 3:         /* twi */
1446                 if (rd & trap_compare((int)regs->gpr[ra], (short) word))
1447                         goto trap;
1448                 return 1;
1449
1450 #ifdef __powerpc64__
1451         case 4:
1452                 /*
1453                  * There are very many instructions with this primary opcode
1454                  * introduced in the ISA as early as v2.03. However, the ones
1455                  * we currently emulate were all introduced with ISA 3.0
1456                  */
1457                 if (!cpu_has_feature(CPU_FTR_ARCH_300))
1458                         goto unknown_opcode;
1459
1460                 switch (word & 0x3f) {
1461                 case 48:        /* maddhd */
1462                         asm volatile(PPC_MADDHD(%0, %1, %2, %3) :
1463                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1464                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1465                         goto compute_done;
1466
1467                 case 49:        /* maddhdu */
1468                         asm volatile(PPC_MADDHDU(%0, %1, %2, %3) :
1469                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1470                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1471                         goto compute_done;
1472
1473                 case 51:        /* maddld */
1474                         asm volatile(PPC_MADDLD(%0, %1, %2, %3) :
1475                                      "=r" (op->val) : "r" (regs->gpr[ra]),
1476                                      "r" (regs->gpr[rb]), "r" (regs->gpr[rc]));
1477                         goto compute_done;
1478                 }
1479
1480                 /*
1481                  * There are other instructions from ISA 3.0 with the same
1482                  * primary opcode which do not have emulation support yet.
1483                  */
1484                 goto unknown_opcode;
1485 #endif
1486
1487         case 7:         /* mulli */
1488                 op->val = regs->gpr[ra] * (short) word;
1489                 goto compute_done;
1490
1491         case 8:         /* subfic */
1492                 imm = (short) word;
1493                 add_with_carry(regs, op, rd, ~regs->gpr[ra], imm, 1);
1494                 return 1;
1495
1496         case 10:        /* cmpli */
1497                 imm = (unsigned short) word;
1498                 val = regs->gpr[ra];
1499 #ifdef __powerpc64__
1500                 if ((rd & 1) == 0)
1501                         val = (unsigned int) val;
1502 #endif
1503                 do_cmp_unsigned(regs, op, val, imm, rd >> 2);
1504                 return 1;
1505
1506         case 11:        /* cmpi */
1507                 imm = (short) word;
1508                 val = regs->gpr[ra];
1509 #ifdef __powerpc64__
1510                 if ((rd & 1) == 0)
1511                         val = (int) val;
1512 #endif
1513                 do_cmp_signed(regs, op, val, imm, rd >> 2);
1514                 return 1;
1515
1516         case 12:        /* addic */
1517                 imm = (short) word;
1518                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1519                 return 1;
1520
1521         case 13:        /* addic. */
1522                 imm = (short) word;
1523                 add_with_carry(regs, op, rd, regs->gpr[ra], imm, 0);
1524                 set_cr0(regs, op);
1525                 return 1;
1526
1527         case 14:        /* addi */
1528                 imm = (short) word;
1529                 if (ra)
1530                         imm += regs->gpr[ra];
1531                 op->val = imm;
1532                 goto compute_done;
1533
1534         case 15:        /* addis */
1535                 imm = ((short) word) << 16;
1536                 if (ra)
1537                         imm += regs->gpr[ra];
1538                 op->val = imm;
1539                 goto compute_done;
1540
1541         case 19:
1542                 if (((word >> 1) & 0x1f) == 2) {
1543                         /* addpcis */
1544                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1545                                 goto unknown_opcode;
1546                         imm = (short) (word & 0xffc1);  /* d0 + d2 fields */
1547                         imm |= (word >> 15) & 0x3e;     /* d1 field */
1548                         op->val = regs->nip + (imm << 16) + 4;
1549                         goto compute_done;
1550                 }
1551                 op->type = UNKNOWN;
1552                 return 0;
1553
1554         case 20:        /* rlwimi */
1555                 mb = (word >> 6) & 0x1f;
1556                 me = (word >> 1) & 0x1f;
1557                 val = DATA32(regs->gpr[rd]);
1558                 imm = MASK32(mb, me);
1559                 op->val = (regs->gpr[ra] & ~imm) | (ROTATE(val, rb) & imm);
1560                 goto logical_done;
1561
1562         case 21:        /* rlwinm */
1563                 mb = (word >> 6) & 0x1f;
1564                 me = (word >> 1) & 0x1f;
1565                 val = DATA32(regs->gpr[rd]);
1566                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1567                 goto logical_done;
1568
1569         case 23:        /* rlwnm */
1570                 mb = (word >> 6) & 0x1f;
1571                 me = (word >> 1) & 0x1f;
1572                 rb = regs->gpr[rb] & 0x1f;
1573                 val = DATA32(regs->gpr[rd]);
1574                 op->val = ROTATE(val, rb) & MASK32(mb, me);
1575                 goto logical_done;
1576
1577         case 24:        /* ori */
1578                 op->val = regs->gpr[rd] | (unsigned short) word;
1579                 goto logical_done_nocc;
1580
1581         case 25:        /* oris */
1582                 imm = (unsigned short) word;
1583                 op->val = regs->gpr[rd] | (imm << 16);
1584                 goto logical_done_nocc;
1585
1586         case 26:        /* xori */
1587                 op->val = regs->gpr[rd] ^ (unsigned short) word;
1588                 goto logical_done_nocc;
1589
1590         case 27:        /* xoris */
1591                 imm = (unsigned short) word;
1592                 op->val = regs->gpr[rd] ^ (imm << 16);
1593                 goto logical_done_nocc;
1594
1595         case 28:        /* andi. */
1596                 op->val = regs->gpr[rd] & (unsigned short) word;
1597                 set_cr0(regs, op);
1598                 goto logical_done_nocc;
1599
1600         case 29:        /* andis. */
1601                 imm = (unsigned short) word;
1602                 op->val = regs->gpr[rd] & (imm << 16);
1603                 set_cr0(regs, op);
1604                 goto logical_done_nocc;
1605
1606 #ifdef __powerpc64__
1607         case 30:        /* rld* */
1608                 mb = ((word >> 6) & 0x1f) | (word & 0x20);
1609                 val = regs->gpr[rd];
1610                 if ((word & 0x10) == 0) {
1611                         sh = rb | ((word & 2) << 4);
1612                         val = ROTATE(val, sh);
1613                         switch ((word >> 2) & 3) {
1614                         case 0:         /* rldicl */
1615                                 val &= MASK64_L(mb);
1616                                 break;
1617                         case 1:         /* rldicr */
1618                                 val &= MASK64_R(mb);
1619                                 break;
1620                         case 2:         /* rldic */
1621                                 val &= MASK64(mb, 63 - sh);
1622                                 break;
1623                         case 3:         /* rldimi */
1624                                 imm = MASK64(mb, 63 - sh);
1625                                 val = (regs->gpr[ra] & ~imm) |
1626                                         (val & imm);
1627                         }
1628                         op->val = val;
1629                         goto logical_done;
1630                 } else {
1631                         sh = regs->gpr[rb] & 0x3f;
1632                         val = ROTATE(val, sh);
1633                         switch ((word >> 1) & 7) {
1634                         case 0:         /* rldcl */
1635                                 op->val = val & MASK64_L(mb);
1636                                 goto logical_done;
1637                         case 1:         /* rldcr */
1638                                 op->val = val & MASK64_R(mb);
1639                                 goto logical_done;
1640                         }
1641                 }
1642 #endif
1643                 op->type = UNKNOWN;     /* illegal instruction */
1644                 return 0;
1645
1646         case 31:
1647                 /* isel occupies 32 minor opcodes */
1648                 if (((word >> 1) & 0x1f) == 15) {
1649                         mb = (word >> 6) & 0x1f; /* bc field */
1650                         val = (regs->ccr >> (31 - mb)) & 1;
1651                         val2 = (ra) ? regs->gpr[ra] : 0;
1652
1653                         op->val = (val) ? val2 : regs->gpr[rb];
1654                         goto compute_done;
1655                 }
1656
1657                 switch ((word >> 1) & 0x3ff) {
1658                 case 4:         /* tw */
1659                         if (rd == 0x1f ||
1660                             (rd & trap_compare((int)regs->gpr[ra],
1661                                                (int)regs->gpr[rb])))
1662                                 goto trap;
1663                         return 1;
1664 #ifdef __powerpc64__
1665                 case 68:        /* td */
1666                         if (rd & trap_compare(regs->gpr[ra], regs->gpr[rb]))
1667                                 goto trap;
1668                         return 1;
1669 #endif
1670                 case 83:        /* mfmsr */
1671                         if (regs->msr & MSR_PR)
1672                                 goto priv;
1673                         op->type = MFMSR;
1674                         op->reg = rd;
1675                         return 0;
1676                 case 146:       /* mtmsr */
1677                         if (regs->msr & MSR_PR)
1678                                 goto priv;
1679                         op->type = MTMSR;
1680                         op->reg = rd;
1681                         op->val = 0xffffffff & ~(MSR_ME | MSR_LE);
1682                         return 0;
1683 #ifdef CONFIG_PPC64
1684                 case 178:       /* mtmsrd */
1685                         if (regs->msr & MSR_PR)
1686                                 goto priv;
1687                         op->type = MTMSR;
1688                         op->reg = rd;
1689                         /* only MSR_EE and MSR_RI get changed if bit 15 set */
1690                         /* mtmsrd doesn't change MSR_HV, MSR_ME or MSR_LE */
1691                         imm = (word & 0x10000)? 0x8002: 0xefffffffffffeffeUL;
1692                         op->val = imm;
1693                         return 0;
1694 #endif
1695
1696                 case 19:        /* mfcr */
1697                         imm = 0xffffffffUL;
1698                         if ((word >> 20) & 1) {
1699                                 imm = 0xf0000000UL;
1700                                 for (sh = 0; sh < 8; ++sh) {
1701                                         if (word & (0x80000 >> sh))
1702                                                 break;
1703                                         imm >>= 4;
1704                                 }
1705                         }
1706                         op->val = regs->ccr & imm;
1707                         goto compute_done;
1708
1709                 case 128:       /* setb */
1710                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1711                                 goto unknown_opcode;
1712                         /*
1713                          * 'ra' encodes the CR field number (bfa) in the top 3 bits.
1714                          * Since each CR field is 4 bits,
1715                          * we can simply mask off the bottom two bits (bfa * 4)
1716                          * to yield the first bit in the CR field.
1717                          */
1718                         ra = ra & ~0x3;
1719                         /* 'val' stores bits of the CR field (bfa) */
1720                         val = regs->ccr >> (CR0_SHIFT - ra);
1721                         /* checks if the LT bit of CR field (bfa) is set */
1722                         if (val & 8)
1723                                 op->val = -1;
1724                         /* checks if the GT bit of CR field (bfa) is set */
1725                         else if (val & 4)
1726                                 op->val = 1;
1727                         else
1728                                 op->val = 0;
1729                         goto compute_done;
1730
1731                 case 144:       /* mtcrf */
1732                         op->type = COMPUTE + SETCC;
1733                         imm = 0xf0000000UL;
1734                         val = regs->gpr[rd];
1735                         op->ccval = regs->ccr;
1736                         for (sh = 0; sh < 8; ++sh) {
1737                                 if (word & (0x80000 >> sh))
1738                                         op->ccval = (op->ccval & ~imm) |
1739                                                 (val & imm);
1740                                 imm >>= 4;
1741                         }
1742                         return 1;
1743
1744                 case 339:       /* mfspr */
1745                         spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1746                         op->type = MFSPR;
1747                         op->reg = rd;
1748                         op->spr = spr;
1749                         if (spr == SPRN_XER || spr == SPRN_LR ||
1750                             spr == SPRN_CTR)
1751                                 return 1;
1752                         return 0;
1753
1754                 case 467:       /* mtspr */
1755                         spr = ((word >> 16) & 0x1f) | ((word >> 6) & 0x3e0);
1756                         op->type = MTSPR;
1757                         op->val = regs->gpr[rd];
1758                         op->spr = spr;
1759                         if (spr == SPRN_XER || spr == SPRN_LR ||
1760                             spr == SPRN_CTR)
1761                                 return 1;
1762                         return 0;
1763
1764 /*
1765  * Compare instructions
1766  */
1767                 case 0: /* cmp */
1768                         val = regs->gpr[ra];
1769                         val2 = regs->gpr[rb];
1770 #ifdef __powerpc64__
1771                         if ((rd & 1) == 0) {
1772                                 /* word (32-bit) compare */
1773                                 val = (int) val;
1774                                 val2 = (int) val2;
1775                         }
1776 #endif
1777                         do_cmp_signed(regs, op, val, val2, rd >> 2);
1778                         return 1;
1779
1780                 case 32:        /* cmpl */
1781                         val = regs->gpr[ra];
1782                         val2 = regs->gpr[rb];
1783 #ifdef __powerpc64__
1784                         if ((rd & 1) == 0) {
1785                                 /* word (32-bit) compare */
1786                                 val = (unsigned int) val;
1787                                 val2 = (unsigned int) val2;
1788                         }
1789 #endif
1790                         do_cmp_unsigned(regs, op, val, val2, rd >> 2);
1791                         return 1;
1792
1793                 case 508: /* cmpb */
1794                         do_cmpb(regs, op, regs->gpr[rd], regs->gpr[rb]);
1795                         goto logical_done_nocc;
1796
1797 /*
1798  * Arithmetic instructions
1799  */
1800                 case 8: /* subfc */
1801                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1802                                        regs->gpr[rb], 1);
1803                         goto arith_done;
1804 #ifdef __powerpc64__
1805                 case 9: /* mulhdu */
1806                         asm("mulhdu %0,%1,%2" : "=r" (op->val) :
1807                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1808                         goto arith_done;
1809 #endif
1810                 case 10:        /* addc */
1811                         add_with_carry(regs, op, rd, regs->gpr[ra],
1812                                        regs->gpr[rb], 0);
1813                         goto arith_done;
1814
1815                 case 11:        /* mulhwu */
1816                         asm("mulhwu %0,%1,%2" : "=r" (op->val) :
1817                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1818                         goto arith_done;
1819
1820                 case 40:        /* subf */
1821                         op->val = regs->gpr[rb] - regs->gpr[ra];
1822                         goto arith_done;
1823 #ifdef __powerpc64__
1824                 case 73:        /* mulhd */
1825                         asm("mulhd %0,%1,%2" : "=r" (op->val) :
1826                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1827                         goto arith_done;
1828 #endif
1829                 case 75:        /* mulhw */
1830                         asm("mulhw %0,%1,%2" : "=r" (op->val) :
1831                             "r" (regs->gpr[ra]), "r" (regs->gpr[rb]));
1832                         goto arith_done;
1833
1834                 case 104:       /* neg */
1835                         op->val = -regs->gpr[ra];
1836                         goto arith_done;
1837
1838                 case 136:       /* subfe */
1839                         add_with_carry(regs, op, rd, ~regs->gpr[ra],
1840                                        regs->gpr[rb], regs->xer & XER_CA);
1841                         goto arith_done;
1842
1843                 case 138:       /* adde */
1844                         add_with_carry(regs, op, rd, regs->gpr[ra],
1845                                        regs->gpr[rb], regs->xer & XER_CA);
1846                         goto arith_done;
1847
1848                 case 200:       /* subfze */
1849                         add_with_carry(regs, op, rd, ~regs->gpr[ra], 0L,
1850                                        regs->xer & XER_CA);
1851                         goto arith_done;
1852
1853                 case 202:       /* addze */
1854                         add_with_carry(regs, op, rd, regs->gpr[ra], 0L,
1855                                        regs->xer & XER_CA);
1856                         goto arith_done;
1857
1858                 case 232:       /* subfme */
1859                         add_with_carry(regs, op, rd, ~regs->gpr[ra], -1L,
1860                                        regs->xer & XER_CA);
1861                         goto arith_done;
1862 #ifdef __powerpc64__
1863                 case 233:       /* mulld */
1864                         op->val = regs->gpr[ra] * regs->gpr[rb];
1865                         goto arith_done;
1866 #endif
1867                 case 234:       /* addme */
1868                         add_with_carry(regs, op, rd, regs->gpr[ra], -1L,
1869                                        regs->xer & XER_CA);
1870                         goto arith_done;
1871
1872                 case 235:       /* mullw */
1873                         op->val = (long)(int) regs->gpr[ra] *
1874                                 (int) regs->gpr[rb];
1875
1876                         goto arith_done;
1877 #ifdef __powerpc64__
1878                 case 265:       /* modud */
1879                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1880                                 goto unknown_opcode;
1881                         op->val = regs->gpr[ra] % regs->gpr[rb];
1882                         goto compute_done;
1883 #endif
1884                 case 266:       /* add */
1885                         op->val = regs->gpr[ra] + regs->gpr[rb];
1886                         goto arith_done;
1887
1888                 case 267:       /* moduw */
1889                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1890                                 goto unknown_opcode;
1891                         op->val = (unsigned int) regs->gpr[ra] %
1892                                 (unsigned int) regs->gpr[rb];
1893                         goto compute_done;
1894 #ifdef __powerpc64__
1895                 case 457:       /* divdu */
1896                         op->val = regs->gpr[ra] / regs->gpr[rb];
1897                         goto arith_done;
1898 #endif
1899                 case 459:       /* divwu */
1900                         op->val = (unsigned int) regs->gpr[ra] /
1901                                 (unsigned int) regs->gpr[rb];
1902                         goto arith_done;
1903 #ifdef __powerpc64__
1904                 case 489:       /* divd */
1905                         op->val = (long int) regs->gpr[ra] /
1906                                 (long int) regs->gpr[rb];
1907                         goto arith_done;
1908 #endif
1909                 case 491:       /* divw */
1910                         op->val = (int) regs->gpr[ra] /
1911                                 (int) regs->gpr[rb];
1912                         goto arith_done;
1913 #ifdef __powerpc64__
1914                 case 425:       /* divde[.] */
1915                         asm volatile(PPC_DIVDE(%0, %1, %2) :
1916                                 "=r" (op->val) : "r" (regs->gpr[ra]),
1917                                 "r" (regs->gpr[rb]));
1918                         goto arith_done;
1919                 case 393:       /* divdeu[.] */
1920                         asm volatile(PPC_DIVDEU(%0, %1, %2) :
1921                                 "=r" (op->val) : "r" (regs->gpr[ra]),
1922                                 "r" (regs->gpr[rb]));
1923                         goto arith_done;
1924 #endif
1925                 case 755:       /* darn */
1926                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1927                                 goto unknown_opcode;
1928                         switch (ra & 0x3) {
1929                         case 0:
1930                                 /* 32-bit conditioned */
1931                                 asm volatile(PPC_DARN(%0, 0) : "=r" (op->val));
1932                                 goto compute_done;
1933
1934                         case 1:
1935                                 /* 64-bit conditioned */
1936                                 asm volatile(PPC_DARN(%0, 1) : "=r" (op->val));
1937                                 goto compute_done;
1938
1939                         case 2:
1940                                 /* 64-bit raw */
1941                                 asm volatile(PPC_DARN(%0, 2) : "=r" (op->val));
1942                                 goto compute_done;
1943                         }
1944
1945                         goto unknown_opcode;
1946 #ifdef __powerpc64__
1947                 case 777:       /* modsd */
1948                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1949                                 goto unknown_opcode;
1950                         op->val = (long int) regs->gpr[ra] %
1951                                 (long int) regs->gpr[rb];
1952                         goto compute_done;
1953 #endif
1954                 case 779:       /* modsw */
1955                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
1956                                 goto unknown_opcode;
1957                         op->val = (int) regs->gpr[ra] %
1958                                 (int) regs->gpr[rb];
1959                         goto compute_done;
1960
1961
1962 /*
1963  * Logical instructions
1964  */
1965                 case 26:        /* cntlzw */
1966                         val = (unsigned int) regs->gpr[rd];
1967                         op->val = ( val ? __builtin_clz(val) : 32 );
1968                         goto logical_done;
1969 #ifdef __powerpc64__
1970                 case 58:        /* cntlzd */
1971                         val = regs->gpr[rd];
1972                         op->val = ( val ? __builtin_clzl(val) : 64 );
1973                         goto logical_done;
1974 #endif
1975                 case 28:        /* and */
1976                         op->val = regs->gpr[rd] & regs->gpr[rb];
1977                         goto logical_done;
1978
1979                 case 60:        /* andc */
1980                         op->val = regs->gpr[rd] & ~regs->gpr[rb];
1981                         goto logical_done;
1982
1983                 case 122:       /* popcntb */
1984                         do_popcnt(regs, op, regs->gpr[rd], 8);
1985                         goto logical_done_nocc;
1986
1987                 case 124:       /* nor */
1988                         op->val = ~(regs->gpr[rd] | regs->gpr[rb]);
1989                         goto logical_done;
1990
1991                 case 154:       /* prtyw */
1992                         do_prty(regs, op, regs->gpr[rd], 32);
1993                         goto logical_done_nocc;
1994
1995                 case 186:       /* prtyd */
1996                         do_prty(regs, op, regs->gpr[rd], 64);
1997                         goto logical_done_nocc;
1998 #ifdef CONFIG_PPC64
1999                 case 252:       /* bpermd */
2000                         do_bpermd(regs, op, regs->gpr[rd], regs->gpr[rb]);
2001                         goto logical_done_nocc;
2002 #endif
2003                 case 284:       /* xor */
2004                         op->val = ~(regs->gpr[rd] ^ regs->gpr[rb]);
2005                         goto logical_done;
2006
2007                 case 316:       /* xor */
2008                         op->val = regs->gpr[rd] ^ regs->gpr[rb];
2009                         goto logical_done;
2010
2011                 case 378:       /* popcntw */
2012                         do_popcnt(regs, op, regs->gpr[rd], 32);
2013                         goto logical_done_nocc;
2014
2015                 case 412:       /* orc */
2016                         op->val = regs->gpr[rd] | ~regs->gpr[rb];
2017                         goto logical_done;
2018
2019                 case 444:       /* or */
2020                         op->val = regs->gpr[rd] | regs->gpr[rb];
2021                         goto logical_done;
2022
2023                 case 476:       /* nand */
2024                         op->val = ~(regs->gpr[rd] & regs->gpr[rb]);
2025                         goto logical_done;
2026 #ifdef CONFIG_PPC64
2027                 case 506:       /* popcntd */
2028                         do_popcnt(regs, op, regs->gpr[rd], 64);
2029                         goto logical_done_nocc;
2030 #endif
2031                 case 538:       /* cnttzw */
2032                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2033                                 goto unknown_opcode;
2034                         val = (unsigned int) regs->gpr[rd];
2035                         op->val = (val ? __builtin_ctz(val) : 32);
2036                         goto logical_done;
2037 #ifdef __powerpc64__
2038                 case 570:       /* cnttzd */
2039                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2040                                 goto unknown_opcode;
2041                         val = regs->gpr[rd];
2042                         op->val = (val ? __builtin_ctzl(val) : 64);
2043                         goto logical_done;
2044 #endif
2045                 case 922:       /* extsh */
2046                         op->val = (signed short) regs->gpr[rd];
2047                         goto logical_done;
2048
2049                 case 954:       /* extsb */
2050                         op->val = (signed char) regs->gpr[rd];
2051                         goto logical_done;
2052 #ifdef __powerpc64__
2053                 case 986:       /* extsw */
2054                         op->val = (signed int) regs->gpr[rd];
2055                         goto logical_done;
2056 #endif
2057
2058 /*
2059  * Shift instructions
2060  */
2061                 case 24:        /* slw */
2062                         sh = regs->gpr[rb] & 0x3f;
2063                         if (sh < 32)
2064                                 op->val = (regs->gpr[rd] << sh) & 0xffffffffUL;
2065                         else
2066                                 op->val = 0;
2067                         goto logical_done;
2068
2069                 case 536:       /* srw */
2070                         sh = regs->gpr[rb] & 0x3f;
2071                         if (sh < 32)
2072                                 op->val = (regs->gpr[rd] & 0xffffffffUL) >> sh;
2073                         else
2074                                 op->val = 0;
2075                         goto logical_done;
2076
2077                 case 792:       /* sraw */
2078                         op->type = COMPUTE + SETREG + SETXER;
2079                         sh = regs->gpr[rb] & 0x3f;
2080                         ival = (signed int) regs->gpr[rd];
2081                         op->val = ival >> (sh < 32 ? sh : 31);
2082                         op->xerval = regs->xer;
2083                         if (ival < 0 && (sh >= 32 || (ival & ((1ul << sh) - 1)) != 0))
2084                                 op->xerval |= XER_CA;
2085                         else
2086                                 op->xerval &= ~XER_CA;
2087                         set_ca32(op, op->xerval & XER_CA);
2088                         goto logical_done;
2089
2090                 case 824:       /* srawi */
2091                         op->type = COMPUTE + SETREG + SETXER;
2092                         sh = rb;
2093                         ival = (signed int) regs->gpr[rd];
2094                         op->val = ival >> sh;
2095                         op->xerval = regs->xer;
2096                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2097                                 op->xerval |= XER_CA;
2098                         else
2099                                 op->xerval &= ~XER_CA;
2100                         set_ca32(op, op->xerval & XER_CA);
2101                         goto logical_done;
2102
2103 #ifdef __powerpc64__
2104                 case 27:        /* sld */
2105                         sh = regs->gpr[rb] & 0x7f;
2106                         if (sh < 64)
2107                                 op->val = regs->gpr[rd] << sh;
2108                         else
2109                                 op->val = 0;
2110                         goto logical_done;
2111
2112                 case 539:       /* srd */
2113                         sh = regs->gpr[rb] & 0x7f;
2114                         if (sh < 64)
2115                                 op->val = regs->gpr[rd] >> sh;
2116                         else
2117                                 op->val = 0;
2118                         goto logical_done;
2119
2120                 case 794:       /* srad */
2121                         op->type = COMPUTE + SETREG + SETXER;
2122                         sh = regs->gpr[rb] & 0x7f;
2123                         ival = (signed long int) regs->gpr[rd];
2124                         op->val = ival >> (sh < 64 ? sh : 63);
2125                         op->xerval = regs->xer;
2126                         if (ival < 0 && (sh >= 64 || (ival & ((1ul << sh) - 1)) != 0))
2127                                 op->xerval |= XER_CA;
2128                         else
2129                                 op->xerval &= ~XER_CA;
2130                         set_ca32(op, op->xerval & XER_CA);
2131                         goto logical_done;
2132
2133                 case 826:       /* sradi with sh_5 = 0 */
2134                 case 827:       /* sradi with sh_5 = 1 */
2135                         op->type = COMPUTE + SETREG + SETXER;
2136                         sh = rb | ((word & 2) << 4);
2137                         ival = (signed long int) regs->gpr[rd];
2138                         op->val = ival >> sh;
2139                         op->xerval = regs->xer;
2140                         if (ival < 0 && (ival & ((1ul << sh) - 1)) != 0)
2141                                 op->xerval |= XER_CA;
2142                         else
2143                                 op->xerval &= ~XER_CA;
2144                         set_ca32(op, op->xerval & XER_CA);
2145                         goto logical_done;
2146
2147                 case 890:       /* extswsli with sh_5 = 0 */
2148                 case 891:       /* extswsli with sh_5 = 1 */
2149                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2150                                 goto unknown_opcode;
2151                         op->type = COMPUTE + SETREG;
2152                         sh = rb | ((word & 2) << 4);
2153                         val = (signed int) regs->gpr[rd];
2154                         if (sh)
2155                                 op->val = ROTATE(val, sh) & MASK64(0, 63 - sh);
2156                         else
2157                                 op->val = val;
2158                         goto logical_done;
2159
2160 #endif /* __powerpc64__ */
2161
2162 /*
2163  * Cache instructions
2164  */
2165                 case 54:        /* dcbst */
2166                         op->type = MKOP(CACHEOP, DCBST, 0);
2167                         op->ea = xform_ea(word, regs);
2168                         return 0;
2169
2170                 case 86:        /* dcbf */
2171                         op->type = MKOP(CACHEOP, DCBF, 0);
2172                         op->ea = xform_ea(word, regs);
2173                         return 0;
2174
2175                 case 246:       /* dcbtst */
2176                         op->type = MKOP(CACHEOP, DCBTST, 0);
2177                         op->ea = xform_ea(word, regs);
2178                         op->reg = rd;
2179                         return 0;
2180
2181                 case 278:       /* dcbt */
2182                         op->type = MKOP(CACHEOP, DCBTST, 0);
2183                         op->ea = xform_ea(word, regs);
2184                         op->reg = rd;
2185                         return 0;
2186
2187                 case 982:       /* icbi */
2188                         op->type = MKOP(CACHEOP, ICBI, 0);
2189                         op->ea = xform_ea(word, regs);
2190                         return 0;
2191
2192                 case 1014:      /* dcbz */
2193                         op->type = MKOP(CACHEOP, DCBZ, 0);
2194                         op->ea = xform_ea(word, regs);
2195                         return 0;
2196                 }
2197                 break;
2198         }
2199
2200 /*
2201  * Loads and stores.
2202  */
2203         op->type = UNKNOWN;
2204         op->update_reg = ra;
2205         op->reg = rd;
2206         op->val = regs->gpr[rd];
2207         u = (word >> 20) & UPDATE;
2208         op->vsx_flags = 0;
2209
2210         switch (opcode) {
2211         case 31:
2212                 u = word & UPDATE;
2213                 op->ea = xform_ea(word, regs);
2214                 switch ((word >> 1) & 0x3ff) {
2215                 case 20:        /* lwarx */
2216                         op->type = MKOP(LARX, 0, 4);
2217                         break;
2218
2219                 case 150:       /* stwcx. */
2220                         op->type = MKOP(STCX, 0, 4);
2221                         break;
2222
2223 #ifdef __powerpc64__
2224                 case 84:        /* ldarx */
2225                         op->type = MKOP(LARX, 0, 8);
2226                         break;
2227
2228                 case 214:       /* stdcx. */
2229                         op->type = MKOP(STCX, 0, 8);
2230                         break;
2231
2232                 case 52:        /* lbarx */
2233                         op->type = MKOP(LARX, 0, 1);
2234                         break;
2235
2236                 case 694:       /* stbcx. */
2237                         op->type = MKOP(STCX, 0, 1);
2238                         break;
2239
2240                 case 116:       /* lharx */
2241                         op->type = MKOP(LARX, 0, 2);
2242                         break;
2243
2244                 case 726:       /* sthcx. */
2245                         op->type = MKOP(STCX, 0, 2);
2246                         break;
2247
2248                 case 276:       /* lqarx */
2249                         if (!((rd & 1) || rd == ra || rd == rb))
2250                                 op->type = MKOP(LARX, 0, 16);
2251                         break;
2252
2253                 case 182:       /* stqcx. */
2254                         if (!(rd & 1))
2255                                 op->type = MKOP(STCX, 0, 16);
2256                         break;
2257 #endif
2258
2259                 case 23:        /* lwzx */
2260                 case 55:        /* lwzux */
2261                         op->type = MKOP(LOAD, u, 4);
2262                         break;
2263
2264                 case 87:        /* lbzx */
2265                 case 119:       /* lbzux */
2266                         op->type = MKOP(LOAD, u, 1);
2267                         break;
2268
2269 #ifdef CONFIG_ALTIVEC
2270                 /*
2271                  * Note: for the load/store vector element instructions,
2272                  * bits of the EA say which field of the VMX register to use.
2273                  */
2274                 case 7:         /* lvebx */
2275                         op->type = MKOP(LOAD_VMX, 0, 1);
2276                         op->element_size = 1;
2277                         break;
2278
2279                 case 39:        /* lvehx */
2280                         op->type = MKOP(LOAD_VMX, 0, 2);
2281                         op->element_size = 2;
2282                         break;
2283
2284                 case 71:        /* lvewx */
2285                         op->type = MKOP(LOAD_VMX, 0, 4);
2286                         op->element_size = 4;
2287                         break;
2288
2289                 case 103:       /* lvx */
2290                 case 359:       /* lvxl */
2291                         op->type = MKOP(LOAD_VMX, 0, 16);
2292                         op->element_size = 16;
2293                         break;
2294
2295                 case 135:       /* stvebx */
2296                         op->type = MKOP(STORE_VMX, 0, 1);
2297                         op->element_size = 1;
2298                         break;
2299
2300                 case 167:       /* stvehx */
2301                         op->type = MKOP(STORE_VMX, 0, 2);
2302                         op->element_size = 2;
2303                         break;
2304
2305                 case 199:       /* stvewx */
2306                         op->type = MKOP(STORE_VMX, 0, 4);
2307                         op->element_size = 4;
2308                         break;
2309
2310                 case 231:       /* stvx */
2311                 case 487:       /* stvxl */
2312                         op->type = MKOP(STORE_VMX, 0, 16);
2313                         break;
2314 #endif /* CONFIG_ALTIVEC */
2315
2316 #ifdef __powerpc64__
2317                 case 21:        /* ldx */
2318                 case 53:        /* ldux */
2319                         op->type = MKOP(LOAD, u, 8);
2320                         break;
2321
2322                 case 149:       /* stdx */
2323                 case 181:       /* stdux */
2324                         op->type = MKOP(STORE, u, 8);
2325                         break;
2326 #endif
2327
2328                 case 151:       /* stwx */
2329                 case 183:       /* stwux */
2330                         op->type = MKOP(STORE, u, 4);
2331                         break;
2332
2333                 case 215:       /* stbx */
2334                 case 247:       /* stbux */
2335                         op->type = MKOP(STORE, u, 1);
2336                         break;
2337
2338                 case 279:       /* lhzx */
2339                 case 311:       /* lhzux */
2340                         op->type = MKOP(LOAD, u, 2);
2341                         break;
2342
2343 #ifdef __powerpc64__
2344                 case 341:       /* lwax */
2345                 case 373:       /* lwaux */
2346                         op->type = MKOP(LOAD, SIGNEXT | u, 4);
2347                         break;
2348 #endif
2349
2350                 case 343:       /* lhax */
2351                 case 375:       /* lhaux */
2352                         op->type = MKOP(LOAD, SIGNEXT | u, 2);
2353                         break;
2354
2355                 case 407:       /* sthx */
2356                 case 439:       /* sthux */
2357                         op->type = MKOP(STORE, u, 2);
2358                         break;
2359
2360 #ifdef __powerpc64__
2361                 case 532:       /* ldbrx */
2362                         op->type = MKOP(LOAD, BYTEREV, 8);
2363                         break;
2364
2365 #endif
2366                 case 533:       /* lswx */
2367                         op->type = MKOP(LOAD_MULTI, 0, regs->xer & 0x7f);
2368                         break;
2369
2370                 case 534:       /* lwbrx */
2371                         op->type = MKOP(LOAD, BYTEREV, 4);
2372                         break;
2373
2374                 case 597:       /* lswi */
2375                         if (rb == 0)
2376                                 rb = 32;        /* # bytes to load */
2377                         op->type = MKOP(LOAD_MULTI, 0, rb);
2378                         op->ea = ra ? regs->gpr[ra] : 0;
2379                         break;
2380
2381 #ifdef CONFIG_PPC_FPU
2382                 case 535:       /* lfsx */
2383                 case 567:       /* lfsux */
2384                         op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2385                         break;
2386
2387                 case 599:       /* lfdx */
2388                 case 631:       /* lfdux */
2389                         op->type = MKOP(LOAD_FP, u, 8);
2390                         break;
2391
2392                 case 663:       /* stfsx */
2393                 case 695:       /* stfsux */
2394                         op->type = MKOP(STORE_FP, u | FPCONV, 4);
2395                         break;
2396
2397                 case 727:       /* stfdx */
2398                 case 759:       /* stfdux */
2399                         op->type = MKOP(STORE_FP, u, 8);
2400                         break;
2401
2402 #ifdef __powerpc64__
2403                 case 791:       /* lfdpx */
2404                         op->type = MKOP(LOAD_FP, 0, 16);
2405                         break;
2406
2407                 case 855:       /* lfiwax */
2408                         op->type = MKOP(LOAD_FP, SIGNEXT, 4);
2409                         break;
2410
2411                 case 887:       /* lfiwzx */
2412                         op->type = MKOP(LOAD_FP, 0, 4);
2413                         break;
2414
2415                 case 919:       /* stfdpx */
2416                         op->type = MKOP(STORE_FP, 0, 16);
2417                         break;
2418
2419                 case 983:       /* stfiwx */
2420                         op->type = MKOP(STORE_FP, 0, 4);
2421                         break;
2422 #endif /* __powerpc64 */
2423 #endif /* CONFIG_PPC_FPU */
2424
2425 #ifdef __powerpc64__
2426                 case 660:       /* stdbrx */
2427                         op->type = MKOP(STORE, BYTEREV, 8);
2428                         op->val = byterev_8(regs->gpr[rd]);
2429                         break;
2430
2431 #endif
2432                 case 661:       /* stswx */
2433                         op->type = MKOP(STORE_MULTI, 0, regs->xer & 0x7f);
2434                         break;
2435
2436                 case 662:       /* stwbrx */
2437                         op->type = MKOP(STORE, BYTEREV, 4);
2438                         op->val = byterev_4(regs->gpr[rd]);
2439                         break;
2440
2441                 case 725:       /* stswi */
2442                         if (rb == 0)
2443                                 rb = 32;        /* # bytes to store */
2444                         op->type = MKOP(STORE_MULTI, 0, rb);
2445                         op->ea = ra ? regs->gpr[ra] : 0;
2446                         break;
2447
2448                 case 790:       /* lhbrx */
2449                         op->type = MKOP(LOAD, BYTEREV, 2);
2450                         break;
2451
2452                 case 918:       /* sthbrx */
2453                         op->type = MKOP(STORE, BYTEREV, 2);
2454                         op->val = byterev_2(regs->gpr[rd]);
2455                         break;
2456
2457 #ifdef CONFIG_VSX
2458                 case 12:        /* lxsiwzx */
2459                         op->reg = rd | ((word & 1) << 5);
2460                         op->type = MKOP(LOAD_VSX, 0, 4);
2461                         op->element_size = 8;
2462                         break;
2463
2464                 case 76:        /* lxsiwax */
2465                         op->reg = rd | ((word & 1) << 5);
2466                         op->type = MKOP(LOAD_VSX, SIGNEXT, 4);
2467                         op->element_size = 8;
2468                         break;
2469
2470                 case 140:       /* stxsiwx */
2471                         op->reg = rd | ((word & 1) << 5);
2472                         op->type = MKOP(STORE_VSX, 0, 4);
2473                         op->element_size = 8;
2474                         break;
2475
2476                 case 268:       /* lxvx */
2477                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2478                                 goto unknown_opcode;
2479                         op->reg = rd | ((word & 1) << 5);
2480                         op->type = MKOP(LOAD_VSX, 0, 16);
2481                         op->element_size = 16;
2482                         op->vsx_flags = VSX_CHECK_VEC;
2483                         break;
2484
2485                 case 269:       /* lxvl */
2486                 case 301: {     /* lxvll */
2487                         int nb;
2488                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2489                                 goto unknown_opcode;
2490                         op->reg = rd | ((word & 1) << 5);
2491                         op->ea = ra ? regs->gpr[ra] : 0;
2492                         nb = regs->gpr[rb] & 0xff;
2493                         if (nb > 16)
2494                                 nb = 16;
2495                         op->type = MKOP(LOAD_VSX, 0, nb);
2496                         op->element_size = 16;
2497                         op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2498                                 VSX_CHECK_VEC;
2499                         break;
2500                 }
2501                 case 332:       /* lxvdsx */
2502                         op->reg = rd | ((word & 1) << 5);
2503                         op->type = MKOP(LOAD_VSX, 0, 8);
2504                         op->element_size = 8;
2505                         op->vsx_flags = VSX_SPLAT;
2506                         break;
2507
2508                 case 333:       /* lxvpx */
2509                         if (!cpu_has_feature(CPU_FTR_ARCH_31))
2510                                 goto unknown_opcode;
2511                         op->reg = VSX_REGISTER_XTP(rd);
2512                         op->type = MKOP(LOAD_VSX, 0, 32);
2513                         op->element_size = 32;
2514                         break;
2515
2516                 case 364:       /* lxvwsx */
2517                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2518                                 goto unknown_opcode;
2519                         op->reg = rd | ((word & 1) << 5);
2520                         op->type = MKOP(LOAD_VSX, 0, 4);
2521                         op->element_size = 4;
2522                         op->vsx_flags = VSX_SPLAT | VSX_CHECK_VEC;
2523                         break;
2524
2525                 case 396:       /* stxvx */
2526                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2527                                 goto unknown_opcode;
2528                         op->reg = rd | ((word & 1) << 5);
2529                         op->type = MKOP(STORE_VSX, 0, 16);
2530                         op->element_size = 16;
2531                         op->vsx_flags = VSX_CHECK_VEC;
2532                         break;
2533
2534                 case 397:       /* stxvl */
2535                 case 429: {     /* stxvll */
2536                         int nb;
2537                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2538                                 goto unknown_opcode;
2539                         op->reg = rd | ((word & 1) << 5);
2540                         op->ea = ra ? regs->gpr[ra] : 0;
2541                         nb = regs->gpr[rb] & 0xff;
2542                         if (nb > 16)
2543                                 nb = 16;
2544                         op->type = MKOP(STORE_VSX, 0, nb);
2545                         op->element_size = 16;
2546                         op->vsx_flags = ((word & 0x20) ? VSX_LDLEFT : 0) |
2547                                 VSX_CHECK_VEC;
2548                         break;
2549                 }
2550                 case 461:       /* stxvpx */
2551                         if (!cpu_has_feature(CPU_FTR_ARCH_31))
2552                                 goto unknown_opcode;
2553                         op->reg = VSX_REGISTER_XTP(rd);
2554                         op->type = MKOP(STORE_VSX, 0, 32);
2555                         op->element_size = 32;
2556                         break;
2557                 case 524:       /* lxsspx */
2558                         op->reg = rd | ((word & 1) << 5);
2559                         op->type = MKOP(LOAD_VSX, 0, 4);
2560                         op->element_size = 8;
2561                         op->vsx_flags = VSX_FPCONV;
2562                         break;
2563
2564                 case 588:       /* lxsdx */
2565                         op->reg = rd | ((word & 1) << 5);
2566                         op->type = MKOP(LOAD_VSX, 0, 8);
2567                         op->element_size = 8;
2568                         break;
2569
2570                 case 652:       /* stxsspx */
2571                         op->reg = rd | ((word & 1) << 5);
2572                         op->type = MKOP(STORE_VSX, 0, 4);
2573                         op->element_size = 8;
2574                         op->vsx_flags = VSX_FPCONV;
2575                         break;
2576
2577                 case 716:       /* stxsdx */
2578                         op->reg = rd | ((word & 1) << 5);
2579                         op->type = MKOP(STORE_VSX, 0, 8);
2580                         op->element_size = 8;
2581                         break;
2582
2583                 case 780:       /* lxvw4x */
2584                         op->reg = rd | ((word & 1) << 5);
2585                         op->type = MKOP(LOAD_VSX, 0, 16);
2586                         op->element_size = 4;
2587                         break;
2588
2589                 case 781:       /* lxsibzx */
2590                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2591                                 goto unknown_opcode;
2592                         op->reg = rd | ((word & 1) << 5);
2593                         op->type = MKOP(LOAD_VSX, 0, 1);
2594                         op->element_size = 8;
2595                         op->vsx_flags = VSX_CHECK_VEC;
2596                         break;
2597
2598                 case 812:       /* lxvh8x */
2599                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2600                                 goto unknown_opcode;
2601                         op->reg = rd | ((word & 1) << 5);
2602                         op->type = MKOP(LOAD_VSX, 0, 16);
2603                         op->element_size = 2;
2604                         op->vsx_flags = VSX_CHECK_VEC;
2605                         break;
2606
2607                 case 813:       /* lxsihzx */
2608                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2609                                 goto unknown_opcode;
2610                         op->reg = rd | ((word & 1) << 5);
2611                         op->type = MKOP(LOAD_VSX, 0, 2);
2612                         op->element_size = 8;
2613                         op->vsx_flags = VSX_CHECK_VEC;
2614                         break;
2615
2616                 case 844:       /* lxvd2x */
2617                         op->reg = rd | ((word & 1) << 5);
2618                         op->type = MKOP(LOAD_VSX, 0, 16);
2619                         op->element_size = 8;
2620                         break;
2621
2622                 case 876:       /* lxvb16x */
2623                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2624                                 goto unknown_opcode;
2625                         op->reg = rd | ((word & 1) << 5);
2626                         op->type = MKOP(LOAD_VSX, 0, 16);
2627                         op->element_size = 1;
2628                         op->vsx_flags = VSX_CHECK_VEC;
2629                         break;
2630
2631                 case 908:       /* stxvw4x */
2632                         op->reg = rd | ((word & 1) << 5);
2633                         op->type = MKOP(STORE_VSX, 0, 16);
2634                         op->element_size = 4;
2635                         break;
2636
2637                 case 909:       /* stxsibx */
2638                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2639                                 goto unknown_opcode;
2640                         op->reg = rd | ((word & 1) << 5);
2641                         op->type = MKOP(STORE_VSX, 0, 1);
2642                         op->element_size = 8;
2643                         op->vsx_flags = VSX_CHECK_VEC;
2644                         break;
2645
2646                 case 940:       /* stxvh8x */
2647                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2648                                 goto unknown_opcode;
2649                         op->reg = rd | ((word & 1) << 5);
2650                         op->type = MKOP(STORE_VSX, 0, 16);
2651                         op->element_size = 2;
2652                         op->vsx_flags = VSX_CHECK_VEC;
2653                         break;
2654
2655                 case 941:       /* stxsihx */
2656                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2657                                 goto unknown_opcode;
2658                         op->reg = rd | ((word & 1) << 5);
2659                         op->type = MKOP(STORE_VSX, 0, 2);
2660                         op->element_size = 8;
2661                         op->vsx_flags = VSX_CHECK_VEC;
2662                         break;
2663
2664                 case 972:       /* stxvd2x */
2665                         op->reg = rd | ((word & 1) << 5);
2666                         op->type = MKOP(STORE_VSX, 0, 16);
2667                         op->element_size = 8;
2668                         break;
2669
2670                 case 1004:      /* stxvb16x */
2671                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2672                                 goto unknown_opcode;
2673                         op->reg = rd | ((word & 1) << 5);
2674                         op->type = MKOP(STORE_VSX, 0, 16);
2675                         op->element_size = 1;
2676                         op->vsx_flags = VSX_CHECK_VEC;
2677                         break;
2678
2679 #endif /* CONFIG_VSX */
2680                 }
2681                 break;
2682
2683         case 32:        /* lwz */
2684         case 33:        /* lwzu */
2685                 op->type = MKOP(LOAD, u, 4);
2686                 op->ea = dform_ea(word, regs);
2687                 break;
2688
2689         case 34:        /* lbz */
2690         case 35:        /* lbzu */
2691                 op->type = MKOP(LOAD, u, 1);
2692                 op->ea = dform_ea(word, regs);
2693                 break;
2694
2695         case 36:        /* stw */
2696         case 37:        /* stwu */
2697                 op->type = MKOP(STORE, u, 4);
2698                 op->ea = dform_ea(word, regs);
2699                 break;
2700
2701         case 38:        /* stb */
2702         case 39:        /* stbu */
2703                 op->type = MKOP(STORE, u, 1);
2704                 op->ea = dform_ea(word, regs);
2705                 break;
2706
2707         case 40:        /* lhz */
2708         case 41:        /* lhzu */
2709                 op->type = MKOP(LOAD, u, 2);
2710                 op->ea = dform_ea(word, regs);
2711                 break;
2712
2713         case 42:        /* lha */
2714         case 43:        /* lhau */
2715                 op->type = MKOP(LOAD, SIGNEXT | u, 2);
2716                 op->ea = dform_ea(word, regs);
2717                 break;
2718
2719         case 44:        /* sth */
2720         case 45:        /* sthu */
2721                 op->type = MKOP(STORE, u, 2);
2722                 op->ea = dform_ea(word, regs);
2723                 break;
2724
2725         case 46:        /* lmw */
2726                 if (ra >= rd)
2727                         break;          /* invalid form, ra in range to load */
2728                 op->type = MKOP(LOAD_MULTI, 0, 4 * (32 - rd));
2729                 op->ea = dform_ea(word, regs);
2730                 break;
2731
2732         case 47:        /* stmw */
2733                 op->type = MKOP(STORE_MULTI, 0, 4 * (32 - rd));
2734                 op->ea = dform_ea(word, regs);
2735                 break;
2736
2737 #ifdef CONFIG_PPC_FPU
2738         case 48:        /* lfs */
2739         case 49:        /* lfsu */
2740                 op->type = MKOP(LOAD_FP, u | FPCONV, 4);
2741                 op->ea = dform_ea(word, regs);
2742                 break;
2743
2744         case 50:        /* lfd */
2745         case 51:        /* lfdu */
2746                 op->type = MKOP(LOAD_FP, u, 8);
2747                 op->ea = dform_ea(word, regs);
2748                 break;
2749
2750         case 52:        /* stfs */
2751         case 53:        /* stfsu */
2752                 op->type = MKOP(STORE_FP, u | FPCONV, 4);
2753                 op->ea = dform_ea(word, regs);
2754                 break;
2755
2756         case 54:        /* stfd */
2757         case 55:        /* stfdu */
2758                 op->type = MKOP(STORE_FP, u, 8);
2759                 op->ea = dform_ea(word, regs);
2760                 break;
2761 #endif
2762
2763 #ifdef __powerpc64__
2764         case 56:        /* lq */
2765                 if (!((rd & 1) || (rd == ra)))
2766                         op->type = MKOP(LOAD, 0, 16);
2767                 op->ea = dqform_ea(word, regs);
2768                 break;
2769 #endif
2770
2771 #ifdef CONFIG_VSX
2772         case 57:        /* lfdp, lxsd, lxssp */
2773                 op->ea = dsform_ea(word, regs);
2774                 switch (word & 3) {
2775                 case 0:         /* lfdp */
2776                         if (rd & 1)
2777                                 break;          /* reg must be even */
2778                         op->type = MKOP(LOAD_FP, 0, 16);
2779                         break;
2780                 case 2:         /* lxsd */
2781                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2782                                 goto unknown_opcode;
2783                         op->reg = rd + 32;
2784                         op->type = MKOP(LOAD_VSX, 0, 8);
2785                         op->element_size = 8;
2786                         op->vsx_flags = VSX_CHECK_VEC;
2787                         break;
2788                 case 3:         /* lxssp */
2789                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2790                                 goto unknown_opcode;
2791                         op->reg = rd + 32;
2792                         op->type = MKOP(LOAD_VSX, 0, 4);
2793                         op->element_size = 8;
2794                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2795                         break;
2796                 }
2797                 break;
2798 #endif /* CONFIG_VSX */
2799
2800 #ifdef __powerpc64__
2801         case 58:        /* ld[u], lwa */
2802                 op->ea = dsform_ea(word, regs);
2803                 switch (word & 3) {
2804                 case 0:         /* ld */
2805                         op->type = MKOP(LOAD, 0, 8);
2806                         break;
2807                 case 1:         /* ldu */
2808                         op->type = MKOP(LOAD, UPDATE, 8);
2809                         break;
2810                 case 2:         /* lwa */
2811                         op->type = MKOP(LOAD, SIGNEXT, 4);
2812                         break;
2813                 }
2814                 break;
2815 #endif
2816
2817 #ifdef CONFIG_VSX
2818         case 6:
2819                 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2820                         goto unknown_opcode;
2821                 op->ea = dqform_ea(word, regs);
2822                 op->reg = VSX_REGISTER_XTP(rd);
2823                 op->element_size = 32;
2824                 switch (word & 0xf) {
2825                 case 0:         /* lxvp */
2826                         op->type = MKOP(LOAD_VSX, 0, 32);
2827                         break;
2828                 case 1:         /* stxvp */
2829                         op->type = MKOP(STORE_VSX, 0, 32);
2830                         break;
2831                 }
2832                 break;
2833
2834         case 61:        /* stfdp, lxv, stxsd, stxssp, stxv */
2835                 switch (word & 7) {
2836                 case 0:         /* stfdp with LSB of DS field = 0 */
2837                 case 4:         /* stfdp with LSB of DS field = 1 */
2838                         op->ea = dsform_ea(word, regs);
2839                         op->type = MKOP(STORE_FP, 0, 16);
2840                         break;
2841
2842                 case 1:         /* lxv */
2843                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2844                                 goto unknown_opcode;
2845                         op->ea = dqform_ea(word, regs);
2846                         if (word & 8)
2847                                 op->reg = rd + 32;
2848                         op->type = MKOP(LOAD_VSX, 0, 16);
2849                         op->element_size = 16;
2850                         op->vsx_flags = VSX_CHECK_VEC;
2851                         break;
2852
2853                 case 2:         /* stxsd with LSB of DS field = 0 */
2854                 case 6:         /* stxsd with LSB of DS field = 1 */
2855                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2856                                 goto unknown_opcode;
2857                         op->ea = dsform_ea(word, regs);
2858                         op->reg = rd + 32;
2859                         op->type = MKOP(STORE_VSX, 0, 8);
2860                         op->element_size = 8;
2861                         op->vsx_flags = VSX_CHECK_VEC;
2862                         break;
2863
2864                 case 3:         /* stxssp with LSB of DS field = 0 */
2865                 case 7:         /* stxssp with LSB of DS field = 1 */
2866                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2867                                 goto unknown_opcode;
2868                         op->ea = dsform_ea(word, regs);
2869                         op->reg = rd + 32;
2870                         op->type = MKOP(STORE_VSX, 0, 4);
2871                         op->element_size = 8;
2872                         op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2873                         break;
2874
2875                 case 5:         /* stxv */
2876                         if (!cpu_has_feature(CPU_FTR_ARCH_300))
2877                                 goto unknown_opcode;
2878                         op->ea = dqform_ea(word, regs);
2879                         if (word & 8)
2880                                 op->reg = rd + 32;
2881                         op->type = MKOP(STORE_VSX, 0, 16);
2882                         op->element_size = 16;
2883                         op->vsx_flags = VSX_CHECK_VEC;
2884                         break;
2885                 }
2886                 break;
2887 #endif /* CONFIG_VSX */
2888
2889 #ifdef __powerpc64__
2890         case 62:        /* std[u] */
2891                 op->ea = dsform_ea(word, regs);
2892                 switch (word & 3) {
2893                 case 0:         /* std */
2894                         op->type = MKOP(STORE, 0, 8);
2895                         break;
2896                 case 1:         /* stdu */
2897                         op->type = MKOP(STORE, UPDATE, 8);
2898                         break;
2899                 case 2:         /* stq */
2900                         if (!(rd & 1))
2901                                 op->type = MKOP(STORE, 0, 16);
2902                         break;
2903                 }
2904                 break;
2905         case 1: /* Prefixed instructions */
2906                 if (!cpu_has_feature(CPU_FTR_ARCH_31))
2907                         goto unknown_opcode;
2908
2909                 prefix_r = GET_PREFIX_R(word);
2910                 ra = GET_PREFIX_RA(suffix);
2911                 op->update_reg = ra;
2912                 rd = (suffix >> 21) & 0x1f;
2913                 op->reg = rd;
2914                 op->val = regs->gpr[rd];
2915
2916                 suffixopcode = get_op(suffix);
2917                 prefixtype = (word >> 24) & 0x3;
2918                 switch (prefixtype) {
2919                 case 0: /* Type 00  Eight-Byte Load/Store */
2920                         if (prefix_r && ra)
2921                                 break;
2922                         op->ea = mlsd_8lsd_ea(word, suffix, regs);
2923                         switch (suffixopcode) {
2924                         case 41:        /* plwa */
2925                                 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 4);
2926                                 break;
2927 #ifdef CONFIG_VSX
2928                         case 42:        /* plxsd */
2929                                 op->reg = rd + 32;
2930                                 op->type = MKOP(LOAD_VSX, PREFIXED, 8);
2931                                 op->element_size = 8;
2932                                 op->vsx_flags = VSX_CHECK_VEC;
2933                                 break;
2934                         case 43:        /* plxssp */
2935                                 op->reg = rd + 32;
2936                                 op->type = MKOP(LOAD_VSX, PREFIXED, 4);
2937                                 op->element_size = 8;
2938                                 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2939                                 break;
2940                         case 46:        /* pstxsd */
2941                                 op->reg = rd + 32;
2942                                 op->type = MKOP(STORE_VSX, PREFIXED, 8);
2943                                 op->element_size = 8;
2944                                 op->vsx_flags = VSX_CHECK_VEC;
2945                                 break;
2946                         case 47:        /* pstxssp */
2947                                 op->reg = rd + 32;
2948                                 op->type = MKOP(STORE_VSX, PREFIXED, 4);
2949                                 op->element_size = 8;
2950                                 op->vsx_flags = VSX_FPCONV | VSX_CHECK_VEC;
2951                                 break;
2952                         case 51:        /* plxv1 */
2953                                 op->reg += 32;
2954                                 fallthrough;
2955                         case 50:        /* plxv0 */
2956                                 op->type = MKOP(LOAD_VSX, PREFIXED, 16);
2957                                 op->element_size = 16;
2958                                 op->vsx_flags = VSX_CHECK_VEC;
2959                                 break;
2960                         case 55:        /* pstxv1 */
2961                                 op->reg = rd + 32;
2962                                 fallthrough;
2963                         case 54:        /* pstxv0 */
2964                                 op->type = MKOP(STORE_VSX, PREFIXED, 16);
2965                                 op->element_size = 16;
2966                                 op->vsx_flags = VSX_CHECK_VEC;
2967                                 break;
2968 #endif /* CONFIG_VSX */
2969                         case 56:        /* plq */
2970                                 op->type = MKOP(LOAD, PREFIXED, 16);
2971                                 break;
2972                         case 57:        /* pld */
2973                                 op->type = MKOP(LOAD, PREFIXED, 8);
2974                                 break;
2975 #ifdef CONFIG_VSX
2976                         case 58:        /* plxvp */
2977                                 op->reg = VSX_REGISTER_XTP(rd);
2978                                 op->type = MKOP(LOAD_VSX, PREFIXED, 32);
2979                                 op->element_size = 32;
2980                                 break;
2981 #endif /* CONFIG_VSX */
2982                         case 60:        /* pstq */
2983                                 op->type = MKOP(STORE, PREFIXED, 16);
2984                                 break;
2985                         case 61:        /* pstd */
2986                                 op->type = MKOP(STORE, PREFIXED, 8);
2987                                 break;
2988 #ifdef CONFIG_VSX
2989                         case 62:        /* pstxvp */
2990                                 op->reg = VSX_REGISTER_XTP(rd);
2991                                 op->type = MKOP(STORE_VSX, PREFIXED, 32);
2992                                 op->element_size = 32;
2993                                 break;
2994 #endif /* CONFIG_VSX */
2995                         }
2996                         break;
2997                 case 1: /* Type 01 Eight-Byte Register-to-Register */
2998                         break;
2999                 case 2: /* Type 10 Modified Load/Store */
3000                         if (prefix_r && ra)
3001                                 break;
3002                         op->ea = mlsd_8lsd_ea(word, suffix, regs);
3003                         switch (suffixopcode) {
3004                         case 32:        /* plwz */
3005                                 op->type = MKOP(LOAD, PREFIXED, 4);
3006                                 break;
3007                         case 34:        /* plbz */
3008                                 op->type = MKOP(LOAD, PREFIXED, 1);
3009                                 break;
3010                         case 36:        /* pstw */
3011                                 op->type = MKOP(STORE, PREFIXED, 4);
3012                                 break;
3013                         case 38:        /* pstb */
3014                                 op->type = MKOP(STORE, PREFIXED, 1);
3015                                 break;
3016                         case 40:        /* plhz */
3017                                 op->type = MKOP(LOAD, PREFIXED, 2);
3018                                 break;
3019                         case 42:        /* plha */
3020                                 op->type = MKOP(LOAD, PREFIXED | SIGNEXT, 2);
3021                                 break;
3022                         case 44:        /* psth */
3023                                 op->type = MKOP(STORE, PREFIXED, 2);
3024                                 break;
3025                         case 48:        /* plfs */
3026                                 op->type = MKOP(LOAD_FP, PREFIXED | FPCONV, 4);
3027                                 break;
3028                         case 50:        /* plfd */
3029                                 op->type = MKOP(LOAD_FP, PREFIXED, 8);
3030                                 break;
3031                         case 52:        /* pstfs */
3032                                 op->type = MKOP(STORE_FP, PREFIXED | FPCONV, 4);
3033                                 break;
3034                         case 54:        /* pstfd */
3035                                 op->type = MKOP(STORE_FP, PREFIXED, 8);
3036                                 break;
3037                         }
3038                         break;
3039                 case 3: /* Type 11 Modified Register-to-Register */
3040                         break;
3041                 }
3042 #endif /* __powerpc64__ */
3043
3044         }
3045
3046         if (OP_IS_LOAD_STORE(op->type) && (op->type & UPDATE)) {
3047                 switch (GETTYPE(op->type)) {
3048                 case LOAD:
3049                         if (ra == rd)
3050                                 goto unknown_opcode;
3051                         fallthrough;
3052                 case STORE:
3053                 case LOAD_FP:
3054                 case STORE_FP:
3055                         if (ra == 0)
3056                                 goto unknown_opcode;
3057                 }
3058         }
3059
3060 #ifdef CONFIG_VSX
3061         if ((GETTYPE(op->type) == LOAD_VSX ||
3062              GETTYPE(op->type) == STORE_VSX) &&
3063             !cpu_has_feature(CPU_FTR_VSX)) {
3064                 return -1;
3065         }
3066 #endif /* CONFIG_VSX */
3067
3068         return 0;
3069
3070  unknown_opcode:
3071         op->type = UNKNOWN;
3072         return 0;
3073
3074  logical_done:
3075         if (word & 1)
3076                 set_cr0(regs, op);
3077  logical_done_nocc:
3078         op->reg = ra;
3079         op->type |= SETREG;
3080         return 1;
3081
3082  arith_done:
3083         if (word & 1)
3084                 set_cr0(regs, op);
3085  compute_done:
3086         op->reg = rd;
3087         op->type |= SETREG;
3088         return 1;
3089
3090  priv:
3091         op->type = INTERRUPT | 0x700;
3092         op->val = SRR1_PROGPRIV;
3093         return 0;
3094
3095  trap:
3096         op->type = INTERRUPT | 0x700;
3097         op->val = SRR1_PROGTRAP;
3098         return 0;
3099 }
3100 EXPORT_SYMBOL_GPL(analyse_instr);
3101 NOKPROBE_SYMBOL(analyse_instr);
3102
3103 /*
3104  * For PPC32 we always use stwu with r1 to change the stack pointer.
3105  * So this emulated store may corrupt the exception frame, now we
3106  * have to provide the exception frame trampoline, which is pushed
3107  * below the kprobed function stack. So we only update gpr[1] but
3108  * don't emulate the real store operation. We will do real store
3109  * operation safely in exception return code by checking this flag.
3110  */
3111 static nokprobe_inline int handle_stack_update(unsigned long ea, struct pt_regs *regs)
3112 {
3113         /*
3114          * Check if we already set since that means we'll
3115          * lose the previous value.
3116          */
3117         WARN_ON(test_thread_flag(TIF_EMULATE_STACK_STORE));
3118         set_thread_flag(TIF_EMULATE_STACK_STORE);
3119         return 0;
3120 }
3121
3122 static nokprobe_inline void do_signext(unsigned long *valp, int size)
3123 {
3124         switch (size) {
3125         case 2:
3126                 *valp = (signed short) *valp;
3127                 break;
3128         case 4:
3129                 *valp = (signed int) *valp;
3130                 break;
3131         }
3132 }
3133
3134 static nokprobe_inline void do_byterev(unsigned long *valp, int size)
3135 {
3136         switch (size) {
3137         case 2:
3138                 *valp = byterev_2(*valp);
3139                 break;
3140         case 4:
3141                 *valp = byterev_4(*valp);
3142                 break;
3143 #ifdef __powerpc64__
3144         case 8:
3145                 *valp = byterev_8(*valp);
3146                 break;
3147 #endif
3148         }
3149 }
3150
3151 /*
3152  * Emulate an instruction that can be executed just by updating
3153  * fields in *regs.
3154  */
3155 void emulate_update_regs(struct pt_regs *regs, struct instruction_op *op)
3156 {
3157         unsigned long next_pc;
3158
3159         next_pc = truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op->type));
3160         switch (GETTYPE(op->type)) {
3161         case COMPUTE:
3162                 if (op->type & SETREG)
3163                         regs->gpr[op->reg] = op->val;
3164                 if (op->type & SETCC)
3165                         regs->ccr = op->ccval;
3166                 if (op->type & SETXER)
3167                         regs->xer = op->xerval;
3168                 break;
3169
3170         case BRANCH:
3171                 if (op->type & SETLK)
3172                         regs->link = next_pc;
3173                 if (op->type & BRTAKEN)
3174                         next_pc = op->val;
3175                 if (op->type & DECCTR)
3176                         --regs->ctr;
3177                 break;
3178
3179         case BARRIER:
3180                 switch (op->type & BARRIER_MASK) {
3181                 case BARRIER_SYNC:
3182                         mb();
3183                         break;
3184                 case BARRIER_ISYNC:
3185                         isync();
3186                         break;
3187                 case BARRIER_EIEIO:
3188                         eieio();
3189                         break;
3190 #ifdef CONFIG_PPC64
3191                 case BARRIER_LWSYNC:
3192                         asm volatile("lwsync" : : : "memory");
3193                         break;
3194                 case BARRIER_PTESYNC:
3195                         asm volatile("ptesync" : : : "memory");
3196                         break;
3197 #endif
3198                 }
3199                 break;
3200
3201         case MFSPR:
3202                 switch (op->spr) {
3203                 case SPRN_XER:
3204                         regs->gpr[op->reg] = regs->xer & 0xffffffffUL;
3205                         break;
3206                 case SPRN_LR:
3207                         regs->gpr[op->reg] = regs->link;
3208                         break;
3209                 case SPRN_CTR:
3210                         regs->gpr[op->reg] = regs->ctr;
3211                         break;
3212                 default:
3213                         WARN_ON_ONCE(1);
3214                 }
3215                 break;
3216
3217         case MTSPR:
3218                 switch (op->spr) {
3219                 case SPRN_XER:
3220                         regs->xer = op->val & 0xffffffffUL;
3221                         break;
3222                 case SPRN_LR:
3223                         regs->link = op->val;
3224                         break;
3225                 case SPRN_CTR:
3226                         regs->ctr = op->val;
3227                         break;
3228                 default:
3229                         WARN_ON_ONCE(1);
3230                 }
3231                 break;
3232
3233         default:
3234                 WARN_ON_ONCE(1);
3235         }
3236         regs_set_return_ip(regs, next_pc);
3237 }
3238 NOKPROBE_SYMBOL(emulate_update_regs);
3239
3240 /*
3241  * Emulate a previously-analysed load or store instruction.
3242  * Return values are:
3243  * 0 = instruction emulated successfully
3244  * -EFAULT = address out of range or access faulted (regs->dar
3245  *           contains the faulting address)
3246  * -EACCES = misaligned access, instruction requires alignment
3247  * -EINVAL = unknown operation in *op
3248  */
3249 int emulate_loadstore(struct pt_regs *regs, struct instruction_op *op)
3250 {
3251         int err, size, type;
3252         int i, rd, nb;
3253         unsigned int cr;
3254         unsigned long val;
3255         unsigned long ea;
3256         bool cross_endian;
3257
3258         err = 0;
3259         size = GETSIZE(op->type);
3260         type = GETTYPE(op->type);
3261         cross_endian = (regs->msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
3262         ea = truncate_if_32bit(regs->msr, op->ea);
3263
3264         switch (type) {
3265         case LARX:
3266                 if (ea & (size - 1))
3267                         return -EACCES;         /* can't handle misaligned */
3268                 if (!address_ok(regs, ea, size))
3269                         return -EFAULT;
3270                 err = 0;
3271                 val = 0;
3272                 switch (size) {
3273 #ifdef __powerpc64__
3274                 case 1:
3275                         __get_user_asmx(val, ea, err, "lbarx");
3276                         break;
3277                 case 2:
3278                         __get_user_asmx(val, ea, err, "lharx");
3279                         break;
3280 #endif
3281                 case 4:
3282                         __get_user_asmx(val, ea, err, "lwarx");
3283                         break;
3284 #ifdef __powerpc64__
3285                 case 8:
3286                         __get_user_asmx(val, ea, err, "ldarx");
3287                         break;
3288                 case 16:
3289                         err = do_lqarx(ea, &regs->gpr[op->reg]);
3290                         break;
3291 #endif
3292                 default:
3293                         return -EINVAL;
3294                 }
3295                 if (err) {
3296                         regs->dar = ea;
3297                         break;
3298                 }
3299                 if (size < 16)
3300                         regs->gpr[op->reg] = val;
3301                 break;
3302
3303         case STCX:
3304                 if (ea & (size - 1))
3305                         return -EACCES;         /* can't handle misaligned */
3306                 if (!address_ok(regs, ea, size))
3307                         return -EFAULT;
3308                 err = 0;
3309                 switch (size) {
3310 #ifdef __powerpc64__
3311                 case 1:
3312                         __put_user_asmx(op->val, ea, err, "stbcx.", cr);
3313                         break;
3314                 case 2:
3315                         __put_user_asmx(op->val, ea, err, "sthcx.", cr);
3316                         break;
3317 #endif
3318                 case 4:
3319                         __put_user_asmx(op->val, ea, err, "stwcx.", cr);
3320                         break;
3321 #ifdef __powerpc64__
3322                 case 8:
3323                         __put_user_asmx(op->val, ea, err, "stdcx.", cr);
3324                         break;
3325                 case 16:
3326                         err = do_stqcx(ea, regs->gpr[op->reg],
3327                                        regs->gpr[op->reg + 1], &cr);
3328                         break;
3329 #endif
3330                 default:
3331                         return -EINVAL;
3332                 }
3333                 if (!err)
3334                         regs->ccr = (regs->ccr & 0x0fffffff) |
3335                                 (cr & 0xe0000000) |
3336                                 ((regs->xer >> 3) & 0x10000000);
3337                 else
3338                         regs->dar = ea;
3339                 break;
3340
3341         case LOAD:
3342 #ifdef __powerpc64__
3343                 if (size == 16) {
3344                         err = emulate_lq(regs, ea, op->reg, cross_endian);
3345                         break;
3346                 }
3347 #endif
3348                 err = read_mem(&regs->gpr[op->reg], ea, size, regs);
3349                 if (!err) {
3350                         if (op->type & SIGNEXT)
3351                                 do_signext(&regs->gpr[op->reg], size);
3352                         if ((op->type & BYTEREV) == (cross_endian ? 0 : BYTEREV))
3353                                 do_byterev(&regs->gpr[op->reg], size);
3354                 }
3355                 break;
3356
3357 #ifdef CONFIG_PPC_FPU
3358         case LOAD_FP:
3359                 /*
3360                  * If the instruction is in userspace, we can emulate it even
3361                  * if the VMX state is not live, because we have the state
3362                  * stored in the thread_struct.  If the instruction is in
3363                  * the kernel, we must not touch the state in the thread_struct.
3364                  */
3365                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3366                         return 0;
3367                 err = do_fp_load(op, ea, regs, cross_endian);
3368                 break;
3369 #endif
3370 #ifdef CONFIG_ALTIVEC
3371         case LOAD_VMX:
3372                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3373                         return 0;
3374                 err = do_vec_load(op->reg, ea, size, regs, cross_endian);
3375                 break;
3376 #endif
3377 #ifdef CONFIG_VSX
3378         case LOAD_VSX: {
3379                 unsigned long msrbit = MSR_VSX;
3380
3381                 /*
3382                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3383                  * when the target of the instruction is a vector register.
3384                  */
3385                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3386                         msrbit = MSR_VEC;
3387                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3388                         return 0;
3389                 err = do_vsx_load(op, ea, regs, cross_endian);
3390                 break;
3391         }
3392 #endif
3393         case LOAD_MULTI:
3394                 if (!address_ok(regs, ea, size))
3395                         return -EFAULT;
3396                 rd = op->reg;
3397                 for (i = 0; i < size; i += 4) {
3398                         unsigned int v32 = 0;
3399
3400                         nb = size - i;
3401                         if (nb > 4)
3402                                 nb = 4;
3403                         err = copy_mem_in((u8 *) &v32, ea, nb, regs);
3404                         if (err)
3405                                 break;
3406                         if (unlikely(cross_endian))
3407                                 v32 = byterev_4(v32);
3408                         regs->gpr[rd] = v32;
3409                         ea += 4;
3410                         /* reg number wraps from 31 to 0 for lsw[ix] */
3411                         rd = (rd + 1) & 0x1f;
3412                 }
3413                 break;
3414
3415         case STORE:
3416 #ifdef __powerpc64__
3417                 if (size == 16) {
3418                         err = emulate_stq(regs, ea, op->reg, cross_endian);
3419                         break;
3420                 }
3421 #endif
3422                 if ((op->type & UPDATE) && size == sizeof(long) &&
3423                     op->reg == 1 && op->update_reg == 1 &&
3424                     !(regs->msr & MSR_PR) &&
3425                     ea >= regs->gpr[1] - STACK_INT_FRAME_SIZE) {
3426                         err = handle_stack_update(ea, regs);
3427                         break;
3428                 }
3429                 if (unlikely(cross_endian))
3430                         do_byterev(&op->val, size);
3431                 err = write_mem(op->val, ea, size, regs);
3432                 break;
3433
3434 #ifdef CONFIG_PPC_FPU
3435         case STORE_FP:
3436                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_FP))
3437                         return 0;
3438                 err = do_fp_store(op, ea, regs, cross_endian);
3439                 break;
3440 #endif
3441 #ifdef CONFIG_ALTIVEC
3442         case STORE_VMX:
3443                 if (!(regs->msr & MSR_PR) && !(regs->msr & MSR_VEC))
3444                         return 0;
3445                 err = do_vec_store(op->reg, ea, size, regs, cross_endian);
3446                 break;
3447 #endif
3448 #ifdef CONFIG_VSX
3449         case STORE_VSX: {
3450                 unsigned long msrbit = MSR_VSX;
3451
3452                 /*
3453                  * Some VSX instructions check the MSR_VEC bit rather than MSR_VSX
3454                  * when the target of the instruction is a vector register.
3455                  */
3456                 if (op->reg >= 32 && (op->vsx_flags & VSX_CHECK_VEC))
3457                         msrbit = MSR_VEC;
3458                 if (!(regs->msr & MSR_PR) && !(regs->msr & msrbit))
3459                         return 0;
3460                 err = do_vsx_store(op, ea, regs, cross_endian);
3461                 break;
3462         }
3463 #endif
3464         case STORE_MULTI:
3465                 if (!address_ok(regs, ea, size))
3466                         return -EFAULT;
3467                 rd = op->reg;
3468                 for (i = 0; i < size; i += 4) {
3469                         unsigned int v32 = regs->gpr[rd];
3470
3471                         nb = size - i;
3472                         if (nb > 4)
3473                                 nb = 4;
3474                         if (unlikely(cross_endian))
3475                                 v32 = byterev_4(v32);
3476                         err = copy_mem_out((u8 *) &v32, ea, nb, regs);
3477                         if (err)
3478                                 break;
3479                         ea += 4;
3480                         /* reg number wraps from 31 to 0 for stsw[ix] */
3481                         rd = (rd + 1) & 0x1f;
3482                 }
3483                 break;
3484
3485         default:
3486                 return -EINVAL;
3487         }
3488
3489         if (err)
3490                 return err;
3491
3492         if (op->type & UPDATE)
3493                 regs->gpr[op->update_reg] = op->ea;
3494
3495         return 0;
3496 }
3497 NOKPROBE_SYMBOL(emulate_loadstore);
3498
3499 /*
3500  * Emulate instructions that cause a transfer of control,
3501  * loads and stores, and a few other instructions.
3502  * Returns 1 if the step was emulated, 0 if not,
3503  * or -1 if the instruction is one that should not be stepped,
3504  * such as an rfid, or a mtmsrd that would clear MSR_RI.
3505  */
3506 int emulate_step(struct pt_regs *regs, struct ppc_inst instr)
3507 {
3508         struct instruction_op op;
3509         int r, err, type;
3510         unsigned long val;
3511         unsigned long ea;
3512
3513         r = analyse_instr(&op, regs, instr);
3514         if (r < 0)
3515                 return r;
3516         if (r > 0) {
3517                 emulate_update_regs(regs, &op);
3518                 return 1;
3519         }
3520
3521         err = 0;
3522         type = GETTYPE(op.type);
3523
3524         if (OP_IS_LOAD_STORE(type)) {
3525                 err = emulate_loadstore(regs, &op);
3526                 if (err)
3527                         return 0;
3528                 goto instr_done;
3529         }
3530
3531         switch (type) {
3532         case CACHEOP:
3533                 ea = truncate_if_32bit(regs->msr, op.ea);
3534                 if (!address_ok(regs, ea, 8))
3535                         return 0;
3536                 switch (op.type & CACHEOP_MASK) {
3537                 case DCBST:
3538                         __cacheop_user_asmx(ea, err, "dcbst");
3539                         break;
3540                 case DCBF:
3541                         __cacheop_user_asmx(ea, err, "dcbf");
3542                         break;
3543                 case DCBTST:
3544                         if (op.reg == 0)
3545                                 prefetchw((void *) ea);
3546                         break;
3547                 case DCBT:
3548                         if (op.reg == 0)
3549                                 prefetch((void *) ea);
3550                         break;
3551                 case ICBI:
3552                         __cacheop_user_asmx(ea, err, "icbi");
3553                         break;
3554                 case DCBZ:
3555                         err = emulate_dcbz(ea, regs);
3556                         break;
3557                 }
3558                 if (err) {
3559                         regs->dar = ea;
3560                         return 0;
3561                 }
3562                 goto instr_done;
3563
3564         case MFMSR:
3565                 regs->gpr[op.reg] = regs->msr & MSR_MASK;
3566                 goto instr_done;
3567
3568         case MTMSR:
3569                 val = regs->gpr[op.reg];
3570                 if ((val & MSR_RI) == 0)
3571                         /* can't step mtmsr[d] that would clear MSR_RI */
3572                         return -1;
3573                 /* here op.val is the mask of bits to change */
3574                 regs_set_return_msr(regs, (regs->msr & ~op.val) | (val & op.val));
3575                 goto instr_done;
3576
3577 #ifdef CONFIG_PPC64
3578         case SYSCALL:   /* sc */
3579                 /*
3580                  * N.B. this uses knowledge about how the syscall
3581                  * entry code works.  If that is changed, this will
3582                  * need to be changed also.
3583                  */
3584                 if (IS_ENABLED(CONFIG_PPC_FAST_ENDIAN_SWITCH) &&
3585                                 cpu_has_feature(CPU_FTR_REAL_LE) &&
3586                                 regs->gpr[0] == 0x1ebe) {
3587                         regs_set_return_msr(regs, regs->msr ^ MSR_LE);
3588                         goto instr_done;
3589                 }
3590                 regs->gpr[9] = regs->gpr[13];
3591                 regs->gpr[10] = MSR_KERNEL;
3592                 regs->gpr[11] = regs->nip + 4;
3593                 regs->gpr[12] = regs->msr & MSR_MASK;
3594                 regs->gpr[13] = (unsigned long) get_paca();
3595                 regs_set_return_ip(regs, (unsigned long) &system_call_common);
3596                 regs_set_return_msr(regs, MSR_KERNEL);
3597                 return 1;
3598
3599 #ifdef CONFIG_PPC_BOOK3S_64
3600         case SYSCALL_VECTORED_0:        /* scv 0 */
3601                 regs->gpr[9] = regs->gpr[13];
3602                 regs->gpr[10] = MSR_KERNEL;
3603                 regs->gpr[11] = regs->nip + 4;
3604                 regs->gpr[12] = regs->msr & MSR_MASK;
3605                 regs->gpr[13] = (unsigned long) get_paca();
3606                 regs_set_return_ip(regs, (unsigned long) &system_call_vectored_emulate);
3607                 regs_set_return_msr(regs, MSR_KERNEL);
3608                 return 1;
3609 #endif
3610
3611         case RFI:
3612                 return -1;
3613 #endif
3614         }
3615         return 0;
3616
3617  instr_done:
3618         regs_set_return_ip(regs,
3619                 truncate_if_32bit(regs->msr, regs->nip + GETLENGTH(op.type)));
3620         return 1;
3621 }
3622 NOKPROBE_SYMBOL(emulate_step);