1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright 2008 Michael Ellerman, IBM Corporation.
6 #include <linux/kprobes.h>
7 #include <linux/mmu_context.h>
8 #include <linux/random.h>
9 #include <linux/vmalloc.h>
10 #include <linux/init.h>
11 #include <linux/cpuhotplug.h>
12 #include <linux/uaccess.h>
13 #include <linux/jump_label.h>
15 #include <asm/debug.h>
16 #include <asm/pgalloc.h>
18 #include <asm/tlbflush.h>
20 #include <asm/code-patching.h>
23 static int __patch_instruction(u32 *exec_addr, ppc_inst_t instr, u32 *patch_addr)
25 if (!ppc_inst_prefixed(instr)) {
26 u32 val = ppc_inst_val(instr);
28 __put_kernel_nofault(patch_addr, &val, u32, failed);
30 u64 val = ppc_inst_as_ulong(instr);
32 __put_kernel_nofault(patch_addr, &val, u64, failed);
35 asm ("dcbst 0, %0; sync; icbi 0,%1; sync; isync" :: "r" (patch_addr),
45 int raw_patch_instruction(u32 *addr, ppc_inst_t instr)
47 return __patch_instruction(addr, instr, addr);
50 struct patch_context {
52 struct vm_struct *area;
59 static DEFINE_PER_CPU(struct patch_context, cpu_patching_context);
61 static int map_patch_area(void *addr, unsigned long text_poke_addr);
62 static void unmap_patch_area(unsigned long addr);
64 static bool mm_patch_enabled(void)
66 return IS_ENABLED(CONFIG_SMP) && radix_enabled();
70 * The following applies for Radix MMU. Hash MMU has different requirements,
71 * and so is not supported.
73 * Changing mm requires context synchronising instructions on both sides of
74 * the context switch, as well as a hwsync between the last instruction for
75 * which the address of an associated storage access was translated using
76 * the current context.
78 * switch_mm_irqs_off() performs an isync after the context switch. It is
79 * the responsibility of the caller to perform the CSI and hwsync before
80 * starting/stopping the temp mm.
82 static struct mm_struct *start_using_temp_mm(struct mm_struct *temp_mm)
84 struct mm_struct *orig_mm = current->active_mm;
86 lockdep_assert_irqs_disabled();
87 switch_mm_irqs_off(orig_mm, temp_mm, current);
89 WARN_ON(!mm_is_thread_local(temp_mm));
91 suspend_breakpoints();
95 static void stop_using_temp_mm(struct mm_struct *temp_mm,
96 struct mm_struct *orig_mm)
98 lockdep_assert_irqs_disabled();
99 switch_mm_irqs_off(temp_mm, orig_mm, current);
100 restore_breakpoints();
103 static int text_area_cpu_up(unsigned int cpu)
105 struct vm_struct *area;
109 area = get_vm_area(PAGE_SIZE, VM_ALLOC);
111 WARN_ONCE(1, "Failed to create text area for cpu %d\n",
116 // Map/unmap the area to ensure all page tables are pre-allocated
117 addr = (unsigned long)area->addr;
118 err = map_patch_area(empty_zero_page, addr);
122 unmap_patch_area(addr);
124 this_cpu_write(cpu_patching_context.area, area);
125 this_cpu_write(cpu_patching_context.addr, addr);
126 this_cpu_write(cpu_patching_context.pte, virt_to_kpte(addr));
131 static int text_area_cpu_down(unsigned int cpu)
133 free_vm_area(this_cpu_read(cpu_patching_context.area));
134 this_cpu_write(cpu_patching_context.area, NULL);
135 this_cpu_write(cpu_patching_context.addr, 0);
136 this_cpu_write(cpu_patching_context.pte, NULL);
140 static void put_patching_mm(struct mm_struct *mm, unsigned long patching_addr)
142 struct mmu_gather tlb;
144 tlb_gather_mmu(&tlb, mm);
145 free_pgd_range(&tlb, patching_addr, patching_addr + PAGE_SIZE, 0, 0);
149 static int text_area_cpu_up_mm(unsigned int cpu)
151 struct mm_struct *mm;
161 * Choose a random page-aligned address from the interval
162 * [PAGE_SIZE .. DEFAULT_MAP_WINDOW - PAGE_SIZE].
163 * The lower address bound is PAGE_SIZE to avoid the zero-page.
165 addr = (1 + (get_random_long() % (DEFAULT_MAP_WINDOW / PAGE_SIZE - 2))) << PAGE_SHIFT;
168 * PTE allocation uses GFP_KERNEL which means we need to
169 * pre-allocate the PTE here because we cannot do the
170 * allocation during patching when IRQs are disabled.
172 * Using get_locked_pte() to avoid open coding, the lock
175 pte = get_locked_pte(mm, addr, &ptl);
178 pte_unmap_unlock(pte, ptl);
180 this_cpu_write(cpu_patching_context.mm, mm);
181 this_cpu_write(cpu_patching_context.addr, addr);
186 put_patching_mm(mm, addr);
191 static int text_area_cpu_down_mm(unsigned int cpu)
193 put_patching_mm(this_cpu_read(cpu_patching_context.mm),
194 this_cpu_read(cpu_patching_context.addr));
196 this_cpu_write(cpu_patching_context.mm, NULL);
197 this_cpu_write(cpu_patching_context.addr, 0);
202 static __ro_after_init DEFINE_STATIC_KEY_FALSE(poking_init_done);
204 void __init poking_init(void)
208 if (mm_patch_enabled())
209 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
210 "powerpc/text_poke_mm:online",
212 text_area_cpu_down_mm);
214 ret = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN,
215 "powerpc/text_poke:online",
219 /* cpuhp_setup_state returns >= 0 on success */
220 if (WARN_ON(ret < 0))
223 static_branch_enable(&poking_init_done);
226 static unsigned long get_patch_pfn(void *addr)
228 if (IS_ENABLED(CONFIG_MODULES) && is_vmalloc_or_module_addr(addr))
229 return vmalloc_to_pfn(addr);
231 return __pa_symbol(addr) >> PAGE_SHIFT;
235 * This can be called for kernel text or a module.
237 static int map_patch_area(void *addr, unsigned long text_poke_addr)
239 unsigned long pfn = get_patch_pfn(addr);
241 return map_kernel_page(text_poke_addr, (pfn << PAGE_SHIFT), PAGE_KERNEL);
244 static void unmap_patch_area(unsigned long addr)
252 pgdp = pgd_offset_k(addr);
253 if (WARN_ON(pgd_none(*pgdp)))
256 p4dp = p4d_offset(pgdp, addr);
257 if (WARN_ON(p4d_none(*p4dp)))
260 pudp = pud_offset(p4dp, addr);
261 if (WARN_ON(pud_none(*pudp)))
264 pmdp = pmd_offset(pudp, addr);
265 if (WARN_ON(pmd_none(*pmdp)))
268 ptep = pte_offset_kernel(pmdp, addr);
269 if (WARN_ON(pte_none(*ptep)))
273 * In hash, pte_clear flushes the tlb, in radix, we have to
275 pte_clear(&init_mm, addr, ptep);
276 flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
279 static int __do_patch_instruction_mm(u32 *addr, ppc_inst_t instr)
283 unsigned long text_poke_addr;
285 unsigned long pfn = get_patch_pfn(addr);
286 struct mm_struct *patching_mm;
287 struct mm_struct *orig_mm;
290 patching_mm = __this_cpu_read(cpu_patching_context.mm);
291 text_poke_addr = __this_cpu_read(cpu_patching_context.addr);
292 patch_addr = (u32 *)(text_poke_addr + offset_in_page(addr));
294 pte = get_locked_pte(patching_mm, text_poke_addr, &ptl);
298 __set_pte_at(patching_mm, text_poke_addr, pte, pfn_pte(pfn, PAGE_KERNEL), 0);
300 /* order PTE update before use, also serves as the hwsync */
301 asm volatile("ptesync": : :"memory");
303 /* order context switch after arbitrary prior code */
306 orig_mm = start_using_temp_mm(patching_mm);
308 err = __patch_instruction(addr, instr, patch_addr);
310 /* context synchronisation performed by __patch_instruction (isync or exception) */
311 stop_using_temp_mm(patching_mm, orig_mm);
313 pte_clear(patching_mm, text_poke_addr, pte);
315 * ptesync to order PTE update before TLB invalidation done
316 * by radix__local_flush_tlb_page_psize (in _tlbiel_va)
318 local_flush_tlb_page_psize(patching_mm, text_poke_addr, mmu_virtual_psize);
320 pte_unmap_unlock(pte, ptl);
325 static int __do_patch_instruction(u32 *addr, ppc_inst_t instr)
329 unsigned long text_poke_addr;
331 unsigned long pfn = get_patch_pfn(addr);
333 text_poke_addr = (unsigned long)__this_cpu_read(cpu_patching_context.addr) & PAGE_MASK;
334 patch_addr = (u32 *)(text_poke_addr + offset_in_page(addr));
336 pte = __this_cpu_read(cpu_patching_context.pte);
337 __set_pte_at(&init_mm, text_poke_addr, pte, pfn_pte(pfn, PAGE_KERNEL), 0);
338 /* See ptesync comment in radix__set_pte_at() */
340 asm volatile("ptesync": : :"memory");
342 err = __patch_instruction(addr, instr, patch_addr);
344 pte_clear(&init_mm, text_poke_addr, pte);
345 flush_tlb_kernel_range(text_poke_addr, text_poke_addr + PAGE_SIZE);
350 int patch_instruction(u32 *addr, ppc_inst_t instr)
356 * During early early boot patch_instruction is called
357 * when text_poke_area is not ready, but we still need
358 * to allow patching. We just do the plain old patching
360 if (!IS_ENABLED(CONFIG_STRICT_KERNEL_RWX) ||
361 !static_branch_likely(&poking_init_done))
362 return raw_patch_instruction(addr, instr);
364 local_irq_save(flags);
365 if (mm_patch_enabled())
366 err = __do_patch_instruction_mm(addr, instr);
368 err = __do_patch_instruction(addr, instr);
369 local_irq_restore(flags);
373 NOKPROBE_SYMBOL(patch_instruction);
375 static int __patch_instructions(u32 *patch_addr, u32 *code, size_t len, bool repeat_instr)
377 unsigned long start = (unsigned long)patch_addr;
379 /* Repeat instruction */
381 ppc_inst_t instr = ppc_inst_read(code);
383 if (ppc_inst_prefixed(instr)) {
384 u64 val = ppc_inst_as_ulong(instr);
386 memset64((u64 *)patch_addr, val, len / 8);
388 u32 val = ppc_inst_val(instr);
390 memset32(patch_addr, val, len / 4);
393 memcpy(patch_addr, code, len);
396 smp_wmb(); /* smp write barrier */
397 flush_icache_range(start, start + len);
402 * A page is mapped and instructions that fit the page are patched.
403 * Assumes 'len' to be (PAGE_SIZE - offset_in_page(addr)) or below.
405 static int __do_patch_instructions_mm(u32 *addr, u32 *code, size_t len, bool repeat_instr)
407 struct mm_struct *patching_mm, *orig_mm;
408 unsigned long pfn = get_patch_pfn(addr);
409 unsigned long text_poke_addr;
415 patching_mm = __this_cpu_read(cpu_patching_context.mm);
416 text_poke_addr = __this_cpu_read(cpu_patching_context.addr);
417 patch_addr = (u32 *)(text_poke_addr + offset_in_page(addr));
419 pte = get_locked_pte(patching_mm, text_poke_addr, &ptl);
423 __set_pte_at(patching_mm, text_poke_addr, pte, pfn_pte(pfn, PAGE_KERNEL), 0);
425 /* order PTE update before use, also serves as the hwsync */
426 asm volatile("ptesync" ::: "memory");
428 /* order context switch after arbitrary prior code */
431 orig_mm = start_using_temp_mm(patching_mm);
433 err = __patch_instructions(patch_addr, code, len, repeat_instr);
435 /* context synchronisation performed by __patch_instructions */
436 stop_using_temp_mm(patching_mm, orig_mm);
438 pte_clear(patching_mm, text_poke_addr, pte);
440 * ptesync to order PTE update before TLB invalidation done
441 * by radix__local_flush_tlb_page_psize (in _tlbiel_va)
443 local_flush_tlb_page_psize(patching_mm, text_poke_addr, mmu_virtual_psize);
445 pte_unmap_unlock(pte, ptl);
451 * A page is mapped and instructions that fit the page are patched.
452 * Assumes 'len' to be (PAGE_SIZE - offset_in_page(addr)) or below.
454 static int __do_patch_instructions(u32 *addr, u32 *code, size_t len, bool repeat_instr)
456 unsigned long pfn = get_patch_pfn(addr);
457 unsigned long text_poke_addr;
462 text_poke_addr = (unsigned long)__this_cpu_read(cpu_patching_context.addr) & PAGE_MASK;
463 patch_addr = (u32 *)(text_poke_addr + offset_in_page(addr));
465 pte = __this_cpu_read(cpu_patching_context.pte);
466 __set_pte_at(&init_mm, text_poke_addr, pte, pfn_pte(pfn, PAGE_KERNEL), 0);
467 /* See ptesync comment in radix__set_pte_at() */
469 asm volatile("ptesync" ::: "memory");
471 err = __patch_instructions(patch_addr, code, len, repeat_instr);
473 pte_clear(&init_mm, text_poke_addr, pte);
474 flush_tlb_kernel_range(text_poke_addr, text_poke_addr + PAGE_SIZE);
480 * Patch 'addr' with 'len' bytes of instructions from 'code'.
482 * If repeat_instr is true, the same instruction is filled for
485 int patch_instructions(u32 *addr, u32 *code, size_t len, bool repeat_instr)
492 plen = min_t(size_t, PAGE_SIZE - offset_in_page(addr), len);
494 local_irq_save(flags);
495 if (mm_patch_enabled())
496 err = __do_patch_instructions_mm(addr, code, plen, repeat_instr);
498 err = __do_patch_instructions(addr, code, plen, repeat_instr);
499 local_irq_restore(flags);
504 addr = (u32 *)((unsigned long)addr + plen);
506 code = (u32 *)((unsigned long)code + plen);
511 NOKPROBE_SYMBOL(patch_instructions);
513 int patch_branch(u32 *addr, unsigned long target, int flags)
517 if (create_branch(&instr, addr, target, flags))
520 return patch_instruction(addr, instr);
524 * Helper to check if a given instruction is a conditional branch
525 * Derived from the conditional checks in analyse_instr()
527 bool is_conditional_branch(ppc_inst_t instr)
529 unsigned int opcode = ppc_inst_primary_opcode(instr);
531 if (opcode == 16) /* bc, bca, bcl, bcla */
534 switch ((ppc_inst_val(instr) >> 1) & 0x3ff) {
535 case 16: /* bclr, bclrl */
536 case 528: /* bcctr, bcctrl */
537 case 560: /* bctar, bctarl */
543 NOKPROBE_SYMBOL(is_conditional_branch);
545 int create_cond_branch(ppc_inst_t *instr, const u32 *addr,
546 unsigned long target, int flags)
551 if (! (flags & BRANCH_ABSOLUTE))
552 offset = offset - (unsigned long)addr;
554 /* Check we can represent the target in the instruction format */
555 if (!is_offset_in_cond_branch_range(offset))
558 /* Mask out the flags and target, so they don't step on each other. */
559 *instr = ppc_inst(0x40000000 | (flags & 0x3FF0003) | (offset & 0xFFFC));
564 int instr_is_relative_branch(ppc_inst_t instr)
566 if (ppc_inst_val(instr) & BRANCH_ABSOLUTE)
569 return instr_is_branch_iform(instr) || instr_is_branch_bform(instr);
572 int instr_is_relative_link_branch(ppc_inst_t instr)
574 return instr_is_relative_branch(instr) && (ppc_inst_val(instr) & BRANCH_SET_LINK);
577 static unsigned long branch_iform_target(const u32 *instr)
581 imm = ppc_inst_val(ppc_inst_read(instr)) & 0x3FFFFFC;
583 /* If the top bit of the immediate value is set this is negative */
587 if ((ppc_inst_val(ppc_inst_read(instr)) & BRANCH_ABSOLUTE) == 0)
588 imm += (unsigned long)instr;
590 return (unsigned long)imm;
593 static unsigned long branch_bform_target(const u32 *instr)
597 imm = ppc_inst_val(ppc_inst_read(instr)) & 0xFFFC;
599 /* If the top bit of the immediate value is set this is negative */
603 if ((ppc_inst_val(ppc_inst_read(instr)) & BRANCH_ABSOLUTE) == 0)
604 imm += (unsigned long)instr;
606 return (unsigned long)imm;
609 unsigned long branch_target(const u32 *instr)
611 if (instr_is_branch_iform(ppc_inst_read(instr)))
612 return branch_iform_target(instr);
613 else if (instr_is_branch_bform(ppc_inst_read(instr)))
614 return branch_bform_target(instr);
619 int translate_branch(ppc_inst_t *instr, const u32 *dest, const u32 *src)
621 unsigned long target;
622 target = branch_target(src);
624 if (instr_is_branch_iform(ppc_inst_read(src)))
625 return create_branch(instr, dest, target,
626 ppc_inst_val(ppc_inst_read(src)));
627 else if (instr_is_branch_bform(ppc_inst_read(src)))
628 return create_cond_branch(instr, dest, target,
629 ppc_inst_val(ppc_inst_read(src)));