2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License, version 2, as
4 * published by the Free Software Foundation.
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
11 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
13 * Derived from book3s_rmhandlers.S and other files, which are:
15 * Copyright SUSE Linux Products GmbH 2009
17 * Authors: Alexander Graf <agraf@suse.de>
20 #include <asm/ppc_asm.h>
21 #include <asm/code-patching-asm.h>
22 #include <asm/kvm_asm.h>
26 #include <asm/ptrace.h>
27 #include <asm/hvcall.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/exception-64s.h>
30 #include <asm/kvm_book3s_asm.h>
31 #include <asm/book3s/64/mmu-hash.h>
35 #define VCPU_GPRS_TM(reg) (((reg) * ULONG_SIZE) + VCPU_GPR_TM)
37 /* Values in HSTATE_NAPPING(r13) */
38 #define NAPPING_CEDE 1
39 #define NAPPING_NOVCPU 2
41 /* Stack frame offsets for kvmppc_hv_entry */
43 #define STACK_SLOT_TRAP (SFS-4)
44 #define STACK_SLOT_CIABR (SFS-16)
45 #define STACK_SLOT_DAWR (SFS-24)
46 #define STACK_SLOT_DAWRX (SFS-32)
49 * Call kvmppc_hv_entry in real mode.
50 * Must be called with interrupts hard-disabled.
54 * LR = return address to continue at after eventually re-enabling MMU
56 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
58 std r0, PPC_LR_STKOFF(r1)
61 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
66 mtmsrd r0,1 /* clear RI in MSR */
72 ld r4, HSTATE_KVM_VCPU(r13)
75 /* Back from guest - restore host state and return to caller */
78 /* Restore host DABR and DABRX */
79 ld r5,HSTATE_DABR(r13)
83 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
86 ld r3,PACA_SPRG_VDSO(r13)
87 mtspr SPRN_SPRG_VDSO_WRITE,r3
89 /* Reload the host's PMU registers */
90 ld r3, PACALPPACAPTR(r13) /* is the host using the PMU? */
91 lbz r4, LPPACA_PMCINUSE(r3)
93 beq 23f /* skip if not */
95 ld r3, HSTATE_MMCR0(r13)
96 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
99 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
100 lwz r3, HSTATE_PMC1(r13)
101 lwz r4, HSTATE_PMC2(r13)
102 lwz r5, HSTATE_PMC3(r13)
103 lwz r6, HSTATE_PMC4(r13)
104 lwz r8, HSTATE_PMC5(r13)
105 lwz r9, HSTATE_PMC6(r13)
112 ld r3, HSTATE_MMCR0(r13)
113 ld r4, HSTATE_MMCR1(r13)
114 ld r5, HSTATE_MMCRA(r13)
115 ld r6, HSTATE_SIAR(r13)
116 ld r7, HSTATE_SDAR(r13)
122 ld r8, HSTATE_MMCR2(r13)
123 ld r9, HSTATE_SIER(r13)
126 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
132 * Reload DEC. HDEC interrupts were disabled when
133 * we reloaded the host's LPCR value.
135 ld r3, HSTATE_DECEXP(r13)
140 /* hwthread_req may have got set by cede or no vcpu, so clear it */
142 stb r0, HSTATE_HWTHREAD_REQ(r13)
145 * For external and machine check interrupts, we need
146 * to call the Linux handler to process the interrupt.
147 * We do that by jumping to absolute address 0x500 for
148 * external interrupts, or the machine_check_fwnmi label
149 * for machine checks (since firmware might have patched
150 * the vector area at 0x200). The [h]rfid at the end of the
151 * handler will return to the book3s_hv_interrupts.S code.
152 * For other interrupts we do the rfid to get back
153 * to the book3s_hv_interrupts.S code here.
155 ld r8, 112+PPC_LR_STKOFF(r1)
157 ld r7, HSTATE_HOST_MSR(r13)
159 cmpwi cr1, r12, BOOK3S_INTERRUPT_MACHINE_CHECK
160 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
162 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
163 beq 15f /* Invoke the H_DOORBELL handler */
164 cmpwi cr2, r12, BOOK3S_INTERRUPT_HMI
165 beq cr2, 14f /* HMI check */
167 /* RFI into the highmem handler, or branch to interrupt handler */
171 mtmsrd r6, 1 /* Clear RI in MSR */
174 beq cr1, 13f /* machine check */
177 /* On POWER7, we have external interrupts set to use HSRR0/1 */
178 11: mtspr SPRN_HSRR0, r8
182 13: b machine_check_fwnmi
184 14: mtspr SPRN_HSRR0, r8
186 b hmi_exception_after_realmode
188 15: mtspr SPRN_HSRR0, r8
192 kvmppc_primary_no_guest:
193 /* We handle this much like a ceded vcpu */
194 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
198 * Make sure the primary has finished the MMU switch.
199 * We should never get here on a secondary thread, but
200 * check it for robustness' sake.
202 ld r5, HSTATE_KVM_VCORE(r13)
203 65: lbz r0, VCORE_IN_GUEST(r5)
210 /* set our bit in napping_threads */
211 ld r5, HSTATE_KVM_VCORE(r13)
212 lbz r7, HSTATE_PTID(r13)
215 addi r6, r5, VCORE_NAPPING_THREADS
220 /* order napping_threads update vs testing entry_exit_map */
223 lwz r7, VCORE_ENTRY_EXIT(r5)
225 bge kvm_novcpu_exit /* another thread already exiting */
226 li r3, NAPPING_NOVCPU
227 stb r3, HSTATE_NAPPING(r13)
229 li r3, 0 /* Don't wake on privileged (OS) doorbell */
234 * Entered from kvm_start_guest if kvm_hstate.napping is set
240 ld r1, HSTATE_HOST_R1(r13)
241 ld r5, HSTATE_KVM_VCORE(r13)
243 stb r0, HSTATE_NAPPING(r13)
245 /* check the wake reason */
246 bl kvmppc_check_wake_reason
249 * Restore volatile registers since we could have called
250 * a C routine in kvmppc_check_wake_reason.
253 ld r5, HSTATE_KVM_VCORE(r13)
255 /* see if any other thread is already exiting */
256 lwz r0, VCORE_ENTRY_EXIT(r5)
260 /* clear our bit in napping_threads */
261 lbz r7, HSTATE_PTID(r13)
264 addi r6, r5, VCORE_NAPPING_THREADS
270 /* See if the wake reason means we need to exit */
274 /* See if our timeslice has expired (HDEC is negative) */
276 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
280 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
281 ld r4, HSTATE_KVM_VCPU(r13)
283 beq kvmppc_primary_no_guest
285 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
286 addi r3, r4, VCPU_TB_RMENTRY
287 bl kvmhv_start_timing
292 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
293 ld r4, HSTATE_KVM_VCPU(r13)
296 addi r3, r4, VCPU_TB_RMEXIT
297 bl kvmhv_accumulate_time
300 stw r12, STACK_SLOT_TRAP(r1)
301 bl kvmhv_commence_exit
303 b kvmhv_switch_to_host
306 * We come in here when wakened from nap mode.
307 * Relocation is off and most register values are lost.
308 * r13 points to the PACA.
310 .globl kvm_start_guest
313 /* Set runlatch bit the minute you wake up from nap */
320 li r0,KVM_HWTHREAD_IN_KVM
321 stb r0,HSTATE_HWTHREAD_STATE(r13)
323 /* NV GPR values from power7_idle() will no longer be valid */
325 stb r0,PACA_NAPSTATELOST(r13)
327 /* were we napping due to cede? */
328 lbz r0,HSTATE_NAPPING(r13)
329 cmpwi r0,NAPPING_CEDE
331 cmpwi r0,NAPPING_NOVCPU
332 beq kvm_novcpu_wakeup
334 ld r1,PACAEMERGSP(r13)
335 subi r1,r1,STACK_FRAME_OVERHEAD
338 * We weren't napping due to cede, so this must be a secondary
339 * thread being woken up to run a guest, or being woken up due
340 * to a stray IPI. (Or due to some machine check or hypervisor
341 * maintenance interrupt while the core is in KVM.)
344 /* Check the wake reason in SRR1 to see why we got here */
345 bl kvmppc_check_wake_reason
347 * kvmppc_check_wake_reason could invoke a C routine, but we
348 * have no volatile registers to restore when we return.
354 /* get vcore pointer, NULL if we have nothing to run */
355 ld r5,HSTATE_KVM_VCORE(r13)
357 /* if we have no vcore to run, go back to sleep */
360 kvm_secondary_got_guest:
362 /* Set HSTATE_DSCR(r13) to something sensible */
363 ld r6, PACA_DSCR_DEFAULT(r13)
364 std r6, HSTATE_DSCR(r13)
366 /* On thread 0 of a subcore, set HDEC to max */
367 lbz r4, HSTATE_PTID(r13)
373 /* and set per-LPAR registers, if doing dynamic micro-threading */
374 ld r6, HSTATE_SPLIT_MODE(r13)
377 ld r0, KVM_SPLIT_RPR(r6)
379 ld r0, KVM_SPLIT_PMMAR(r6)
381 ld r0, KVM_SPLIT_LDBAR(r6)
385 /* Order load of vcpu after load of vcore */
387 ld r4, HSTATE_KVM_VCPU(r13)
390 /* Back from the guest, go back to nap */
391 /* Clear our vcpu and vcore pointers so we don't come back in early */
393 std r0, HSTATE_KVM_VCPU(r13)
395 * Once we clear HSTATE_KVM_VCORE(r13), the code in
396 * kvmppc_run_core() is going to assume that all our vcpu
397 * state is visible in memory. This lwsync makes sure
401 std r0, HSTATE_KVM_VCORE(r13)
404 * All secondaries exiting guest will fall through this path.
405 * Before proceeding, just check for HMI interrupt and
406 * invoke opal hmi handler. By now we are sure that the
407 * primary thread on this core/subcore has already made partition
408 * switch/TB resync and we are good to call opal hmi handler.
410 cmpwi r12, BOOK3S_INTERRUPT_HMI
413 li r3,0 /* NULL argument */
414 bl hmi_exception_realmode
416 * At this point we have finished executing in the guest.
417 * We need to wait for hwthread_req to become zero, since
418 * we may not turn on the MMU while hwthread_req is non-zero.
419 * While waiting we also need to check if we get given a vcpu to run.
422 lbz r3, HSTATE_HWTHREAD_REQ(r13)
426 li r0, KVM_HWTHREAD_IN_KERNEL
427 stb r0, HSTATE_HWTHREAD_STATE(r13)
428 /* need to recheck hwthread_req after a barrier, to avoid race */
430 lbz r3, HSTATE_HWTHREAD_REQ(r13)
434 * We jump to pnv_wakeup_loss, which will return to the caller
435 * of power7_nap in the powernv cpu offline loop. The value we
436 * put in r3 becomes the return value for power7_nap.
440 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
446 ld r5, HSTATE_KVM_VCORE(r13)
449 ld r3, HSTATE_SPLIT_MODE(r13)
452 lbz r0, KVM_SPLIT_DO_NAP(r3)
458 b kvm_secondary_got_guest
460 54: li r0, KVM_HWTHREAD_IN_KVM
461 stb r0, HSTATE_HWTHREAD_STATE(r13)
465 * Here the primary thread is trying to return the core to
466 * whole-core mode, so we need to nap.
470 * When secondaries are napping in kvm_unsplit_nap() with
471 * hwthread_req = 1, HMI goes ignored even though subcores are
472 * already exited the guest. Hence HMI keeps waking up secondaries
473 * from nap in a loop and secondaries always go back to nap since
474 * no vcore is assigned to them. This makes impossible for primary
475 * thread to get hold of secondary threads resulting into a soft
476 * lockup in KVM path.
478 * Let us check if HMI is pending and handle it before we go to nap.
480 cmpwi r12, BOOK3S_INTERRUPT_HMI
482 li r3, 0 /* NULL argument */
483 bl hmi_exception_realmode
486 * Ensure that secondary doesn't nap when it has
487 * its vcore pointer set.
489 sync /* matches smp_mb() before setting split_info.do_nap */
490 ld r0, HSTATE_KVM_VCORE(r13)
493 /* clear any pending message */
495 lis r6, (PPC_DBELL_SERVER << (63-36))@h
497 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
498 /* Set kvm_split_mode.napped[tid] = 1 */
499 ld r3, HSTATE_SPLIT_MODE(r13)
501 lhz r4, PACAPACAINDEX(r13)
502 clrldi r4, r4, 61 /* micro-threading => P8 => 8 threads/core */
503 addi r4, r4, KVM_SPLIT_NAPPED
505 /* Check the do_nap flag again after setting napped[] */
507 lbz r0, KVM_SPLIT_DO_NAP(r3)
510 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
512 rlwimi r4, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
515 std r0, HSTATE_SCRATCH0(r13)
517 ld r0, HSTATE_SCRATCH0(r13)
527 /******************************************************************************
531 *****************************************************************************/
533 .global kvmppc_hv_entry
538 * R4 = vcpu pointer (or NULL)
543 * all other volatile GPRS = free
546 std r0, PPC_LR_STKOFF(r1)
549 /* Save R1 in the PACA */
550 std r1, HSTATE_HOST_R1(r13)
552 li r6, KVM_GUEST_MODE_HOST_HV
553 stb r6, HSTATE_IN_GUEST(r13)
555 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
556 /* Store initial timestamp */
559 addi r3, r4, VCPU_TB_RMENTRY
560 bl kvmhv_start_timing
570 * POWER7/POWER8 host -> guest partition switch code.
571 * We don't have to lock against concurrent tlbies,
572 * but we do have to coordinate across hardware threads.
574 /* Set bit in entry map iff exit map is zero. */
575 ld r5, HSTATE_KVM_VCORE(r13)
577 lbz r6, HSTATE_PTID(r13)
579 addi r9, r5, VCORE_ENTRY_EXIT
581 cmpwi r3, 0x100 /* any threads starting to exit? */
582 bge secondary_too_late /* if so we're too late to the party */
587 /* Primary thread switches to guest partition. */
588 ld r9,VCORE_KVM(r5) /* pointer to struct kvm */
593 li r0,LPID_RSVD /* switch to reserved LPID */
596 mtspr SPRN_SDR1,r6 /* switch to partition page table */
600 /* See if we need to flush the TLB */
601 lhz r6,PACAPACAINDEX(r13) /* test_bit(cpu, need_tlb_flush) */
602 clrldi r7,r6,64-6 /* extract bit number (6 bits) */
603 srdi r6,r6,6 /* doubleword number */
604 sldi r6,r6,3 /* address offset */
606 addi r6,r6,KVM_NEED_FLUSH /* dword in kvm->arch.need_tlb_flush */
612 23: ldarx r7,0,r6 /* if set, clear the bit */
616 /* Flush the TLB of any entries for this LPID */
617 /* use arch 2.07S as a proxy for POWER8 */
619 li r6,512 /* POWER8 has 512 sets */
621 li r6,128 /* POWER7 has 128 sets */
622 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
624 li r7,0x800 /* IS field = 0b10 */
631 /* Add timebase offset onto timebase */
632 22: ld r8,VCORE_TB_OFFSET(r5)
635 mftb r6 /* current host timebase */
637 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
638 mftb r7 /* check if lower 24 bits overflowed */
643 addis r8,r8,0x100 /* if so, increment upper 40 bits */
646 /* Load guest PCR value to select appropriate compat mode */
647 37: ld r7, VCORE_PCR(r5)
654 /* DPDES and VTB are shared between threads */
655 ld r8, VCORE_DPDES(r5)
659 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
661 /* Mark the subcore state as inside guest */
662 bl kvmppc_subcore_enter_guest
664 ld r5, HSTATE_KVM_VCORE(r13)
665 ld r4, HSTATE_KVM_VCPU(r13)
667 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
669 /* Do we have a guest vcpu to run? */
671 beq kvmppc_primary_no_guest
674 /* Load up guest SLB entries */
675 lwz r5,VCPU_SLB_MAX(r4)
680 1: ld r8,VCPU_SLB_E(r6)
683 addi r6,r6,VCPU_SLB_SIZE
686 /* Increment yield count if they have a VPA */
690 li r6, LPPACA_YIELDCOUNT
695 stb r6, VCPU_VPA_DIRTY(r4)
698 /* Save purr/spurr */
701 std r5,HSTATE_PURR(r13)
702 std r6,HSTATE_SPURR(r13)
708 /* Save host values of some registers */
713 std r5, STACK_SLOT_CIABR(r1)
714 std r6, STACK_SLOT_DAWR(r1)
715 std r7, STACK_SLOT_DAWRX(r1)
716 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
719 /* Set partition DABR */
720 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
721 lwz r5,VCPU_DABRX(r4)
726 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
728 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
731 END_FTR_SECTION_IFSET(CPU_FTR_TM)
734 /* Load guest PMU registers */
735 /* R4 is live here (vcpu pointer) */
737 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
738 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
742 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
745 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
746 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
747 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
748 lwz r6, VCPU_PMC + 8(r4)
749 lwz r7, VCPU_PMC + 12(r4)
750 lwz r8, VCPU_PMC + 16(r4)
751 lwz r9, VCPU_PMC + 20(r4)
759 ld r5, VCPU_MMCR + 8(r4)
760 ld r6, VCPU_MMCR + 16(r4)
768 ld r5, VCPU_MMCR + 24(r4)
770 lwz r7, VCPU_PMC + 24(r4)
771 lwz r8, VCPU_PMC + 28(r4)
772 ld r9, VCPU_MMCR + 32(r4)
778 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
782 /* Load up FP, VMX and VSX registers */
785 ld r14, VCPU_GPR(R14)(r4)
786 ld r15, VCPU_GPR(R15)(r4)
787 ld r16, VCPU_GPR(R16)(r4)
788 ld r17, VCPU_GPR(R17)(r4)
789 ld r18, VCPU_GPR(R18)(r4)
790 ld r19, VCPU_GPR(R19)(r4)
791 ld r20, VCPU_GPR(R20)(r4)
792 ld r21, VCPU_GPR(R21)(r4)
793 ld r22, VCPU_GPR(R22)(r4)
794 ld r23, VCPU_GPR(R23)(r4)
795 ld r24, VCPU_GPR(R24)(r4)
796 ld r25, VCPU_GPR(R25)(r4)
797 ld r26, VCPU_GPR(R26)(r4)
798 ld r27, VCPU_GPR(R27)(r4)
799 ld r28, VCPU_GPR(R28)(r4)
800 ld r29, VCPU_GPR(R29)(r4)
801 ld r30, VCPU_GPR(R30)(r4)
802 ld r31, VCPU_GPR(R31)(r4)
804 /* Switch DSCR to guest value */
809 /* Skip next section on POWER7 */
811 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
812 /* Load up POWER8-specific registers */
814 lwz r6, VCPU_PSPB(r4)
820 ld r6, VCPU_DAWRX(r4)
821 ld r7, VCPU_CIABR(r4)
828 ld r8, VCPU_EBBHR(r4)
831 ld r5, VCPU_EBBRR(r4)
832 ld r6, VCPU_BESCR(r4)
833 ld r7, VCPU_CSIGR(r4)
839 ld r5, VCPU_TCSCR(r4)
841 lwz r7, VCPU_GUEST_PID(r4)
850 * Set the decrementer to the guest decrementer.
852 ld r8,VCPU_DEC_EXPIRES(r4)
853 /* r8 is a host timebase value here, convert to guest TB */
854 ld r5,HSTATE_KVM_VCORE(r13)
855 ld r6,VCORE_TB_OFFSET(r5)
862 ld r5, VCPU_SPRG0(r4)
863 ld r6, VCPU_SPRG1(r4)
864 ld r7, VCPU_SPRG2(r4)
865 ld r8, VCPU_SPRG3(r4)
871 /* Load up DAR and DSISR */
873 lwz r6, VCPU_DSISR(r4)
877 /* Restore AMR and UAMOR, set AMOR to all 1s */
885 /* Restore state of CTRL run bit; assume 1 on entry */
893 /* Secondary threads wait for primary to have done partition switch */
894 ld r5, HSTATE_KVM_VCORE(r13)
895 lbz r6, HSTATE_PTID(r13)
898 lbz r0, VCORE_IN_GUEST(r5)
902 20: lwz r3, VCORE_ENTRY_EXIT(r5)
905 lbz r0, VCORE_IN_GUEST(r5)
915 /* Check if HDEC expires soon */
917 cmpwi r3, 512 /* 1 microsecond */
920 deliver_guest_interrupt:
927 kvmppc_cede_reentry: /* r4 = vcpu, r13 = paca */
935 /* r11 = vcpu->arch.msr & ~MSR_HV */
936 rldicl r11, r11, 63 - MSR_HV_LG, 1
937 rotldi r11, r11, 1 + MSR_HV_LG
940 /* Check if we can deliver an external or decrementer interrupt now */
941 ld r0, VCPU_PENDING_EXC(r4)
942 rldicl r0, r0, 64 - BOOK3S_IRQPRIO_EXTERNAL_LEVEL, 63
944 andi. r8, r11, MSR_EE
946 /* Insert EXTERNAL_LEVEL bit into LPCR at the MER bit position */
947 rldimi r8, r0, LPCR_MER_SH, 63 - LPCR_MER_SH
951 li r0, BOOK3S_INTERRUPT_EXTERNAL
955 li r0, BOOK3S_INTERRUPT_DECREMENTER
958 12: mtspr SPRN_SRR0, r10
962 bl kvmppc_msr_interrupt
968 * R10: value for HSRR0
969 * R11: value for HSRR1
974 stb r0,VCPU_CEDED(r4) /* cancel cede */
978 /* Activate guest mode, so faults get handled by KVM */
979 li r9, KVM_GUEST_MODE_GUEST_HV
980 stb r9, HSTATE_IN_GUEST(r13)
982 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
983 /* Accumulate timing */
984 addi r3, r4, VCPU_TB_GUEST
985 bl kvmhv_accumulate_time
993 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
996 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1003 ld r1, VCPU_GPR(R1)(r4)
1004 ld r2, VCPU_GPR(R2)(r4)
1005 ld r3, VCPU_GPR(R3)(r4)
1006 ld r5, VCPU_GPR(R5)(r4)
1007 ld r6, VCPU_GPR(R6)(r4)
1008 ld r7, VCPU_GPR(R7)(r4)
1009 ld r8, VCPU_GPR(R8)(r4)
1010 ld r9, VCPU_GPR(R9)(r4)
1011 ld r10, VCPU_GPR(R10)(r4)
1012 ld r11, VCPU_GPR(R11)(r4)
1013 ld r12, VCPU_GPR(R12)(r4)
1014 ld r13, VCPU_GPR(R13)(r4)
1018 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1019 ld r0, VCPU_GPR(R0)(r4)
1020 ld r4, VCPU_GPR(R4)(r4)
1026 stw r12, STACK_SLOT_TRAP(r1)
1029 stw r12, VCPU_TRAP(r4)
1030 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1031 addi r3, r4, VCPU_TB_RMEXIT
1032 bl kvmhv_accumulate_time
1034 11: b kvmhv_switch_to_host
1041 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1042 12: stw r12, VCPU_TRAP(r4)
1044 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1045 addi r3, r4, VCPU_TB_RMEXIT
1046 bl kvmhv_accumulate_time
1050 /******************************************************************************
1054 *****************************************************************************/
1057 * We come here from the first-level interrupt handlers.
1059 .globl kvmppc_interrupt_hv
1060 kvmppc_interrupt_hv:
1062 * Register contents:
1063 * R12 = interrupt vector
1065 * guest CR, R12 saved in shadow VCPU SCRATCH1/0
1066 * guest R13 saved in SPRN_SCRATCH0
1068 std r9, HSTATE_SCRATCH2(r13)
1070 lbz r9, HSTATE_IN_GUEST(r13)
1071 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1072 beq kvmppc_bad_host_intr
1073 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1074 cmpwi r9, KVM_GUEST_MODE_GUEST
1075 ld r9, HSTATE_SCRATCH2(r13)
1076 beq kvmppc_interrupt_pr
1078 /* We're now back in the host but in guest MMU context */
1079 li r9, KVM_GUEST_MODE_HOST_HV
1080 stb r9, HSTATE_IN_GUEST(r13)
1082 ld r9, HSTATE_KVM_VCPU(r13)
1084 /* Save registers */
1086 std r0, VCPU_GPR(R0)(r9)
1087 std r1, VCPU_GPR(R1)(r9)
1088 std r2, VCPU_GPR(R2)(r9)
1089 std r3, VCPU_GPR(R3)(r9)
1090 std r4, VCPU_GPR(R4)(r9)
1091 std r5, VCPU_GPR(R5)(r9)
1092 std r6, VCPU_GPR(R6)(r9)
1093 std r7, VCPU_GPR(R7)(r9)
1094 std r8, VCPU_GPR(R8)(r9)
1095 ld r0, HSTATE_SCRATCH2(r13)
1096 std r0, VCPU_GPR(R9)(r9)
1097 std r10, VCPU_GPR(R10)(r9)
1098 std r11, VCPU_GPR(R11)(r9)
1099 ld r3, HSTATE_SCRATCH0(r13)
1100 lwz r4, HSTATE_SCRATCH1(r13)
1101 std r3, VCPU_GPR(R12)(r9)
1104 ld r3, HSTATE_CFAR(r13)
1105 std r3, VCPU_CFAR(r9)
1106 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1108 ld r4, HSTATE_PPR(r13)
1109 std r4, VCPU_PPR(r9)
1110 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1112 /* Restore R1/R2 so we can handle faults */
1113 ld r1, HSTATE_HOST_R1(r13)
1116 mfspr r10, SPRN_SRR0
1117 mfspr r11, SPRN_SRR1
1118 std r10, VCPU_SRR0(r9)
1119 std r11, VCPU_SRR1(r9)
1120 andi. r0, r12, 2 /* need to read HSRR0/1? */
1122 mfspr r10, SPRN_HSRR0
1123 mfspr r11, SPRN_HSRR1
1125 1: std r10, VCPU_PC(r9)
1126 std r11, VCPU_MSR(r9)
1130 std r3, VCPU_GPR(R13)(r9)
1133 stw r12,VCPU_TRAP(r9)
1135 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1136 addi r3, r9, VCPU_TB_RMINTR
1138 bl kvmhv_accumulate_time
1139 ld r5, VCPU_GPR(R5)(r9)
1140 ld r6, VCPU_GPR(R6)(r9)
1141 ld r7, VCPU_GPR(R7)(r9)
1142 ld r8, VCPU_GPR(R8)(r9)
1145 /* Save HEIR (HV emulation assist reg) in emul_inst
1146 if this is an HEI (HV emulation interrupt, e40) */
1147 li r3,KVM_INST_FETCH_FAILED
1148 stw r3,VCPU_LAST_INST(r9)
1149 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1152 11: stw r3,VCPU_HEIR(r9)
1154 /* these are volatile across C function calls */
1157 std r3, VCPU_CTR(r9)
1158 std r4, VCPU_XER(r9)
1160 /* If this is a page table miss then see if it's theirs or ours */
1161 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1163 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1166 /* See if this is a leftover HDEC interrupt */
1167 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1172 bge fast_guest_return
1174 /* See if this is an hcall we can handle in real mode */
1175 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1176 beq hcall_try_real_mode
1178 /* Hypervisor doorbell - exit only if host IPI flag set */
1179 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1181 lbz r0, HSTATE_HOST_IPI(r13)
1186 /* External interrupt ? */
1187 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1188 bne+ guest_exit_cont
1190 /* External interrupt, first check for host_ipi. If this is
1191 * set, we know the host wants us out so let's do it now
1196 * Restore the active volatile registers after returning from
1199 ld r9, HSTATE_KVM_VCPU(r13)
1200 li r12, BOOK3S_INTERRUPT_EXTERNAL
1203 * kvmppc_read_intr return codes:
1205 * Exit to host (r3 > 0)
1206 * 1 An interrupt is pending that needs to be handled by the host
1207 * Exit guest and return to host by branching to guest_exit_cont
1209 * 2 Passthrough that needs completion in the host
1210 * Exit guest and return to host by branching to guest_exit_cont
1211 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1212 * to indicate to the host to complete handling the interrupt
1214 * Before returning to guest, we check if any CPU is heading out
1215 * to the host and if so, we head out also. If no CPUs are heading
1216 * check return values <= 0.
1218 * Return to guest (r3 <= 0)
1219 * 0 No external interrupt is pending
1220 * -1 A guest wakeup IPI (which has now been cleared)
1221 * In either case, we return to guest to deliver any pending
1224 * -2 A PCI passthrough external interrupt was handled
1225 * (interrupt was delivered directly to guest)
1226 * Return to guest to deliver any pending guest interrupts.
1232 /* Return code = 2 */
1233 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1234 stw r12, VCPU_TRAP(r9)
1237 1: /* Return code <= 1 */
1241 /* Return code <= 0 */
1242 4: ld r5, HSTATE_KVM_VCORE(r13)
1243 lwz r0, VCORE_ENTRY_EXIT(r5)
1246 blt deliver_guest_interrupt
1248 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1249 /* Save more register state */
1252 std r6, VCPU_DAR(r9)
1253 stw r7, VCPU_DSISR(r9)
1254 /* don't overwrite fault_dar/fault_dsisr if HDSI */
1255 cmpwi r12,BOOK3S_INTERRUPT_H_DATA_STORAGE
1257 std r6, VCPU_FAULT_DAR(r9)
1258 stw r7, VCPU_FAULT_DSISR(r9)
1260 /* See if it is a machine check */
1261 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1262 beq machine_check_realmode
1264 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1265 addi r3, r9, VCPU_TB_RMEXIT
1267 bl kvmhv_accumulate_time
1270 /* Possibly flush the link stack here. */
1272 patch_site 1b patch__call_kvm_flush_link_stack
1274 stw r12, STACK_SLOT_TRAP(r1)
1276 /* Increment exit count, poke other threads to exit */
1277 bl kvmhv_commence_exit
1279 ld r9, HSTATE_KVM_VCPU(r13)
1281 /* Stop others sending VCPU interrupts to this physical CPU */
1283 stw r0, VCPU_CPU(r9)
1284 stw r0, VCPU_THREAD_CPU(r9)
1286 /* Save guest CTRL register, set runlatch to 1 */
1288 stw r6,VCPU_CTRL(r9)
1294 /* Read the guest SLB and save it away */
1295 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1301 andis. r0,r8,SLB_ESID_V@h
1303 add r8,r8,r6 /* put index in */
1305 std r8,VCPU_SLB_E(r7)
1306 std r3,VCPU_SLB_V(r7)
1307 addi r7,r7,VCPU_SLB_SIZE
1311 stw r5,VCPU_SLB_MAX(r9)
1314 * Save the guest PURR/SPURR
1319 ld r8,VCPU_SPURR(r9)
1320 std r5,VCPU_PURR(r9)
1321 std r6,VCPU_SPURR(r9)
1326 * Restore host PURR/SPURR and add guest times
1327 * so that the time in the guest gets accounted.
1329 ld r3,HSTATE_PURR(r13)
1330 ld r4,HSTATE_SPURR(r13)
1341 /* r5 is a guest timebase value here, convert to host TB */
1342 ld r3,HSTATE_KVM_VCORE(r13)
1343 ld r4,VCORE_TB_OFFSET(r3)
1345 std r5,VCPU_DEC_EXPIRES(r9)
1349 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1350 /* Save POWER8-specific registers */
1354 std r5, VCPU_IAMR(r9)
1355 stw r6, VCPU_PSPB(r9)
1356 std r7, VCPU_FSCR(r9)
1360 std r7, VCPU_TAR(r9)
1361 mfspr r8, SPRN_EBBHR
1362 std r8, VCPU_EBBHR(r9)
1363 mfspr r5, SPRN_EBBRR
1364 mfspr r6, SPRN_BESCR
1365 mfspr r7, SPRN_CSIGR
1367 std r5, VCPU_EBBRR(r9)
1368 std r6, VCPU_BESCR(r9)
1369 std r7, VCPU_CSIGR(r9)
1370 std r8, VCPU_TACR(r9)
1371 mfspr r5, SPRN_TCSCR
1375 std r5, VCPU_TCSCR(r9)
1376 std r6, VCPU_ACOP(r9)
1377 stw r7, VCPU_GUEST_PID(r9)
1378 std r8, VCPU_WORT(r9)
1380 * Restore various registers to 0, where non-zero values
1381 * set by the guest could disrupt the host.
1386 mtspr SPRN_TCSCR, r0
1388 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1391 mtspr SPRN_MMCRS, r0
1394 /* Save and reset AMR and UAMOR before turning on the MMU */
1398 std r6,VCPU_UAMOR(r9)
1401 mtspr SPRN_UAMOR, r6
1403 /* Switch DSCR back to host value */
1405 ld r7, HSTATE_DSCR(r13)
1406 std r8, VCPU_DSCR(r9)
1409 /* Save non-volatile GPRs */
1410 std r14, VCPU_GPR(R14)(r9)
1411 std r15, VCPU_GPR(R15)(r9)
1412 std r16, VCPU_GPR(R16)(r9)
1413 std r17, VCPU_GPR(R17)(r9)
1414 std r18, VCPU_GPR(R18)(r9)
1415 std r19, VCPU_GPR(R19)(r9)
1416 std r20, VCPU_GPR(R20)(r9)
1417 std r21, VCPU_GPR(R21)(r9)
1418 std r22, VCPU_GPR(R22)(r9)
1419 std r23, VCPU_GPR(R23)(r9)
1420 std r24, VCPU_GPR(R24)(r9)
1421 std r25, VCPU_GPR(R25)(r9)
1422 std r26, VCPU_GPR(R26)(r9)
1423 std r27, VCPU_GPR(R27)(r9)
1424 std r28, VCPU_GPR(R28)(r9)
1425 std r29, VCPU_GPR(R29)(r9)
1426 std r30, VCPU_GPR(R30)(r9)
1427 std r31, VCPU_GPR(R31)(r9)
1430 mfspr r3, SPRN_SPRG0
1431 mfspr r4, SPRN_SPRG1
1432 mfspr r5, SPRN_SPRG2
1433 mfspr r6, SPRN_SPRG3
1434 std r3, VCPU_SPRG0(r9)
1435 std r4, VCPU_SPRG1(r9)
1436 std r5, VCPU_SPRG2(r9)
1437 std r6, VCPU_SPRG3(r9)
1443 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1446 END_FTR_SECTION_IFSET(CPU_FTR_TM)
1449 /* Increment yield count if they have a VPA */
1450 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1453 li r4, LPPACA_YIELDCOUNT
1458 stb r3, VCPU_VPA_DIRTY(r9)
1460 /* Save PMU registers if requested */
1461 /* r8 and cr0.eq are live here */
1464 * POWER8 seems to have a hardware bug where setting
1465 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
1466 * when some counters are already negative doesn't seem
1467 * to cause a performance monitor alert (and hence interrupt).
1468 * The effect of this is that when saving the PMU state,
1469 * if there is no PMU alert pending when we read MMCR0
1470 * before freezing the counters, but one becomes pending
1471 * before we read the counters, we lose it.
1472 * To work around this, we need a way to freeze the counters
1473 * before reading MMCR0. Normally, freezing the counters
1474 * is done by writing MMCR0 (to set MMCR0[FC]) which
1475 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
1476 * we can also freeze the counters using MMCR2, by writing
1477 * 1s to all the counter freeze condition bits (there are
1478 * 9 bits each for 6 counters).
1480 li r3, -1 /* set all freeze bits */
1482 mfspr r10, SPRN_MMCR2
1483 mtspr SPRN_MMCR2, r3
1485 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1487 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
1488 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
1489 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
1490 mfspr r6, SPRN_MMCRA
1491 /* Clear MMCRA in order to disable SDAR updates */
1493 mtspr SPRN_MMCRA, r7
1495 beq 21f /* if no VPA, save PMU stuff anyway */
1496 lbz r7, LPPACA_PMCINUSE(r8)
1497 cmpwi r7, 0 /* did they ask for PMU stuff to be saved? */
1499 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
1501 21: mfspr r5, SPRN_MMCR1
1504 std r4, VCPU_MMCR(r9)
1505 std r5, VCPU_MMCR + 8(r9)
1506 std r6, VCPU_MMCR + 16(r9)
1508 std r10, VCPU_MMCR + 24(r9)
1509 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1510 std r7, VCPU_SIAR(r9)
1511 std r8, VCPU_SDAR(r9)
1518 stw r3, VCPU_PMC(r9)
1519 stw r4, VCPU_PMC + 4(r9)
1520 stw r5, VCPU_PMC + 8(r9)
1521 stw r6, VCPU_PMC + 12(r9)
1522 stw r7, VCPU_PMC + 16(r9)
1523 stw r8, VCPU_PMC + 20(r9)
1526 mfspr r6, SPRN_SPMC1
1527 mfspr r7, SPRN_SPMC2
1528 mfspr r8, SPRN_MMCRS
1529 std r5, VCPU_SIER(r9)
1530 stw r6, VCPU_PMC + 24(r9)
1531 stw r7, VCPU_PMC + 28(r9)
1532 std r8, VCPU_MMCR + 32(r9)
1534 mtspr SPRN_MMCRS, r4
1535 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1543 /* Restore host values of some registers */
1545 ld r5, STACK_SLOT_CIABR(r1)
1546 ld r6, STACK_SLOT_DAWR(r1)
1547 ld r7, STACK_SLOT_DAWRX(r1)
1548 mtspr SPRN_CIABR, r5
1550 mtspr SPRN_DAWRX, r7
1551 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1554 * POWER7/POWER8 guest -> host partition switch code.
1555 * We don't have to lock against tlbies but we do
1556 * have to coordinate the hardware threads.
1557 * Here STACK_SLOT_TRAP(r1) contains the trap number.
1559 kvmhv_switch_to_host:
1560 /* Secondary threads wait for primary to do partition switch */
1561 ld r5,HSTATE_KVM_VCORE(r13)
1562 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1563 lbz r3,HSTATE_PTID(r13)
1567 13: lbz r3,VCORE_IN_GUEST(r5)
1573 /* Primary thread waits for all the secondaries to exit guest */
1574 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1575 rlwinm r0,r3,32-8,0xff
1581 /* Did we actually switch to the guest at all? */
1582 lbz r6, VCORE_IN_GUEST(r5)
1586 /* Primary thread switches back to host partition */
1587 ld r6,KVM_HOST_SDR1(r4)
1588 lwz r7,KVM_HOST_LPID(r4)
1589 li r8,LPID_RSVD /* switch to reserved LPID */
1592 mtspr SPRN_SDR1,r6 /* switch to partition page table */
1597 /* DPDES and VTB are shared between threads */
1598 mfspr r7, SPRN_DPDES
1600 std r7, VCORE_DPDES(r5)
1601 std r8, VCORE_VTB(r5)
1602 /* clear DPDES so we don't get guest doorbells in the host */
1604 mtspr SPRN_DPDES, r8
1605 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1607 /* If HMI, call kvmppc_realmode_hmi_handler() */
1608 lwz r12, STACK_SLOT_TRAP(r1)
1609 cmpwi r12, BOOK3S_INTERRUPT_HMI
1611 bl kvmppc_realmode_hmi_handler
1614 * At this point kvmppc_realmode_hmi_handler would have resync-ed
1615 * the TB. Hence it is not required to subtract guest timebase
1616 * offset from timebase. So, skip it.
1618 * Also, do not call kvmppc_subcore_exit_guest() because it has
1619 * been invoked as part of kvmppc_realmode_hmi_handler().
1624 /* Subtract timebase offset from timebase */
1625 ld r8,VCORE_TB_OFFSET(r5)
1628 mftb r6 /* current guest timebase */
1630 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1631 mftb r7 /* check if lower 24 bits overflowed */
1636 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1639 17: bl kvmppc_subcore_exit_guest
1641 30: ld r5,HSTATE_KVM_VCORE(r13)
1642 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1645 ld r0, VCORE_PCR(r5)
1651 /* Signal secondary CPUs to continue */
1652 stb r0,VCORE_IN_GUEST(r5)
1653 19: lis r8,0x7fff /* MAX_INT@h */
1656 16: ld r8,KVM_HOST_LPCR(r4)
1660 /* load host SLB entries */
1661 ld r8,PACA_SLBSHADOWPTR(r13)
1663 .rept SLB_NUM_BOLTED
1664 li r3, SLBSHADOW_SAVEAREA
1668 andis. r7,r5,SLB_ESID_V@h
1674 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1675 /* Finish timing, if we have a vcpu */
1676 ld r4, HSTATE_KVM_VCPU(r13)
1680 bl kvmhv_accumulate_time
1683 /* Unset guest mode */
1684 li r0, KVM_GUEST_MODE_NONE
1685 stb r0, HSTATE_IN_GUEST(r13)
1687 lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */
1688 ld r0, SFS+PPC_LR_STKOFF(r1)
1694 .global kvm_flush_link_stack
1695 kvm_flush_link_stack:
1696 /* Save LR into r0 */
1699 /* Flush the link stack. On Power8 it's up to 32 entries in size. */
1704 /* And on Power9 it's up to 64. */
1709 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1716 * Check whether an HDSI is an HPTE not found fault or something else.
1717 * If it is an HPTE not found fault that is due to the guest accessing
1718 * a page that they have mapped but which we have paged out, then
1719 * we continue on with the guest exit path. In all other cases,
1720 * reflect the HDSI to the guest as a DSI.
1724 mfspr r6, SPRN_HDSISR
1725 /* HPTE not found fault or protection fault? */
1726 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1727 beq 1f /* if not, send it to the guest */
1728 andi. r0, r11, MSR_DR /* data relocation enabled? */
1731 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1732 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
1733 bne 7f /* if no SLB entry found */
1734 4: std r4, VCPU_FAULT_DAR(r9)
1735 stw r6, VCPU_FAULT_DSISR(r9)
1737 /* Search the hash table. */
1738 mr r3, r9 /* vcpu pointer */
1739 li r7, 1 /* data fault */
1740 bl kvmppc_hpte_hv_fault
1741 ld r9, HSTATE_KVM_VCPU(r13)
1743 ld r11, VCPU_MSR(r9)
1744 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1745 cmpdi r3, 0 /* retry the instruction */
1747 cmpdi r3, -1 /* handle in kernel mode */
1749 cmpdi r3, -2 /* MMIO emulation; need instr word */
1752 /* Synthesize a DSI (or DSegI) for the guest */
1753 ld r4, VCPU_FAULT_DAR(r9)
1755 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
1756 mtspr SPRN_DSISR, r6
1757 7: mtspr SPRN_DAR, r4
1758 mtspr SPRN_SRR0, r10
1759 mtspr SPRN_SRR1, r11
1761 bl kvmppc_msr_interrupt
1762 fast_interrupt_c_return:
1763 6: ld r7, VCPU_CTR(r9)
1770 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1771 ld r5, KVM_VRMA_SLB_V(r5)
1774 /* If this is for emulated MMIO, load the instruction word */
1775 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1777 /* Set guest mode to 'jump over instruction' so if lwz faults
1778 * we'll just continue at the next IP. */
1779 li r0, KVM_GUEST_MODE_SKIP
1780 stb r0, HSTATE_IN_GUEST(r13)
1782 /* Do the access with MSR:DR enabled */
1784 ori r4, r3, MSR_DR /* Enable paging for data */
1789 /* Store the result */
1790 stw r8, VCPU_LAST_INST(r9)
1792 /* Unset guest mode. */
1793 li r0, KVM_GUEST_MODE_HOST_HV
1794 stb r0, HSTATE_IN_GUEST(r13)
1798 * Similarly for an HISI, reflect it to the guest as an ISI unless
1799 * it is an HPTE not found fault for a page that we have paged out.
1802 andis. r0, r11, SRR1_ISI_NOPT@h
1804 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1807 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1808 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
1809 bne 7f /* if no SLB entry found */
1811 /* Search the hash table. */
1812 mr r3, r9 /* vcpu pointer */
1815 li r7, 0 /* instruction fault */
1816 bl kvmppc_hpte_hv_fault
1817 ld r9, HSTATE_KVM_VCPU(r13)
1819 ld r11, VCPU_MSR(r9)
1820 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1821 cmpdi r3, 0 /* retry the instruction */
1822 beq fast_interrupt_c_return
1823 cmpdi r3, -1 /* handle in kernel mode */
1826 /* Synthesize an ISI (or ISegI) for the guest */
1828 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
1829 7: mtspr SPRN_SRR0, r10
1830 mtspr SPRN_SRR1, r11
1832 bl kvmppc_msr_interrupt
1833 b fast_interrupt_c_return
1835 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1836 ld r5, KVM_VRMA_SLB_V(r6)
1840 * Try to handle an hcall in real mode.
1841 * Returns to the guest if we handle it, or continues on up to
1842 * the kernel if we can't (i.e. if we don't have a handler for
1843 * it, or if the handler returns H_TOO_HARD).
1845 * r5 - r8 contain hcall args,
1846 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
1848 hcall_try_real_mode:
1849 ld r3,VCPU_GPR(R3)(r9)
1851 /* sc 1 from userspace - reflect to guest syscall */
1852 bne sc_1_fast_return
1854 cmpldi r3,hcall_real_table_end - hcall_real_table
1856 /* See if this hcall is enabled for in-kernel handling */
1858 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
1859 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
1861 ld r0, KVM_ENABLED_HCALLS(r4)
1862 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
1866 /* Get pointer to handler, if any, and call it */
1867 LOAD_REG_ADDR(r4, hcall_real_table)
1873 mr r3,r9 /* get vcpu pointer */
1874 ld r4,VCPU_GPR(R4)(r9)
1877 beq hcall_real_fallback
1878 ld r4,HSTATE_KVM_VCPU(r13)
1879 std r3,VCPU_GPR(R3)(r4)
1887 li r10, BOOK3S_INTERRUPT_SYSCALL
1888 bl kvmppc_msr_interrupt
1892 /* We've attempted a real mode hcall, but it's punted it back
1893 * to userspace. We need to restore some clobbered volatiles
1894 * before resuming the pass-it-to-qemu path */
1895 hcall_real_fallback:
1896 li r12,BOOK3S_INTERRUPT_SYSCALL
1897 ld r9, HSTATE_KVM_VCPU(r13)
1901 .globl hcall_real_table
1903 .long 0 /* 0 - unused */
1904 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
1905 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
1906 .long DOTSYM(kvmppc_h_read) - hcall_real_table
1907 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
1908 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
1909 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
1910 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
1911 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
1912 .long 0 /* 0x24 - H_SET_SPRG0 */
1913 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
1928 #ifdef CONFIG_KVM_XICS
1929 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
1930 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
1931 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
1932 .long 0 /* 0x70 - H_IPOLL */
1933 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
1935 .long 0 /* 0x64 - H_EOI */
1936 .long 0 /* 0x68 - H_CPPR */
1937 .long 0 /* 0x6c - H_IPI */
1938 .long 0 /* 0x70 - H_IPOLL */
1939 .long 0 /* 0x74 - H_XIRR */
1967 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
1968 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
1984 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
1988 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
1989 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
1990 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2103 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2104 .globl hcall_real_table_end
2105 hcall_real_table_end:
2107 _GLOBAL(kvmppc_h_set_xdabr)
2108 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2110 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2113 6: li r3, H_PARAMETER
2116 _GLOBAL(kvmppc_h_set_dabr)
2117 li r5, DABRX_USER | DABRX_KERNEL
2121 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2122 std r4,VCPU_DABR(r3)
2123 stw r5, VCPU_DABRX(r3)
2124 mtspr SPRN_DABRX, r5
2125 /* Work around P7 bug where DABR can get corrupted on mtspr */
2126 1: mtspr SPRN_DABR,r4
2134 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2135 2: rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2136 rlwimi r5, r4, 2, DAWRX_WT
2138 std r4, VCPU_DAWR(r3)
2139 std r5, VCPU_DAWRX(r3)
2141 mtspr SPRN_DAWRX, r5
2145 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2147 std r11,VCPU_MSR(r3)
2149 stb r0,VCPU_CEDED(r3)
2150 sync /* order setting ceded vs. testing prodded */
2151 lbz r5,VCPU_PRODDED(r3)
2153 bne kvm_cede_prodded
2154 li r12,0 /* set trap to 0 to say hcall is handled */
2155 stw r12,VCPU_TRAP(r3)
2157 std r0,VCPU_GPR(R3)(r3)
2160 * Set our bit in the bitmask of napping threads unless all the
2161 * other threads are already napping, in which case we send this
2164 ld r5,HSTATE_KVM_VCORE(r13)
2165 lbz r6,HSTATE_PTID(r13)
2166 lwz r8,VCORE_ENTRY_EXIT(r5)
2170 addi r6,r5,VCORE_NAPPING_THREADS
2177 /* order napping_threads update vs testing entry_exit_map */
2180 stb r0,HSTATE_NAPPING(r13)
2181 lwz r7,VCORE_ENTRY_EXIT(r5)
2183 bge 33f /* another thread already exiting */
2186 * Although not specifically required by the architecture, POWER7
2187 * preserves the following registers in nap mode, even if an SMT mode
2188 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2189 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2191 /* Save non-volatile GPRs */
2192 std r14, VCPU_GPR(R14)(r3)
2193 std r15, VCPU_GPR(R15)(r3)
2194 std r16, VCPU_GPR(R16)(r3)
2195 std r17, VCPU_GPR(R17)(r3)
2196 std r18, VCPU_GPR(R18)(r3)
2197 std r19, VCPU_GPR(R19)(r3)
2198 std r20, VCPU_GPR(R20)(r3)
2199 std r21, VCPU_GPR(R21)(r3)
2200 std r22, VCPU_GPR(R22)(r3)
2201 std r23, VCPU_GPR(R23)(r3)
2202 std r24, VCPU_GPR(R24)(r3)
2203 std r25, VCPU_GPR(R25)(r3)
2204 std r26, VCPU_GPR(R26)(r3)
2205 std r27, VCPU_GPR(R27)(r3)
2206 std r28, VCPU_GPR(R28)(r3)
2207 std r29, VCPU_GPR(R29)(r3)
2208 std r30, VCPU_GPR(R30)(r3)
2209 std r31, VCPU_GPR(R31)(r3)
2214 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2216 ld r9, HSTATE_KVM_VCPU(r13)
2218 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2222 * Set DEC to the smaller of DEC and HDEC, so that we wake
2223 * no later than the end of our timeslice (HDEC interrupts
2224 * don't wake us from nap).
2233 /* save expiry time of guest decrementer */
2236 ld r4, HSTATE_KVM_VCPU(r13)
2237 ld r5, HSTATE_KVM_VCORE(r13)
2238 ld r6, VCORE_TB_OFFSET(r5)
2239 subf r3, r6, r3 /* convert to host TB value */
2240 std r3, VCPU_DEC_EXPIRES(r4)
2242 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2243 ld r4, HSTATE_KVM_VCPU(r13)
2244 addi r3, r4, VCPU_TB_CEDE
2245 bl kvmhv_accumulate_time
2248 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2251 * Take a nap until a decrementer or external or doobell interrupt
2252 * occurs, with PECE1 and PECE0 set in LPCR.
2253 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2254 * Also clear the runlatch bit before napping.
2257 mfspr r0, SPRN_CTRLF
2259 mtspr SPRN_CTRLT, r0
2262 stb r0,HSTATE_HWTHREAD_REQ(r13)
2264 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2266 ori r5, r5, LPCR_PECEDH
2267 rlwimi r5, r3, 0, LPCR_PECEDP
2268 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2272 std r0, HSTATE_SCRATCH0(r13)
2274 ld r0, HSTATE_SCRATCH0(r13)
2286 /* get vcpu pointer */
2287 ld r4, HSTATE_KVM_VCPU(r13)
2289 /* Woken by external or decrementer interrupt */
2290 ld r1, HSTATE_HOST_R1(r13)
2292 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2293 addi r3, r4, VCPU_TB_RMINTR
2294 bl kvmhv_accumulate_time
2297 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2299 bl kvmppc_restore_tm
2300 END_FTR_SECTION_IFSET(CPU_FTR_TM)
2303 /* load up FP state */
2306 /* Restore guest decrementer */
2307 ld r3, VCPU_DEC_EXPIRES(r4)
2308 ld r5, HSTATE_KVM_VCORE(r13)
2309 ld r6, VCORE_TB_OFFSET(r5)
2310 add r3, r3, r6 /* convert host TB to guest TB value */
2316 ld r14, VCPU_GPR(R14)(r4)
2317 ld r15, VCPU_GPR(R15)(r4)
2318 ld r16, VCPU_GPR(R16)(r4)
2319 ld r17, VCPU_GPR(R17)(r4)
2320 ld r18, VCPU_GPR(R18)(r4)
2321 ld r19, VCPU_GPR(R19)(r4)
2322 ld r20, VCPU_GPR(R20)(r4)
2323 ld r21, VCPU_GPR(R21)(r4)
2324 ld r22, VCPU_GPR(R22)(r4)
2325 ld r23, VCPU_GPR(R23)(r4)
2326 ld r24, VCPU_GPR(R24)(r4)
2327 ld r25, VCPU_GPR(R25)(r4)
2328 ld r26, VCPU_GPR(R26)(r4)
2329 ld r27, VCPU_GPR(R27)(r4)
2330 ld r28, VCPU_GPR(R28)(r4)
2331 ld r29, VCPU_GPR(R29)(r4)
2332 ld r30, VCPU_GPR(R30)(r4)
2333 ld r31, VCPU_GPR(R31)(r4)
2335 /* Check the wake reason in SRR1 to see why we got here */
2336 bl kvmppc_check_wake_reason
2339 * Restore volatile registers since we could have called a
2340 * C routine in kvmppc_check_wake_reason
2342 * r3 tells us whether we need to return to host or not
2343 * WARNING: it gets checked further down:
2344 * should not modify r3 until this check is done.
2346 ld r4, HSTATE_KVM_VCPU(r13)
2348 /* clear our bit in vcore->napping_threads */
2349 34: ld r5,HSTATE_KVM_VCORE(r13)
2350 lbz r7,HSTATE_PTID(r13)
2353 addi r6,r5,VCORE_NAPPING_THREADS
2359 stb r0,HSTATE_NAPPING(r13)
2361 /* See if the wake reason saved in r3 means we need to exit */
2362 stw r12, VCPU_TRAP(r4)
2367 /* see if any other thread is already exiting */
2368 lwz r0,VCORE_ENTRY_EXIT(r5)
2372 b kvmppc_cede_reentry /* if not go back to guest */
2374 /* cede when already previously prodded case */
2377 stb r0,VCPU_PRODDED(r3)
2378 sync /* order testing prodded vs. clearing ceded */
2379 stb r0,VCPU_CEDED(r3)
2383 /* we've ceded but we want to give control to the host */
2385 ld r9, HSTATE_KVM_VCPU(r13)
2388 /* Try to handle a machine check in real mode */
2389 machine_check_realmode:
2390 mr r3, r9 /* get vcpu pointer */
2391 bl kvmppc_realmode_machine_check
2393 ld r9, HSTATE_KVM_VCPU(r13)
2394 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2396 * Deliver unhandled/fatal (e.g. UE) MCE errors to guest through
2397 * machine check interrupt (set HSRR0 to 0x200). And for handled
2398 * errors (no-fatal), just go back to guest execution with current
2399 * HSRR0 instead of exiting guest. This new approach will inject
2400 * machine check to guest for fatal error causing guest to crash.
2402 * The old code used to return to host for unhandled errors which
2403 * was causing guest to hang with soft lockups inside guest and
2404 * makes it difficult to recover guest instance.
2406 * if we receive machine check with MSR(RI=0) then deliver it to
2407 * guest as machine check causing guest to crash.
2409 ld r11, VCPU_MSR(r9)
2410 rldicl. r0, r11, 64-MSR_HV_LG, 63 /* check if it happened in HV mode */
2411 bne mc_cont /* if so, exit to host */
2412 andi. r10, r11, MSR_RI /* check for unrecoverable exception */
2413 beq 1f /* Deliver a machine check to guest */
2415 cmpdi r3, 0 /* Did we handle MCE ? */
2416 bne 2f /* Continue guest execution. */
2417 /* If not, deliver a machine check. SRR0/1 are already set */
2418 1: li r10, BOOK3S_INTERRUPT_MACHINE_CHECK
2419 bl kvmppc_msr_interrupt
2420 2: b fast_interrupt_c_return
2423 * Check the reason we woke from nap, and take appropriate action.
2425 * 0 if nothing needs to be done
2426 * 1 if something happened that needs to be handled by the host
2427 * -1 if there was a guest wakeup (IPI or msgsnd)
2428 * -2 if we handled a PCI passthrough interrupt (returned by
2429 * kvmppc_read_intr only)
2431 * Also sets r12 to the interrupt vector for any interrupt that needs
2432 * to be handled now by the host (0x500 for external interrupt), or zero.
2433 * Modifies all volatile registers (since it may call a C function).
2434 * This routine calls kvmppc_read_intr, a C function, if an external
2435 * interrupt is pending.
2437 kvmppc_check_wake_reason:
2440 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2442 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2443 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2444 cmpwi r6, 8 /* was it an external interrupt? */
2445 beq 7f /* if so, see what it was */
2448 cmpwi r6, 6 /* was it the decrementer? */
2451 cmpwi r6, 5 /* privileged doorbell? */
2453 cmpwi r6, 3 /* hypervisor doorbell? */
2455 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2456 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2458 li r3, 1 /* anything else, return 1 */
2461 /* hypervisor doorbell */
2462 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2465 * Clear the doorbell as we will invoke the handler
2466 * explicitly in the guest exit path.
2468 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2470 /* see if it's a host IPI */
2472 lbz r0, HSTATE_HOST_IPI(r13)
2475 /* if not, return -1 */
2479 /* Woken up due to Hypervisor maintenance interrupt */
2480 4: li r12, BOOK3S_INTERRUPT_HMI
2484 /* external interrupt - create a stack frame so we can call C */
2486 std r0, PPC_LR_STKOFF(r1)
2487 stdu r1, -PPC_MIN_STKFRM(r1)
2490 li r12, BOOK3S_INTERRUPT_EXTERNAL
2495 * Return code of 2 means PCI passthrough interrupt, but
2496 * we need to return back to host to complete handling the
2497 * interrupt. Trap reason is expected in r12 by guest
2500 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2502 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2503 addi r1, r1, PPC_MIN_STKFRM
2508 * Save away FP, VMX and VSX registers.
2510 * N.B. r30 and r31 are volatile across this function,
2511 * thus it is not callable from C.
2518 #ifdef CONFIG_ALTIVEC
2520 oris r8,r8,MSR_VEC@h
2521 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2525 oris r8,r8,MSR_VSX@h
2526 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2529 addi r3,r3,VCPU_FPRS
2531 #ifdef CONFIG_ALTIVEC
2533 addi r3,r31,VCPU_VRS
2535 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2537 mfspr r6,SPRN_VRSAVE
2538 stw r6,VCPU_VRSAVE(r31)
2543 * Load up FP, VMX and VSX registers
2545 * N.B. r30 and r31 are volatile across this function,
2546 * thus it is not callable from C.
2553 #ifdef CONFIG_ALTIVEC
2555 oris r8,r8,MSR_VEC@h
2556 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2560 oris r8,r8,MSR_VSX@h
2561 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2564 addi r3,r4,VCPU_FPRS
2566 #ifdef CONFIG_ALTIVEC
2568 addi r3,r31,VCPU_VRS
2570 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2572 lwz r7,VCPU_VRSAVE(r31)
2573 mtspr SPRN_VRSAVE,r7
2578 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2580 * Save transactional state and TM-related registers.
2581 * Called with r9 pointing to the vcpu struct.
2582 * This can modify all checkpointed registers, but
2583 * restores r1, r2 and r9 (vcpu pointer) before exit.
2587 std r0, PPC_LR_STKOFF(r1)
2592 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
2596 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2597 beq 1f /* TM not active in guest. */
2599 std r1, HSTATE_HOST_R1(r13)
2600 li r3, TM_CAUSE_KVM_RESCHED
2602 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
2606 /* All GPRs are volatile at this point. */
2609 /* Temporarily store r13 and r9 so we have some regs to play with */
2612 std r9, PACATMSCRATCH(r13)
2613 ld r9, HSTATE_KVM_VCPU(r13)
2615 /* Get a few more GPRs free. */
2616 std r29, VCPU_GPRS_TM(29)(r9)
2617 std r30, VCPU_GPRS_TM(30)(r9)
2618 std r31, VCPU_GPRS_TM(31)(r9)
2620 /* Save away PPR and DSCR soon so don't run with user values. */
2623 mfspr r30, SPRN_DSCR
2624 ld r29, HSTATE_DSCR(r13)
2625 mtspr SPRN_DSCR, r29
2627 /* Save all but r9, r13 & r29-r31 */
2630 .if (reg != 9) && (reg != 13)
2631 std reg, VCPU_GPRS_TM(reg)(r9)
2635 /* ... now save r13 */
2637 std r4, VCPU_GPRS_TM(13)(r9)
2638 /* ... and save r9 */
2639 ld r4, PACATMSCRATCH(r13)
2640 std r4, VCPU_GPRS_TM(9)(r9)
2642 /* Reload stack pointer and TOC. */
2643 ld r1, HSTATE_HOST_R1(r13)
2646 /* Set MSR RI now we have r1 and r13 back. */
2650 /* Save away checkpinted SPRs. */
2651 std r31, VCPU_PPR_TM(r9)
2652 std r30, VCPU_DSCR_TM(r9)
2659 std r5, VCPU_LR_TM(r9)
2660 stw r6, VCPU_CR_TM(r9)
2661 std r7, VCPU_CTR_TM(r9)
2662 std r8, VCPU_AMR_TM(r9)
2663 std r10, VCPU_TAR_TM(r9)
2664 std r11, VCPU_XER_TM(r9)
2666 /* Restore r12 as trap number. */
2667 lwz r12, VCPU_TRAP(r9)
2670 addi r3, r9, VCPU_FPRS_TM
2672 addi r3, r9, VCPU_VRS_TM
2674 mfspr r6, SPRN_VRSAVE
2675 stw r6, VCPU_VRSAVE_TM(r9)
2678 * We need to save these SPRs after the treclaim so that the software
2679 * error code is recorded correctly in the TEXASR. Also the user may
2680 * change these outside of a transaction, so they must always be
2683 mfspr r5, SPRN_TFHAR
2684 mfspr r6, SPRN_TFIAR
2685 mfspr r7, SPRN_TEXASR
2686 std r5, VCPU_TFHAR(r9)
2687 std r6, VCPU_TFIAR(r9)
2688 std r7, VCPU_TEXASR(r9)
2690 ld r0, PPC_LR_STKOFF(r1)
2695 * Restore transactional state and TM-related registers.
2696 * Called with r4 pointing to the vcpu struct.
2697 * This potentially modifies all checkpointed registers.
2698 * It restores r1, r2, r4 from the PACA.
2702 std r0, PPC_LR_STKOFF(r1)
2704 /* Turn on TM/FP/VSX/VMX so we can restore them. */
2710 oris r5, r5, (MSR_VEC | MSR_VSX)@h
2714 * The user may change these outside of a transaction, so they must
2715 * always be context switched.
2717 ld r5, VCPU_TFHAR(r4)
2718 ld r6, VCPU_TFIAR(r4)
2719 ld r7, VCPU_TEXASR(r4)
2720 mtspr SPRN_TFHAR, r5
2721 mtspr SPRN_TFIAR, r6
2722 mtspr SPRN_TEXASR, r7
2725 rldicl. r5, r5, 64 - MSR_TS_S_LG, 62
2726 beqlr /* TM not active in guest */
2727 std r1, HSTATE_HOST_R1(r13)
2729 /* Make sure the failure summary is set, otherwise we'll program check
2730 * when we trechkpt. It's possible that this might have been not set
2731 * on a kvmppc_set_one_reg() call but we shouldn't let this crash the
2734 oris r7, r7, (TEXASR_FS)@h
2735 mtspr SPRN_TEXASR, r7
2738 * We need to load up the checkpointed state for the guest.
2739 * We need to do this early as it will blow away any GPRs, VSRs and
2744 addi r3, r31, VCPU_FPRS_TM
2746 addi r3, r31, VCPU_VRS_TM
2749 lwz r7, VCPU_VRSAVE_TM(r4)
2750 mtspr SPRN_VRSAVE, r7
2752 ld r5, VCPU_LR_TM(r4)
2753 lwz r6, VCPU_CR_TM(r4)
2754 ld r7, VCPU_CTR_TM(r4)
2755 ld r8, VCPU_AMR_TM(r4)
2756 ld r9, VCPU_TAR_TM(r4)
2757 ld r10, VCPU_XER_TM(r4)
2766 * Load up PPR and DSCR values but don't put them in the actual SPRs
2767 * till the last moment to avoid running with userspace PPR and DSCR for
2770 ld r29, VCPU_DSCR_TM(r4)
2771 ld r30, VCPU_PPR_TM(r4)
2773 std r2, PACATMSCRATCH(r13) /* Save TOC */
2775 /* Clear the MSR RI since r1, r13 are all going to be foobar. */
2779 /* Load GPRs r0-r28 */
2782 ld reg, VCPU_GPRS_TM(reg)(r31)
2786 mtspr SPRN_DSCR, r29
2789 /* Load final GPRs */
2790 ld 29, VCPU_GPRS_TM(29)(r31)
2791 ld 30, VCPU_GPRS_TM(30)(r31)
2792 ld 31, VCPU_GPRS_TM(31)(r31)
2794 /* TM checkpointed state is now setup. All GPRs are now volatile. */
2797 /* Now let's get back the state we need. */
2800 ld r29, HSTATE_DSCR(r13)
2801 mtspr SPRN_DSCR, r29
2802 ld r4, HSTATE_KVM_VCPU(r13)
2803 ld r1, HSTATE_HOST_R1(r13)
2804 ld r2, PACATMSCRATCH(r13)
2806 /* Set the MSR RI since we have our registers back. */
2810 ld r0, PPC_LR_STKOFF(r1)
2816 * We come here if we get any exception or interrupt while we are
2817 * executing host real mode code while in guest MMU context.
2818 * For now just spin, but we should do something better.
2820 kvmppc_bad_host_intr:
2824 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2825 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2826 * r11 has the guest MSR value (in/out)
2827 * r9 has a vcpu pointer (in)
2828 * r0 is used as a scratch register
2830 kvmppc_msr_interrupt:
2831 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2832 cmpwi r0, 2 /* Check if we are in transactional state.. */
2833 ld r11, VCPU_INTR_MSR(r9)
2835 /* ... if transactional, change to suspended */
2837 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2841 * This works around a hardware bug on POWER8E processors, where
2842 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
2843 * performance monitor interrupt. Instead, when we need to have
2844 * an interrupt pending, we have to arrange for a counter to overflow.
2848 mtspr SPRN_MMCR2, r3
2849 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
2850 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
2851 mtspr SPRN_MMCR0, r3
2858 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2860 * Start timing an activity
2861 * r3 = pointer to time accumulation struct, r4 = vcpu
2864 ld r5, HSTATE_KVM_VCORE(r13)
2865 lbz r6, VCORE_IN_GUEST(r5)
2867 beq 5f /* if in guest, need to */
2868 ld r6, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
2871 std r3, VCPU_CUR_ACTIVITY(r4)
2872 std r5, VCPU_ACTIVITY_START(r4)
2876 * Accumulate time to one activity and start another.
2877 * r3 = pointer to new time accumulation struct, r4 = vcpu
2879 kvmhv_accumulate_time:
2880 ld r5, HSTATE_KVM_VCORE(r13)
2881 lbz r8, VCORE_IN_GUEST(r5)
2883 beq 4f /* if in guest, need to */
2884 ld r8, VCORE_TB_OFFSET(r5) /* subtract timebase offset */
2885 4: ld r5, VCPU_CUR_ACTIVITY(r4)
2886 ld r6, VCPU_ACTIVITY_START(r4)
2887 std r3, VCPU_CUR_ACTIVITY(r4)
2890 std r7, VCPU_ACTIVITY_START(r4)
2894 ld r8, TAS_SEQCOUNT(r5)
2897 std r8, TAS_SEQCOUNT(r5)
2899 ld r7, TAS_TOTAL(r5)
2901 std r7, TAS_TOTAL(r5)
2907 3: std r3, TAS_MIN(r5)
2913 std r8, TAS_SEQCOUNT(r5)