1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
6 * Derived from book3s_rmhandlers.S and other files, which are:
8 * Copyright SUSE Linux Products GmbH 2009
10 * Authors: Alexander Graf <agraf@suse.de>
13 #include <asm/ppc_asm.h>
14 #include <asm/code-patching-asm.h>
15 #include <asm/kvm_asm.h>
19 #include <asm/ptrace.h>
20 #include <asm/hvcall.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/exception-64s.h>
23 #include <asm/kvm_book3s_asm.h>
24 #include <asm/book3s/64/mmu-hash.h>
25 #include <asm/export.h>
28 #include <asm/xive-regs.h>
29 #include <asm/thread_info.h>
30 #include <asm/asm-compat.h>
31 #include <asm/feature-fixups.h>
32 #include <asm/cpuidle.h>
33 #include <asm/ultravisor-api.h>
35 /* Sign-extend HDEC if not on POWER9 */
36 #define EXTEND_HDEC(reg) \
39 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
41 /* Values in HSTATE_NAPPING(r13) */
42 #define NAPPING_CEDE 1
43 #define NAPPING_NOVCPU 2
44 #define NAPPING_UNSPLIT 3
46 /* Stack frame offsets for kvmppc_hv_entry */
48 #define STACK_SLOT_TRAP (SFS-4)
49 #define STACK_SLOT_SHORT_PATH (SFS-8)
50 #define STACK_SLOT_TID (SFS-16)
51 #define STACK_SLOT_PSSCR (SFS-24)
52 #define STACK_SLOT_PID (SFS-32)
53 #define STACK_SLOT_IAMR (SFS-40)
54 #define STACK_SLOT_CIABR (SFS-48)
55 #define STACK_SLOT_DAWR (SFS-56)
56 #define STACK_SLOT_DAWRX (SFS-64)
57 #define STACK_SLOT_HFSCR (SFS-72)
58 #define STACK_SLOT_AMR (SFS-80)
59 #define STACK_SLOT_UAMOR (SFS-88)
60 /* the following is used by the P9 short path */
61 #define STACK_SLOT_NVGPRS (SFS-152) /* 18 gprs */
64 * Call kvmppc_hv_entry in real mode.
65 * Must be called with interrupts hard-disabled.
69 * LR = return address to continue at after eventually re-enabling MMU
71 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
73 std r0, PPC_LR_STKOFF(r1)
76 std r10, HSTATE_HOST_MSR(r13)
77 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
82 mtmsrd r0,1 /* clear RI in MSR */
89 /* On P9, do LPCR setting, if necessary */
90 ld r3, HSTATE_SPLIT_MODE(r13)
93 lwz r4, KVM_SPLIT_DO_SET(r3)
99 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
101 ld r4, HSTATE_KVM_VCPU(r13)
104 /* Back from guest - restore host state and return to caller */
107 /* Restore host DABR and DABRX */
108 ld r5,HSTATE_DABR(r13)
112 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
115 ld r3,PACA_SPRG_VDSO(r13)
116 mtspr SPRN_SPRG_VDSO_WRITE,r3
118 /* Reload the host's PMU registers */
119 bl kvmhv_load_host_pmu
122 * Reload DEC. HDEC interrupts were disabled when
123 * we reloaded the host's LPCR value.
125 ld r3, HSTATE_DECEXP(r13)
130 /* hwthread_req may have got set by cede or no vcpu, so clear it */
132 stb r0, HSTATE_HWTHREAD_REQ(r13)
135 * For external interrupts we need to call the Linux
136 * handler to process the interrupt. We do that by jumping
137 * to absolute address 0x500 for external interrupts.
138 * The [h]rfid at the end of the handler will return to
139 * the book3s_hv_interrupts.S code. For other interrupts
140 * we do the rfid to get back to the book3s_hv_interrupts.S
143 ld r8, 112+PPC_LR_STKOFF(r1)
145 ld r7, HSTATE_HOST_MSR(r13)
147 /* Return the trap number on this thread as the return value */
151 * If we came back from the guest via a relocation-on interrupt,
152 * we will be in virtual mode at this point, which makes it a
153 * little easier to get back to the caller.
156 andi. r0, r0, MSR_IR /* in real mode? */
159 /* RFI into the highmem handler */
163 mtmsrd r6, 1 /* Clear RI in MSR */
168 /* Virtual-mode return */
173 kvmppc_primary_no_guest:
174 /* We handle this much like a ceded vcpu */
175 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
176 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
177 /* HDEC value came from DEC in the first place, it will fit */
181 * Make sure the primary has finished the MMU switch.
182 * We should never get here on a secondary thread, but
183 * check it for robustness' sake.
185 ld r5, HSTATE_KVM_VCORE(r13)
186 65: lbz r0, VCORE_IN_GUEST(r5)
193 /* set our bit in napping_threads */
194 ld r5, HSTATE_KVM_VCORE(r13)
195 lbz r7, HSTATE_PTID(r13)
198 addi r6, r5, VCORE_NAPPING_THREADS
203 /* order napping_threads update vs testing entry_exit_map */
206 lwz r7, VCORE_ENTRY_EXIT(r5)
208 bge kvm_novcpu_exit /* another thread already exiting */
209 li r3, NAPPING_NOVCPU
210 stb r3, HSTATE_NAPPING(r13)
212 li r3, 0 /* Don't wake on privileged (OS) doorbell */
217 * Entered from kvm_start_guest if kvm_hstate.napping is set
223 ld r1, HSTATE_HOST_R1(r13)
224 ld r5, HSTATE_KVM_VCORE(r13)
226 stb r0, HSTATE_NAPPING(r13)
228 /* check the wake reason */
229 bl kvmppc_check_wake_reason
232 * Restore volatile registers since we could have called
233 * a C routine in kvmppc_check_wake_reason.
236 ld r5, HSTATE_KVM_VCORE(r13)
238 /* see if any other thread is already exiting */
239 lwz r0, VCORE_ENTRY_EXIT(r5)
243 /* clear our bit in napping_threads */
244 lbz r7, HSTATE_PTID(r13)
247 addi r6, r5, VCORE_NAPPING_THREADS
253 /* See if the wake reason means we need to exit */
257 /* See if our timeslice has expired (HDEC is negative) */
260 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
264 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
265 ld r4, HSTATE_KVM_VCPU(r13)
267 beq kvmppc_primary_no_guest
269 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
270 addi r3, r4, VCPU_TB_RMENTRY
271 bl kvmhv_start_timing
276 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
277 ld r4, HSTATE_KVM_VCPU(r13)
280 addi r3, r4, VCPU_TB_RMEXIT
281 bl kvmhv_accumulate_time
284 stw r12, STACK_SLOT_TRAP(r1)
285 bl kvmhv_commence_exit
287 b kvmhv_switch_to_host
290 * We come in here when wakened from Linux offline idle code.
292 * r3 contains the SRR1 wakeup value, SRR1 is trashed.
294 _GLOBAL(idle_kvm_start_guest)
297 std r5, 8(r1) // Save CR in caller's frame
298 std r0, 16(r1) // Save LR in caller's frame
299 // Create frame on emergency stack
300 ld r4, PACAEMERGSP(r13)
301 stdu r1, -SWITCH_FRAME_SIZE(r4)
302 // Switch to new frame on emergency stack
304 std r3, 32(r1) // Save SRR1 wakeup value
308 * Could avoid this and pass it through in r3. For now,
309 * code expects it to be in SRR1.
314 stb r0,PACA_FTRACE_ENABLED(r13)
316 li r0,KVM_HWTHREAD_IN_KVM
317 stb r0,HSTATE_HWTHREAD_STATE(r13)
319 /* kvm cede / napping does not come through here */
320 lbz r0,HSTATE_NAPPING(r13)
327 stb r0, HSTATE_NAPPING(r13)
332 * We weren't napping due to cede, so this must be a secondary
333 * thread being woken up to run a guest, or being woken up due
334 * to a stray IPI. (Or due to some machine check or hypervisor
335 * maintenance interrupt while the core is in KVM.)
338 /* Check the wake reason in SRR1 to see why we got here */
339 bl kvmppc_check_wake_reason
341 * kvmppc_check_wake_reason could invoke a C routine, but we
342 * have no volatile registers to restore when we return.
348 /* get vcore pointer, NULL if we have nothing to run */
349 ld r5,HSTATE_KVM_VCORE(r13)
351 /* if we have no vcore to run, go back to sleep */
354 kvm_secondary_got_guest:
356 // About to go to guest, clear saved SRR1
360 /* Set HSTATE_DSCR(r13) to something sensible */
361 ld r6, PACA_DSCR_DEFAULT(r13)
362 std r6, HSTATE_DSCR(r13)
364 /* On thread 0 of a subcore, set HDEC to max */
365 lbz r4, HSTATE_PTID(r13)
368 LOAD_REG_ADDR(r6, decrementer_max)
371 /* and set per-LPAR registers, if doing dynamic micro-threading */
372 ld r6, HSTATE_SPLIT_MODE(r13)
376 ld r0, KVM_SPLIT_RPR(r6)
378 ld r0, KVM_SPLIT_PMMAR(r6)
380 ld r0, KVM_SPLIT_LDBAR(r6)
384 /* On P9 we use the split_info for coordinating LPCR changes */
385 lwz r4, KVM_SPLIT_DO_SET(r6)
392 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
394 /* Order load of vcpu after load of vcore */
396 ld r4, HSTATE_KVM_VCPU(r13)
399 /* Back from the guest, go back to nap */
400 /* Clear our vcpu and vcore pointers so we don't come back in early */
402 std r0, HSTATE_KVM_VCPU(r13)
404 * Once we clear HSTATE_KVM_VCORE(r13), the code in
405 * kvmppc_run_core() is going to assume that all our vcpu
406 * state is visible in memory. This lwsync makes sure
410 std r0, HSTATE_KVM_VCORE(r13)
413 * All secondaries exiting guest will fall through this path.
414 * Before proceeding, just check for HMI interrupt and
415 * invoke opal hmi handler. By now we are sure that the
416 * primary thread on this core/subcore has already made partition
417 * switch/TB resync and we are good to call opal hmi handler.
419 cmpwi r12, BOOK3S_INTERRUPT_HMI
422 li r3,0 /* NULL argument */
423 bl hmi_exception_realmode
425 * At this point we have finished executing in the guest.
426 * We need to wait for hwthread_req to become zero, since
427 * we may not turn on the MMU while hwthread_req is non-zero.
428 * While waiting we also need to check if we get given a vcpu to run.
431 lbz r3, HSTATE_HWTHREAD_REQ(r13)
435 li r0, KVM_HWTHREAD_IN_KERNEL
436 stb r0, HSTATE_HWTHREAD_STATE(r13)
437 /* need to recheck hwthread_req after a barrier, to avoid race */
439 lbz r3, HSTATE_HWTHREAD_REQ(r13)
444 * Jump to idle_return_gpr_loss, which returns to the
445 * idle_kvm_start_guest caller.
449 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
451 // Return SRR1 wakeup value, or 0 if we went into the guest
454 ld r1, 0(r1) // Switch back to caller stack
455 ld r0, 16(r1) // Reload LR
456 ld r5, 8(r1) // Reload CR
462 ld r5, HSTATE_KVM_VCORE(r13)
465 ld r3, HSTATE_SPLIT_MODE(r13)
468 lwz r0, KVM_SPLIT_DO_SET(r3)
471 lwz r0, KVM_SPLIT_DO_RESTORE(r3)
474 lbz r0, KVM_SPLIT_DO_NAP(r3)
480 b kvm_secondary_got_guest
482 54: li r0, KVM_HWTHREAD_IN_KVM
483 stb r0, HSTATE_HWTHREAD_STATE(r13)
487 /* Set LPCR, LPIDR etc. on P9 */
495 bl kvmhv_p9_restore_lpcr
500 * Here the primary thread is trying to return the core to
501 * whole-core mode, so we need to nap.
505 * When secondaries are napping in kvm_unsplit_nap() with
506 * hwthread_req = 1, HMI goes ignored even though subcores are
507 * already exited the guest. Hence HMI keeps waking up secondaries
508 * from nap in a loop and secondaries always go back to nap since
509 * no vcore is assigned to them. This makes impossible for primary
510 * thread to get hold of secondary threads resulting into a soft
511 * lockup in KVM path.
513 * Let us check if HMI is pending and handle it before we go to nap.
515 cmpwi r12, BOOK3S_INTERRUPT_HMI
517 li r3, 0 /* NULL argument */
518 bl hmi_exception_realmode
521 * Ensure that secondary doesn't nap when it has
522 * its vcore pointer set.
524 sync /* matches smp_mb() before setting split_info.do_nap */
525 ld r0, HSTATE_KVM_VCORE(r13)
528 /* clear any pending message */
530 lis r6, (PPC_DBELL_SERVER << (63-36))@h
532 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
533 /* Set kvm_split_mode.napped[tid] = 1 */
534 ld r3, HSTATE_SPLIT_MODE(r13)
536 lbz r4, HSTATE_TID(r13)
537 addi r4, r4, KVM_SPLIT_NAPPED
539 /* Check the do_nap flag again after setting napped[] */
541 lbz r0, KVM_SPLIT_DO_NAP(r3)
544 li r3, NAPPING_UNSPLIT
545 stb r3, HSTATE_NAPPING(r13)
546 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
548 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
555 /******************************************************************************
559 *****************************************************************************/
561 .global kvmppc_hv_entry
566 * R4 = vcpu pointer (or NULL)
571 * all other volatile GPRS = free
572 * Does not preserve non-volatile GPRs or CR fields
575 std r0, PPC_LR_STKOFF(r1)
578 /* Save R1 in the PACA */
579 std r1, HSTATE_HOST_R1(r13)
581 li r6, KVM_GUEST_MODE_HOST_HV
582 stb r6, HSTATE_IN_GUEST(r13)
584 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
585 /* Store initial timestamp */
588 addi r3, r4, VCPU_TB_RMENTRY
589 bl kvmhv_start_timing
593 ld r5, HSTATE_KVM_VCORE(r13)
594 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
597 * POWER7/POWER8 host -> guest partition switch code.
598 * We don't have to lock against concurrent tlbies,
599 * but we do have to coordinate across hardware threads.
601 /* Set bit in entry map iff exit map is zero. */
603 lbz r6, HSTATE_PTID(r13)
605 addi r8, r5, VCORE_ENTRY_EXIT
607 cmpwi r3, 0x100 /* any threads starting to exit? */
608 bge secondary_too_late /* if so we're too late to the party */
613 /* Primary thread switches to guest partition. */
620 li r0,LPID_RSVD /* switch to reserved LPID */
623 mtspr SPRN_SDR1,r6 /* switch to partition page table */
624 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
628 /* See if we need to flush the TLB. */
629 mr r3, r9 /* kvm pointer */
630 lhz r4, PACAPACAINDEX(r13) /* physical cpu number */
631 li r5, 0 /* nested vcpu pointer */
632 bl kvmppc_check_need_tlb_flush
634 ld r5, HSTATE_KVM_VCORE(r13)
636 /* Add timebase offset onto timebase */
637 22: ld r8,VCORE_TB_OFFSET(r5)
640 std r8, VCORE_TB_OFFSET_APPL(r5)
641 mftb r6 /* current host timebase */
643 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
644 mftb r7 /* check if lower 24 bits overflowed */
649 addis r8,r8,0x100 /* if so, increment upper 40 bits */
652 /* Load guest PCR value to select appropriate compat mode */
653 37: ld r7, VCORE_PCR(r5)
654 LOAD_REG_IMMEDIATE(r6, PCR_MASK)
662 /* DPDES and VTB are shared between threads */
663 ld r8, VCORE_DPDES(r5)
667 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
669 /* Mark the subcore state as inside guest */
670 bl kvmppc_subcore_enter_guest
672 ld r5, HSTATE_KVM_VCORE(r13)
673 ld r4, HSTATE_KVM_VCPU(r13)
675 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
677 /* Do we have a guest vcpu to run? */
679 beq kvmppc_primary_no_guest
681 /* Increment yield count if they have a VPA */
685 li r6, LPPACA_YIELDCOUNT
690 stb r6, VCPU_VPA_DIRTY(r4)
693 /* Save purr/spurr */
696 std r5,HSTATE_PURR(r13)
697 std r6,HSTATE_SPURR(r13)
703 /* Save host values of some registers */
708 std r5, STACK_SLOT_TID(r1)
709 std r6, STACK_SLOT_PSSCR(r1)
710 std r7, STACK_SLOT_PID(r1)
712 std r5, STACK_SLOT_HFSCR(r1)
713 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
717 mfspr r7, SPRN_DAWRX0
719 std r5, STACK_SLOT_CIABR(r1)
720 std r6, STACK_SLOT_DAWR(r1)
721 std r7, STACK_SLOT_DAWRX(r1)
722 std r8, STACK_SLOT_IAMR(r1)
723 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
726 std r5, STACK_SLOT_AMR(r1)
728 std r6, STACK_SLOT_UAMOR(r1)
731 /* Set partition DABR */
732 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
733 lwz r5,VCPU_DABRX(r4)
738 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
740 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
742 * Branch around the call if both CPU_FTR_TM and
743 * CPU_FTR_P9_TM_HV_ASSIST are off.
747 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
749 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
753 li r5, 0 /* don't preserve non-vol regs */
754 bl kvmppc_restore_tm_hv
756 ld r4, HSTATE_KVM_VCPU(r13)
760 /* Load guest PMU registers; r4 = vcpu pointer here */
762 bl kvmhv_load_guest_pmu
764 /* Load up FP, VMX and VSX registers */
765 ld r4, HSTATE_KVM_VCPU(r13)
768 ld r14, VCPU_GPR(R14)(r4)
769 ld r15, VCPU_GPR(R15)(r4)
770 ld r16, VCPU_GPR(R16)(r4)
771 ld r17, VCPU_GPR(R17)(r4)
772 ld r18, VCPU_GPR(R18)(r4)
773 ld r19, VCPU_GPR(R19)(r4)
774 ld r20, VCPU_GPR(R20)(r4)
775 ld r21, VCPU_GPR(R21)(r4)
776 ld r22, VCPU_GPR(R22)(r4)
777 ld r23, VCPU_GPR(R23)(r4)
778 ld r24, VCPU_GPR(R24)(r4)
779 ld r25, VCPU_GPR(R25)(r4)
780 ld r26, VCPU_GPR(R26)(r4)
781 ld r27, VCPU_GPR(R27)(r4)
782 ld r28, VCPU_GPR(R28)(r4)
783 ld r29, VCPU_GPR(R29)(r4)
784 ld r30, VCPU_GPR(R30)(r4)
785 ld r31, VCPU_GPR(R31)(r4)
787 /* Switch DSCR to guest value */
792 /* Skip next section on POWER7 */
794 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
795 /* Load up POWER8-specific registers */
797 lwz r6, VCPU_PSPB(r4)
803 * Handle broken DAWR case by not writing it. This means we
804 * can still store the DAWR register for migration.
806 LOAD_REG_ADDR(r5, dawr_force_enable)
811 ld r6, VCPU_DAWRX(r4)
813 mtspr SPRN_DAWRX0, r6
815 ld r7, VCPU_CIABR(r4)
820 ld r8, VCPU_EBBHR(r4)
823 ld r5, VCPU_EBBRR(r4)
824 ld r6, VCPU_BESCR(r4)
825 lwz r7, VCPU_GUEST_PID(r4)
832 /* POWER8-only registers */
833 ld r5, VCPU_TCSCR(r4)
835 ld r7, VCPU_CSIGR(r4)
843 /* POWER9-only registers */
845 ld r6, VCPU_PSSCR(r4)
846 lbz r8, HSTATE_FAKE_SUSPEND(r13)
847 oris r6, r6, PSSCR_EC@h /* This makes stop trap to HV */
848 rldimi r6, r8, PSSCR_FAKE_SUSPEND_LG, 63 - PSSCR_FAKE_SUSPEND_LG
849 ld r7, VCPU_HFSCR(r4)
853 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
856 ld r5, VCPU_SPRG0(r4)
857 ld r6, VCPU_SPRG1(r4)
858 ld r7, VCPU_SPRG2(r4)
859 ld r8, VCPU_SPRG3(r4)
865 /* Load up DAR and DSISR */
867 lwz r6, VCPU_DSISR(r4)
871 /* Restore AMR and UAMOR, set AMOR to all 1s */
879 /* Restore state of CTRL run bit; assume 1 on entry */
887 /* Secondary threads wait for primary to have done partition switch */
888 ld r5, HSTATE_KVM_VCORE(r13)
889 lbz r6, HSTATE_PTID(r13)
892 lbz r0, VCORE_IN_GUEST(r5)
896 20: lwz r3, VCORE_ENTRY_EXIT(r5)
899 lbz r0, VCORE_IN_GUEST(r5)
910 * Set the decrementer to the guest decrementer.
912 ld r8,VCPU_DEC_EXPIRES(r4)
913 /* r8 is a host timebase value here, convert to guest TB */
914 ld r5,HSTATE_KVM_VCORE(r13)
915 ld r6,VCORE_TB_OFFSET_APPL(r5)
921 /* Check if HDEC expires soon */
924 cmpdi r3, 512 /* 1 microsecond */
927 /* For hash guest, clear out and reload the SLB */
929 lbz r0, KVM_RADIX(r6)
937 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
938 lwz r5,VCPU_SLB_MAX(r4)
943 1: ld r8,VCPU_SLB_E(r6)
946 addi r6,r6,VCPU_SLB_SIZE
950 #ifdef CONFIG_KVM_XICS
951 /* We are entering the guest on that thread, push VCPU to XIVE */
952 ld r11, VCPU_XIVE_SAVED_STATE(r4)
954 lwz r8, VCPU_XIVE_CAM_WORD(r4)
957 li r7, TM_QW1_OS + TM_WORD2
959 andi. r0, r0, MSR_DR /* in real mode? */
961 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
968 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
975 stb r9, VCPU_XIVE_PUSHED(r4)
979 * We clear the irq_pending flag. There is a small chance of a
980 * race vs. the escalation interrupt happening on another
981 * processor setting it again, but the only consequence is to
982 * cause a spurrious wakeup on the next H_CEDE which is not an
986 stb r0, VCPU_IRQ_PENDING(r4)
989 * In single escalation mode, if the escalation interrupt is
992 lbz r0, VCPU_XIVE_ESC_ON(r4)
995 li r9, XIVE_ESB_SET_PQ_01
996 beq 4f /* in real mode? */
997 ld r10, VCPU_XIVE_ESC_VADDR(r4)
1000 4: ld r10, VCPU_XIVE_ESC_RADDR(r4)
1004 /* We have a possible subtle race here: The escalation interrupt might
1005 * have fired and be on its way to the host queue while we mask it,
1006 * and if we unmask it early enough (re-cede right away), there is
1007 * a theorical possibility that it fires again, thus landing in the
1008 * target queue more than once which is a big no-no.
1010 * Fortunately, solving this is rather easy. If the above load setting
1011 * PQ to 01 returns a previous value where P is set, then we know the
1012 * escalation interrupt is somewhere on its way to the host. In that
1013 * case we simply don't clear the xive_esc_on flag below. It will be
1014 * eventually cleared by the handler for the escalation interrupt.
1016 * Then, when doing a cede, we check that flag again before re-enabling
1017 * the escalation interrupt, and if set, we abort the cede.
1019 andi. r0, r0, XIVE_ESB_VAL_P
1022 /* Now P is 0, we can clear the flag */
1024 stb r0, VCPU_XIVE_ESC_ON(r4)
1027 #endif /* CONFIG_KVM_XICS */
1030 stw r0, STACK_SLOT_SHORT_PATH(r1)
1032 deliver_guest_interrupt: /* r4 = vcpu, r13 = paca */
1033 /* Check if we can deliver an external or decrementer interrupt now */
1034 ld r0, VCPU_PENDING_EXC(r4)
1036 /* On POWER9, also check for emulated doorbell interrupt */
1037 lbz r3, VCPU_DBELL_REQ(r4)
1039 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1043 bl kvmppc_guest_entry_inject_int
1044 ld r4, HSTATE_KVM_VCPU(r13)
1046 ld r6, VCPU_SRR0(r4)
1047 ld r7, VCPU_SRR1(r4)
1053 ld r11, VCPU_MSR(r4)
1054 /* r11 = vcpu->arch.msr & ~MSR_HV */
1055 rldicl r11, r11, 63 - MSR_HV_LG, 1
1056 rotldi r11, r11, 1 + MSR_HV_LG
1057 ori r11, r11, MSR_ME
1067 * R10: value for HSRR0
1068 * R11: value for HSRR1
1073 stb r0,VCPU_CEDED(r4) /* cancel cede */
1074 mtspr SPRN_HSRR0,r10
1075 mtspr SPRN_HSRR1,r11
1077 /* Activate guest mode, so faults get handled by KVM */
1078 li r9, KVM_GUEST_MODE_GUEST_HV
1079 stb r9, HSTATE_IN_GUEST(r13)
1081 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1082 /* Accumulate timing */
1083 addi r3, r4, VCPU_TB_GUEST
1084 bl kvmhv_accumulate_time
1090 ld r5, VCPU_CFAR(r4)
1092 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1095 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1100 ld r1, VCPU_GPR(R1)(r4)
1101 ld r5, VCPU_GPR(R5)(r4)
1102 ld r8, VCPU_GPR(R8)(r4)
1103 ld r9, VCPU_GPR(R9)(r4)
1104 ld r10, VCPU_GPR(R10)(r4)
1105 ld r11, VCPU_GPR(R11)(r4)
1106 ld r12, VCPU_GPR(R12)(r4)
1107 ld r13, VCPU_GPR(R13)(r4)
1111 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1113 /* Move canary into DSISR to check for later */
1116 mtspr SPRN_HDSISR, r0
1117 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1120 lbz r7, KVM_SECURE_GUEST(r6)
1122 ld r6, VCPU_GPR(R6)(r4)
1123 ld r7, VCPU_GPR(R7)(r4)
1129 ld r0, VCPU_GPR(R0)(r4)
1130 ld r2, VCPU_GPR(R2)(r4)
1131 ld r3, VCPU_GPR(R3)(r4)
1132 ld r4, VCPU_GPR(R4)(r4)
1136 * Use UV_RETURN ultracall to return control back to the Ultravisor after
1137 * processing an hypercall or interrupt that was forwarded (a.k.a. reflected)
1138 * to the Hypervisor.
1140 * All registers have already been loaded, except:
1142 * R2 = SRR1, so UV can detect a synthesized interrupt (if any)
1149 ld r0, VCPU_GPR(R3)(r4)
1152 ori r3, r3, UV_RETURN
1153 ld r4, VCPU_GPR(R4)(r4)
1157 * Enter the guest on a P9 or later system where we have exactly
1158 * one vcpu per vcore and we don't need to go to real mode
1159 * (which implies that host and guest are both using radix MMU mode).
1161 * Most SPRs and all the VSRs have been loaded already.
1163 _GLOBAL(__kvmhv_vcpu_entry_p9)
1164 EXPORT_SYMBOL_GPL(__kvmhv_vcpu_entry_p9)
1166 std r0, PPC_LR_STKOFF(r1)
1170 stw r0, STACK_SLOT_SHORT_PATH(r1)
1172 std r3, HSTATE_KVM_VCPU(r13)
1176 std r1, HSTATE_HOST_R1(r13)
1180 std reg, STACK_SLOT_NVGPRS + ((reg - 14) * 8)(r1)
1186 ld reg, __VCPU_GPR(reg)(r3)
1191 std r10, HSTATE_HOST_MSR(r13)
1194 b fast_guest_entry_c
1195 guest_exit_short_path:
1197 li r0, KVM_GUEST_MODE_NONE
1198 stb r0, HSTATE_IN_GUEST(r13)
1202 std reg, __VCPU_GPR(reg)(r9)
1208 ld reg, STACK_SLOT_NVGPRS + ((reg - 14) * 8)(r1)
1215 mr r3, r12 /* trap number */
1218 ld r0, PPC_LR_STKOFF(r1)
1221 /* If we are in real mode, do a rfid to get back to the caller */
1223 andi. r5, r4, MSR_IR
1225 rldicl r5, r4, 64 - MSR_TS_S_LG, 62 /* extract TS field */
1227 ld r10, HSTATE_HOST_MSR(r13)
1228 rldimi r10, r5, MSR_TS_S_LG, 63 - MSR_TS_T_LG
1229 mtspr SPRN_SRR1, r10
1235 stw r12, STACK_SLOT_TRAP(r1)
1238 stw r12, VCPU_TRAP(r4)
1239 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1240 addi r3, r4, VCPU_TB_RMEXIT
1241 bl kvmhv_accumulate_time
1243 11: b kvmhv_switch_to_host
1250 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
1251 12: stw r12, VCPU_TRAP(r4)
1253 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1254 addi r3, r4, VCPU_TB_RMEXIT
1255 bl kvmhv_accumulate_time
1259 /******************************************************************************
1263 *****************************************************************************/
1266 * We come here from the first-level interrupt handlers.
1268 .globl kvmppc_interrupt_hv
1269 kvmppc_interrupt_hv:
1271 * Register contents:
1272 * R12 = (guest CR << 32) | interrupt vector
1274 * guest R12 saved in shadow VCPU SCRATCH0
1275 * guest R13 saved in SPRN_SCRATCH0
1277 std r9, HSTATE_SCRATCH2(r13)
1278 lbz r9, HSTATE_IN_GUEST(r13)
1279 cmpwi r9, KVM_GUEST_MODE_HOST_HV
1280 beq kvmppc_bad_host_intr
1281 #ifdef CONFIG_KVM_BOOK3S_PR_POSSIBLE
1282 cmpwi r9, KVM_GUEST_MODE_GUEST
1283 ld r9, HSTATE_SCRATCH2(r13)
1284 beq kvmppc_interrupt_pr
1286 /* We're now back in the host but in guest MMU context */
1287 li r9, KVM_GUEST_MODE_HOST_HV
1288 stb r9, HSTATE_IN_GUEST(r13)
1290 ld r9, HSTATE_KVM_VCPU(r13)
1292 /* Save registers */
1294 std r0, VCPU_GPR(R0)(r9)
1295 std r1, VCPU_GPR(R1)(r9)
1296 std r2, VCPU_GPR(R2)(r9)
1297 std r3, VCPU_GPR(R3)(r9)
1298 std r4, VCPU_GPR(R4)(r9)
1299 std r5, VCPU_GPR(R5)(r9)
1300 std r6, VCPU_GPR(R6)(r9)
1301 std r7, VCPU_GPR(R7)(r9)
1302 std r8, VCPU_GPR(R8)(r9)
1303 ld r0, HSTATE_SCRATCH2(r13)
1304 std r0, VCPU_GPR(R9)(r9)
1305 std r10, VCPU_GPR(R10)(r9)
1306 std r11, VCPU_GPR(R11)(r9)
1307 ld r3, HSTATE_SCRATCH0(r13)
1308 std r3, VCPU_GPR(R12)(r9)
1309 /* CR is in the high half of r12 */
1313 ld r3, HSTATE_CFAR(r13)
1314 std r3, VCPU_CFAR(r9)
1315 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1317 ld r4, HSTATE_PPR(r13)
1318 std r4, VCPU_PPR(r9)
1319 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1321 /* Restore R1/R2 so we can handle faults */
1322 ld r1, HSTATE_HOST_R1(r13)
1325 mfspr r10, SPRN_SRR0
1326 mfspr r11, SPRN_SRR1
1327 std r10, VCPU_SRR0(r9)
1328 std r11, VCPU_SRR1(r9)
1329 /* trap is in the low half of r12, clear CR from the high half */
1331 andi. r0, r12, 2 /* need to read HSRR0/1? */
1333 mfspr r10, SPRN_HSRR0
1334 mfspr r11, SPRN_HSRR1
1336 1: std r10, VCPU_PC(r9)
1337 std r11, VCPU_MSR(r9)
1341 std r3, VCPU_GPR(R13)(r9)
1344 stw r12,VCPU_TRAP(r9)
1347 * Now that we have saved away SRR0/1 and HSRR0/1,
1348 * interrupts are recoverable in principle, so set MSR_RI.
1349 * This becomes important for relocation-on interrupts from
1350 * the guest, which we can get in radix mode on POWER9.
1355 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1356 addi r3, r9, VCPU_TB_RMINTR
1358 bl kvmhv_accumulate_time
1359 ld r5, VCPU_GPR(R5)(r9)
1360 ld r6, VCPU_GPR(R6)(r9)
1361 ld r7, VCPU_GPR(R7)(r9)
1362 ld r8, VCPU_GPR(R8)(r9)
1365 /* Save HEIR (HV emulation assist reg) in emul_inst
1366 if this is an HEI (HV emulation interrupt, e40) */
1367 li r3,KVM_INST_FETCH_FAILED
1368 stw r3,VCPU_LAST_INST(r9)
1369 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1372 11: stw r3,VCPU_HEIR(r9)
1374 /* these are volatile across C function calls */
1377 std r3, VCPU_CTR(r9)
1378 std r4, VCPU_XER(r9)
1380 /* Save more register state */
1383 std r3, VCPU_DAR(r9)
1384 stw r4, VCPU_DSISR(r9)
1386 /* If this is a page table miss then see if it's theirs or ours */
1387 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1389 std r3, VCPU_FAULT_DAR(r9)
1390 stw r4, VCPU_FAULT_DSISR(r9)
1391 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1394 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1395 /* For softpatch interrupt, go off and do TM instruction emulation */
1396 cmpwi r12, BOOK3S_INTERRUPT_HV_SOFTPATCH
1400 /* See if this is a leftover HDEC interrupt */
1401 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1407 bge fast_guest_return
1409 /* See if this is an hcall we can handle in real mode */
1410 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1411 beq hcall_try_real_mode
1413 /* Hypervisor doorbell - exit only if host IPI flag set */
1414 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1419 /* always exit if we're running a nested guest */
1420 ld r0, VCPU_NESTED(r9)
1423 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1424 lbz r0, HSTATE_HOST_IPI(r13)
1426 beq maybe_reenter_guest
1429 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1430 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1432 mfspr r3, SPRN_HFSCR
1433 std r3, VCPU_HFSCR(r9)
1436 /* External interrupt ? */
1437 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1438 beq kvmppc_guest_external
1439 /* See if it is a machine check */
1440 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1441 beq machine_check_realmode
1442 /* Or a hypervisor maintenance interrupt */
1443 cmpwi r12, BOOK3S_INTERRUPT_HMI
1446 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1448 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1449 addi r3, r9, VCPU_TB_RMEXIT
1451 bl kvmhv_accumulate_time
1453 #ifdef CONFIG_KVM_XICS
1454 /* We are exiting, pull the VP from the XIVE */
1455 lbz r0, VCPU_XIVE_PUSHED(r9)
1458 li r7, TM_SPC_PULL_OS_CTX
1461 andi. r0, r0, MSR_DR /* in real mode? */
1463 ld r10, HSTATE_XIVE_TIMA_VIRT(r13)
1466 /* First load to pull the context, we ignore the value */
1469 /* Second load to recover the context state (Words 0 and 1) */
1472 2: ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
1475 /* First load to pull the context, we ignore the value */
1478 /* Second load to recover the context state (Words 0 and 1) */
1480 3: std r11, VCPU_XIVE_SAVED_STATE(r9)
1481 /* Fixup some of the state for the next load */
1484 stb r10, VCPU_XIVE_PUSHED(r9)
1485 stb r10, (VCPU_XIVE_SAVED_STATE+3)(r9)
1486 stb r0, (VCPU_XIVE_SAVED_STATE+4)(r9)
1489 #endif /* CONFIG_KVM_XICS */
1492 * Possibly flush the link stack here, before we do a blr in
1493 * guest_exit_short_path.
1496 patch_site 1b patch__call_kvm_flush_link_stack
1498 /* If we came in through the P9 short path, go back out to C now */
1499 lwz r0, STACK_SLOT_SHORT_PATH(r1)
1501 bne guest_exit_short_path
1503 /* For hash guest, read the guest SLB and save it away */
1505 lbz r0, KVM_RADIX(r5)
1508 bne 3f /* for radix, save 0 entries */
1509 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1514 andis. r0,r8,SLB_ESID_V@h
1516 add r8,r8,r6 /* put index in */
1518 std r8,VCPU_SLB_E(r7)
1519 std r3,VCPU_SLB_V(r7)
1520 addi r7,r7,VCPU_SLB_SIZE
1524 /* Finally clear out the SLB */
1529 3: stw r5,VCPU_SLB_MAX(r9)
1531 /* load host SLB entries */
1532 BEGIN_MMU_FTR_SECTION
1534 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
1535 ld r8,PACA_SLBSHADOWPTR(r13)
1537 .rept SLB_NUM_BOLTED
1538 li r3, SLBSHADOW_SAVEAREA
1542 andis. r7,r5,SLB_ESID_V@h
1550 stw r12, STACK_SLOT_TRAP(r1)
1553 /* Do this before kvmhv_commence_exit so we know TB is guest TB */
1554 ld r3, HSTATE_KVM_VCORE(r13)
1557 /* On P9, if the guest has large decr enabled, don't sign extend */
1559 ld r4, VCORE_LPCR(r3)
1560 andis. r4, r4, LPCR_LD@h
1562 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1565 /* r5 is a guest timebase value here, convert to host TB */
1566 ld r4,VCORE_TB_OFFSET_APPL(r3)
1568 std r5,VCPU_DEC_EXPIRES(r9)
1570 /* Increment exit count, poke other threads to exit */
1572 bl kvmhv_commence_exit
1574 ld r9, HSTATE_KVM_VCPU(r13)
1576 /* Stop others sending VCPU interrupts to this physical CPU */
1578 stw r0, VCPU_CPU(r9)
1579 stw r0, VCPU_THREAD_CPU(r9)
1581 /* Save guest CTRL register, set runlatch to 1 */
1583 stw r6,VCPU_CTRL(r9)
1590 * Save the guest PURR/SPURR
1595 ld r8,VCPU_SPURR(r9)
1596 std r5,VCPU_PURR(r9)
1597 std r6,VCPU_SPURR(r9)
1602 * Restore host PURR/SPURR and add guest times
1603 * so that the time in the guest gets accounted.
1605 ld r3,HSTATE_PURR(r13)
1606 ld r4,HSTATE_SPURR(r13)
1614 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1615 /* Save POWER8-specific registers */
1619 std r5, VCPU_IAMR(r9)
1620 stw r6, VCPU_PSPB(r9)
1621 std r7, VCPU_FSCR(r9)
1625 std r7, VCPU_TAR(r9)
1626 mfspr r8, SPRN_EBBHR
1627 std r8, VCPU_EBBHR(r9)
1628 mfspr r5, SPRN_EBBRR
1629 mfspr r6, SPRN_BESCR
1632 std r5, VCPU_EBBRR(r9)
1633 std r6, VCPU_BESCR(r9)
1634 stw r7, VCPU_GUEST_PID(r9)
1635 std r8, VCPU_WORT(r9)
1637 mfspr r5, SPRN_TCSCR
1639 mfspr r7, SPRN_CSIGR
1641 std r5, VCPU_TCSCR(r9)
1642 std r6, VCPU_ACOP(r9)
1643 std r7, VCPU_CSIGR(r9)
1644 std r8, VCPU_TACR(r9)
1647 mfspr r6, SPRN_PSSCR
1648 std r5, VCPU_TID(r9)
1649 rldicl r6, r6, 4, 50 /* r6 &= PSSCR_GUEST_VIS */
1651 std r6, VCPU_PSSCR(r9)
1652 /* Restore host HFSCR value */
1653 ld r7, STACK_SLOT_HFSCR(r1)
1654 mtspr SPRN_HFSCR, r7
1655 ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
1657 * Restore various registers to 0, where non-zero values
1658 * set by the guest could disrupt the host.
1664 mtspr SPRN_TCSCR, r0
1665 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1668 mtspr SPRN_MMCRS, r0
1669 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1671 /* Save and restore AMR, IAMR and UAMOR before turning on the MMU */
1672 ld r8, STACK_SLOT_IAMR(r1)
1675 8: /* Power7 jumps back in here */
1679 std r6,VCPU_UAMOR(r9)
1680 ld r5,STACK_SLOT_AMR(r1)
1681 ld r6,STACK_SLOT_UAMOR(r1)
1683 mtspr SPRN_UAMOR, r6
1685 /* Switch DSCR back to host value */
1687 ld r7, HSTATE_DSCR(r13)
1688 std r8, VCPU_DSCR(r9)
1691 /* Save non-volatile GPRs */
1692 std r14, VCPU_GPR(R14)(r9)
1693 std r15, VCPU_GPR(R15)(r9)
1694 std r16, VCPU_GPR(R16)(r9)
1695 std r17, VCPU_GPR(R17)(r9)
1696 std r18, VCPU_GPR(R18)(r9)
1697 std r19, VCPU_GPR(R19)(r9)
1698 std r20, VCPU_GPR(R20)(r9)
1699 std r21, VCPU_GPR(R21)(r9)
1700 std r22, VCPU_GPR(R22)(r9)
1701 std r23, VCPU_GPR(R23)(r9)
1702 std r24, VCPU_GPR(R24)(r9)
1703 std r25, VCPU_GPR(R25)(r9)
1704 std r26, VCPU_GPR(R26)(r9)
1705 std r27, VCPU_GPR(R27)(r9)
1706 std r28, VCPU_GPR(R28)(r9)
1707 std r29, VCPU_GPR(R29)(r9)
1708 std r30, VCPU_GPR(R30)(r9)
1709 std r31, VCPU_GPR(R31)(r9)
1712 mfspr r3, SPRN_SPRG0
1713 mfspr r4, SPRN_SPRG1
1714 mfspr r5, SPRN_SPRG2
1715 mfspr r6, SPRN_SPRG3
1716 std r3, VCPU_SPRG0(r9)
1717 std r4, VCPU_SPRG1(r9)
1718 std r5, VCPU_SPRG2(r9)
1719 std r6, VCPU_SPRG3(r9)
1725 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1727 * Branch around the call if both CPU_FTR_TM and
1728 * CPU_FTR_P9_TM_HV_ASSIST are off.
1732 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
1734 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
1738 li r5, 0 /* don't preserve non-vol regs */
1739 bl kvmppc_save_tm_hv
1741 ld r9, HSTATE_KVM_VCPU(r13)
1745 /* Increment yield count if they have a VPA */
1746 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1749 li r4, LPPACA_YIELDCOUNT
1754 stb r3, VCPU_VPA_DIRTY(r9)
1756 /* Save PMU registers if requested */
1757 /* r8 and cr0.eq are live here */
1760 beq 21f /* if no VPA, save PMU stuff anyway */
1761 lbz r4, LPPACA_PMCINUSE(r8)
1762 21: bl kvmhv_save_guest_pmu
1763 ld r9, HSTATE_KVM_VCPU(r13)
1765 /* Restore host values of some registers */
1767 ld r5, STACK_SLOT_CIABR(r1)
1768 ld r6, STACK_SLOT_DAWR(r1)
1769 ld r7, STACK_SLOT_DAWRX(r1)
1770 mtspr SPRN_CIABR, r5
1772 * If the DAWR doesn't work, it's ok to write these here as
1773 * this value should always be zero
1775 mtspr SPRN_DAWR0, r6
1776 mtspr SPRN_DAWRX0, r7
1777 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1779 ld r5, STACK_SLOT_TID(r1)
1780 ld r6, STACK_SLOT_PSSCR(r1)
1781 ld r7, STACK_SLOT_PID(r1)
1783 mtspr SPRN_PSSCR, r6
1785 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1787 #ifdef CONFIG_PPC_RADIX_MMU
1789 * Are we running hash or radix ?
1792 lbz r0, KVM_RADIX(r5)
1797 * Radix: do eieio; tlbsync; ptesync sequence in case we
1798 * interrupted the guest between a tlbie and a ptesync.
1805 /* Radix: Handle the case where the guest used an illegal PID */
1806 LOAD_REG_ADDR(r4, mmu_base_pid)
1807 lwz r3, VCPU_GUEST_PID(r9)
1813 * Illegal PID, the HW might have prefetched and cached in the TLB
1814 * some translations for the LPID 0 / guest PID combination which
1815 * Linux doesn't know about, so we need to flush that PID out of
1816 * the TLB. First we need to set LPIDR to 0 so tlbiel applies to
1817 * the right context.
1823 /* Then do a congruence class local flush */
1825 lwz r0,KVM_TLB_SETS(r6)
1827 li r7,0x400 /* IS field = 0b01 */
1829 sldi r0,r3,32 /* RS has PID */
1830 1: PPC_TLBIEL(7,0,2,1,1) /* RIC=2, PRS=1, R=1 */
1834 END_FTR_SECTION_IFSET(CPU_FTR_P9_RADIX_PREFETCH_BUG)
1837 #endif /* CONFIG_PPC_RADIX_MMU */
1840 * cp_abort is required if the processor supports local copy-paste
1841 * to clear the copy buffer that was under control of the guest.
1845 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
1848 * POWER7/POWER8 guest -> host partition switch code.
1849 * We don't have to lock against tlbies but we do
1850 * have to coordinate the hardware threads.
1851 * Here STACK_SLOT_TRAP(r1) contains the trap number.
1853 kvmhv_switch_to_host:
1854 /* Secondary threads wait for primary to do partition switch */
1855 ld r5,HSTATE_KVM_VCORE(r13)
1856 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1857 lbz r3,HSTATE_PTID(r13)
1861 13: lbz r3,VCORE_IN_GUEST(r5)
1867 /* Primary thread waits for all the secondaries to exit guest */
1868 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1869 rlwinm r0,r3,32-8,0xff
1875 /* Did we actually switch to the guest at all? */
1876 lbz r6, VCORE_IN_GUEST(r5)
1880 /* Primary thread switches back to host partition */
1881 lwz r7,KVM_HOST_LPID(r4)
1883 ld r6,KVM_HOST_SDR1(r4)
1884 li r8,LPID_RSVD /* switch to reserved LPID */
1887 mtspr SPRN_SDR1,r6 /* switch to host page table */
1888 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
1893 /* DPDES and VTB are shared between threads */
1894 mfspr r7, SPRN_DPDES
1896 std r7, VCORE_DPDES(r5)
1897 std r8, VCORE_VTB(r5)
1898 /* clear DPDES so we don't get guest doorbells in the host */
1900 mtspr SPRN_DPDES, r8
1901 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1903 /* Subtract timebase offset from timebase */
1904 ld r8, VCORE_TB_OFFSET_APPL(r5)
1908 std r0, VCORE_TB_OFFSET_APPL(r5)
1909 mftb r6 /* current guest timebase */
1911 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1912 mftb r7 /* check if lower 24 bits overflowed */
1917 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1922 * If this is an HMI, we called kvmppc_realmode_hmi_handler
1923 * above, which may or may not have already called
1924 * kvmppc_subcore_exit_guest. Fortunately, all that
1925 * kvmppc_subcore_exit_guest does is clear a flag, so calling
1926 * it again here is benign even if kvmppc_realmode_hmi_handler
1927 * has already called it.
1929 bl kvmppc_subcore_exit_guest
1931 30: ld r5,HSTATE_KVM_VCORE(r13)
1932 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1935 ld r0, VCORE_PCR(r5)
1936 LOAD_REG_IMMEDIATE(r6, PCR_MASK)
1941 /* Signal secondary CPUs to continue */
1943 stb r0,VCORE_IN_GUEST(r5)
1944 19: lis r8,0x7fff /* MAX_INT@h */
1949 /* On POWER9 with HPT-on-radix we need to wait for all other threads */
1950 ld r3, HSTATE_SPLIT_MODE(r13)
1953 lwz r8, KVM_SPLIT_DO_RESTORE(r3)
1956 bl kvmhv_p9_restore_lpcr
1960 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1961 ld r8,KVM_HOST_LPCR(r4)
1965 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
1966 /* Finish timing, if we have a vcpu */
1967 ld r4, HSTATE_KVM_VCPU(r13)
1971 bl kvmhv_accumulate_time
1974 /* Unset guest mode */
1975 li r0, KVM_GUEST_MODE_NONE
1976 stb r0, HSTATE_IN_GUEST(r13)
1978 lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */
1979 ld r0, SFS+PPC_LR_STKOFF(r1)
1985 .global kvm_flush_link_stack
1986 kvm_flush_link_stack:
1987 /* Save LR into r0 */
1990 /* Flush the link stack. On Power8 it's up to 32 entries in size. */
1995 /* And on Power9 it's up to 64. */
2000 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2006 kvmppc_guest_external:
2007 /* External interrupt, first check for host_ipi. If this is
2008 * set, we know the host wants us out so let's do it now
2013 * Restore the active volatile registers after returning from
2016 ld r9, HSTATE_KVM_VCPU(r13)
2017 li r12, BOOK3S_INTERRUPT_EXTERNAL
2020 * kvmppc_read_intr return codes:
2022 * Exit to host (r3 > 0)
2023 * 1 An interrupt is pending that needs to be handled by the host
2024 * Exit guest and return to host by branching to guest_exit_cont
2026 * 2 Passthrough that needs completion in the host
2027 * Exit guest and return to host by branching to guest_exit_cont
2028 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
2029 * to indicate to the host to complete handling the interrupt
2031 * Before returning to guest, we check if any CPU is heading out
2032 * to the host and if so, we head out also. If no CPUs are heading
2033 * check return values <= 0.
2035 * Return to guest (r3 <= 0)
2036 * 0 No external interrupt is pending
2037 * -1 A guest wakeup IPI (which has now been cleared)
2038 * In either case, we return to guest to deliver any pending
2041 * -2 A PCI passthrough external interrupt was handled
2042 * (interrupt was delivered directly to guest)
2043 * Return to guest to deliver any pending guest interrupts.
2049 /* Return code = 2 */
2050 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2051 stw r12, VCPU_TRAP(r9)
2054 1: /* Return code <= 1 */
2058 /* Return code <= 0 */
2059 maybe_reenter_guest:
2060 ld r5, HSTATE_KVM_VCORE(r13)
2061 lwz r0, VCORE_ENTRY_EXIT(r5)
2064 blt deliver_guest_interrupt
2067 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2069 * Softpatch interrupt for transactional memory emulation cases
2070 * on POWER9 DD2.2. This is early in the guest exit path - we
2071 * haven't saved registers or done a treclaim yet.
2074 /* Save instruction image in HEIR */
2076 stw r3, VCPU_HEIR(r9)
2079 * The cases we want to handle here are those where the guest
2080 * is in real suspend mode and is trying to transition to
2081 * transactional mode.
2083 lbz r0, HSTATE_FAKE_SUSPEND(r13)
2084 cmpwi r0, 0 /* keep exiting guest if in fake suspend */
2086 rldicl r3, r11, 64 - MSR_TS_S_LG, 62
2087 cmpwi r3, 1 /* or if not in suspend state */
2090 /* Call C code to do the emulation */
2092 bl kvmhv_p9_tm_emulation_early
2094 ld r9, HSTATE_KVM_VCPU(r13)
2095 li r12, BOOK3S_INTERRUPT_HV_SOFTPATCH
2097 beq guest_exit_cont /* continue exiting if not handled */
2099 ld r11, VCPU_MSR(r9)
2100 b fast_interrupt_c_return /* go back to guest if handled */
2101 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2104 * Check whether an HDSI is an HPTE not found fault or something else.
2105 * If it is an HPTE not found fault that is due to the guest accessing
2106 * a page that they have mapped but which we have paged out, then
2107 * we continue on with the guest exit path. In all other cases,
2108 * reflect the HDSI to the guest as a DSI.
2112 lbz r0, KVM_RADIX(r3)
2114 mfspr r6, SPRN_HDSISR
2116 /* Look for DSISR canary. If we find it, retry instruction */
2119 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2121 bne .Lradix_hdsi /* on radix, just save DAR/DSISR/ASDR */
2122 /* HPTE not found fault or protection fault? */
2123 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
2124 beq 1f /* if not, send it to the guest */
2125 andi. r0, r11, MSR_DR /* data relocation enabled? */
2128 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2130 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2132 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2133 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
2134 bne 7f /* if no SLB entry found */
2135 4: std r4, VCPU_FAULT_DAR(r9)
2136 stw r6, VCPU_FAULT_DSISR(r9)
2138 /* Search the hash table. */
2139 mr r3, r9 /* vcpu pointer */
2140 li r7, 1 /* data fault */
2141 bl kvmppc_hpte_hv_fault
2142 ld r9, HSTATE_KVM_VCPU(r13)
2144 ld r11, VCPU_MSR(r9)
2145 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
2146 cmpdi r3, 0 /* retry the instruction */
2148 cmpdi r3, -1 /* handle in kernel mode */
2150 cmpdi r3, -2 /* MMIO emulation; need instr word */
2153 /* Synthesize a DSI (or DSegI) for the guest */
2154 ld r4, VCPU_FAULT_DAR(r9)
2156 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
2157 mtspr SPRN_DSISR, r6
2158 7: mtspr SPRN_DAR, r4
2159 mtspr SPRN_SRR0, r10
2160 mtspr SPRN_SRR1, r11
2162 bl kvmppc_msr_interrupt
2163 fast_interrupt_c_return:
2164 6: ld r7, VCPU_CTR(r9)
2171 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
2172 ld r5, KVM_VRMA_SLB_V(r5)
2175 /* If this is for emulated MMIO, load the instruction word */
2176 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
2178 /* Set guest mode to 'jump over instruction' so if lwz faults
2179 * we'll just continue at the next IP. */
2180 li r0, KVM_GUEST_MODE_SKIP
2181 stb r0, HSTATE_IN_GUEST(r13)
2183 /* Do the access with MSR:DR enabled */
2185 ori r4, r3, MSR_DR /* Enable paging for data */
2190 /* Store the result */
2191 stw r8, VCPU_LAST_INST(r9)
2193 /* Unset guest mode. */
2194 li r0, KVM_GUEST_MODE_HOST_HV
2195 stb r0, HSTATE_IN_GUEST(r13)
2199 std r4, VCPU_FAULT_DAR(r9)
2200 stw r6, VCPU_FAULT_DSISR(r9)
2203 std r5, VCPU_FAULT_GPA(r9)
2207 * Similarly for an HISI, reflect it to the guest as an ISI unless
2208 * it is an HPTE not found fault for a page that we have paged out.
2212 lbz r0, KVM_RADIX(r3)
2214 bne .Lradix_hisi /* for radix, just save ASDR */
2215 andis. r0, r11, SRR1_ISI_NOPT@h
2217 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
2220 mfspr r5, SPRN_ASDR /* on POWER9, use ASDR to get VSID */
2222 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2224 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
2225 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
2226 bne 7f /* if no SLB entry found */
2228 /* Search the hash table. */
2229 mr r3, r9 /* vcpu pointer */
2232 li r7, 0 /* instruction fault */
2233 bl kvmppc_hpte_hv_fault
2234 ld r9, HSTATE_KVM_VCPU(r13)
2236 ld r11, VCPU_MSR(r9)
2237 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
2238 cmpdi r3, 0 /* retry the instruction */
2239 beq fast_interrupt_c_return
2240 cmpdi r3, -1 /* handle in kernel mode */
2243 /* Synthesize an ISI (or ISegI) for the guest */
2245 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
2246 7: mtspr SPRN_SRR0, r10
2247 mtspr SPRN_SRR1, r11
2249 bl kvmppc_msr_interrupt
2250 b fast_interrupt_c_return
2252 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
2253 ld r5, KVM_VRMA_SLB_V(r6)
2257 * Try to handle an hcall in real mode.
2258 * Returns to the guest if we handle it, or continues on up to
2259 * the kernel if we can't (i.e. if we don't have a handler for
2260 * it, or if the handler returns H_TOO_HARD).
2262 * r5 - r8 contain hcall args,
2263 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
2265 hcall_try_real_mode:
2266 ld r3,VCPU_GPR(R3)(r9)
2268 /* sc 1 from userspace - reflect to guest syscall */
2269 bne sc_1_fast_return
2270 /* sc 1 from nested guest - give it to L1 to handle */
2271 ld r0, VCPU_NESTED(r9)
2275 cmpldi r3,hcall_real_table_end - hcall_real_table
2277 /* See if this hcall is enabled for in-kernel handling */
2279 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
2280 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
2282 ld r0, KVM_ENABLED_HCALLS(r4)
2283 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
2287 /* Get pointer to handler, if any, and call it */
2288 LOAD_REG_ADDR(r4, hcall_real_table)
2294 mr r3,r9 /* get vcpu pointer */
2295 ld r4,VCPU_GPR(R4)(r9)
2298 beq hcall_real_fallback
2299 ld r4,HSTATE_KVM_VCPU(r13)
2300 std r3,VCPU_GPR(R3)(r4)
2308 li r10, BOOK3S_INTERRUPT_SYSCALL
2309 bl kvmppc_msr_interrupt
2313 /* We've attempted a real mode hcall, but it's punted it back
2314 * to userspace. We need to restore some clobbered volatiles
2315 * before resuming the pass-it-to-qemu path */
2316 hcall_real_fallback:
2317 li r12,BOOK3S_INTERRUPT_SYSCALL
2318 ld r9, HSTATE_KVM_VCPU(r13)
2322 .globl hcall_real_table
2324 .long 0 /* 0 - unused */
2325 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
2326 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
2327 .long DOTSYM(kvmppc_h_read) - hcall_real_table
2328 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
2329 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
2330 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
2331 #ifdef CONFIG_SPAPR_TCE_IOMMU
2332 .long DOTSYM(kvmppc_h_get_tce) - hcall_real_table
2333 .long DOTSYM(kvmppc_rm_h_put_tce) - hcall_real_table
2338 .long 0 /* 0x24 - H_SET_SPRG0 */
2339 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
2340 .long DOTSYM(kvmppc_rm_h_page_init) - hcall_real_table
2354 #ifdef CONFIG_KVM_XICS
2355 .long DOTSYM(kvmppc_rm_h_eoi) - hcall_real_table
2356 .long DOTSYM(kvmppc_rm_h_cppr) - hcall_real_table
2357 .long DOTSYM(kvmppc_rm_h_ipi) - hcall_real_table
2358 .long DOTSYM(kvmppc_rm_h_ipoll) - hcall_real_table
2359 .long DOTSYM(kvmppc_rm_h_xirr) - hcall_real_table
2361 .long 0 /* 0x64 - H_EOI */
2362 .long 0 /* 0x68 - H_CPPR */
2363 .long 0 /* 0x6c - H_IPI */
2364 .long 0 /* 0x70 - H_IPOLL */
2365 .long 0 /* 0x74 - H_XIRR */
2393 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
2394 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
2410 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
2414 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
2415 #ifdef CONFIG_SPAPR_TCE_IOMMU
2416 .long DOTSYM(kvmppc_rm_h_stuff_tce) - hcall_real_table
2417 .long DOTSYM(kvmppc_rm_h_put_tce_indirect) - hcall_real_table
2533 #ifdef CONFIG_KVM_XICS
2534 .long DOTSYM(kvmppc_rm_h_xirr_x) - hcall_real_table
2536 .long 0 /* 0x2fc - H_XIRR_X*/
2538 .long DOTSYM(kvmppc_h_random) - hcall_real_table
2539 .globl hcall_real_table_end
2540 hcall_real_table_end:
2542 _GLOBAL_TOC(kvmppc_h_set_xdabr)
2543 EXPORT_SYMBOL_GPL(kvmppc_h_set_xdabr)
2544 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2546 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2549 6: li r3, H_PARAMETER
2552 _GLOBAL_TOC(kvmppc_h_set_dabr)
2553 EXPORT_SYMBOL_GPL(kvmppc_h_set_dabr)
2554 li r5, DABRX_USER | DABRX_KERNEL
2558 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2559 std r4,VCPU_DABR(r3)
2560 stw r5, VCPU_DABRX(r3)
2561 mtspr SPRN_DABRX, r5
2562 /* Work around P7 bug where DABR can get corrupted on mtspr */
2563 1: mtspr SPRN_DABR,r4
2572 LOAD_REG_ADDR(r11, dawr_force_enable)
2579 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2580 rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2581 rlwimi r5, r4, 2, DAWRX_WT
2583 std r4, VCPU_DAWR(r3)
2584 std r5, VCPU_DAWRX(r3)
2586 * If came in through the real mode hcall handler then it is necessary
2587 * to write the registers since the return path won't. Otherwise it is
2588 * sufficient to store then in the vcpu struct as they will be loaded
2589 * next time the vcpu is run.
2592 andi. r6, r6, MSR_DR /* in real mode? */
2594 mtspr SPRN_DAWR0, r4
2595 mtspr SPRN_DAWRX0, r5
2599 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2601 std r11,VCPU_MSR(r3)
2603 stb r0,VCPU_CEDED(r3)
2604 sync /* order setting ceded vs. testing prodded */
2605 lbz r5,VCPU_PRODDED(r3)
2607 bne kvm_cede_prodded
2608 li r12,0 /* set trap to 0 to say hcall is handled */
2609 stw r12,VCPU_TRAP(r3)
2611 std r0,VCPU_GPR(R3)(r3)
2614 * Set our bit in the bitmask of napping threads unless all the
2615 * other threads are already napping, in which case we send this
2618 ld r5,HSTATE_KVM_VCORE(r13)
2619 lbz r6,HSTATE_PTID(r13)
2620 lwz r8,VCORE_ENTRY_EXIT(r5)
2624 addi r6,r5,VCORE_NAPPING_THREADS
2631 /* order napping_threads update vs testing entry_exit_map */
2634 stb r0,HSTATE_NAPPING(r13)
2635 lwz r7,VCORE_ENTRY_EXIT(r5)
2637 bge 33f /* another thread already exiting */
2640 * Although not specifically required by the architecture, POWER7
2641 * preserves the following registers in nap mode, even if an SMT mode
2642 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2643 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2645 /* Save non-volatile GPRs */
2646 std r14, VCPU_GPR(R14)(r3)
2647 std r15, VCPU_GPR(R15)(r3)
2648 std r16, VCPU_GPR(R16)(r3)
2649 std r17, VCPU_GPR(R17)(r3)
2650 std r18, VCPU_GPR(R18)(r3)
2651 std r19, VCPU_GPR(R19)(r3)
2652 std r20, VCPU_GPR(R20)(r3)
2653 std r21, VCPU_GPR(R21)(r3)
2654 std r22, VCPU_GPR(R22)(r3)
2655 std r23, VCPU_GPR(R23)(r3)
2656 std r24, VCPU_GPR(R24)(r3)
2657 std r25, VCPU_GPR(R25)(r3)
2658 std r26, VCPU_GPR(R26)(r3)
2659 std r27, VCPU_GPR(R27)(r3)
2660 std r28, VCPU_GPR(R28)(r3)
2661 std r29, VCPU_GPR(R29)(r3)
2662 std r30, VCPU_GPR(R30)(r3)
2663 std r31, VCPU_GPR(R31)(r3)
2668 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2670 * Branch around the call if both CPU_FTR_TM and
2671 * CPU_FTR_P9_TM_HV_ASSIST are off.
2675 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
2677 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2679 ld r3, HSTATE_KVM_VCPU(r13)
2681 li r5, 0 /* don't preserve non-vol regs */
2682 bl kvmppc_save_tm_hv
2688 * Set DEC to the smaller of DEC and HDEC, so that we wake
2689 * no later than the end of our timeslice (HDEC interrupts
2690 * don't wake us from nap).
2696 /* On P9 check whether the guest has large decrementer mode enabled */
2697 ld r6, HSTATE_KVM_VCORE(r13)
2698 ld r6, VCORE_LPCR(r6)
2699 andis. r6, r6, LPCR_LD@h
2701 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
2708 /* save expiry time of guest decrementer */
2710 ld r4, HSTATE_KVM_VCPU(r13)
2711 ld r5, HSTATE_KVM_VCORE(r13)
2712 ld r6, VCORE_TB_OFFSET_APPL(r5)
2713 subf r3, r6, r3 /* convert to host TB value */
2714 std r3, VCPU_DEC_EXPIRES(r4)
2716 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2717 ld r4, HSTATE_KVM_VCPU(r13)
2718 addi r3, r4, VCPU_TB_CEDE
2719 bl kvmhv_accumulate_time
2722 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2724 /* Go back to host stack */
2725 ld r1, HSTATE_HOST_R1(r13)
2728 * Take a nap until a decrementer or external or doobell interrupt
2729 * occurs, with PECE1 and PECE0 set in LPCR.
2730 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2731 * Also clear the runlatch bit before napping.
2734 mfspr r0, SPRN_CTRLF
2736 mtspr SPRN_CTRLT, r0
2739 stb r0,HSTATE_HWTHREAD_REQ(r13)
2741 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2743 ori r5, r5, LPCR_PECEDH
2744 rlwimi r5, r3, 0, LPCR_PECEDP
2745 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2747 kvm_nap_sequence: /* desired LPCR value in r5 */
2750 * PSSCR bits: exit criterion = 1 (wakeup based on LPCR at sreset)
2751 * enable state loss = 1 (allow SMT mode switch)
2752 * requested level = 0 (just stop dispatching)
2754 lis r3, (PSSCR_EC | PSSCR_ESL)@h
2755 /* Set LPCR_PECE_HVEE bit to enable wakeup by HV interrupts */
2756 li r4, LPCR_PECE_HVEE@higher
2760 li r3, PNV_THREAD_NAP
2761 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
2766 bl isa300_idle_stop_mayloss
2768 bl isa206_idle_insn_mayloss
2769 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
2771 mfspr r0, SPRN_CTRLF
2773 mtspr SPRN_CTRLT, r0
2778 stb r0, PACA_FTRACE_ENABLED(r13)
2780 li r0, KVM_HWTHREAD_IN_KVM
2781 stb r0, HSTATE_HWTHREAD_STATE(r13)
2783 lbz r0, HSTATE_NAPPING(r13)
2784 cmpwi r0, NAPPING_CEDE
2786 cmpwi r0, NAPPING_NOVCPU
2787 beq kvm_novcpu_wakeup
2788 cmpwi r0, NAPPING_UNSPLIT
2789 beq kvm_unsplit_wakeup
2790 twi 31,0,0 /* Nap state must not be zero */
2798 /* Woken by external or decrementer interrupt */
2800 /* get vcpu pointer */
2801 ld r4, HSTATE_KVM_VCPU(r13)
2803 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
2804 addi r3, r4, VCPU_TB_RMINTR
2805 bl kvmhv_accumulate_time
2808 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2810 * Branch around the call if both CPU_FTR_TM and
2811 * CPU_FTR_P9_TM_HV_ASSIST are off.
2815 END_FTR_SECTION(CPU_FTR_TM | CPU_FTR_P9_TM_HV_ASSIST, 0)
2817 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2821 li r5, 0 /* don't preserve non-vol regs */
2822 bl kvmppc_restore_tm_hv
2824 ld r4, HSTATE_KVM_VCPU(r13)
2828 /* load up FP state */
2831 /* Restore guest decrementer */
2832 ld r3, VCPU_DEC_EXPIRES(r4)
2833 ld r5, HSTATE_KVM_VCORE(r13)
2834 ld r6, VCORE_TB_OFFSET_APPL(r5)
2835 add r3, r3, r6 /* convert host TB to guest TB value */
2841 ld r14, VCPU_GPR(R14)(r4)
2842 ld r15, VCPU_GPR(R15)(r4)
2843 ld r16, VCPU_GPR(R16)(r4)
2844 ld r17, VCPU_GPR(R17)(r4)
2845 ld r18, VCPU_GPR(R18)(r4)
2846 ld r19, VCPU_GPR(R19)(r4)
2847 ld r20, VCPU_GPR(R20)(r4)
2848 ld r21, VCPU_GPR(R21)(r4)
2849 ld r22, VCPU_GPR(R22)(r4)
2850 ld r23, VCPU_GPR(R23)(r4)
2851 ld r24, VCPU_GPR(R24)(r4)
2852 ld r25, VCPU_GPR(R25)(r4)
2853 ld r26, VCPU_GPR(R26)(r4)
2854 ld r27, VCPU_GPR(R27)(r4)
2855 ld r28, VCPU_GPR(R28)(r4)
2856 ld r29, VCPU_GPR(R29)(r4)
2857 ld r30, VCPU_GPR(R30)(r4)
2858 ld r31, VCPU_GPR(R31)(r4)
2860 /* Check the wake reason in SRR1 to see why we got here */
2861 bl kvmppc_check_wake_reason
2864 * Restore volatile registers since we could have called a
2865 * C routine in kvmppc_check_wake_reason
2867 * r3 tells us whether we need to return to host or not
2868 * WARNING: it gets checked further down:
2869 * should not modify r3 until this check is done.
2871 ld r4, HSTATE_KVM_VCPU(r13)
2873 /* clear our bit in vcore->napping_threads */
2874 34: ld r5,HSTATE_KVM_VCORE(r13)
2875 lbz r7,HSTATE_PTID(r13)
2878 addi r6,r5,VCORE_NAPPING_THREADS
2884 stb r0,HSTATE_NAPPING(r13)
2886 /* See if the wake reason saved in r3 means we need to exit */
2887 stw r12, VCPU_TRAP(r4)
2891 b maybe_reenter_guest
2893 /* cede when already previously prodded case */
2896 stb r0,VCPU_PRODDED(r3)
2897 sync /* order testing prodded vs. clearing ceded */
2898 stb r0,VCPU_CEDED(r3)
2902 /* we've ceded but we want to give control to the host */
2904 ld r9, HSTATE_KVM_VCPU(r13)
2905 #ifdef CONFIG_KVM_XICS
2906 /* are we using XIVE with single escalation? */
2907 ld r10, VCPU_XIVE_ESC_VADDR(r9)
2910 li r6, XIVE_ESB_SET_PQ_00
2912 * If we still have a pending escalation, abort the cede,
2913 * and we must set PQ to 10 rather than 00 so that we don't
2914 * potentially end up with two entries for the escalation
2915 * interrupt in the XIVE interrupt queue. In that case
2916 * we also don't want to set xive_esc_on to 1 here in
2917 * case we race with xive_esc_irq().
2919 lbz r5, VCPU_XIVE_ESC_ON(r9)
2923 stb r0, VCPU_CEDED(r9)
2925 * The escalation interrupts are special as we don't EOI them.
2926 * There is no need to use the load-after-store ordering offset
2927 * to set PQ to 10 as we won't use StoreEOI.
2929 li r6, XIVE_ESB_SET_PQ_10
2932 stb r0, VCPU_XIVE_ESC_ON(r9)
2933 /* make sure store to xive_esc_on is seen before xive_esc_irq runs */
2935 5: /* Enable XIVE escalation */
2937 andi. r0, r0, MSR_DR /* in real mode? */
2941 1: ld r10, VCPU_XIVE_ESC_RADDR(r9)
2944 #endif /* CONFIG_KVM_XICS */
2945 3: b guest_exit_cont
2947 /* Try to do machine check recovery in real mode */
2948 machine_check_realmode:
2949 mr r3, r9 /* get vcpu pointer */
2950 bl kvmppc_realmode_machine_check
2952 /* all machine checks go to virtual mode for further handling */
2953 ld r9, HSTATE_KVM_VCPU(r13)
2954 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2958 * Call C code to handle a HMI in real mode.
2959 * Only the primary thread does the call, secondary threads are handled
2960 * by calling hmi_exception_realmode() after kvmppc_hv_entry returns.
2961 * r9 points to the vcpu on entry
2964 lbz r0, HSTATE_PTID(r13)
2967 bl kvmppc_realmode_hmi_handler
2968 ld r9, HSTATE_KVM_VCPU(r13)
2969 li r12, BOOK3S_INTERRUPT_HMI
2973 * Check the reason we woke from nap, and take appropriate action.
2975 * 0 if nothing needs to be done
2976 * 1 if something happened that needs to be handled by the host
2977 * -1 if there was a guest wakeup (IPI or msgsnd)
2978 * -2 if we handled a PCI passthrough interrupt (returned by
2979 * kvmppc_read_intr only)
2981 * Also sets r12 to the interrupt vector for any interrupt that needs
2982 * to be handled now by the host (0x500 for external interrupt), or zero.
2983 * Modifies all volatile registers (since it may call a C function).
2984 * This routine calls kvmppc_read_intr, a C function, if an external
2985 * interrupt is pending.
2987 kvmppc_check_wake_reason:
2990 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2992 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2993 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2994 cmpwi r6, 8 /* was it an external interrupt? */
2995 beq 7f /* if so, see what it was */
2998 cmpwi r6, 6 /* was it the decrementer? */
3001 cmpwi r6, 5 /* privileged doorbell? */
3003 cmpwi r6, 3 /* hypervisor doorbell? */
3005 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3006 cmpwi r6, 0xa /* Hypervisor maintenance ? */
3008 li r3, 1 /* anything else, return 1 */
3011 /* hypervisor doorbell */
3012 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
3015 * Clear the doorbell as we will invoke the handler
3016 * explicitly in the guest exit path.
3018 lis r6, (PPC_DBELL_SERVER << (63-36))@h
3020 /* see if it's a host IPI */
3025 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
3026 lbz r0, HSTATE_HOST_IPI(r13)
3029 /* if not, return -1 */
3033 /* Woken up due to Hypervisor maintenance interrupt */
3034 4: li r12, BOOK3S_INTERRUPT_HMI
3038 /* external interrupt - create a stack frame so we can call C */
3040 std r0, PPC_LR_STKOFF(r1)
3041 stdu r1, -PPC_MIN_STKFRM(r1)
3044 li r12, BOOK3S_INTERRUPT_EXTERNAL
3049 * Return code of 2 means PCI passthrough interrupt, but
3050 * we need to return back to host to complete handling the
3051 * interrupt. Trap reason is expected in r12 by guest
3054 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
3056 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
3057 addi r1, r1, PPC_MIN_STKFRM
3062 * Save away FP, VMX and VSX registers.
3064 * N.B. r30 and r31 are volatile across this function,
3065 * thus it is not callable from C.
3072 #ifdef CONFIG_ALTIVEC
3074 oris r8,r8,MSR_VEC@h
3075 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3079 oris r8,r8,MSR_VSX@h
3080 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
3083 addi r3,r3,VCPU_FPRS
3085 #ifdef CONFIG_ALTIVEC
3087 addi r3,r31,VCPU_VRS
3089 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3091 mfspr r6,SPRN_VRSAVE
3092 stw r6,VCPU_VRSAVE(r31)
3097 * Load up FP, VMX and VSX registers
3099 * N.B. r30 and r31 are volatile across this function,
3100 * thus it is not callable from C.
3107 #ifdef CONFIG_ALTIVEC
3109 oris r8,r8,MSR_VEC@h
3110 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3114 oris r8,r8,MSR_VSX@h
3115 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
3118 addi r3,r4,VCPU_FPRS
3120 #ifdef CONFIG_ALTIVEC
3122 addi r3,r31,VCPU_VRS
3124 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
3126 lwz r7,VCPU_VRSAVE(r31)
3127 mtspr SPRN_VRSAVE,r7
3132 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
3134 * Save transactional state and TM-related registers.
3135 * Called with r3 pointing to the vcpu struct and r4 containing
3136 * the guest MSR value.
3137 * r5 is non-zero iff non-volatile register state needs to be maintained.
3138 * If r5 == 0, this can modify all checkpointed registers, but
3139 * restores r1 and r2 before exit.
3141 _GLOBAL_TOC(kvmppc_save_tm_hv)
3142 EXPORT_SYMBOL_GPL(kvmppc_save_tm_hv)
3143 /* See if we need to handle fake suspend mode */
3146 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
3148 lbz r0, HSTATE_FAKE_SUSPEND(r13) /* Were we fake suspended? */
3150 beq __kvmppc_save_tm
3152 /* The following code handles the fake_suspend = 1 case */
3154 std r0, PPC_LR_STKOFF(r1)
3155 stdu r1, -TM_FRAME_SIZE(r1)
3160 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
3163 rldicl. r8, r8, 64 - MSR_TS_S_LG, 62 /* Did we actually hrfid? */
3166 bl pnv_power9_force_smt4_catch
3167 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
3171 * It's possible that treclaim. may modify registers, if we have lost
3172 * track of fake-suspend state in the guest due to it using rfscv.
3173 * Save and restore registers in case this occurs.
3178 /* SPRN_TAR would need to be saved here if the kernel ever used it */
3186 std r1, HSTATE_HOST_R1(r13)
3188 /* We have to treclaim here because that's the only way to do S->N */
3189 li r3, TM_CAUSE_KVM_RESCHED
3193 ld r1, HSTATE_HOST_R1(r13)
3207 * We were in fake suspend, so we are not going to save the
3208 * register state as the guest checkpointed state (since
3209 * we already have it), therefore we can now use any volatile GPR.
3210 * In fact treclaim in fake suspend state doesn't modify
3215 bl pnv_power9_force_smt4_release
3216 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
3220 mfspr r3, SPRN_PSSCR
3221 /* PSSCR_FAKE_SUSPEND is a write-only bit, but clear it anyway */
3222 li r0, PSSCR_FAKE_SUSPEND
3224 mtspr SPRN_PSSCR, r3
3226 /* Don't save TEXASR, use value from last exit in real suspend state */
3227 ld r9, HSTATE_KVM_VCPU(r13)
3228 mfspr r5, SPRN_TFHAR
3229 mfspr r6, SPRN_TFIAR
3230 std r5, VCPU_TFHAR(r9)
3231 std r6, VCPU_TFIAR(r9)
3233 addi r1, r1, TM_FRAME_SIZE
3234 ld r0, PPC_LR_STKOFF(r1)
3239 * Restore transactional state and TM-related registers.
3240 * Called with r3 pointing to the vcpu struct
3241 * and r4 containing the guest MSR value.
3242 * r5 is non-zero iff non-volatile register state needs to be maintained.
3243 * This potentially modifies all checkpointed registers.
3244 * It restores r1 and r2 from the PACA.
3246 _GLOBAL_TOC(kvmppc_restore_tm_hv)
3247 EXPORT_SYMBOL_GPL(kvmppc_restore_tm_hv)
3249 * If we are doing TM emulation for the guest on a POWER9 DD2,
3250 * then we don't actually do a trechkpt -- we either set up
3251 * fake-suspend mode, or emulate a TM rollback.
3254 b __kvmppc_restore_tm
3255 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
3257 std r0, PPC_LR_STKOFF(r1)
3260 stb r0, HSTATE_FAKE_SUSPEND(r13)
3262 /* Turn on TM so we can restore TM SPRs */
3265 rldimi r5, r0, MSR_TM_LG, 63-MSR_TM_LG
3269 * The user may change these outside of a transaction, so they must
3270 * always be context switched.
3272 ld r5, VCPU_TFHAR(r3)
3273 ld r6, VCPU_TFIAR(r3)
3274 ld r7, VCPU_TEXASR(r3)
3275 mtspr SPRN_TFHAR, r5
3276 mtspr SPRN_TFIAR, r6
3277 mtspr SPRN_TEXASR, r7
3279 rldicl. r5, r4, 64 - MSR_TS_S_LG, 62
3280 beqlr /* TM not active in guest */
3282 /* Make sure the failure summary is set */
3283 oris r7, r7, (TEXASR_FS)@h
3284 mtspr SPRN_TEXASR, r7
3286 cmpwi r5, 1 /* check for suspended state */
3288 stb r5, HSTATE_FAKE_SUSPEND(r13)
3289 b 9f /* and return */
3290 10: stdu r1, -PPC_MIN_STKFRM(r1)
3291 /* guest is in transactional state, so simulate rollback */
3292 bl kvmhv_emulate_tm_rollback
3294 addi r1, r1, PPC_MIN_STKFRM
3295 9: ld r0, PPC_LR_STKOFF(r1)
3298 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
3301 * We come here if we get any exception or interrupt while we are
3302 * executing host real mode code while in guest MMU context.
3303 * r12 is (CR << 32) | vector
3304 * r13 points to our PACA
3305 * r12 is saved in HSTATE_SCRATCH0(r13)
3306 * r9 is saved in HSTATE_SCRATCH2(r13)
3307 * r13 is saved in HSPRG1
3308 * cfar is saved in HSTATE_CFAR(r13)
3309 * ppr is saved in HSTATE_PPR(r13)
3311 kvmppc_bad_host_intr:
3313 * Switch to the emergency stack, but start half-way down in
3314 * case we were already on it.
3318 ld r1, PACAEMERGSP(r13)
3319 subi r1, r1, THREAD_SIZE/2 + INT_FRAME_SIZE
3332 mfspr r3, SPRN_HSRR0
3333 mfspr r4, SPRN_HSRR1
3335 mfspr r6, SPRN_HDSISR
3337 1: mfspr r3, SPRN_SRR0
3340 mfspr r6, SPRN_DSISR
3345 ld r9, HSTATE_SCRATCH2(r13)
3346 ld r12, HSTATE_SCRATCH0(r13)
3351 ld r5, HSTATE_CFAR(r13)
3352 std r5, ORIG_GPR3(r1)
3356 lbz r6, PACAIRQSOFTMASK(r13)
3362 LOAD_REG_IMMEDIATE(3, 0x7265677368657265)
3363 std r3, STACK_FRAME_OVERHEAD-16(r1)
3366 * On POWER9 do a minimal restore of the MMU and call C code,
3367 * which will print a message and panic.
3368 * XXX On POWER7 and POWER8, we just spin here since we don't
3369 * know what the other threads are doing (and we don't want to
3370 * coordinate with them) - but at least we now have register state
3371 * in memory that we might be able to look at from another CPU.
3375 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
3376 ld r9, HSTATE_KVM_VCPU(r13)
3377 ld r10, VCPU_KVM(r9)
3382 mtspr SPRN_CIABR, r0
3383 mtspr SPRN_DAWRX0, r0
3385 BEGIN_MMU_FTR_SECTION
3387 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
3392 ld r8, PACA_SLBSHADOWPTR(r13)
3393 .rept SLB_NUM_BOLTED
3394 li r3, SLBSHADOW_SAVEAREA
3398 andis. r7, r5, SLB_ESID_V@h
3404 4: lwz r7, KVM_HOST_LPID(r10)
3407 ld r8, KVM_HOST_LPCR(r10)
3410 li r0, KVM_GUEST_MODE_NONE
3411 stb r0, HSTATE_IN_GUEST(r13)
3414 * Turn on the MMU and jump to C code
3418 addi r3, r3, 9f - 5b
3420 rldimi r3, r4, 62, 0 /* ensure 0xc000000000000000 bits are set */
3421 ld r4, PACAKMSR(r13)
3425 9: addi r3, r1, STACK_FRAME_OVERHEAD
3426 bl kvmppc_bad_interrupt
3430 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
3431 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
3432 * r11 has the guest MSR value (in/out)
3433 * r9 has a vcpu pointer (in)
3434 * r0 is used as a scratch register
3436 kvmppc_msr_interrupt:
3437 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
3438 cmpwi r0, 2 /* Check if we are in transactional state.. */
3439 ld r11, VCPU_INTR_MSR(r9)
3441 /* ... if transactional, change to suspended */
3443 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
3447 * Load up guest PMU state. R3 points to the vcpu struct.
3449 _GLOBAL(kvmhv_load_guest_pmu)
3450 EXPORT_SYMBOL_GPL(kvmhv_load_guest_pmu)
3454 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
3455 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
3458 ld r3, VCPU_MMCR(r4)
3459 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
3460 cmpwi r5, MMCR0_PMAO
3461 beql kvmppc_fix_pmao
3462 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
3463 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
3464 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
3465 lwz r6, VCPU_PMC + 8(r4)
3466 lwz r7, VCPU_PMC + 12(r4)
3467 lwz r8, VCPU_PMC + 16(r4)
3468 lwz r9, VCPU_PMC + 20(r4)
3475 ld r3, VCPU_MMCR(r4)
3476 ld r5, VCPU_MMCR + 8(r4)
3477 ld r6, VCPU_MMCRA(r4)
3478 ld r7, VCPU_SIAR(r4)
3479 ld r8, VCPU_SDAR(r4)
3480 mtspr SPRN_MMCR1, r5
3481 mtspr SPRN_MMCRA, r6
3485 ld r5, VCPU_MMCR + 24(r4)
3486 ld r6, VCPU_SIER + 8(r4)
3487 ld r7, VCPU_SIER + 16(r4)
3488 mtspr SPRN_MMCR3, r5
3489 mtspr SPRN_SIER2, r6
3490 mtspr SPRN_SIER3, r7
3491 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
3493 ld r5, VCPU_MMCR + 16(r4)
3494 ld r6, VCPU_SIER(r4)
3495 mtspr SPRN_MMCR2, r5
3497 BEGIN_FTR_SECTION_NESTED(96)
3498 lwz r7, VCPU_PMC + 24(r4)
3499 lwz r8, VCPU_PMC + 28(r4)
3500 ld r9, VCPU_MMCRS(r4)
3501 mtspr SPRN_SPMC1, r7
3502 mtspr SPRN_SPMC2, r8
3503 mtspr SPRN_MMCRS, r9
3504 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
3505 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3506 mtspr SPRN_MMCR0, r3
3512 * Reload host PMU state saved in the PACA by kvmhv_save_host_pmu.
3514 _GLOBAL(kvmhv_load_host_pmu)
3515 EXPORT_SYMBOL_GPL(kvmhv_load_host_pmu)
3517 lbz r4, PACA_PMCINUSE(r13) /* is the host using the PMU? */
3519 beq 23f /* skip if not */
3521 ld r3, HSTATE_MMCR0(r13)
3522 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
3523 cmpwi r4, MMCR0_PMAO
3524 beql kvmppc_fix_pmao
3525 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
3526 lwz r3, HSTATE_PMC1(r13)
3527 lwz r4, HSTATE_PMC2(r13)
3528 lwz r5, HSTATE_PMC3(r13)
3529 lwz r6, HSTATE_PMC4(r13)
3530 lwz r8, HSTATE_PMC5(r13)
3531 lwz r9, HSTATE_PMC6(r13)
3538 ld r3, HSTATE_MMCR0(r13)
3539 ld r4, HSTATE_MMCR1(r13)
3540 ld r5, HSTATE_MMCRA(r13)
3541 ld r6, HSTATE_SIAR(r13)
3542 ld r7, HSTATE_SDAR(r13)
3543 mtspr SPRN_MMCR1, r4
3544 mtspr SPRN_MMCRA, r5
3548 ld r8, HSTATE_MMCR2(r13)
3549 ld r9, HSTATE_SIER(r13)
3550 mtspr SPRN_MMCR2, r8
3552 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3554 ld r5, HSTATE_MMCR3(r13)
3555 ld r6, HSTATE_SIER2(r13)
3556 ld r7, HSTATE_SIER3(r13)
3557 mtspr SPRN_MMCR3, r5
3558 mtspr SPRN_SIER2, r6
3559 mtspr SPRN_SIER3, r7
3560 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
3561 mtspr SPRN_MMCR0, r3
3567 * Save guest PMU state into the vcpu struct.
3568 * r3 = vcpu, r4 = full save flag (PMU in use flag set in VPA)
3570 _GLOBAL(kvmhv_save_guest_pmu)
3571 EXPORT_SYMBOL_GPL(kvmhv_save_guest_pmu)
3576 * POWER8 seems to have a hardware bug where setting
3577 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
3578 * when some counters are already negative doesn't seem
3579 * to cause a performance monitor alert (and hence interrupt).
3580 * The effect of this is that when saving the PMU state,
3581 * if there is no PMU alert pending when we read MMCR0
3582 * before freezing the counters, but one becomes pending
3583 * before we read the counters, we lose it.
3584 * To work around this, we need a way to freeze the counters
3585 * before reading MMCR0. Normally, freezing the counters
3586 * is done by writing MMCR0 (to set MMCR0[FC]) which
3587 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
3588 * we can also freeze the counters using MMCR2, by writing
3589 * 1s to all the counter freeze condition bits (there are
3590 * 9 bits each for 6 counters).
3592 li r3, -1 /* set all freeze bits */
3594 mfspr r10, SPRN_MMCR2
3595 mtspr SPRN_MMCR2, r3
3597 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3599 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
3600 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
3601 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
3602 mfspr r6, SPRN_MMCRA
3603 /* Clear MMCRA in order to disable SDAR updates */
3605 mtspr SPRN_MMCRA, r7
3607 cmpwi r8, 0 /* did they ask for PMU stuff to be saved? */
3609 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
3611 21: mfspr r5, SPRN_MMCR1
3614 std r4, VCPU_MMCR(r9)
3615 std r5, VCPU_MMCR + 8(r9)
3616 std r6, VCPU_MMCRA(r9)
3618 std r10, VCPU_MMCR + 16(r9)
3619 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3621 mfspr r5, SPRN_MMCR3
3622 mfspr r6, SPRN_SIER2
3623 mfspr r7, SPRN_SIER3
3624 std r5, VCPU_MMCR + 24(r9)
3625 std r6, VCPU_SIER + 8(r9)
3626 std r7, VCPU_SIER + 16(r9)
3627 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_31)
3628 std r7, VCPU_SIAR(r9)
3629 std r8, VCPU_SDAR(r9)
3636 stw r3, VCPU_PMC(r9)
3637 stw r4, VCPU_PMC + 4(r9)
3638 stw r5, VCPU_PMC + 8(r9)
3639 stw r6, VCPU_PMC + 12(r9)
3640 stw r7, VCPU_PMC + 16(r9)
3641 stw r8, VCPU_PMC + 20(r9)
3644 std r5, VCPU_SIER(r9)
3645 BEGIN_FTR_SECTION_NESTED(96)
3646 mfspr r6, SPRN_SPMC1
3647 mfspr r7, SPRN_SPMC2
3648 mfspr r8, SPRN_MMCRS
3649 stw r6, VCPU_PMC + 24(r9)
3650 stw r7, VCPU_PMC + 28(r9)
3651 std r8, VCPU_MMCRS(r9)
3653 mtspr SPRN_MMCRS, r4
3654 END_FTR_SECTION_NESTED(CPU_FTR_ARCH_300, 0, 96)
3655 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
3659 * This works around a hardware bug on POWER8E processors, where
3660 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
3661 * performance monitor interrupt. Instead, when we need to have
3662 * an interrupt pending, we have to arrange for a counter to overflow.
3666 mtspr SPRN_MMCR2, r3
3667 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
3668 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
3669 mtspr SPRN_MMCR0, r3
3676 #ifdef CONFIG_KVM_BOOK3S_HV_EXIT_TIMING
3678 * Start timing an activity
3679 * r3 = pointer to time accumulation struct, r4 = vcpu
3682 ld r5, HSTATE_KVM_VCORE(r13)
3683 ld r6, VCORE_TB_OFFSET_APPL(r5)
3685 subf r5, r6, r5 /* subtract current timebase offset */
3686 std r3, VCPU_CUR_ACTIVITY(r4)
3687 std r5, VCPU_ACTIVITY_START(r4)
3691 * Accumulate time to one activity and start another.
3692 * r3 = pointer to new time accumulation struct, r4 = vcpu
3694 kvmhv_accumulate_time:
3695 ld r5, HSTATE_KVM_VCORE(r13)
3696 ld r8, VCORE_TB_OFFSET_APPL(r5)
3697 ld r5, VCPU_CUR_ACTIVITY(r4)
3698 ld r6, VCPU_ACTIVITY_START(r4)
3699 std r3, VCPU_CUR_ACTIVITY(r4)
3701 subf r7, r8, r7 /* subtract current timebase offset */
3702 std r7, VCPU_ACTIVITY_START(r4)
3706 ld r8, TAS_SEQCOUNT(r5)
3709 std r8, TAS_SEQCOUNT(r5)
3711 ld r7, TAS_TOTAL(r5)
3713 std r7, TAS_TOTAL(r5)
3719 3: std r3, TAS_MIN(r5)
3725 std r8, TAS_SEQCOUNT(r5)