1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
6 * Derived from book3s_rmhandlers.S and other files, which are:
8 * Copyright SUSE Linux Products GmbH 2009
10 * Authors: Alexander Graf <agraf@suse.de>
13 #include <asm/ppc_asm.h>
14 #include <asm/code-patching-asm.h>
15 #include <asm/kvm_asm.h>
19 #include <asm/ptrace.h>
20 #include <asm/hvcall.h>
21 #include <asm/asm-offsets.h>
22 #include <asm/exception-64s.h>
23 #include <asm/kvm_book3s_asm.h>
24 #include <asm/book3s/64/mmu-hash.h>
25 #include <asm/export.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-compat.h>
30 #include <asm/feature-fixups.h>
31 #include <asm/cpuidle.h>
33 /* Values in HSTATE_NAPPING(r13) */
34 #define NAPPING_CEDE 1
35 #define NAPPING_NOVCPU 2
36 #define NAPPING_UNSPLIT 3
38 /* Stack frame offsets for kvmppc_hv_entry */
40 #define STACK_SLOT_TRAP (SFS-4)
41 #define STACK_SLOT_TID (SFS-16)
42 #define STACK_SLOT_PSSCR (SFS-24)
43 #define STACK_SLOT_PID (SFS-32)
44 #define STACK_SLOT_IAMR (SFS-40)
45 #define STACK_SLOT_CIABR (SFS-48)
46 #define STACK_SLOT_DAWR0 (SFS-56)
47 #define STACK_SLOT_DAWRX0 (SFS-64)
48 #define STACK_SLOT_HFSCR (SFS-72)
49 #define STACK_SLOT_AMR (SFS-80)
50 #define STACK_SLOT_UAMOR (SFS-88)
51 #define STACK_SLOT_FSCR (SFS-96)
54 * Use the last LPID (all implemented LPID bits = 1) for partition switching.
55 * This is reserved in the LPID allocator. POWER7 only implements 0x3ff, but
56 * we write 0xfff into the LPID SPR anyway, which seems to work and just
57 * ignores the top bits.
59 #define LPID_RSVD 0xfff
62 * Call kvmppc_hv_entry in real mode.
63 * Must be called with interrupts hard-disabled.
67 * LR = return address to continue at after eventually re-enabling MMU
69 _GLOBAL_TOC(kvmppc_hv_entry_trampoline)
71 std r0, PPC_LR_STKOFF(r1)
74 std r10, HSTATE_HOST_MSR(r13)
75 LOAD_REG_ADDR(r5, kvmppc_call_hv_entry)
80 mtmsrd r0,1 /* clear RI in MSR */
86 ld r4, HSTATE_KVM_VCPU(r13)
89 /* Back from guest - restore host state and return to caller */
92 /* Restore host DABR and DABRX */
93 ld r5,HSTATE_DABR(r13)
97 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
100 ld r3,PACA_SPRG_VDSO(r13)
101 mtspr SPRN_SPRG_VDSO_WRITE,r3
103 /* Reload the host's PMU registers */
104 bl kvmhv_load_host_pmu
107 * Reload DEC. HDEC interrupts were disabled when
108 * we reloaded the host's LPCR value.
110 ld r3, HSTATE_DECEXP(r13)
115 /* hwthread_req may have got set by cede or no vcpu, so clear it */
117 stb r0, HSTATE_HWTHREAD_REQ(r13)
120 * For external interrupts we need to call the Linux
121 * handler to process the interrupt. We do that by jumping
122 * to absolute address 0x500 for external interrupts.
123 * The [h]rfid at the end of the handler will return to
124 * the book3s_hv_interrupts.S code. For other interrupts
125 * we do the rfid to get back to the book3s_hv_interrupts.S
128 ld r8, 112+PPC_LR_STKOFF(r1)
130 ld r7, HSTATE_HOST_MSR(r13)
132 /* Return the trap number on this thread as the return value */
135 /* RFI into the highmem handler */
139 mtmsrd r6, 1 /* Clear RI in MSR */
144 kvmppc_primary_no_guest:
145 /* We handle this much like a ceded vcpu */
146 /* put the HDEC into the DEC, since HDEC interrupts don't wake us */
147 /* HDEC may be larger than DEC for arch >= v3.00, but since the */
148 /* HDEC value came from DEC in the first place, it will fit */
152 * Make sure the primary has finished the MMU switch.
153 * We should never get here on a secondary thread, but
154 * check it for robustness' sake.
156 ld r5, HSTATE_KVM_VCORE(r13)
157 65: lbz r0, VCORE_IN_GUEST(r5)
164 /* set our bit in napping_threads */
165 ld r5, HSTATE_KVM_VCORE(r13)
166 lbz r7, HSTATE_PTID(r13)
169 addi r6, r5, VCORE_NAPPING_THREADS
174 /* order napping_threads update vs testing entry_exit_map */
177 lwz r7, VCORE_ENTRY_EXIT(r5)
179 bge kvm_novcpu_exit /* another thread already exiting */
180 li r3, NAPPING_NOVCPU
181 stb r3, HSTATE_NAPPING(r13)
183 li r3, 0 /* Don't wake on privileged (OS) doorbell */
188 * Entered from kvm_start_guest if kvm_hstate.napping is set
194 ld r1, HSTATE_HOST_R1(r13)
195 ld r5, HSTATE_KVM_VCORE(r13)
197 stb r0, HSTATE_NAPPING(r13)
199 /* check the wake reason */
200 bl kvmppc_check_wake_reason
203 * Restore volatile registers since we could have called
204 * a C routine in kvmppc_check_wake_reason.
207 ld r5, HSTATE_KVM_VCORE(r13)
209 /* see if any other thread is already exiting */
210 lwz r0, VCORE_ENTRY_EXIT(r5)
214 /* clear our bit in napping_threads */
215 lbz r7, HSTATE_PTID(r13)
218 addi r6, r5, VCORE_NAPPING_THREADS
224 /* See if the wake reason means we need to exit */
228 /* See if our timeslice has expired (HDEC is negative) */
231 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
235 /* Got an IPI but other vcpus aren't yet exiting, must be a latecomer */
236 ld r4, HSTATE_KVM_VCPU(r13)
238 beq kvmppc_primary_no_guest
240 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
241 addi r3, r4, VCPU_TB_RMENTRY
242 bl kvmhv_start_timing
247 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
248 ld r4, HSTATE_KVM_VCPU(r13)
251 addi r3, r4, VCPU_TB_RMEXIT
252 bl kvmhv_accumulate_time
255 stw r12, STACK_SLOT_TRAP(r1)
256 bl kvmhv_commence_exit
258 b kvmhv_switch_to_host
261 * We come in here when wakened from Linux offline idle code.
263 * r3 contains the SRR1 wakeup value, SRR1 is trashed.
265 _GLOBAL(idle_kvm_start_guest)
268 std r5, 8(r1) // Save CR in caller's frame
269 std r0, 16(r1) // Save LR in caller's frame
270 // Create frame on emergency stack
271 ld r4, PACAEMERGSP(r13)
272 stdu r1, -SWITCH_FRAME_SIZE(r4)
273 // Switch to new frame on emergency stack
275 std r3, 32(r1) // Save SRR1 wakeup value
279 * Could avoid this and pass it through in r3. For now,
280 * code expects it to be in SRR1.
285 stb r0,PACA_FTRACE_ENABLED(r13)
287 li r0,KVM_HWTHREAD_IN_KVM
288 stb r0,HSTATE_HWTHREAD_STATE(r13)
290 /* kvm cede / napping does not come through here */
291 lbz r0,HSTATE_NAPPING(r13)
298 stb r0, HSTATE_NAPPING(r13)
303 * We weren't napping due to cede, so this must be a secondary
304 * thread being woken up to run a guest, or being woken up due
305 * to a stray IPI. (Or due to some machine check or hypervisor
306 * maintenance interrupt while the core is in KVM.)
309 /* Check the wake reason in SRR1 to see why we got here */
310 bl kvmppc_check_wake_reason
312 * kvmppc_check_wake_reason could invoke a C routine, but we
313 * have no volatile registers to restore when we return.
319 /* get vcore pointer, NULL if we have nothing to run */
320 ld r5,HSTATE_KVM_VCORE(r13)
322 /* if we have no vcore to run, go back to sleep */
325 kvm_secondary_got_guest:
327 // About to go to guest, clear saved SRR1
331 /* Set HSTATE_DSCR(r13) to something sensible */
332 ld r6, PACA_DSCR_DEFAULT(r13)
333 std r6, HSTATE_DSCR(r13)
335 /* On thread 0 of a subcore, set HDEC to max */
336 lbz r4, HSTATE_PTID(r13)
339 lis r6,0x7fff /* MAX_INT@h */
341 /* and set per-LPAR registers, if doing dynamic micro-threading */
342 ld r6, HSTATE_SPLIT_MODE(r13)
345 ld r0, KVM_SPLIT_RPR(r6)
347 ld r0, KVM_SPLIT_PMMAR(r6)
349 ld r0, KVM_SPLIT_LDBAR(r6)
353 /* Order load of vcpu after load of vcore */
355 ld r4, HSTATE_KVM_VCPU(r13)
358 /* Back from the guest, go back to nap */
359 /* Clear our vcpu and vcore pointers so we don't come back in early */
361 std r0, HSTATE_KVM_VCPU(r13)
363 * Once we clear HSTATE_KVM_VCORE(r13), the code in
364 * kvmppc_run_core() is going to assume that all our vcpu
365 * state is visible in memory. This lwsync makes sure
369 std r0, HSTATE_KVM_VCORE(r13)
372 * All secondaries exiting guest will fall through this path.
373 * Before proceeding, just check for HMI interrupt and
374 * invoke opal hmi handler. By now we are sure that the
375 * primary thread on this core/subcore has already made partition
376 * switch/TB resync and we are good to call opal hmi handler.
378 cmpwi r12, BOOK3S_INTERRUPT_HMI
381 li r3,0 /* NULL argument */
382 bl hmi_exception_realmode
384 * At this point we have finished executing in the guest.
385 * We need to wait for hwthread_req to become zero, since
386 * we may not turn on the MMU while hwthread_req is non-zero.
387 * While waiting we also need to check if we get given a vcpu to run.
390 lbz r3, HSTATE_HWTHREAD_REQ(r13)
394 li r0, KVM_HWTHREAD_IN_KERNEL
395 stb r0, HSTATE_HWTHREAD_STATE(r13)
396 /* need to recheck hwthread_req after a barrier, to avoid race */
398 lbz r3, HSTATE_HWTHREAD_REQ(r13)
403 * Jump to idle_return_gpr_loss, which returns to the
404 * idle_kvm_start_guest caller.
408 rlwimi r4, r3, 0, LPCR_PECE0 | LPCR_PECE1
410 // Return SRR1 wakeup value, or 0 if we went into the guest
413 ld r1, 0(r1) // Switch back to caller stack
414 ld r0, 16(r1) // Reload LR
415 ld r5, 8(r1) // Reload CR
422 ld r5, HSTATE_KVM_VCORE(r13)
425 ld r3, HSTATE_SPLIT_MODE(r13)
428 lbz r0, KVM_SPLIT_DO_NAP(r3)
434 b kvm_secondary_got_guest
436 54: li r0, KVM_HWTHREAD_IN_KVM
437 stb r0, HSTATE_HWTHREAD_STATE(r13)
441 * Here the primary thread is trying to return the core to
442 * whole-core mode, so we need to nap.
446 * When secondaries are napping in kvm_unsplit_nap() with
447 * hwthread_req = 1, HMI goes ignored even though subcores are
448 * already exited the guest. Hence HMI keeps waking up secondaries
449 * from nap in a loop and secondaries always go back to nap since
450 * no vcore is assigned to them. This makes impossible for primary
451 * thread to get hold of secondary threads resulting into a soft
452 * lockup in KVM path.
454 * Let us check if HMI is pending and handle it before we go to nap.
456 cmpwi r12, BOOK3S_INTERRUPT_HMI
458 li r3, 0 /* NULL argument */
459 bl hmi_exception_realmode
462 * Ensure that secondary doesn't nap when it has
463 * its vcore pointer set.
465 sync /* matches smp_mb() before setting split_info.do_nap */
466 ld r0, HSTATE_KVM_VCORE(r13)
469 /* clear any pending message */
471 lis r6, (PPC_DBELL_SERVER << (63-36))@h
473 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
474 /* Set kvm_split_mode.napped[tid] = 1 */
475 ld r3, HSTATE_SPLIT_MODE(r13)
477 lhz r4, PACAPACAINDEX(r13)
478 clrldi r4, r4, 61 /* micro-threading => P8 => 8 threads/core */
479 addi r4, r4, KVM_SPLIT_NAPPED
481 /* Check the do_nap flag again after setting napped[] */
483 lbz r0, KVM_SPLIT_DO_NAP(r3)
486 li r3, NAPPING_UNSPLIT
487 stb r3, HSTATE_NAPPING(r13)
488 li r3, (LPCR_PECEDH | LPCR_PECE0) >> 4
490 rlwimi r5, r3, 4, (LPCR_PECEDP | LPCR_PECEDH | LPCR_PECE0 | LPCR_PECE1)
497 /******************************************************************************
501 *****************************************************************************/
503 .global kvmppc_hv_entry
508 * R4 = vcpu pointer (or NULL)
513 * all other volatile GPRS = free
514 * Does not preserve non-volatile GPRs or CR fields
517 std r0, PPC_LR_STKOFF(r1)
520 /* Save R1 in the PACA */
521 std r1, HSTATE_HOST_R1(r13)
523 li r6, KVM_GUEST_MODE_HOST_HV
524 stb r6, HSTATE_IN_GUEST(r13)
526 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
527 /* Store initial timestamp */
530 addi r3, r4, VCPU_TB_RMENTRY
531 bl kvmhv_start_timing
535 ld r5, HSTATE_KVM_VCORE(r13)
536 ld r9, VCORE_KVM(r5) /* pointer to struct kvm */
539 * POWER7/POWER8 host -> guest partition switch code.
540 * We don't have to lock against concurrent tlbies,
541 * but we do have to coordinate across hardware threads.
543 /* Set bit in entry map iff exit map is zero. */
545 lbz r6, HSTATE_PTID(r13)
547 addi r8, r5, VCORE_ENTRY_EXIT
549 cmpwi r3, 0x100 /* any threads starting to exit? */
550 bge secondary_too_late /* if so we're too late to the party */
555 /* Primary thread switches to guest partition. */
561 li r0,LPID_RSVD /* switch to reserved LPID */
564 mtspr SPRN_SDR1,r6 /* switch to partition page table */
568 /* See if we need to flush the TLB. */
569 mr r3, r9 /* kvm pointer */
570 lhz r4, PACAPACAINDEX(r13) /* physical cpu number */
571 li r5, 0 /* nested vcpu pointer */
572 bl kvmppc_check_need_tlb_flush
574 ld r5, HSTATE_KVM_VCORE(r13)
576 /* Add timebase offset onto timebase */
577 22: ld r8,VCORE_TB_OFFSET(r5)
580 std r8, VCORE_TB_OFFSET_APPL(r5)
581 mftb r6 /* current host timebase */
583 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
584 mftb r7 /* check if lower 24 bits overflowed */
589 addis r8,r8,0x100 /* if so, increment upper 40 bits */
592 /* Load guest PCR value to select appropriate compat mode */
593 37: ld r7, VCORE_PCR(r5)
594 LOAD_REG_IMMEDIATE(r6, PCR_MASK)
602 /* DPDES and VTB are shared between threads */
603 ld r8, VCORE_DPDES(r5)
607 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
609 /* Mark the subcore state as inside guest */
610 bl kvmppc_subcore_enter_guest
612 ld r5, HSTATE_KVM_VCORE(r13)
613 ld r4, HSTATE_KVM_VCPU(r13)
615 stb r0,VCORE_IN_GUEST(r5) /* signal secondaries to continue */
617 /* Do we have a guest vcpu to run? */
619 beq kvmppc_primary_no_guest
621 /* Increment yield count if they have a VPA */
625 li r6, LPPACA_YIELDCOUNT
630 stb r6, VCPU_VPA_DIRTY(r4)
633 /* Save purr/spurr */
636 std r5,HSTATE_PURR(r13)
637 std r6,HSTATE_SPURR(r13)
643 /* Save host values of some registers */
647 mfspr r7, SPRN_DAWRX0
649 std r5, STACK_SLOT_CIABR(r1)
650 std r6, STACK_SLOT_DAWR0(r1)
651 std r7, STACK_SLOT_DAWRX0(r1)
652 std r8, STACK_SLOT_IAMR(r1)
654 std r5, STACK_SLOT_FSCR(r1)
655 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
658 std r5, STACK_SLOT_AMR(r1)
660 std r6, STACK_SLOT_UAMOR(r1)
663 /* Set partition DABR */
664 /* Do this before re-enabling PMU to avoid P7 DABR corruption bug */
665 lwz r5,VCPU_DABRX(r4)
670 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
672 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
675 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
677 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
681 li r5, 0 /* don't preserve non-vol regs */
682 bl kvmppc_restore_tm_hv
684 ld r4, HSTATE_KVM_VCPU(r13)
688 /* Load guest PMU registers; r4 = vcpu pointer here */
690 bl kvmhv_load_guest_pmu
692 /* Load up FP, VMX and VSX registers */
693 ld r4, HSTATE_KVM_VCPU(r13)
696 ld r14, VCPU_GPR(R14)(r4)
697 ld r15, VCPU_GPR(R15)(r4)
698 ld r16, VCPU_GPR(R16)(r4)
699 ld r17, VCPU_GPR(R17)(r4)
700 ld r18, VCPU_GPR(R18)(r4)
701 ld r19, VCPU_GPR(R19)(r4)
702 ld r20, VCPU_GPR(R20)(r4)
703 ld r21, VCPU_GPR(R21)(r4)
704 ld r22, VCPU_GPR(R22)(r4)
705 ld r23, VCPU_GPR(R23)(r4)
706 ld r24, VCPU_GPR(R24)(r4)
707 ld r25, VCPU_GPR(R25)(r4)
708 ld r26, VCPU_GPR(R26)(r4)
709 ld r27, VCPU_GPR(R27)(r4)
710 ld r28, VCPU_GPR(R28)(r4)
711 ld r29, VCPU_GPR(R29)(r4)
712 ld r30, VCPU_GPR(R30)(r4)
713 ld r31, VCPU_GPR(R31)(r4)
715 /* Switch DSCR to guest value */
720 /* Skip next section on POWER7 */
722 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
723 /* Load up POWER8-specific registers */
725 lwz r6, VCPU_PSPB(r4)
731 * Handle broken DAWR case by not writing it. This means we
732 * can still store the DAWR register for migration.
734 LOAD_REG_ADDR(r5, dawr_force_enable)
738 ld r5, VCPU_DAWR0(r4)
739 ld r6, VCPU_DAWRX0(r4)
741 mtspr SPRN_DAWRX0, r6
743 ld r7, VCPU_CIABR(r4)
748 ld r8, VCPU_EBBHR(r4)
751 ld r5, VCPU_EBBRR(r4)
752 ld r6, VCPU_BESCR(r4)
753 lwz r7, VCPU_GUEST_PID(r4)
759 /* POWER8-only registers */
760 ld r5, VCPU_TCSCR(r4)
762 ld r7, VCPU_CSIGR(r4)
771 ld r5, VCPU_SPRG0(r4)
772 ld r6, VCPU_SPRG1(r4)
773 ld r7, VCPU_SPRG2(r4)
774 ld r8, VCPU_SPRG3(r4)
780 /* Load up DAR and DSISR */
782 lwz r6, VCPU_DSISR(r4)
786 /* Restore AMR and UAMOR, set AMOR to all 1s */
792 /* Restore state of CTRL run bit; the host currently has it set to 1 */
799 /* Secondary threads wait for primary to have done partition switch */
800 ld r5, HSTATE_KVM_VCORE(r13)
801 lbz r6, HSTATE_PTID(r13)
804 lbz r0, VCORE_IN_GUEST(r5)
808 20: lwz r3, VCORE_ENTRY_EXIT(r5)
811 lbz r0, VCORE_IN_GUEST(r5)
822 * Set the decrementer to the guest decrementer.
824 ld r8,VCPU_DEC_EXPIRES(r4)
829 /* Check if HDEC expires soon */
832 cmpdi r3, 512 /* 1 microsecond */
835 /* Clear out and reload the SLB */
841 /* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
842 lwz r5,VCPU_SLB_MAX(r4)
847 1: ld r8,VCPU_SLB_E(r6)
850 addi r6,r6,VCPU_SLB_SIZE
854 deliver_guest_interrupt: /* r4 = vcpu, r13 = paca */
855 /* Check if we can deliver an external or decrementer interrupt now */
856 ld r0, VCPU_PENDING_EXC(r4)
860 bl kvmppc_guest_entry_inject_int
861 ld r4, HSTATE_KVM_VCPU(r13)
870 /* r11 = vcpu->arch.msr & ~MSR_HV */
871 rldicl r11, r11, 63 - MSR_HV_LG, 1
872 rotldi r11, r11, 1 + MSR_HV_LG
883 * R10: value for HSRR0
884 * R11: value for HSRR1
889 stb r0,VCPU_CEDED(r4) /* cancel cede */
893 /* Activate guest mode, so faults get handled by KVM */
894 li r9, KVM_GUEST_MODE_GUEST_HV
895 stb r9, HSTATE_IN_GUEST(r13)
897 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
898 /* Accumulate timing */
899 addi r3, r4, VCPU_TB_GUEST
900 bl kvmhv_accumulate_time
908 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
911 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
916 ld r1, VCPU_GPR(R1)(r4)
917 ld r5, VCPU_GPR(R5)(r4)
918 ld r8, VCPU_GPR(R8)(r4)
919 ld r9, VCPU_GPR(R9)(r4)
920 ld r10, VCPU_GPR(R10)(r4)
921 ld r11, VCPU_GPR(R11)(r4)
922 ld r12, VCPU_GPR(R12)(r4)
923 ld r13, VCPU_GPR(R13)(r4)
927 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
929 ld r6, VCPU_GPR(R6)(r4)
930 ld r7, VCPU_GPR(R7)(r4)
935 ld r0, VCPU_GPR(R0)(r4)
936 ld r2, VCPU_GPR(R2)(r4)
937 ld r3, VCPU_GPR(R3)(r4)
938 ld r4, VCPU_GPR(R4)(r4)
944 stw r12, STACK_SLOT_TRAP(r1)
947 stw r12, VCPU_TRAP(r4)
948 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
949 addi r3, r4, VCPU_TB_RMEXIT
950 bl kvmhv_accumulate_time
952 11: b kvmhv_switch_to_host
959 li r12, BOOK3S_INTERRUPT_HV_DECREMENTER
960 12: stw r12, VCPU_TRAP(r4)
962 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
963 addi r3, r4, VCPU_TB_RMEXIT
964 bl kvmhv_accumulate_time
968 /******************************************************************************
972 *****************************************************************************/
975 * We come here from the first-level interrupt handlers.
977 .globl kvmppc_interrupt_hv
981 * R9 = HSTATE_IN_GUEST
982 * R12 = (guest CR << 32) | interrupt vector
984 * guest R12 saved in shadow VCPU SCRATCH0
985 * guest R13 saved in SPRN_SCRATCH0
986 * guest R9 saved in HSTATE_SCRATCH2
988 /* We're now back in the host but in guest MMU context */
989 cmpwi r9,KVM_GUEST_MODE_HOST_HV
990 beq kvmppc_bad_host_intr
991 li r9, KVM_GUEST_MODE_HOST_HV
992 stb r9, HSTATE_IN_GUEST(r13)
994 ld r9, HSTATE_KVM_VCPU(r13)
998 std r0, VCPU_GPR(R0)(r9)
999 std r1, VCPU_GPR(R1)(r9)
1000 std r2, VCPU_GPR(R2)(r9)
1001 std r3, VCPU_GPR(R3)(r9)
1002 std r4, VCPU_GPR(R4)(r9)
1003 std r5, VCPU_GPR(R5)(r9)
1004 std r6, VCPU_GPR(R6)(r9)
1005 std r7, VCPU_GPR(R7)(r9)
1006 std r8, VCPU_GPR(R8)(r9)
1007 ld r0, HSTATE_SCRATCH2(r13)
1008 std r0, VCPU_GPR(R9)(r9)
1009 std r10, VCPU_GPR(R10)(r9)
1010 std r11, VCPU_GPR(R11)(r9)
1011 ld r3, HSTATE_SCRATCH0(r13)
1012 std r3, VCPU_GPR(R12)(r9)
1013 /* CR is in the high half of r12 */
1017 ld r3, HSTATE_CFAR(r13)
1018 std r3, VCPU_CFAR(r9)
1019 END_FTR_SECTION_IFSET(CPU_FTR_CFAR)
1021 ld r4, HSTATE_PPR(r13)
1022 std r4, VCPU_PPR(r9)
1023 END_FTR_SECTION_IFSET(CPU_FTR_HAS_PPR)
1025 /* Restore R1/R2 so we can handle faults */
1026 ld r1, HSTATE_HOST_R1(r13)
1029 mfspr r10, SPRN_SRR0
1030 mfspr r11, SPRN_SRR1
1031 std r10, VCPU_SRR0(r9)
1032 std r11, VCPU_SRR1(r9)
1033 /* trap is in the low half of r12, clear CR from the high half */
1035 andi. r0, r12, 2 /* need to read HSRR0/1? */
1037 mfspr r10, SPRN_HSRR0
1038 mfspr r11, SPRN_HSRR1
1040 1: std r10, VCPU_PC(r9)
1041 std r11, VCPU_MSR(r9)
1045 std r3, VCPU_GPR(R13)(r9)
1048 stw r12,VCPU_TRAP(r9)
1051 * Now that we have saved away SRR0/1 and HSRR0/1,
1052 * interrupts are recoverable in principle, so set MSR_RI.
1053 * This becomes important for relocation-on interrupts from
1054 * the guest, which we can get in radix mode on POWER9.
1059 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
1060 addi r3, r9, VCPU_TB_RMINTR
1062 bl kvmhv_accumulate_time
1063 ld r5, VCPU_GPR(R5)(r9)
1064 ld r6, VCPU_GPR(R6)(r9)
1065 ld r7, VCPU_GPR(R7)(r9)
1066 ld r8, VCPU_GPR(R8)(r9)
1069 /* Save HEIR (HV emulation assist reg) in emul_inst
1070 if this is an HEI (HV emulation interrupt, e40) */
1071 li r3,KVM_INST_FETCH_FAILED
1072 stw r3,VCPU_LAST_INST(r9)
1073 cmpwi r12,BOOK3S_INTERRUPT_H_EMUL_ASSIST
1076 11: stw r3,VCPU_HEIR(r9)
1078 /* these are volatile across C function calls */
1081 std r3, VCPU_CTR(r9)
1082 std r4, VCPU_XER(r9)
1084 /* Save more register state */
1087 std r3, VCPU_DAR(r9)
1088 stw r4, VCPU_DSISR(r9)
1090 /* If this is a page table miss then see if it's theirs or ours */
1091 cmpwi r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1093 std r3, VCPU_FAULT_DAR(r9)
1094 stw r4, VCPU_FAULT_DSISR(r9)
1095 cmpwi r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1098 /* See if this is a leftover HDEC interrupt */
1099 cmpwi r12,BOOK3S_INTERRUPT_HV_DECREMENTER
1105 bge fast_guest_return
1107 /* See if this is an hcall we can handle in real mode */
1108 cmpwi r12,BOOK3S_INTERRUPT_SYSCALL
1109 beq hcall_try_real_mode
1111 /* Hypervisor doorbell - exit only if host IPI flag set */
1112 cmpwi r12, BOOK3S_INTERRUPT_H_DOORBELL
1114 lbz r0, HSTATE_HOST_IPI(r13)
1116 beq maybe_reenter_guest
1119 /* If it's a hypervisor facility unavailable interrupt, save HFSCR */
1120 cmpwi r12, BOOK3S_INTERRUPT_H_FAC_UNAVAIL
1122 mfspr r3, SPRN_HFSCR
1123 std r3, VCPU_HFSCR(r9)
1126 /* External interrupt ? */
1127 cmpwi r12, BOOK3S_INTERRUPT_EXTERNAL
1128 beq kvmppc_guest_external
1129 /* See if it is a machine check */
1130 cmpwi r12, BOOK3S_INTERRUPT_MACHINE_CHECK
1131 beq machine_check_realmode
1132 /* Or a hypervisor maintenance interrupt */
1133 cmpwi r12, BOOK3S_INTERRUPT_HMI
1136 guest_exit_cont: /* r9 = vcpu, r12 = trap, r13 = paca */
1138 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
1139 addi r3, r9, VCPU_TB_RMEXIT
1141 bl kvmhv_accumulate_time
1145 * Possibly flush the link stack here, before we do a blr in
1146 * kvmhv_switch_to_host.
1149 patch_site 1b patch__call_kvm_flush_link_stack
1151 /* For hash guest, read the guest SLB and save it away */
1153 lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
1158 andis. r0,r8,SLB_ESID_V@h
1160 add r8,r8,r6 /* put index in */
1162 std r8,VCPU_SLB_E(r7)
1163 std r3,VCPU_SLB_V(r7)
1164 addi r7,r7,VCPU_SLB_SIZE
1168 /* Finally clear out the SLB */
1173 stw r5,VCPU_SLB_MAX(r9)
1175 /* load host SLB entries */
1176 ld r8,PACA_SLBSHADOWPTR(r13)
1178 .rept SLB_NUM_BOLTED
1179 li r3, SLBSHADOW_SAVEAREA
1183 andis. r7,r5,SLB_ESID_V@h
1190 stw r12, STACK_SLOT_TRAP(r1)
1193 /* Do this before kvmhv_commence_exit so we know TB is guest TB */
1194 ld r3, HSTATE_KVM_VCORE(r13)
1199 std r5,VCPU_DEC_EXPIRES(r9)
1201 /* Increment exit count, poke other threads to exit */
1203 bl kvmhv_commence_exit
1205 ld r9, HSTATE_KVM_VCPU(r13)
1207 /* Stop others sending VCPU interrupts to this physical CPU */
1209 stw r0, VCPU_CPU(r9)
1210 stw r0, VCPU_THREAD_CPU(r9)
1212 /* Save guest CTRL register, set runlatch to 1 if it was clear */
1214 stw r6,VCPU_CTRL(r9)
1221 * Save the guest PURR/SPURR
1226 ld r8,VCPU_SPURR(r9)
1227 std r5,VCPU_PURR(r9)
1228 std r6,VCPU_SPURR(r9)
1233 * Restore host PURR/SPURR and add guest times
1234 * so that the time in the guest gets accounted.
1236 ld r3,HSTATE_PURR(r13)
1237 ld r4,HSTATE_SPURR(r13)
1245 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
1246 /* Save POWER8-specific registers */
1250 std r5, VCPU_IAMR(r9)
1251 stw r6, VCPU_PSPB(r9)
1252 std r7, VCPU_FSCR(r9)
1256 std r7, VCPU_TAR(r9)
1257 mfspr r8, SPRN_EBBHR
1258 std r8, VCPU_EBBHR(r9)
1259 mfspr r5, SPRN_EBBRR
1260 mfspr r6, SPRN_BESCR
1263 std r5, VCPU_EBBRR(r9)
1264 std r6, VCPU_BESCR(r9)
1265 stw r7, VCPU_GUEST_PID(r9)
1266 std r8, VCPU_WORT(r9)
1267 mfspr r5, SPRN_TCSCR
1269 mfspr r7, SPRN_CSIGR
1271 std r5, VCPU_TCSCR(r9)
1272 std r6, VCPU_ACOP(r9)
1273 std r7, VCPU_CSIGR(r9)
1274 std r8, VCPU_TACR(r9)
1276 ld r5, STACK_SLOT_FSCR(r1)
1278 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1280 * Restore various registers to 0, where non-zero values
1281 * set by the guest could disrupt the host.
1286 mtspr SPRN_TCSCR, r0
1287 /* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
1290 mtspr SPRN_MMCRS, r0
1292 /* Save and restore AMR, IAMR and UAMOR before turning on the MMU */
1293 ld r8, STACK_SLOT_IAMR(r1)
1296 8: /* Power7 jumps back in here */
1300 std r6,VCPU_UAMOR(r9)
1301 ld r5,STACK_SLOT_AMR(r1)
1302 ld r6,STACK_SLOT_UAMOR(r1)
1304 mtspr SPRN_UAMOR, r6
1306 /* Switch DSCR back to host value */
1308 ld r7, HSTATE_DSCR(r13)
1309 std r8, VCPU_DSCR(r9)
1312 /* Save non-volatile GPRs */
1313 std r14, VCPU_GPR(R14)(r9)
1314 std r15, VCPU_GPR(R15)(r9)
1315 std r16, VCPU_GPR(R16)(r9)
1316 std r17, VCPU_GPR(R17)(r9)
1317 std r18, VCPU_GPR(R18)(r9)
1318 std r19, VCPU_GPR(R19)(r9)
1319 std r20, VCPU_GPR(R20)(r9)
1320 std r21, VCPU_GPR(R21)(r9)
1321 std r22, VCPU_GPR(R22)(r9)
1322 std r23, VCPU_GPR(R23)(r9)
1323 std r24, VCPU_GPR(R24)(r9)
1324 std r25, VCPU_GPR(R25)(r9)
1325 std r26, VCPU_GPR(R26)(r9)
1326 std r27, VCPU_GPR(R27)(r9)
1327 std r28, VCPU_GPR(R28)(r9)
1328 std r29, VCPU_GPR(R29)(r9)
1329 std r30, VCPU_GPR(R30)(r9)
1330 std r31, VCPU_GPR(R31)(r9)
1333 mfspr r3, SPRN_SPRG0
1334 mfspr r4, SPRN_SPRG1
1335 mfspr r5, SPRN_SPRG2
1336 mfspr r6, SPRN_SPRG3
1337 std r3, VCPU_SPRG0(r9)
1338 std r4, VCPU_SPRG1(r9)
1339 std r5, VCPU_SPRG2(r9)
1340 std r6, VCPU_SPRG3(r9)
1346 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1349 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
1351 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
1355 li r5, 0 /* don't preserve non-vol regs */
1356 bl kvmppc_save_tm_hv
1358 ld r9, HSTATE_KVM_VCPU(r13)
1362 /* Increment yield count if they have a VPA */
1363 ld r8, VCPU_VPA(r9) /* do they have a VPA? */
1366 li r4, LPPACA_YIELDCOUNT
1371 stb r3, VCPU_VPA_DIRTY(r9)
1373 /* Save PMU registers if requested */
1374 /* r8 and cr0.eq are live here */
1377 beq 21f /* if no VPA, save PMU stuff anyway */
1378 lbz r4, LPPACA_PMCINUSE(r8)
1379 21: bl kvmhv_save_guest_pmu
1380 ld r9, HSTATE_KVM_VCPU(r13)
1382 /* Restore host values of some registers */
1384 ld r5, STACK_SLOT_CIABR(r1)
1385 ld r6, STACK_SLOT_DAWR0(r1)
1386 ld r7, STACK_SLOT_DAWRX0(r1)
1387 mtspr SPRN_CIABR, r5
1389 * If the DAWR doesn't work, it's ok to write these here as
1390 * this value should always be zero
1392 mtspr SPRN_DAWR0, r6
1393 mtspr SPRN_DAWRX0, r7
1394 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1397 * POWER7/POWER8 guest -> host partition switch code.
1398 * We don't have to lock against tlbies but we do
1399 * have to coordinate the hardware threads.
1400 * Here STACK_SLOT_TRAP(r1) contains the trap number.
1402 kvmhv_switch_to_host:
1403 /* Secondary threads wait for primary to do partition switch */
1404 ld r5,HSTATE_KVM_VCORE(r13)
1405 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1406 lbz r3,HSTATE_PTID(r13)
1410 13: lbz r3,VCORE_IN_GUEST(r5)
1416 /* Primary thread waits for all the secondaries to exit guest */
1417 15: lwz r3,VCORE_ENTRY_EXIT(r5)
1418 rlwinm r0,r3,32-8,0xff
1424 /* Did we actually switch to the guest at all? */
1425 lbz r6, VCORE_IN_GUEST(r5)
1429 /* Primary thread switches back to host partition */
1430 lwz r7,KVM_HOST_LPID(r4)
1431 ld r6,KVM_HOST_SDR1(r4)
1432 li r8,LPID_RSVD /* switch to reserved LPID */
1435 mtspr SPRN_SDR1,r6 /* switch to host page table */
1440 /* DPDES and VTB are shared between threads */
1441 mfspr r7, SPRN_DPDES
1443 std r7, VCORE_DPDES(r5)
1444 std r8, VCORE_VTB(r5)
1445 /* clear DPDES so we don't get guest doorbells in the host */
1447 mtspr SPRN_DPDES, r8
1448 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
1450 /* Subtract timebase offset from timebase */
1451 ld r8, VCORE_TB_OFFSET_APPL(r5)
1455 std r0, VCORE_TB_OFFSET_APPL(r5)
1456 mftb r6 /* current guest timebase */
1458 mtspr SPRN_TBU40,r8 /* update upper 40 bits */
1459 mftb r7 /* check if lower 24 bits overflowed */
1464 addis r8,r8,0x100 /* if so, increment upper 40 bits */
1469 * If this is an HMI, we called kvmppc_realmode_hmi_handler
1470 * above, which may or may not have already called
1471 * kvmppc_subcore_exit_guest. Fortunately, all that
1472 * kvmppc_subcore_exit_guest does is clear a flag, so calling
1473 * it again here is benign even if kvmppc_realmode_hmi_handler
1474 * has already called it.
1476 bl kvmppc_subcore_exit_guest
1478 30: ld r5,HSTATE_KVM_VCORE(r13)
1479 ld r4,VCORE_KVM(r5) /* pointer to struct kvm */
1482 ld r0, VCORE_PCR(r5)
1483 LOAD_REG_IMMEDIATE(r6, PCR_MASK)
1488 /* Signal secondary CPUs to continue */
1490 stb r0,VCORE_IN_GUEST(r5)
1491 19: lis r8,0x7fff /* MAX_INT@h */
1494 16: ld r8,KVM_HOST_LPCR(r4)
1498 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
1499 /* Finish timing, if we have a vcpu */
1500 ld r4, HSTATE_KVM_VCPU(r13)
1504 bl kvmhv_accumulate_time
1507 /* Unset guest mode */
1508 li r0, KVM_GUEST_MODE_NONE
1509 stb r0, HSTATE_IN_GUEST(r13)
1511 lwz r12, STACK_SLOT_TRAP(r1) /* return trap # in r12 */
1512 ld r0, SFS+PPC_LR_STKOFF(r1)
1518 .global kvm_flush_link_stack
1519 kvm_flush_link_stack:
1520 /* Save LR into r0 */
1523 /* Flush the link stack. On Power8 it's up to 32 entries in size. */
1528 /* And on Power9 it's up to 64. */
1533 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
1539 kvmppc_guest_external:
1540 /* External interrupt, first check for host_ipi. If this is
1541 * set, we know the host wants us out so let's do it now
1546 * Restore the active volatile registers after returning from
1549 ld r9, HSTATE_KVM_VCPU(r13)
1550 li r12, BOOK3S_INTERRUPT_EXTERNAL
1553 * kvmppc_read_intr return codes:
1555 * Exit to host (r3 > 0)
1556 * 1 An interrupt is pending that needs to be handled by the host
1557 * Exit guest and return to host by branching to guest_exit_cont
1559 * 2 Passthrough that needs completion in the host
1560 * Exit guest and return to host by branching to guest_exit_cont
1561 * However, we also set r12 to BOOK3S_INTERRUPT_HV_RM_HARD
1562 * to indicate to the host to complete handling the interrupt
1564 * Before returning to guest, we check if any CPU is heading out
1565 * to the host and if so, we head out also. If no CPUs are heading
1566 * check return values <= 0.
1568 * Return to guest (r3 <= 0)
1569 * 0 No external interrupt is pending
1570 * -1 A guest wakeup IPI (which has now been cleared)
1571 * In either case, we return to guest to deliver any pending
1574 * -2 A PCI passthrough external interrupt was handled
1575 * (interrupt was delivered directly to guest)
1576 * Return to guest to deliver any pending guest interrupts.
1582 /* Return code = 2 */
1583 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
1584 stw r12, VCPU_TRAP(r9)
1587 1: /* Return code <= 1 */
1591 /* Return code <= 0 */
1592 maybe_reenter_guest:
1593 ld r5, HSTATE_KVM_VCORE(r13)
1594 lwz r0, VCORE_ENTRY_EXIT(r5)
1597 blt deliver_guest_interrupt
1601 * Check whether an HDSI is an HPTE not found fault or something else.
1602 * If it is an HPTE not found fault that is due to the guest accessing
1603 * a page that they have mapped but which we have paged out, then
1604 * we continue on with the guest exit path. In all other cases,
1605 * reflect the HDSI to the guest as a DSI.
1609 mfspr r6, SPRN_HDSISR
1610 /* HPTE not found fault or protection fault? */
1611 andis. r0, r6, (DSISR_NOHPTE | DSISR_PROTFAULT)@h
1612 beq 1f /* if not, send it to the guest */
1613 andi. r0, r11, MSR_DR /* data relocation enabled? */
1616 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1617 li r0, BOOK3S_INTERRUPT_DATA_SEGMENT
1618 bne 7f /* if no SLB entry found */
1619 4: std r4, VCPU_FAULT_DAR(r9)
1620 stw r6, VCPU_FAULT_DSISR(r9)
1622 /* Search the hash table. */
1623 mr r3, r9 /* vcpu pointer */
1624 li r7, 1 /* data fault */
1625 bl kvmppc_hpte_hv_fault
1626 ld r9, HSTATE_KVM_VCPU(r13)
1628 ld r11, VCPU_MSR(r9)
1629 li r12, BOOK3S_INTERRUPT_H_DATA_STORAGE
1630 cmpdi r3, 0 /* retry the instruction */
1632 cmpdi r3, -1 /* handle in kernel mode */
1634 cmpdi r3, -2 /* MMIO emulation; need instr word */
1637 /* Synthesize a DSI (or DSegI) for the guest */
1638 ld r4, VCPU_FAULT_DAR(r9)
1640 1: li r0, BOOK3S_INTERRUPT_DATA_STORAGE
1641 mtspr SPRN_DSISR, r6
1642 7: mtspr SPRN_DAR, r4
1643 mtspr SPRN_SRR0, r10
1644 mtspr SPRN_SRR1, r11
1646 bl kvmppc_msr_interrupt
1647 fast_interrupt_c_return:
1648 6: ld r7, VCPU_CTR(r9)
1655 3: ld r5, VCPU_KVM(r9) /* not relocated, use VRMA */
1656 ld r5, KVM_VRMA_SLB_V(r5)
1659 /* If this is for emulated MMIO, load the instruction word */
1660 2: li r8, KVM_INST_FETCH_FAILED /* In case lwz faults */
1662 /* Set guest mode to 'jump over instruction' so if lwz faults
1663 * we'll just continue at the next IP. */
1664 li r0, KVM_GUEST_MODE_SKIP
1665 stb r0, HSTATE_IN_GUEST(r13)
1667 /* Do the access with MSR:DR enabled */
1669 ori r4, r3, MSR_DR /* Enable paging for data */
1674 /* Store the result */
1675 stw r8, VCPU_LAST_INST(r9)
1677 /* Unset guest mode. */
1678 li r0, KVM_GUEST_MODE_HOST_HV
1679 stb r0, HSTATE_IN_GUEST(r13)
1683 * Similarly for an HISI, reflect it to the guest as an ISI unless
1684 * it is an HPTE not found fault for a page that we have paged out.
1687 andis. r0, r11, SRR1_ISI_NOPT@h
1689 andi. r0, r11, MSR_IR /* instruction relocation enabled? */
1692 PPC_SLBFEE_DOT(R5, R0) /* if so, look up SLB */
1693 li r0, BOOK3S_INTERRUPT_INST_SEGMENT
1694 bne 7f /* if no SLB entry found */
1696 /* Search the hash table. */
1697 mr r3, r9 /* vcpu pointer */
1700 li r7, 0 /* instruction fault */
1701 bl kvmppc_hpte_hv_fault
1702 ld r9, HSTATE_KVM_VCPU(r13)
1704 ld r11, VCPU_MSR(r9)
1705 li r12, BOOK3S_INTERRUPT_H_INST_STORAGE
1706 cmpdi r3, 0 /* retry the instruction */
1707 beq fast_interrupt_c_return
1708 cmpdi r3, -1 /* handle in kernel mode */
1711 /* Synthesize an ISI (or ISegI) for the guest */
1713 1: li r0, BOOK3S_INTERRUPT_INST_STORAGE
1714 7: mtspr SPRN_SRR0, r10
1715 mtspr SPRN_SRR1, r11
1717 bl kvmppc_msr_interrupt
1718 b fast_interrupt_c_return
1720 3: ld r6, VCPU_KVM(r9) /* not relocated, use VRMA */
1721 ld r5, KVM_VRMA_SLB_V(r6)
1725 * Try to handle an hcall in real mode.
1726 * Returns to the guest if we handle it, or continues on up to
1727 * the kernel if we can't (i.e. if we don't have a handler for
1728 * it, or if the handler returns H_TOO_HARD).
1730 * r5 - r8 contain hcall args,
1731 * r9 = vcpu, r10 = pc, r11 = msr, r12 = trap, r13 = paca
1733 hcall_try_real_mode:
1734 ld r3,VCPU_GPR(R3)(r9)
1736 /* sc 1 from userspace - reflect to guest syscall */
1737 bne sc_1_fast_return
1739 cmpldi r3,hcall_real_table_end - hcall_real_table
1741 /* See if this hcall is enabled for in-kernel handling */
1743 srdi r0, r3, 8 /* r0 = (r3 / 4) >> 6 */
1744 sldi r0, r0, 3 /* index into kvm->arch.enabled_hcalls[] */
1746 ld r0, KVM_ENABLED_HCALLS(r4)
1747 rlwinm r4, r3, 32-2, 0x3f /* r4 = (r3 / 4) & 0x3f */
1751 /* Get pointer to handler, if any, and call it */
1752 LOAD_REG_ADDR(r4, hcall_real_table)
1758 mr r3,r9 /* get vcpu pointer */
1759 ld r4,VCPU_GPR(R4)(r9)
1762 beq hcall_real_fallback
1763 ld r4,HSTATE_KVM_VCPU(r13)
1764 std r3,VCPU_GPR(R3)(r4)
1772 li r10, BOOK3S_INTERRUPT_SYSCALL
1773 bl kvmppc_msr_interrupt
1777 /* We've attempted a real mode hcall, but it's punted it back
1778 * to userspace. We need to restore some clobbered volatiles
1779 * before resuming the pass-it-to-qemu path */
1780 hcall_real_fallback:
1781 li r12,BOOK3S_INTERRUPT_SYSCALL
1782 ld r9, HSTATE_KVM_VCPU(r13)
1786 .globl hcall_real_table
1788 .long 0 /* 0 - unused */
1789 .long DOTSYM(kvmppc_h_remove) - hcall_real_table
1790 .long DOTSYM(kvmppc_h_enter) - hcall_real_table
1791 .long DOTSYM(kvmppc_h_read) - hcall_real_table
1792 .long DOTSYM(kvmppc_h_clear_mod) - hcall_real_table
1793 .long DOTSYM(kvmppc_h_clear_ref) - hcall_real_table
1794 .long DOTSYM(kvmppc_h_protect) - hcall_real_table
1797 .long 0 /* 0x24 - H_SET_SPRG0 */
1798 .long DOTSYM(kvmppc_h_set_dabr) - hcall_real_table
1799 .long DOTSYM(kvmppc_rm_h_page_init) - hcall_real_table
1813 #ifdef CONFIG_KVM_XICS
1814 .long DOTSYM(xics_rm_h_eoi) - hcall_real_table
1815 .long DOTSYM(xics_rm_h_cppr) - hcall_real_table
1816 .long DOTSYM(xics_rm_h_ipi) - hcall_real_table
1817 .long 0 /* 0x70 - H_IPOLL */
1818 .long DOTSYM(xics_rm_h_xirr) - hcall_real_table
1820 .long 0 /* 0x64 - H_EOI */
1821 .long 0 /* 0x68 - H_CPPR */
1822 .long 0 /* 0x6c - H_IPI */
1823 .long 0 /* 0x70 - H_IPOLL */
1824 .long 0 /* 0x74 - H_XIRR */
1852 .long DOTSYM(kvmppc_h_cede) - hcall_real_table
1853 .long DOTSYM(kvmppc_rm_h_confer) - hcall_real_table
1869 .long DOTSYM(kvmppc_h_bulk_remove) - hcall_real_table
1873 .long DOTSYM(kvmppc_h_set_xdabr) - hcall_real_table
1987 #ifdef CONFIG_KVM_XICS
1988 .long DOTSYM(xics_rm_h_xirr_x) - hcall_real_table
1990 .long 0 /* 0x2fc - H_XIRR_X*/
1992 .long DOTSYM(kvmppc_rm_h_random) - hcall_real_table
1993 .globl hcall_real_table_end
1994 hcall_real_table_end:
1996 _GLOBAL_TOC(kvmppc_h_set_xdabr)
1997 EXPORT_SYMBOL_GPL(kvmppc_h_set_xdabr)
1998 andi. r0, r5, DABRX_USER | DABRX_KERNEL
2000 li r0, DABRX_USER | DABRX_KERNEL | DABRX_BTI
2003 6: li r3, H_PARAMETER
2006 _GLOBAL_TOC(kvmppc_h_set_dabr)
2007 EXPORT_SYMBOL_GPL(kvmppc_h_set_dabr)
2008 li r5, DABRX_USER | DABRX_KERNEL
2012 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2013 std r4,VCPU_DABR(r3)
2014 stw r5, VCPU_DABRX(r3)
2015 mtspr SPRN_DABRX, r5
2016 /* Work around P7 bug where DABR can get corrupted on mtspr */
2017 1: mtspr SPRN_DABR,r4
2026 LOAD_REG_ADDR(r11, dawr_force_enable)
2033 /* Emulate H_SET_DABR/X on P8 for the sake of compat mode guests */
2034 rlwimi r5, r4, 5, DAWRX_DR | DAWRX_DW
2035 rlwimi r5, r4, 2, DAWRX_WT
2037 std r4, VCPU_DAWR0(r3)
2038 std r5, VCPU_DAWRX0(r3)
2040 * If came in through the real mode hcall handler then it is necessary
2041 * to write the registers since the return path won't. Otherwise it is
2042 * sufficient to store then in the vcpu struct as they will be loaded
2043 * next time the vcpu is run.
2046 andi. r6, r6, MSR_DR /* in real mode? */
2048 mtspr SPRN_DAWR0, r4
2049 mtspr SPRN_DAWRX0, r5
2053 _GLOBAL(kvmppc_h_cede) /* r3 = vcpu pointer, r11 = msr, r13 = paca */
2055 std r11,VCPU_MSR(r3)
2057 stb r0,VCPU_CEDED(r3)
2058 sync /* order setting ceded vs. testing prodded */
2059 lbz r5,VCPU_PRODDED(r3)
2061 bne kvm_cede_prodded
2062 li r12,0 /* set trap to 0 to say hcall is handled */
2063 stw r12,VCPU_TRAP(r3)
2065 std r0,VCPU_GPR(R3)(r3)
2068 * Set our bit in the bitmask of napping threads unless all the
2069 * other threads are already napping, in which case we send this
2072 ld r5,HSTATE_KVM_VCORE(r13)
2073 lbz r6,HSTATE_PTID(r13)
2074 lwz r8,VCORE_ENTRY_EXIT(r5)
2078 addi r6,r5,VCORE_NAPPING_THREADS
2085 /* order napping_threads update vs testing entry_exit_map */
2088 stb r0,HSTATE_NAPPING(r13)
2089 lwz r7,VCORE_ENTRY_EXIT(r5)
2091 bge 33f /* another thread already exiting */
2094 * Although not specifically required by the architecture, POWER7
2095 * preserves the following registers in nap mode, even if an SMT mode
2096 * switch occurs: SLB entries, PURR, SPURR, AMOR, UAMOR, AMR, SPRG0-3,
2097 * DAR, DSISR, DABR, DABRX, DSCR, PMCx, MMCRx, SIAR, SDAR.
2099 /* Save non-volatile GPRs */
2100 std r14, VCPU_GPR(R14)(r3)
2101 std r15, VCPU_GPR(R15)(r3)
2102 std r16, VCPU_GPR(R16)(r3)
2103 std r17, VCPU_GPR(R17)(r3)
2104 std r18, VCPU_GPR(R18)(r3)
2105 std r19, VCPU_GPR(R19)(r3)
2106 std r20, VCPU_GPR(R20)(r3)
2107 std r21, VCPU_GPR(R21)(r3)
2108 std r22, VCPU_GPR(R22)(r3)
2109 std r23, VCPU_GPR(R23)(r3)
2110 std r24, VCPU_GPR(R24)(r3)
2111 std r25, VCPU_GPR(R25)(r3)
2112 std r26, VCPU_GPR(R26)(r3)
2113 std r27, VCPU_GPR(R27)(r3)
2114 std r28, VCPU_GPR(R28)(r3)
2115 std r29, VCPU_GPR(R29)(r3)
2116 std r30, VCPU_GPR(R30)(r3)
2117 std r31, VCPU_GPR(R31)(r3)
2122 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2125 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
2127 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2129 ld r3, HSTATE_KVM_VCPU(r13)
2131 li r5, 0 /* don't preserve non-vol regs */
2132 bl kvmppc_save_tm_hv
2138 * Set DEC to the smaller of DEC and HDEC, so that we wake
2139 * no later than the end of our timeslice (HDEC interrupts
2140 * don't wake us from nap).
2151 /* save expiry time of guest decrementer */
2153 ld r4, HSTATE_KVM_VCPU(r13)
2154 std r3, VCPU_DEC_EXPIRES(r4)
2156 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
2157 ld r4, HSTATE_KVM_VCPU(r13)
2158 addi r3, r4, VCPU_TB_CEDE
2159 bl kvmhv_accumulate_time
2162 lis r3, LPCR_PECEDP@h /* Do wake on privileged doorbell */
2164 /* Go back to host stack */
2165 ld r1, HSTATE_HOST_R1(r13)
2168 * Take a nap until a decrementer or external or doobell interrupt
2169 * occurs, with PECE1 and PECE0 set in LPCR.
2170 * On POWER8, set PECEDH, and if we are ceding, also set PECEDP.
2171 * Also clear the runlatch bit before napping.
2175 mtspr SPRN_CTRLT, r0
2178 stb r0,HSTATE_HWTHREAD_REQ(r13)
2180 ori r5,r5,LPCR_PECE0 | LPCR_PECE1
2182 ori r5, r5, LPCR_PECEDH
2183 rlwimi r5, r3, 0, LPCR_PECEDP
2184 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2186 kvm_nap_sequence: /* desired LPCR value in r5 */
2187 li r3, PNV_THREAD_NAP
2191 bl isa206_idle_insn_mayloss
2194 mtspr SPRN_CTRLT, r0
2199 stb r0, PACA_FTRACE_ENABLED(r13)
2201 li r0, KVM_HWTHREAD_IN_KVM
2202 stb r0, HSTATE_HWTHREAD_STATE(r13)
2204 lbz r0, HSTATE_NAPPING(r13)
2205 cmpwi r0, NAPPING_CEDE
2207 cmpwi r0, NAPPING_NOVCPU
2208 beq kvm_novcpu_wakeup
2209 cmpwi r0, NAPPING_UNSPLIT
2210 beq kvm_unsplit_wakeup
2211 twi 31,0,0 /* Nap state must not be zero */
2219 /* Woken by external or decrementer interrupt */
2221 /* get vcpu pointer */
2222 ld r4, HSTATE_KVM_VCPU(r13)
2224 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
2225 addi r3, r4, VCPU_TB_RMINTR
2226 bl kvmhv_accumulate_time
2229 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2232 END_FTR_SECTION_IFCLR(CPU_FTR_TM)
2234 * NOTE THAT THIS TRASHES ALL NON-VOLATILE REGISTERS (but not CR)
2238 li r5, 0 /* don't preserve non-vol regs */
2239 bl kvmppc_restore_tm_hv
2241 ld r4, HSTATE_KVM_VCPU(r13)
2245 /* load up FP state */
2248 /* Restore guest decrementer */
2249 ld r3, VCPU_DEC_EXPIRES(r4)
2255 ld r14, VCPU_GPR(R14)(r4)
2256 ld r15, VCPU_GPR(R15)(r4)
2257 ld r16, VCPU_GPR(R16)(r4)
2258 ld r17, VCPU_GPR(R17)(r4)
2259 ld r18, VCPU_GPR(R18)(r4)
2260 ld r19, VCPU_GPR(R19)(r4)
2261 ld r20, VCPU_GPR(R20)(r4)
2262 ld r21, VCPU_GPR(R21)(r4)
2263 ld r22, VCPU_GPR(R22)(r4)
2264 ld r23, VCPU_GPR(R23)(r4)
2265 ld r24, VCPU_GPR(R24)(r4)
2266 ld r25, VCPU_GPR(R25)(r4)
2267 ld r26, VCPU_GPR(R26)(r4)
2268 ld r27, VCPU_GPR(R27)(r4)
2269 ld r28, VCPU_GPR(R28)(r4)
2270 ld r29, VCPU_GPR(R29)(r4)
2271 ld r30, VCPU_GPR(R30)(r4)
2272 ld r31, VCPU_GPR(R31)(r4)
2274 /* Check the wake reason in SRR1 to see why we got here */
2275 bl kvmppc_check_wake_reason
2278 * Restore volatile registers since we could have called a
2279 * C routine in kvmppc_check_wake_reason
2281 * r3 tells us whether we need to return to host or not
2282 * WARNING: it gets checked further down:
2283 * should not modify r3 until this check is done.
2285 ld r4, HSTATE_KVM_VCPU(r13)
2287 /* clear our bit in vcore->napping_threads */
2288 34: ld r5,HSTATE_KVM_VCORE(r13)
2289 lbz r7,HSTATE_PTID(r13)
2292 addi r6,r5,VCORE_NAPPING_THREADS
2298 stb r0,HSTATE_NAPPING(r13)
2300 /* See if the wake reason saved in r3 means we need to exit */
2301 stw r12, VCPU_TRAP(r4)
2305 b maybe_reenter_guest
2307 /* cede when already previously prodded case */
2310 stb r0,VCPU_PRODDED(r3)
2311 sync /* order testing prodded vs. clearing ceded */
2312 stb r0,VCPU_CEDED(r3)
2316 /* we've ceded but we want to give control to the host */
2318 ld r9, HSTATE_KVM_VCPU(r13)
2321 /* Try to do machine check recovery in real mode */
2322 machine_check_realmode:
2323 mr r3, r9 /* get vcpu pointer */
2324 bl kvmppc_realmode_machine_check
2326 /* all machine checks go to virtual mode for further handling */
2327 ld r9, HSTATE_KVM_VCPU(r13)
2328 li r12, BOOK3S_INTERRUPT_MACHINE_CHECK
2332 * Call C code to handle a HMI in real mode.
2333 * Only the primary thread does the call, secondary threads are handled
2334 * by calling hmi_exception_realmode() after kvmppc_hv_entry returns.
2335 * r9 points to the vcpu on entry
2338 lbz r0, HSTATE_PTID(r13)
2341 bl kvmppc_realmode_hmi_handler
2342 ld r9, HSTATE_KVM_VCPU(r13)
2343 li r12, BOOK3S_INTERRUPT_HMI
2347 * Check the reason we woke from nap, and take appropriate action.
2349 * 0 if nothing needs to be done
2350 * 1 if something happened that needs to be handled by the host
2351 * -1 if there was a guest wakeup (IPI or msgsnd)
2352 * -2 if we handled a PCI passthrough interrupt (returned by
2353 * kvmppc_read_intr only)
2355 * Also sets r12 to the interrupt vector for any interrupt that needs
2356 * to be handled now by the host (0x500 for external interrupt), or zero.
2357 * Modifies all volatile registers (since it may call a C function).
2358 * This routine calls kvmppc_read_intr, a C function, if an external
2359 * interrupt is pending.
2361 kvmppc_check_wake_reason:
2364 rlwinm r6, r6, 45-31, 0xf /* extract wake reason field (P8) */
2366 rlwinm r6, r6, 45-31, 0xe /* P7 wake reason field is 3 bits */
2367 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_207S)
2368 cmpwi r6, 8 /* was it an external interrupt? */
2369 beq 7f /* if so, see what it was */
2372 cmpwi r6, 6 /* was it the decrementer? */
2375 cmpwi r6, 5 /* privileged doorbell? */
2377 cmpwi r6, 3 /* hypervisor doorbell? */
2379 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2380 cmpwi r6, 0xa /* Hypervisor maintenance ? */
2382 li r3, 1 /* anything else, return 1 */
2385 /* hypervisor doorbell */
2386 3: li r12, BOOK3S_INTERRUPT_H_DOORBELL
2389 * Clear the doorbell as we will invoke the handler
2390 * explicitly in the guest exit path.
2392 lis r6, (PPC_DBELL_SERVER << (63-36))@h
2394 /* see if it's a host IPI */
2396 lbz r0, HSTATE_HOST_IPI(r13)
2399 /* if not, return -1 */
2403 /* Woken up due to Hypervisor maintenance interrupt */
2404 4: li r12, BOOK3S_INTERRUPT_HMI
2408 /* external interrupt - create a stack frame so we can call C */
2410 std r0, PPC_LR_STKOFF(r1)
2411 stdu r1, -PPC_MIN_STKFRM(r1)
2414 li r12, BOOK3S_INTERRUPT_EXTERNAL
2419 * Return code of 2 means PCI passthrough interrupt, but
2420 * we need to return back to host to complete handling the
2421 * interrupt. Trap reason is expected in r12 by guest
2424 li r12, BOOK3S_INTERRUPT_HV_RM_HARD
2426 ld r0, PPC_MIN_STKFRM+PPC_LR_STKOFF(r1)
2427 addi r1, r1, PPC_MIN_STKFRM
2432 * Save away FP, VMX and VSX registers.
2434 * N.B. r30 and r31 are volatile across this function,
2435 * thus it is not callable from C.
2442 #ifdef CONFIG_ALTIVEC
2444 oris r8,r8,MSR_VEC@h
2445 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2449 oris r8,r8,MSR_VSX@h
2450 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2453 addi r3,r3,VCPU_FPRS
2455 #ifdef CONFIG_ALTIVEC
2457 addi r3,r31,VCPU_VRS
2459 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2461 mfspr r6,SPRN_VRSAVE
2462 stw r6,VCPU_VRSAVE(r31)
2467 * Load up FP, VMX and VSX registers
2469 * N.B. r30 and r31 are volatile across this function,
2470 * thus it is not callable from C.
2477 #ifdef CONFIG_ALTIVEC
2479 oris r8,r8,MSR_VEC@h
2480 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2484 oris r8,r8,MSR_VSX@h
2485 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
2488 addi r3,r4,VCPU_FPRS
2490 #ifdef CONFIG_ALTIVEC
2492 addi r3,r31,VCPU_VRS
2494 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
2496 lwz r7,VCPU_VRSAVE(r31)
2497 mtspr SPRN_VRSAVE,r7
2502 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2504 * Save transactional state and TM-related registers.
2505 * Called with r3 pointing to the vcpu struct and r4 containing
2506 * the guest MSR value.
2507 * r5 is non-zero iff non-volatile register state needs to be maintained.
2508 * If r5 == 0, this can modify all checkpointed registers, but
2509 * restores r1 and r2 before exit.
2511 _GLOBAL_TOC(kvmppc_save_tm_hv)
2512 EXPORT_SYMBOL_GPL(kvmppc_save_tm_hv)
2513 /* See if we need to handle fake suspend mode */
2516 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
2518 lbz r0, HSTATE_FAKE_SUSPEND(r13) /* Were we fake suspended? */
2520 beq __kvmppc_save_tm
2522 /* The following code handles the fake_suspend = 1 case */
2524 std r0, PPC_LR_STKOFF(r1)
2525 stdu r1, -TM_FRAME_SIZE(r1)
2530 rldimi r8, r0, MSR_TM_LG, 63-MSR_TM_LG
2533 rldicl. r8, r8, 64 - MSR_TS_S_LG, 62 /* Did we actually hrfid? */
2536 bl pnv_power9_force_smt4_catch
2537 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
2541 * It's possible that treclaim. may modify registers, if we have lost
2542 * track of fake-suspend state in the guest due to it using rfscv.
2543 * Save and restore registers in case this occurs.
2548 /* SPRN_TAR would need to be saved here if the kernel ever used it */
2556 std r1, HSTATE_HOST_R1(r13)
2558 /* We have to treclaim here because that's the only way to do S->N */
2559 li r3, TM_CAUSE_KVM_RESCHED
2563 ld r1, HSTATE_HOST_R1(r13)
2577 * We were in fake suspend, so we are not going to save the
2578 * register state as the guest checkpointed state (since
2579 * we already have it), therefore we can now use any volatile GPR.
2580 * In fact treclaim in fake suspend state doesn't modify
2585 bl pnv_power9_force_smt4_release
2586 END_FTR_SECTION_IFSET(CPU_FTR_P9_TM_XER_SO_BUG)
2590 mfspr r3, SPRN_PSSCR
2591 /* PSSCR_FAKE_SUSPEND is a write-only bit, but clear it anyway */
2592 li r0, PSSCR_FAKE_SUSPEND
2594 mtspr SPRN_PSSCR, r3
2596 /* Don't save TEXASR, use value from last exit in real suspend state */
2597 ld r9, HSTATE_KVM_VCPU(r13)
2598 mfspr r5, SPRN_TFHAR
2599 mfspr r6, SPRN_TFIAR
2600 std r5, VCPU_TFHAR(r9)
2601 std r6, VCPU_TFIAR(r9)
2603 addi r1, r1, TM_FRAME_SIZE
2604 ld r0, PPC_LR_STKOFF(r1)
2609 * Restore transactional state and TM-related registers.
2610 * Called with r3 pointing to the vcpu struct
2611 * and r4 containing the guest MSR value.
2612 * r5 is non-zero iff non-volatile register state needs to be maintained.
2613 * This potentially modifies all checkpointed registers.
2614 * It restores r1 and r2 from the PACA.
2616 _GLOBAL_TOC(kvmppc_restore_tm_hv)
2617 EXPORT_SYMBOL_GPL(kvmppc_restore_tm_hv)
2619 * If we are doing TM emulation for the guest on a POWER9 DD2,
2620 * then we don't actually do a trechkpt -- we either set up
2621 * fake-suspend mode, or emulate a TM rollback.
2624 b __kvmppc_restore_tm
2625 END_FTR_SECTION_IFCLR(CPU_FTR_P9_TM_HV_ASSIST)
2627 std r0, PPC_LR_STKOFF(r1)
2630 stb r0, HSTATE_FAKE_SUSPEND(r13)
2632 /* Turn on TM so we can restore TM SPRs */
2635 rldimi r5, r0, MSR_TM_LG, 63-MSR_TM_LG
2639 * The user may change these outside of a transaction, so they must
2640 * always be context switched.
2642 ld r5, VCPU_TFHAR(r3)
2643 ld r6, VCPU_TFIAR(r3)
2644 ld r7, VCPU_TEXASR(r3)
2645 mtspr SPRN_TFHAR, r5
2646 mtspr SPRN_TFIAR, r6
2647 mtspr SPRN_TEXASR, r7
2649 rldicl. r5, r4, 64 - MSR_TS_S_LG, 62
2650 beqlr /* TM not active in guest */
2652 /* Make sure the failure summary is set */
2653 oris r7, r7, (TEXASR_FS)@h
2654 mtspr SPRN_TEXASR, r7
2656 cmpwi r5, 1 /* check for suspended state */
2658 stb r5, HSTATE_FAKE_SUSPEND(r13)
2659 b 9f /* and return */
2660 10: stdu r1, -PPC_MIN_STKFRM(r1)
2661 /* guest is in transactional state, so simulate rollback */
2662 bl kvmhv_emulate_tm_rollback
2664 addi r1, r1, PPC_MIN_STKFRM
2665 9: ld r0, PPC_LR_STKOFF(r1)
2668 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2671 * We come here if we get any exception or interrupt while we are
2672 * executing host real mode code while in guest MMU context.
2673 * r12 is (CR << 32) | vector
2674 * r13 points to our PACA
2675 * r12 is saved in HSTATE_SCRATCH0(r13)
2676 * r9 is saved in HSTATE_SCRATCH2(r13)
2677 * r13 is saved in HSPRG1
2678 * cfar is saved in HSTATE_CFAR(r13)
2679 * ppr is saved in HSTATE_PPR(r13)
2681 kvmppc_bad_host_intr:
2683 * Switch to the emergency stack, but start half-way down in
2684 * case we were already on it.
2688 ld r1, PACAEMERGSP(r13)
2689 subi r1, r1, THREAD_SIZE/2 + INT_FRAME_SIZE
2701 mfspr r3, SPRN_HSRR0
2702 mfspr r4, SPRN_HSRR1
2704 mfspr r6, SPRN_HDSISR
2706 1: mfspr r3, SPRN_SRR0
2709 mfspr r6, SPRN_DSISR
2714 ld r9, HSTATE_SCRATCH2(r13)
2715 ld r12, HSTATE_SCRATCH0(r13)
2717 SAVE_GPRS(9, 12, r1)
2720 ld r5, HSTATE_CFAR(r13)
2721 std r5, ORIG_GPR3(r1)
2725 lbz r6, PACAIRQSOFTMASK(r13)
2731 LOAD_REG_IMMEDIATE(3, STACK_FRAME_REGS_MARKER)
2732 std r3, STACK_FRAME_OVERHEAD-16(r1)
2735 * XXX On POWER7 and POWER8, we just spin here since we don't
2736 * know what the other threads are doing (and we don't want to
2737 * coordinate with them) - but at least we now have register state
2738 * in memory that we might be able to look at from another CPU.
2743 * This mimics the MSR transition on IRQ delivery. The new guest MSR is taken
2744 * from VCPU_INTR_MSR and is modified based on the required TM state changes.
2745 * r11 has the guest MSR value (in/out)
2746 * r9 has a vcpu pointer (in)
2747 * r0 is used as a scratch register
2749 kvmppc_msr_interrupt:
2750 rldicl r0, r11, 64 - MSR_TS_S_LG, 62
2751 cmpwi r0, 2 /* Check if we are in transactional state.. */
2752 ld r11, VCPU_INTR_MSR(r9)
2754 /* ... if transactional, change to suspended */
2756 1: rldimi r11, r0, MSR_TS_S_LG, 63 - MSR_TS_T_LG
2760 * void kvmhv_load_guest_pmu(struct kvm_vcpu *vcpu)
2762 * Load up guest PMU state. R3 points to the vcpu struct.
2764 kvmhv_load_guest_pmu:
2768 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
2769 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
2772 ld r3, VCPU_MMCR(r4)
2773 andi. r5, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
2774 cmpwi r5, MMCR0_PMAO
2775 beql kvmppc_fix_pmao
2776 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
2777 lwz r3, VCPU_PMC(r4) /* always load up guest PMU registers */
2778 lwz r5, VCPU_PMC + 4(r4) /* to prevent information leak */
2779 lwz r6, VCPU_PMC + 8(r4)
2780 lwz r7, VCPU_PMC + 12(r4)
2781 lwz r8, VCPU_PMC + 16(r4)
2782 lwz r9, VCPU_PMC + 20(r4)
2789 ld r3, VCPU_MMCR(r4)
2790 ld r5, VCPU_MMCR + 8(r4)
2791 ld r6, VCPU_MMCRA(r4)
2792 ld r7, VCPU_SIAR(r4)
2793 ld r8, VCPU_SDAR(r4)
2794 mtspr SPRN_MMCR1, r5
2795 mtspr SPRN_MMCRA, r6
2799 ld r5, VCPU_MMCR + 16(r4)
2800 ld r6, VCPU_SIER(r4)
2801 mtspr SPRN_MMCR2, r5
2803 lwz r7, VCPU_PMC + 24(r4)
2804 lwz r8, VCPU_PMC + 28(r4)
2805 ld r9, VCPU_MMCRS(r4)
2806 mtspr SPRN_SPMC1, r7
2807 mtspr SPRN_SPMC2, r8
2808 mtspr SPRN_MMCRS, r9
2809 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2810 mtspr SPRN_MMCR0, r3
2816 * void kvmhv_load_host_pmu(void)
2818 * Reload host PMU state saved in the PACA by kvmhv_save_host_pmu.
2820 kvmhv_load_host_pmu:
2822 lbz r4, PACA_PMCINUSE(r13) /* is the host using the PMU? */
2824 beq 23f /* skip if not */
2826 ld r3, HSTATE_MMCR0(r13)
2827 andi. r4, r3, MMCR0_PMAO_SYNC | MMCR0_PMAO
2828 cmpwi r4, MMCR0_PMAO
2829 beql kvmppc_fix_pmao
2830 END_FTR_SECTION_IFSET(CPU_FTR_PMAO_BUG)
2831 lwz r3, HSTATE_PMC1(r13)
2832 lwz r4, HSTATE_PMC2(r13)
2833 lwz r5, HSTATE_PMC3(r13)
2834 lwz r6, HSTATE_PMC4(r13)
2835 lwz r8, HSTATE_PMC5(r13)
2836 lwz r9, HSTATE_PMC6(r13)
2843 ld r3, HSTATE_MMCR0(r13)
2844 ld r4, HSTATE_MMCR1(r13)
2845 ld r5, HSTATE_MMCRA(r13)
2846 ld r6, HSTATE_SIAR(r13)
2847 ld r7, HSTATE_SDAR(r13)
2848 mtspr SPRN_MMCR1, r4
2849 mtspr SPRN_MMCRA, r5
2853 ld r8, HSTATE_MMCR2(r13)
2854 ld r9, HSTATE_SIER(r13)
2855 mtspr SPRN_MMCR2, r8
2857 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2858 mtspr SPRN_MMCR0, r3
2864 * void kvmhv_save_guest_pmu(struct kvm_vcpu *vcpu, bool pmu_in_use)
2866 * Save guest PMU state into the vcpu struct.
2867 * r3 = vcpu, r4 = full save flag (PMU in use flag set in VPA)
2869 kvmhv_save_guest_pmu:
2874 * POWER8 seems to have a hardware bug where setting
2875 * MMCR0[PMAE] along with MMCR0[PMC1CE] and/or MMCR0[PMCjCE]
2876 * when some counters are already negative doesn't seem
2877 * to cause a performance monitor alert (and hence interrupt).
2878 * The effect of this is that when saving the PMU state,
2879 * if there is no PMU alert pending when we read MMCR0
2880 * before freezing the counters, but one becomes pending
2881 * before we read the counters, we lose it.
2882 * To work around this, we need a way to freeze the counters
2883 * before reading MMCR0. Normally, freezing the counters
2884 * is done by writing MMCR0 (to set MMCR0[FC]) which
2885 * unavoidably writes MMCR0[PMA0] as well. On POWER8,
2886 * we can also freeze the counters using MMCR2, by writing
2887 * 1s to all the counter freeze condition bits (there are
2888 * 9 bits each for 6 counters).
2890 li r3, -1 /* set all freeze bits */
2892 mfspr r10, SPRN_MMCR2
2893 mtspr SPRN_MMCR2, r3
2895 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2897 sldi r3, r3, 31 /* MMCR0_FC (freeze counters) bit */
2898 mfspr r4, SPRN_MMCR0 /* save MMCR0 */
2899 mtspr SPRN_MMCR0, r3 /* freeze all counters, disable ints */
2900 mfspr r6, SPRN_MMCRA
2901 /* Clear MMCRA in order to disable SDAR updates */
2903 mtspr SPRN_MMCRA, r7
2905 cmpwi r8, 0 /* did they ask for PMU stuff to be saved? */
2907 std r3, VCPU_MMCR(r9) /* if not, set saved MMCR0 to FC */
2909 21: mfspr r5, SPRN_MMCR1
2912 std r4, VCPU_MMCR(r9)
2913 std r5, VCPU_MMCR + 8(r9)
2914 std r6, VCPU_MMCRA(r9)
2916 std r10, VCPU_MMCR + 16(r9)
2917 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2918 std r7, VCPU_SIAR(r9)
2919 std r8, VCPU_SDAR(r9)
2926 stw r3, VCPU_PMC(r9)
2927 stw r4, VCPU_PMC + 4(r9)
2928 stw r5, VCPU_PMC + 8(r9)
2929 stw r6, VCPU_PMC + 12(r9)
2930 stw r7, VCPU_PMC + 16(r9)
2931 stw r8, VCPU_PMC + 20(r9)
2934 std r5, VCPU_SIER(r9)
2935 mfspr r6, SPRN_SPMC1
2936 mfspr r7, SPRN_SPMC2
2937 mfspr r8, SPRN_MMCRS
2938 stw r6, VCPU_PMC + 24(r9)
2939 stw r7, VCPU_PMC + 28(r9)
2940 std r8, VCPU_MMCRS(r9)
2942 mtspr SPRN_MMCRS, r4
2943 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
2947 * This works around a hardware bug on POWER8E processors, where
2948 * writing a 1 to the MMCR0[PMAO] bit doesn't generate a
2949 * performance monitor interrupt. Instead, when we need to have
2950 * an interrupt pending, we have to arrange for a counter to overflow.
2954 mtspr SPRN_MMCR2, r3
2955 lis r3, (MMCR0_PMXE | MMCR0_FCECE)@h
2956 ori r3, r3, MMCR0_PMCjCE | MMCR0_C56RUN
2957 mtspr SPRN_MMCR0, r3
2964 #ifdef CONFIG_KVM_BOOK3S_HV_P8_TIMING
2966 * Start timing an activity
2967 * r3 = pointer to time accumulation struct, r4 = vcpu
2970 ld r5, HSTATE_KVM_VCORE(r13)
2971 ld r6, VCORE_TB_OFFSET_APPL(r5)
2973 subf r5, r6, r5 /* subtract current timebase offset */
2974 std r3, VCPU_CUR_ACTIVITY(r4)
2975 std r5, VCPU_ACTIVITY_START(r4)
2979 * Accumulate time to one activity and start another.
2980 * r3 = pointer to new time accumulation struct, r4 = vcpu
2982 kvmhv_accumulate_time:
2983 ld r5, HSTATE_KVM_VCORE(r13)
2984 ld r8, VCORE_TB_OFFSET_APPL(r5)
2985 ld r5, VCPU_CUR_ACTIVITY(r4)
2986 ld r6, VCPU_ACTIVITY_START(r4)
2987 std r3, VCPU_CUR_ACTIVITY(r4)
2989 subf r7, r8, r7 /* subtract current timebase offset */
2990 std r7, VCPU_ACTIVITY_START(r4)
2994 ld r8, TAS_SEQCOUNT(r5)
2997 std r8, TAS_SEQCOUNT(r5)
2999 ld r7, TAS_TOTAL(r5)
3001 std r7, TAS_TOTAL(r5)
3007 3: std r3, TAS_MIN(r5)
3013 std r8, TAS_SEQCOUNT(r5)