1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright 2011 Paul Mackerras, IBM Corp. <paulus@au1.ibm.com>
7 #include <linux/kvm_host.h>
8 #include <linux/preempt.h>
9 #include <linux/export.h>
10 #include <linux/sched.h>
11 #include <linux/spinlock.h>
12 #include <linux/init.h>
13 #include <linux/memblock.h>
14 #include <linux/sizes.h>
15 #include <linux/cma.h>
16 #include <linux/bitops.h>
18 #include <asm/asm-prototypes.h>
19 #include <asm/cputable.h>
20 #include <asm/interrupt.h>
21 #include <asm/kvm_ppc.h>
22 #include <asm/kvm_book3s.h>
23 #include <asm/machdep.h>
26 #include <asm/dbell.h>
27 #include <asm/cputhreads.h>
32 #define KVM_CMA_CHUNK_ORDER 18
34 #include "book3s_xics.h"
35 #include "book3s_xive.h"
38 * Hash page table alignment on newer cpus(CPU_FTR_ARCH_206)
39 * should be power of 2.
41 #define HPT_ALIGN_PAGES ((1 << 18) >> PAGE_SHIFT) /* 256k */
43 * By default we reserve 5% of memory for hash pagetable allocation.
45 static unsigned long kvm_cma_resv_ratio = 5;
47 static struct cma *kvm_cma;
49 static int __init early_parse_kvm_cma_resv(char *p)
51 pr_debug("%s(%s)\n", __func__, p);
54 return kstrtoul(p, 0, &kvm_cma_resv_ratio);
56 early_param("kvm_cma_resv_ratio", early_parse_kvm_cma_resv);
58 struct page *kvm_alloc_hpt_cma(unsigned long nr_pages)
60 VM_BUG_ON(order_base_2(nr_pages) < KVM_CMA_CHUNK_ORDER - PAGE_SHIFT);
62 return cma_alloc(kvm_cma, nr_pages, order_base_2(HPT_ALIGN_PAGES),
65 EXPORT_SYMBOL_GPL(kvm_alloc_hpt_cma);
67 void kvm_free_hpt_cma(struct page *page, unsigned long nr_pages)
69 cma_release(kvm_cma, page, nr_pages);
71 EXPORT_SYMBOL_GPL(kvm_free_hpt_cma);
74 * kvm_cma_reserve() - reserve area for kvm hash pagetable
76 * This function reserves memory from early allocator. It should be
77 * called by arch specific code once the memblock allocator
78 * has been activated and all other subsystems have already allocated/reserved
81 void __init kvm_cma_reserve(void)
83 unsigned long align_size;
84 phys_addr_t selected_size;
87 * We need CMA reservation only when we are in HV mode
89 if (!cpu_has_feature(CPU_FTR_HVMODE))
92 selected_size = PAGE_ALIGN(memblock_phys_mem_size() * kvm_cma_resv_ratio / 100);
94 pr_info("%s: reserving %ld MiB for global area\n", __func__,
95 (unsigned long)selected_size / SZ_1M);
96 align_size = HPT_ALIGN_PAGES << PAGE_SHIFT;
97 cma_declare_contiguous(0, selected_size, 0, align_size,
98 KVM_CMA_CHUNK_ORDER - PAGE_SHIFT, false, "kvm_cma",
104 * Real-mode H_CONFER implementation.
105 * We check if we are the only vcpu out of this virtual core
106 * still running in the guest and not ceded. If so, we pop up
107 * to the virtual-mode implementation; if not, just return to
110 long int kvmppc_rm_h_confer(struct kvm_vcpu *vcpu, int target,
111 unsigned int yield_count)
113 struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore;
114 int ptid = local_paca->kvm_hstate.ptid;
117 int threads_conferring;
118 u64 stop = get_tb() + 10 * tb_ticks_per_usec;
119 int rv = H_SUCCESS; /* => don't yield */
121 set_bit(ptid, &vc->conferring_threads);
122 while ((get_tb() < stop) && !VCORE_IS_EXITING(vc)) {
123 threads_running = VCORE_ENTRY_MAP(vc);
124 threads_ceded = vc->napping_threads;
125 threads_conferring = vc->conferring_threads;
126 if ((threads_ceded | threads_conferring) == threads_running) {
127 rv = H_TOO_HARD; /* => do yield */
131 clear_bit(ptid, &vc->conferring_threads);
136 * When running HV mode KVM we need to block certain operations while KVM VMs
137 * exist in the system. We use a counter of VMs to track this.
139 * One of the operations we need to block is onlining of secondaries, so we
140 * protect hv_vm_count with cpus_read_lock/unlock().
142 static atomic_t hv_vm_count;
144 void kvm_hv_vm_activated(void)
147 atomic_inc(&hv_vm_count);
150 EXPORT_SYMBOL_GPL(kvm_hv_vm_activated);
152 void kvm_hv_vm_deactivated(void)
155 atomic_dec(&hv_vm_count);
158 EXPORT_SYMBOL_GPL(kvm_hv_vm_deactivated);
160 bool kvm_hv_mode_active(void)
162 return atomic_read(&hv_vm_count) != 0;
165 extern int hcall_real_table[], hcall_real_table_end[];
167 int kvmppc_hcall_impl_hv_realmode(unsigned long cmd)
170 if (cmd < hcall_real_table_end - hcall_real_table &&
171 hcall_real_table[cmd])
176 EXPORT_SYMBOL_GPL(kvmppc_hcall_impl_hv_realmode);
178 int kvmppc_hwrng_present(void)
180 return ppc_md.get_random_seed != NULL;
182 EXPORT_SYMBOL_GPL(kvmppc_hwrng_present);
184 long kvmppc_rm_h_random(struct kvm_vcpu *vcpu)
186 if (ppc_md.get_random_seed &&
187 ppc_md.get_random_seed(&vcpu->arch.regs.gpr[4]))
194 * Send an interrupt or message to another CPU.
195 * The caller needs to include any barrier needed to order writes
196 * to memory vs. the IPI/message.
198 void kvmhv_rm_send_ipi(int cpu)
200 void __iomem *xics_phys;
201 unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER);
203 /* On POWER9 we can use msgsnd for any destination cpu. */
204 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
205 msg |= get_hard_smp_processor_id(cpu);
206 __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg));
210 /* On POWER8 for IPIs to threads in the same core, use msgsnd. */
211 if (cpu_has_feature(CPU_FTR_ARCH_207S) &&
212 cpu_first_thread_sibling(cpu) ==
213 cpu_first_thread_sibling(raw_smp_processor_id())) {
214 msg |= cpu_thread_in_core(cpu);
215 __asm__ __volatile__ (PPC_MSGSND(%0) : : "r" (msg));
219 /* We should never reach this */
220 if (WARN_ON_ONCE(xics_on_xive()))
223 /* Else poke the target with an IPI */
224 xics_phys = paca_ptrs[cpu]->kvm_hstate.xics_phys;
226 __raw_rm_writeb(IPI_PRIORITY, xics_phys + XICS_MFRR);
228 opal_int_set_mfrr(get_hard_smp_processor_id(cpu), IPI_PRIORITY);
232 * The following functions are called from the assembly code
233 * in book3s_hv_rmhandlers.S.
235 static void kvmhv_interrupt_vcore(struct kvmppc_vcore *vc, int active)
239 /* Order setting of exit map vs. msgsnd/IPI */
241 for (; active; active >>= 1, ++cpu)
243 kvmhv_rm_send_ipi(cpu);
246 void kvmhv_commence_exit(int trap)
248 struct kvmppc_vcore *vc = local_paca->kvm_hstate.kvm_vcore;
249 int ptid = local_paca->kvm_hstate.ptid;
250 struct kvm_split_mode *sip = local_paca->kvm_hstate.kvm_split_mode;
253 /* Set our bit in the threads-exiting-guest map in the 0xff00
254 bits of vcore->entry_exit_map */
257 ee = vc->entry_exit_map;
258 } while (cmpxchg(&vc->entry_exit_map, ee, ee | me) != ee);
260 /* Are we the first here? */
265 * Trigger the other threads in this vcore to exit the guest.
266 * If this is a hypervisor decrementer interrupt then they
267 * will be already on their way out of the guest.
269 if (trap != BOOK3S_INTERRUPT_HV_DECREMENTER)
270 kvmhv_interrupt_vcore(vc, ee & ~(1 << ptid));
273 * If we are doing dynamic micro-threading, interrupt the other
274 * subcores to pull them out of their guests too.
279 for (i = 0; i < MAX_SUBCORES; ++i) {
284 ee = vc->entry_exit_map;
285 /* Already asked to exit? */
288 } while (cmpxchg(&vc->entry_exit_map, ee,
289 ee | VCORE_EXIT_REQ) != ee);
291 kvmhv_interrupt_vcore(vc, ee);
295 struct kvmppc_host_rm_ops *kvmppc_host_rm_ops_hv;
296 EXPORT_SYMBOL_GPL(kvmppc_host_rm_ops_hv);
298 #ifdef CONFIG_KVM_XICS
299 static struct kvmppc_irq_map *get_irqmap(struct kvmppc_passthru_irqmap *pimap,
305 * We access the mapped array here without a lock. That
306 * is safe because we never reduce the number of entries
307 * in the array and we never change the v_hwirq field of
308 * an entry once it is set.
310 * We have also carefully ordered the stores in the writer
311 * and the loads here in the reader, so that if we find a matching
312 * hwirq here, the associated GSI and irq_desc fields are valid.
314 for (i = 0; i < pimap->n_mapped; i++) {
315 if (xisr == pimap->mapped[i].r_hwirq) {
317 * Order subsequent reads in the caller to serialize
321 return &pimap->mapped[i];
328 * If we have an interrupt that's not an IPI, check if we have a
329 * passthrough adapter and if so, check if this external interrupt
330 * is for the adapter.
331 * We will attempt to deliver the IRQ directly to the target VCPU's
332 * ICP, the virtual ICP (based on affinity - the xive value in ICS).
334 * If the delivery fails or if this is not for a passthrough adapter,
335 * return to the host to handle this interrupt. We earlier
336 * saved a copy of the XIRR in the PACA, it will be picked up by
337 * the host ICP driver.
339 static int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again)
341 struct kvmppc_passthru_irqmap *pimap;
342 struct kvmppc_irq_map *irq_map;
343 struct kvm_vcpu *vcpu;
345 vcpu = local_paca->kvm_hstate.kvm_vcpu;
348 pimap = kvmppc_get_passthru_irqmap(vcpu->kvm);
351 irq_map = get_irqmap(pimap, xisr);
355 /* We're handling this interrupt, generic code doesn't need to */
356 local_paca->kvm_hstate.saved_xirr = 0;
358 return kvmppc_deliver_irq_passthru(vcpu, xirr, irq_map, pimap, again);
362 static inline int kvmppc_check_passthru(u32 xisr, __be32 xirr, bool *again)
369 * Determine what sort of external interrupt is pending (if any).
371 * 0 if no interrupt is pending
372 * 1 if an interrupt is pending that needs to be handled by the host
373 * 2 Passthrough that needs completion in the host
374 * -1 if there was a guest wakeup IPI (which has now been cleared)
375 * -2 if there is PCI passthrough external interrupt that was handled
377 static long kvmppc_read_one_intr(bool *again);
379 long kvmppc_read_intr(void)
390 rc = kvmppc_read_one_intr(&again);
391 if (rc && (ret == 0 || rc > ret))
397 static long kvmppc_read_one_intr(bool *again)
399 void __iomem *xics_phys;
409 /* see if a host IPI is pending */
410 host_ipi = local_paca->kvm_hstate.host_ipi;
414 /* Now read the interrupt from the ICP */
415 xics_phys = local_paca->kvm_hstate.xics_phys;
418 rc = opal_int_get_xirr(&xirr, false);
420 xirr = __raw_rm_readl(xics_phys + XICS_XIRR);
425 * Save XIRR for later. Since we get control in reverse endian
426 * on LE systems, save it byte reversed and fetch it back in
427 * host endian. Note that xirr is the value read from the
428 * XIRR register, while h_xirr is the host endian version.
430 h_xirr = be32_to_cpu(xirr);
431 local_paca->kvm_hstate.saved_xirr = h_xirr;
432 xisr = h_xirr & 0xffffff;
434 * Ensure that the store/load complete to guarantee all side
435 * effects of loading from XIRR has completed
439 /* if nothing pending in the ICP */
443 /* We found something in the ICP...
445 * If it is an IPI, clear the MFRR and EOI it.
447 if (xisr == XICS_IPI) {
450 __raw_rm_writeb(0xff, xics_phys + XICS_MFRR);
451 __raw_rm_writel(xirr, xics_phys + XICS_XIRR);
453 opal_int_set_mfrr(hard_smp_processor_id(), 0xff);
454 rc = opal_int_eoi(h_xirr);
456 /* If rc > 0, there is another interrupt pending */
460 * Need to ensure side effects of above stores
461 * complete before proceeding.
466 * We need to re-check host IPI now in case it got set in the
467 * meantime. If it's clear, we bounce the interrupt to the
470 host_ipi = local_paca->kvm_hstate.host_ipi;
471 if (unlikely(host_ipi != 0)) {
472 /* We raced with the host,
473 * we need to resend that IPI, bummer
476 __raw_rm_writeb(IPI_PRIORITY,
477 xics_phys + XICS_MFRR);
479 opal_int_set_mfrr(hard_smp_processor_id(),
481 /* Let side effects complete */
486 /* OK, it's an IPI for us */
487 local_paca->kvm_hstate.saved_xirr = 0;
491 return kvmppc_check_passthru(xisr, xirr, again);
494 #ifdef CONFIG_KVM_XICS
495 unsigned long kvmppc_rm_h_xirr(struct kvm_vcpu *vcpu)
497 if (!kvmppc_xics_enabled(vcpu))
500 return xive_rm_h_xirr(vcpu);
502 return xics_rm_h_xirr(vcpu);
505 unsigned long kvmppc_rm_h_xirr_x(struct kvm_vcpu *vcpu)
507 if (!kvmppc_xics_enabled(vcpu))
509 vcpu->arch.regs.gpr[5] = get_tb();
511 return xive_rm_h_xirr(vcpu);
513 return xics_rm_h_xirr(vcpu);
516 unsigned long kvmppc_rm_h_ipoll(struct kvm_vcpu *vcpu, unsigned long server)
518 if (!kvmppc_xics_enabled(vcpu))
521 return xive_rm_h_ipoll(vcpu, server);
526 int kvmppc_rm_h_ipi(struct kvm_vcpu *vcpu, unsigned long server,
529 if (!kvmppc_xics_enabled(vcpu))
532 return xive_rm_h_ipi(vcpu, server, mfrr);
534 return xics_rm_h_ipi(vcpu, server, mfrr);
537 int kvmppc_rm_h_cppr(struct kvm_vcpu *vcpu, unsigned long cppr)
539 if (!kvmppc_xics_enabled(vcpu))
542 return xive_rm_h_cppr(vcpu, cppr);
544 return xics_rm_h_cppr(vcpu, cppr);
547 int kvmppc_rm_h_eoi(struct kvm_vcpu *vcpu, unsigned long xirr)
549 if (!kvmppc_xics_enabled(vcpu))
552 return xive_rm_h_eoi(vcpu, xirr);
554 return xics_rm_h_eoi(vcpu, xirr);
556 #endif /* CONFIG_KVM_XICS */
558 void kvmppc_bad_interrupt(struct pt_regs *regs)
561 * 100 could happen at any time, 200 can happen due to invalid real
562 * address access for example (or any time due to a hardware problem).
564 if (TRAP(regs) == 0x100) {
565 get_paca()->in_nmi++;
566 system_reset_exception(regs);
567 get_paca()->in_nmi--;
568 } else if (TRAP(regs) == 0x200) {
569 machine_check_exception(regs);
571 die("Bad interrupt in KVM entry/exit code", regs, SIGABRT);
573 panic("Bad KVM trap");
576 static void kvmppc_end_cede(struct kvm_vcpu *vcpu)
578 vcpu->arch.ceded = 0;
579 if (vcpu->arch.timer_running) {
580 hrtimer_try_to_cancel(&vcpu->arch.dec_timer);
581 vcpu->arch.timer_running = 0;
585 void kvmppc_set_msr_hv(struct kvm_vcpu *vcpu, u64 msr)
587 /* Guest must always run with ME enabled, HV disabled. */
588 msr = (msr | MSR_ME) & ~MSR_HV;
591 * Check for illegal transactional state bit combination
592 * and if we find it, force the TS field to a safe state.
594 if ((msr & MSR_TS_MASK) == MSR_TS_MASK)
596 vcpu->arch.shregs.msr = msr;
597 kvmppc_end_cede(vcpu);
599 EXPORT_SYMBOL_GPL(kvmppc_set_msr_hv);
601 static void inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags)
603 unsigned long msr, pc, new_msr, new_pc;
605 msr = kvmppc_get_msr(vcpu);
606 pc = kvmppc_get_pc(vcpu);
607 new_msr = vcpu->arch.intr_msr;
610 /* If transactional, change to suspend mode on IRQ delivery */
611 if (MSR_TM_TRANSACTIONAL(msr))
614 new_msr |= msr & MSR_TS_MASK;
617 * Perform MSR and PC adjustment for LPCR[AIL]=3 if it is set and
618 * applicable. AIL=2 is not supported.
620 * AIL does not apply to SRESET, MCE, or HMI (which is never
621 * delivered to the guest), and does not apply if IR=0 or DR=0.
623 if (vec != BOOK3S_INTERRUPT_SYSTEM_RESET &&
624 vec != BOOK3S_INTERRUPT_MACHINE_CHECK &&
625 (vcpu->arch.vcore->lpcr & LPCR_AIL) == LPCR_AIL_3 &&
626 (msr & (MSR_IR|MSR_DR)) == (MSR_IR|MSR_DR) ) {
627 new_msr |= MSR_IR | MSR_DR;
628 new_pc += 0xC000000000004000ULL;
631 kvmppc_set_srr0(vcpu, pc);
632 kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags);
633 kvmppc_set_pc(vcpu, new_pc);
634 vcpu->arch.shregs.msr = new_msr;
637 void kvmppc_inject_interrupt_hv(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags)
639 inject_interrupt(vcpu, vec, srr1_flags);
640 kvmppc_end_cede(vcpu);
642 EXPORT_SYMBOL_GPL(kvmppc_inject_interrupt_hv);
645 * Is there a PRIV_DOORBELL pending for the guest (on POWER9)?
646 * Can we inject a Decrementer or a External interrupt?
648 void kvmppc_guest_entry_inject_int(struct kvm_vcpu *vcpu)
653 /* Insert EXTERNAL bit into LPCR at the MER bit position */
654 ext = (vcpu->arch.pending_exceptions >> BOOK3S_IRQPRIO_EXTERNAL) & 1;
655 lpcr = mfspr(SPRN_LPCR);
656 lpcr |= ext << LPCR_MER_SH;
657 mtspr(SPRN_LPCR, lpcr);
660 if (vcpu->arch.shregs.msr & MSR_EE) {
662 inject_interrupt(vcpu, BOOK3S_INTERRUPT_EXTERNAL, 0);
664 long int dec = mfspr(SPRN_DEC);
665 if (!(lpcr & LPCR_LD))
668 inject_interrupt(vcpu,
669 BOOK3S_INTERRUPT_DECREMENTER, 0);
673 if (vcpu->arch.doorbell_request) {
674 mtspr(SPRN_DPDES, 1);
675 vcpu->arch.vcore->dpdes = 1;
677 vcpu->arch.doorbell_request = 0;
681 static void flush_guest_tlb(struct kvm *kvm)
683 unsigned long rb, set;
685 rb = PPC_BIT(52); /* IS = 2 */
686 if (kvm_is_radix(kvm)) {
687 /* R=1 PRS=1 RIC=2 */
688 asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
689 : : "r" (rb), "i" (1), "i" (1), "i" (2),
691 for (set = 1; set < kvm->arch.tlb_sets; ++set) {
692 rb += PPC_BIT(51); /* increment set number */
693 /* R=1 PRS=1 RIC=0 */
694 asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
695 : : "r" (rb), "i" (1), "i" (1), "i" (0),
698 asm volatile("ptesync": : :"memory");
699 // POWER9 congruence-class TLBIEL leaves ERAT. Flush it now.
700 asm volatile(PPC_RADIX_INVALIDATE_ERAT_GUEST : : :"memory");
702 for (set = 0; set < kvm->arch.tlb_sets; ++set) {
703 /* R=0 PRS=0 RIC=0 */
704 asm volatile(PPC_TLBIEL(%0, %4, %3, %2, %1)
705 : : "r" (rb), "i" (0), "i" (0), "i" (0),
707 rb += PPC_BIT(51); /* increment set number */
709 asm volatile("ptesync": : :"memory");
710 // POWER9 congruence-class TLBIEL leaves ERAT. Flush it now.
711 if (cpu_has_feature(CPU_FTR_ARCH_300))
712 asm volatile(PPC_ISA_3_0_INVALIDATE_ERAT : : :"memory");
716 void kvmppc_check_need_tlb_flush(struct kvm *kvm, int pcpu,
717 struct kvm_nested_guest *nested)
719 cpumask_t *need_tlb_flush;
722 * On POWER9, individual threads can come in here, but the
723 * TLB is shared between the 4 threads in a core, hence
724 * invalidating on one thread invalidates for all.
725 * Thus we make all 4 threads use the same bit.
727 if (cpu_has_feature(CPU_FTR_ARCH_300))
728 pcpu = cpu_first_tlb_thread_sibling(pcpu);
731 need_tlb_flush = &nested->need_tlb_flush;
733 need_tlb_flush = &kvm->arch.need_tlb_flush;
735 if (cpumask_test_cpu(pcpu, need_tlb_flush)) {
736 flush_guest_tlb(kvm);
738 /* Clear the bit after the TLB flush */
739 cpumask_clear_cpu(pcpu, need_tlb_flush);
742 EXPORT_SYMBOL_GPL(kvmppc_check_need_tlb_flush);