1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <asm/processor.h>
3 #include <asm/ppc_asm.h>
5 #include <asm/asm-offsets.h>
6 #include <asm/cputable.h>
7 #include <asm/thread_info.h>
9 #include <asm/ptrace.h>
10 #include <asm/export.h>
11 #include <asm/asm-compat.h>
14 * Load state from memory into VMX registers including VSCR.
15 * Assumes the caller has enabled VMX in the MSR.
17 _GLOBAL(load_vr_state)
23 EXPORT_SYMBOL(load_vr_state)
24 _ASM_NOKPROBE_SYMBOL(load_vr_state); /* used by restore_math */
27 * Store VMX state into memory, including VSCR.
28 * Assumes the caller has enabled VMX in the MSR.
30 _GLOBAL(store_vr_state)
37 EXPORT_SYMBOL(store_vr_state)
40 * Disable VMX for the task which had it previously,
41 * and save its vector registers in its thread_struct.
42 * Enables the VMX for use in the kernel on return.
43 * On SMP we know the VMX is free, since we give it up every
44 * switch (ie, no lazy save of the vector registers).
46 * Note that on 32-bit this can only use registers that will be
47 * restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
49 _GLOBAL(load_up_altivec)
50 mfmsr r5 /* grab the current MSR */
52 MTMSRD(r5) /* enable use of AltiVec now */
56 * While userspace in general ignores VRSAVE, glibc uses it as a boolean
57 * to optimise userspace context save/restore. Whenever we take an
58 * altivec unavailable exception we must set VRSAVE to something non
59 * zero. Set it to all 1s. See also the programming note in the ISA.
67 /* enable use of VMX after return */
69 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
71 #ifdef CONFIG_VMAP_STACK
75 ld r4,PACACURRENT(r13)
76 addi r5,r4,THREAD /* Get THREAD */
77 oris r12,r12,MSR_VEC@h
81 stb r4,THREAD_LOAD_VEC(r5)
82 addi r6,r5,THREAD_VRSTATE
85 stw r4,THREAD_USED_VR(r5)
89 /* restore registers and return */
91 _ASM_NOKPROBE_SYMBOL(load_up_altivec)
95 * Save the vector registers to its thread_struct
98 addi r3,r3,THREAD /* want THREAD of task */
99 PPC_LL r7,THREAD_VRSAVEAREA(r3)
100 PPC_LL r5,PT_REGS(r3)
103 addi r7,r3,THREAD_VRSTATE
104 2: SAVE_32VRS(0,r4,r7)
114 #error This asm code isn't ready for 32-bit kernels
118 * load_up_vsx(unused, unused, tsk)
119 * Disable VSX for the task which had it previously,
120 * and save its vector registers in its thread_struct.
121 * Reuse the fp and vsx saves, but first check to see if they have
122 * been saved already.
125 /* Load FP and VSX registers if they haven't been done yet */
127 beql+ load_up_fpu /* skip if already loaded */
128 andis. r5,r12,MSR_VEC@h
129 beql+ load_up_altivec /* skip if already loaded */
131 ld r4,PACACURRENT(r13)
132 addi r4,r4,THREAD /* Get THREAD */
134 stw r6,THREAD_USED_VSR(r4) /* ... also set thread used vsr */
135 /* enable use of VSX after return */
136 oris r12,r12,MSR_VSX@h
138 b fast_interrupt_return
140 #endif /* CONFIG_VSX */
144 * The routines below are in assembler so we can closely control the
145 * usage of floating-point registers. These routines must be called
146 * with preempt disabled.
153 .long 0x3f800000 /* 1.0 in single-precision FP */
155 .long 0x3f000000 /* 0.5 in single-precision FP */
157 #define LDCONST(fr, name) \
166 .tc FD_3ff00000_0[TC],0x3ff0000000000000 /* 1.0 */
168 .tc FD_3fe00000_0[TC],0x3fe0000000000000 /* 0.5 */
170 #define LDCONST(fr, name) \
176 * Internal routine to enable floating point and set FPSCR to 0.
177 * Don't call it from C; it doesn't use the normal calling convention.
209 * Vector add, floating point.
226 * Vector subtract, floating point.
243 * Vector multiply and add, floating point.
255 fmadds fr0,fr0,fr2,fr1
263 * Vector negative multiply and subtract, floating point.
275 fnmsubs fr0,fr0,fr2,fr1
283 * Vector reciprocal estimate. We just compute 1.0/x.
284 * r3 -> destination, r4 -> source.
301 * Vector reciprocal square-root estimate, floating point.
302 * We use the frsqrte instruction for the initial estimate followed
303 * by 2 iterations of Newton-Raphson to get sufficient accuracy.
304 * r3 -> destination, r4 -> source.
319 frsqrte fr1,fr0 /* r = frsqrte(s) */
320 fmuls fr3,fr1,fr0 /* r * s */
321 fmuls fr2,fr1,fr5 /* r * 0.5 */
322 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
323 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */
324 fmuls fr3,fr1,fr0 /* r * s */
325 fmuls fr2,fr1,fr5 /* r * 0.5 */
326 fnmsubs fr3,fr1,fr3,fr4 /* 1 - s * r * r */
327 fmadds fr1,fr2,fr3,fr1 /* r = r + 0.5 * r * (1 - s * r * r) */