2 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
3 * Copyright 2007-2010 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
10 * Modified by Cort Dougan (cort@cs.nmt.edu)
11 * and Paul Mackerras (paulus@samba.org)
15 * This file handles the architecture-dependent parts of hardware exceptions
18 #include <linux/errno.h>
19 #include <linux/sched.h>
20 #include <linux/sched/debug.h>
21 #include <linux/kernel.h>
23 #include <linux/stddef.h>
24 #include <linux/unistd.h>
25 #include <linux/ptrace.h>
26 #include <linux/user.h>
27 #include <linux/interrupt.h>
28 #include <linux/init.h>
29 #include <linux/extable.h>
30 #include <linux/module.h> /* print_modules */
31 #include <linux/prctl.h>
32 #include <linux/delay.h>
33 #include <linux/kprobes.h>
34 #include <linux/kexec.h>
35 #include <linux/backlight.h>
36 #include <linux/bug.h>
37 #include <linux/kdebug.h>
38 #include <linux/ratelimit.h>
39 #include <linux/context_tracking.h>
41 #include <asm/emulated_ops.h>
42 #include <asm/pgtable.h>
43 #include <linux/uaccess.h>
44 #include <asm/debugfs.h>
46 #include <asm/machdep.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/backlight.h>
54 #include <asm/firmware.h>
55 #include <asm/processor.h>
58 #include <asm/kexec.h>
59 #include <asm/ppc-opcode.h>
61 #include <asm/fadump.h>
62 #include <asm/switch_to.h>
64 #include <asm/debug.h>
65 #include <asm/asm-prototypes.h>
67 #include <sysdev/fsl_pci.h>
68 #include <asm/kprobes.h>
70 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
71 int (*__debugger)(struct pt_regs *regs) __read_mostly;
72 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
73 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
74 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
75 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
76 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
77 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
79 EXPORT_SYMBOL(__debugger);
80 EXPORT_SYMBOL(__debugger_ipi);
81 EXPORT_SYMBOL(__debugger_bpt);
82 EXPORT_SYMBOL(__debugger_sstep);
83 EXPORT_SYMBOL(__debugger_iabr_match);
84 EXPORT_SYMBOL(__debugger_break_match);
85 EXPORT_SYMBOL(__debugger_fault_handler);
88 /* Transactional Memory trap debug */
90 #define TM_DEBUG(x...) printk(KERN_INFO x)
92 #define TM_DEBUG(x...) do { } while(0)
96 * Trap & Exception support
99 #ifdef CONFIG_PMAC_BACKLIGHT
100 static void pmac_backlight_unblank(void)
102 mutex_lock(&pmac_backlight_mutex);
103 if (pmac_backlight) {
104 struct backlight_properties *props;
106 props = &pmac_backlight->props;
107 props->brightness = props->max_brightness;
108 props->power = FB_BLANK_UNBLANK;
109 backlight_update_status(pmac_backlight);
111 mutex_unlock(&pmac_backlight_mutex);
114 static inline void pmac_backlight_unblank(void) { }
118 * If oops/die is expected to crash the machine, return true here.
120 * This should not be expected to be 100% accurate, there may be
121 * notifiers registered or other unexpected conditions that may bring
122 * down the kernel. Or if the current process in the kernel is holding
123 * locks or has other critical state, the kernel may become effectively
126 bool die_will_crash(void)
128 if (should_fadump_crash())
130 if (kexec_should_crash(current))
132 if (in_interrupt() || panic_on_oops ||
133 !current->pid || is_global_init(current))
139 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
140 static int die_owner = -1;
141 static unsigned int die_nest_count;
142 static int die_counter;
144 static unsigned long oops_begin(struct pt_regs *regs)
151 /* racy, but better than risking deadlock. */
152 raw_local_irq_save(flags);
153 cpu = smp_processor_id();
154 if (!arch_spin_trylock(&die_lock)) {
155 if (cpu == die_owner)
156 /* nested oops. should stop eventually */;
158 arch_spin_lock(&die_lock);
164 if (machine_is(powermac))
165 pmac_backlight_unblank();
168 NOKPROBE_SYMBOL(oops_begin);
170 static void oops_end(unsigned long flags, struct pt_regs *regs,
174 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
178 if (!die_nest_count) {
179 /* Nest count reaches zero, release the lock. */
181 arch_spin_unlock(&die_lock);
183 raw_local_irq_restore(flags);
186 * system_reset_excption handles debugger, crash dump, panic, for 0x100
188 if (TRAP(regs) == 0x100)
191 crash_fadump(regs, "die oops");
193 if (kexec_should_crash(current))
200 * While our oops output is serialised by a spinlock, output
201 * from panic() called below can race and corrupt it. If we
202 * know we are going to panic, delay for 1 second so we have a
203 * chance to get clean backtraces from all CPUs that are oopsing.
205 if (in_interrupt() || panic_on_oops || !current->pid ||
206 is_global_init(current)) {
207 mdelay(MSEC_PER_SEC);
211 panic("Fatal exception in interrupt");
213 panic("Fatal exception");
216 NOKPROBE_SYMBOL(oops_end);
218 static int __die(const char *str, struct pt_regs *regs, long err)
220 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
222 if (IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN))
227 if (IS_ENABLED(CONFIG_PREEMPT))
230 if (IS_ENABLED(CONFIG_SMP))
231 pr_cont("SMP NR_CPUS=%d ", NR_CPUS);
233 if (debug_pagealloc_enabled())
234 pr_cont("DEBUG_PAGEALLOC ");
236 if (IS_ENABLED(CONFIG_NUMA))
239 pr_cont("%s\n", ppc_md.name ? ppc_md.name : "");
241 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
249 NOKPROBE_SYMBOL(__die);
251 void die(const char *str, struct pt_regs *regs, long err)
256 * system_reset_excption handles debugger, crash dump, panic, for 0x100
258 if (TRAP(regs) != 0x100) {
263 flags = oops_begin(regs);
264 if (__die(str, regs, err))
266 oops_end(flags, regs, err);
268 NOKPROBE_SYMBOL(die);
270 void user_single_step_siginfo(struct task_struct *tsk,
271 struct pt_regs *regs, siginfo_t *info)
273 memset(info, 0, sizeof(*info));
274 info->si_signo = SIGTRAP;
275 info->si_code = TRAP_TRACE;
276 info->si_addr = (void __user *)regs->nip;
279 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
282 const char fmt32[] = KERN_INFO "%s[%d]: unhandled signal %d " \
283 "at %08lx nip %08lx lr %08lx code %x\n";
284 const char fmt64[] = KERN_INFO "%s[%d]: unhandled signal %d " \
285 "at %016lx nip %016lx lr %016lx code %x\n";
287 if (!user_mode(regs)) {
288 die("Exception in kernel mode", regs, signr);
292 if (show_unhandled_signals && unhandled_signal(current, signr)) {
293 printk_ratelimited(regs->msr & MSR_64BIT ? fmt64 : fmt32,
294 current->comm, current->pid, signr,
295 addr, regs->nip, regs->link, code);
298 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
301 current->thread.trap_nr = code;
302 memset(&info, 0, sizeof(info));
303 info.si_signo = signr;
305 info.si_addr = (void __user *) addr;
306 force_sig_info(signr, &info, current);
309 void system_reset_exception(struct pt_regs *regs)
312 * Avoid crashes in case of nested NMI exceptions. Recoverability
313 * is determined by RI and in_nmi
315 bool nested = in_nmi();
319 __this_cpu_inc(irq_stat.sreset_irqs);
321 /* See if any machine dependent calls */
322 if (ppc_md.system_reset_exception) {
323 if (ppc_md.system_reset_exception(regs))
331 * A system reset is a request to dump, so we always send
332 * it through the crashdump code (if fadump or kdump are
335 crash_fadump(regs, "System Reset");
340 * We aren't the primary crash CPU. We need to send it
341 * to a holding pattern to avoid it ending up in the panic
344 crash_kexec_secondary(regs);
347 * No debugger or crash dump registered, print logs then
350 die("System Reset", regs, SIGABRT);
352 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */
353 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
354 nmi_panic(regs, "System Reset");
357 #ifdef CONFIG_PPC_BOOK3S_64
358 BUG_ON(get_paca()->in_nmi == 0);
359 if (get_paca()->in_nmi > 1)
360 die("Unrecoverable nested System Reset", regs, SIGABRT);
362 /* Must die if the interrupt is not recoverable */
363 if (!(regs->msr & MSR_RI)) {
364 /* For the reason explained in die_mce, nmi_exit before die */
366 die("Unrecoverable System Reset", regs, SIGABRT);
372 /* What should we do here? We could issue a shutdown or hard reset. */
376 * I/O accesses can cause machine checks on powermacs.
377 * Check if the NIP corresponds to the address of a sync
378 * instruction for which there is an entry in the exception
380 * Note that the 601 only takes a machine check on TEA
381 * (transfer error ack) signal assertion, and does not
382 * set any of the top 16 bits of SRR1.
385 static inline int check_io_access(struct pt_regs *regs)
388 unsigned long msr = regs->msr;
389 const struct exception_table_entry *entry;
390 unsigned int *nip = (unsigned int *)regs->nip;
392 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
393 && (entry = search_exception_tables(regs->nip)) != NULL) {
395 * Check that it's a sync instruction, or somewhere
396 * in the twi; isync; nop sequence that inb/inw/inl uses.
397 * As the address is in the exception table
398 * we should be able to read the instr there.
399 * For the debug message, we look at the preceding
402 if (*nip == PPC_INST_NOP)
404 else if (*nip == PPC_INST_ISYNC)
406 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) {
410 rb = (*nip >> 11) & 0x1f;
411 printk(KERN_DEBUG "%s bad port %lx at %p\n",
412 (*nip & 0x100)? "OUT to": "IN from",
413 regs->gpr[rb] - _IO_BASE, nip);
415 regs->nip = extable_fixup(entry);
419 #endif /* CONFIG_PPC32 */
423 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
424 /* On 4xx, the reason for the machine check or program exception
426 #define get_reason(regs) ((regs)->dsisr)
427 #define REASON_FP ESR_FP
428 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
429 #define REASON_PRIVILEGED ESR_PPR
430 #define REASON_TRAP ESR_PTR
432 /* single-step stuff */
433 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
434 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
437 /* On non-4xx, the reason for the machine check or program
438 exception is in the MSR. */
439 #define get_reason(regs) ((regs)->msr)
440 #define REASON_TM SRR1_PROGTM
441 #define REASON_FP SRR1_PROGFPE
442 #define REASON_ILLEGAL SRR1_PROGILL
443 #define REASON_PRIVILEGED SRR1_PROGPRIV
444 #define REASON_TRAP SRR1_PROGTRAP
446 #define single_stepping(regs) ((regs)->msr & MSR_SE)
447 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
450 #if defined(CONFIG_E500)
451 int machine_check_e500mc(struct pt_regs *regs)
453 unsigned long mcsr = mfspr(SPRN_MCSR);
454 unsigned long pvr = mfspr(SPRN_PVR);
455 unsigned long reason = mcsr;
458 if (reason & MCSR_LD) {
459 recoverable = fsl_rio_mcheck_exception(regs);
460 if (recoverable == 1)
464 printk("Machine check in kernel mode.\n");
465 printk("Caused by (from MCSR=%lx): ", reason);
467 if (reason & MCSR_MCP)
468 printk("Machine Check Signal\n");
470 if (reason & MCSR_ICPERR) {
471 printk("Instruction Cache Parity Error\n");
474 * This is recoverable by invalidating the i-cache.
476 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
477 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
481 * This will generally be accompanied by an instruction
482 * fetch error report -- only treat MCSR_IF as fatal
483 * if it wasn't due to an L1 parity error.
488 if (reason & MCSR_DCPERR_MC) {
489 printk("Data Cache Parity Error\n");
492 * In write shadow mode we auto-recover from the error, but it
493 * may still get logged and cause a machine check. We should
494 * only treat the non-write shadow case as non-recoverable.
496 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
497 * is not implemented but L1 data cache always runs in write
498 * shadow mode. Hence on data cache parity errors HW will
499 * automatically invalidate the L1 Data Cache.
501 if (PVR_VER(pvr) != PVR_VER_E6500) {
502 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
507 if (reason & MCSR_L2MMU_MHIT) {
508 printk("Hit on multiple TLB entries\n");
512 if (reason & MCSR_NMI)
513 printk("Non-maskable interrupt\n");
515 if (reason & MCSR_IF) {
516 printk("Instruction Fetch Error Report\n");
520 if (reason & MCSR_LD) {
521 printk("Load Error Report\n");
525 if (reason & MCSR_ST) {
526 printk("Store Error Report\n");
530 if (reason & MCSR_LDG) {
531 printk("Guarded Load Error Report\n");
535 if (reason & MCSR_TLBSYNC)
536 printk("Simultaneous tlbsync operations\n");
538 if (reason & MCSR_BSL2_ERR) {
539 printk("Level 2 Cache Error\n");
543 if (reason & MCSR_MAV) {
546 addr = mfspr(SPRN_MCAR);
547 addr |= (u64)mfspr(SPRN_MCARU) << 32;
549 printk("Machine Check %s Address: %#llx\n",
550 reason & MCSR_MEA ? "Effective" : "Physical", addr);
554 mtspr(SPRN_MCSR, mcsr);
555 return mfspr(SPRN_MCSR) == 0 && recoverable;
558 int machine_check_e500(struct pt_regs *regs)
560 unsigned long reason = mfspr(SPRN_MCSR);
562 if (reason & MCSR_BUS_RBERR) {
563 if (fsl_rio_mcheck_exception(regs))
565 if (fsl_pci_mcheck_exception(regs))
569 printk("Machine check in kernel mode.\n");
570 printk("Caused by (from MCSR=%lx): ", reason);
572 if (reason & MCSR_MCP)
573 printk("Machine Check Signal\n");
574 if (reason & MCSR_ICPERR)
575 printk("Instruction Cache Parity Error\n");
576 if (reason & MCSR_DCP_PERR)
577 printk("Data Cache Push Parity Error\n");
578 if (reason & MCSR_DCPERR)
579 printk("Data Cache Parity Error\n");
580 if (reason & MCSR_BUS_IAERR)
581 printk("Bus - Instruction Address Error\n");
582 if (reason & MCSR_BUS_RAERR)
583 printk("Bus - Read Address Error\n");
584 if (reason & MCSR_BUS_WAERR)
585 printk("Bus - Write Address Error\n");
586 if (reason & MCSR_BUS_IBERR)
587 printk("Bus - Instruction Data Error\n");
588 if (reason & MCSR_BUS_RBERR)
589 printk("Bus - Read Data Bus Error\n");
590 if (reason & MCSR_BUS_WBERR)
591 printk("Bus - Write Data Bus Error\n");
592 if (reason & MCSR_BUS_IPERR)
593 printk("Bus - Instruction Parity Error\n");
594 if (reason & MCSR_BUS_RPERR)
595 printk("Bus - Read Parity Error\n");
600 int machine_check_generic(struct pt_regs *regs)
604 #elif defined(CONFIG_E200)
605 int machine_check_e200(struct pt_regs *regs)
607 unsigned long reason = mfspr(SPRN_MCSR);
609 printk("Machine check in kernel mode.\n");
610 printk("Caused by (from MCSR=%lx): ", reason);
612 if (reason & MCSR_MCP)
613 printk("Machine Check Signal\n");
614 if (reason & MCSR_CP_PERR)
615 printk("Cache Push Parity Error\n");
616 if (reason & MCSR_CPERR)
617 printk("Cache Parity Error\n");
618 if (reason & MCSR_EXCP_ERR)
619 printk("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
620 if (reason & MCSR_BUS_IRERR)
621 printk("Bus - Read Bus Error on instruction fetch\n");
622 if (reason & MCSR_BUS_DRERR)
623 printk("Bus - Read Bus Error on data load\n");
624 if (reason & MCSR_BUS_WRERR)
625 printk("Bus - Write Bus Error on buffered store or cache line push\n");
629 #elif defined(CONFIG_PPC32)
630 int machine_check_generic(struct pt_regs *regs)
632 unsigned long reason = regs->msr;
634 printk("Machine check in kernel mode.\n");
635 printk("Caused by (from SRR1=%lx): ", reason);
636 switch (reason & 0x601F0000) {
638 printk("Machine check signal\n");
640 case 0: /* for 601 */
642 case 0x140000: /* 7450 MSS error and TEA */
643 printk("Transfer error ack signal\n");
646 printk("Data parity error signal\n");
649 printk("Address parity error signal\n");
652 printk("L1 Data Cache error\n");
655 printk("L1 Instruction Cache error\n");
658 printk("L2 data cache parity error\n");
661 printk("Unknown values in msr\n");
665 #endif /* everything else */
667 void machine_check_exception(struct pt_regs *regs)
670 bool nested = in_nmi();
674 /* 64s accounts the mce in machine_check_early when in HVMODE */
675 if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64) || !cpu_has_feature(CPU_FTR_HVMODE))
676 __this_cpu_inc(irq_stat.mce_exceptions);
678 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
680 /* See if any machine dependent calls. In theory, we would want
681 * to call the CPU first, and call the ppc_md. one if the CPU
682 * one returns a positive number. However there is existing code
683 * that assumes the board gets a first chance, so let's keep it
684 * that way for now and fix things later. --BenH.
686 if (ppc_md.machine_check_exception)
687 recover = ppc_md.machine_check_exception(regs);
688 else if (cur_cpu_spec->machine_check)
689 recover = cur_cpu_spec->machine_check(regs);
694 if (debugger_fault_handler(regs))
697 if (check_io_access(regs))
703 die("Machine check", regs, SIGBUS);
705 /* Must die if the interrupt is not recoverable */
706 if (!(regs->msr & MSR_RI))
707 die("Unrecoverable Machine check", regs, SIGBUS);
716 void SMIException(struct pt_regs *regs)
718 die("System Management Interrupt", regs, SIGABRT);
721 void handle_hmi_exception(struct pt_regs *regs)
723 struct pt_regs *old_regs;
725 old_regs = set_irq_regs(regs);
728 if (ppc_md.handle_hmi_exception)
729 ppc_md.handle_hmi_exception(regs);
732 set_irq_regs(old_regs);
735 void unknown_exception(struct pt_regs *regs)
737 enum ctx_state prev_state = exception_enter();
739 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
740 regs->nip, regs->msr, regs->trap);
742 _exception(SIGTRAP, regs, 0, 0);
744 exception_exit(prev_state);
747 void instruction_breakpoint_exception(struct pt_regs *regs)
749 enum ctx_state prev_state = exception_enter();
751 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
752 5, SIGTRAP) == NOTIFY_STOP)
754 if (debugger_iabr_match(regs))
756 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
759 exception_exit(prev_state);
762 void RunModeException(struct pt_regs *regs)
764 _exception(SIGTRAP, regs, 0, 0);
767 void single_step_exception(struct pt_regs *regs)
769 enum ctx_state prev_state = exception_enter();
771 clear_single_step(regs);
773 if (kprobe_post_handler(regs))
776 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
777 5, SIGTRAP) == NOTIFY_STOP)
779 if (debugger_sstep(regs))
782 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
785 exception_exit(prev_state);
787 NOKPROBE_SYMBOL(single_step_exception);
790 * After we have successfully emulated an instruction, we have to
791 * check if the instruction was being single-stepped, and if so,
792 * pretend we got a single-step exception. This was pointed out
793 * by Kumar Gala. -- paulus
795 static void emulate_single_step(struct pt_regs *regs)
797 if (single_stepping(regs))
798 single_step_exception(regs);
801 static inline int __parse_fpscr(unsigned long fpscr)
805 /* Invalid operation */
806 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
810 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
814 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
818 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
822 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
828 static void parse_fpe(struct pt_regs *regs)
832 flush_fp_to_thread(current);
834 code = __parse_fpscr(current->thread.fp_state.fpscr);
836 _exception(SIGFPE, regs, code, regs->nip);
840 * Illegal instruction emulation support. Originally written to
841 * provide the PVR to user applications using the mfspr rd, PVR.
842 * Return non-zero if we can't emulate, or -EFAULT if the associated
843 * memory access caused an access fault. Return zero on success.
845 * There are a couple of ways to do this, either "decode" the instruction
846 * or directly match lots of bits. In this case, matching lots of
847 * bits is faster and easier.
850 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
852 u8 rT = (instword >> 21) & 0x1f;
853 u8 rA = (instword >> 16) & 0x1f;
854 u8 NB_RB = (instword >> 11) & 0x1f;
859 /* Early out if we are an invalid form of lswx */
860 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
861 if ((rT == rA) || (rT == NB_RB))
864 EA = (rA == 0) ? 0 : regs->gpr[rA];
866 switch (instword & PPC_INST_STRING_MASK) {
870 num_bytes = regs->xer & 0x7f;
874 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
880 while (num_bytes != 0)
883 u32 shift = 8 * (3 - (pos & 0x3));
885 /* if process is 32-bit, clear upper 32 bits of EA */
886 if ((regs->msr & MSR_64BIT) == 0)
889 switch ((instword & PPC_INST_STRING_MASK)) {
892 if (get_user(val, (u8 __user *)EA))
894 /* first time updating this reg,
898 regs->gpr[rT] |= val << shift;
902 val = regs->gpr[rT] >> shift;
903 if (put_user(val, (u8 __user *)EA))
907 /* move EA to next address */
911 /* manage our position within the register */
922 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
927 ra = (instword >> 16) & 0x1f;
928 rs = (instword >> 21) & 0x1f;
931 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
932 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
933 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
939 static int emulate_isel(struct pt_regs *regs, u32 instword)
941 u8 rT = (instword >> 21) & 0x1f;
942 u8 rA = (instword >> 16) & 0x1f;
943 u8 rB = (instword >> 11) & 0x1f;
944 u8 BC = (instword >> 6) & 0x1f;
948 tmp = (rA == 0) ? 0 : regs->gpr[rA];
949 bit = (regs->ccr >> (31 - BC)) & 0x1;
951 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
956 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
957 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
959 /* If we're emulating a load/store in an active transaction, we cannot
960 * emulate it as the kernel operates in transaction suspended context.
961 * We need to abort the transaction. This creates a persistent TM
962 * abort so tell the user what caused it with a new code.
964 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
972 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
978 static int emulate_instruction(struct pt_regs *regs)
983 if (!user_mode(regs))
985 CHECK_FULL_REGS(regs);
987 if (get_user(instword, (u32 __user *)(regs->nip)))
990 /* Emulate the mfspr rD, PVR. */
991 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
992 PPC_WARN_EMULATED(mfpvr, regs);
993 rd = (instword >> 21) & 0x1f;
994 regs->gpr[rd] = mfspr(SPRN_PVR);
998 /* Emulating the dcba insn is just a no-op. */
999 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
1000 PPC_WARN_EMULATED(dcba, regs);
1004 /* Emulate the mcrxr insn. */
1005 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
1006 int shift = (instword >> 21) & 0x1c;
1007 unsigned long msk = 0xf0000000UL >> shift;
1009 PPC_WARN_EMULATED(mcrxr, regs);
1010 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
1011 regs->xer &= ~0xf0000000UL;
1015 /* Emulate load/store string insn. */
1016 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1017 if (tm_abort_check(regs,
1018 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1020 PPC_WARN_EMULATED(string, regs);
1021 return emulate_string_inst(regs, instword);
1024 /* Emulate the popcntb (Population Count Bytes) instruction. */
1025 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1026 PPC_WARN_EMULATED(popcntb, regs);
1027 return emulate_popcntb_inst(regs, instword);
1030 /* Emulate isel (Integer Select) instruction */
1031 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1032 PPC_WARN_EMULATED(isel, regs);
1033 return emulate_isel(regs, instword);
1036 /* Emulate sync instruction variants */
1037 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1038 PPC_WARN_EMULATED(sync, regs);
1039 asm volatile("sync");
1044 /* Emulate the mfspr rD, DSCR. */
1045 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1046 PPC_INST_MFSPR_DSCR_USER) ||
1047 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1048 PPC_INST_MFSPR_DSCR)) &&
1049 cpu_has_feature(CPU_FTR_DSCR)) {
1050 PPC_WARN_EMULATED(mfdscr, regs);
1051 rd = (instword >> 21) & 0x1f;
1052 regs->gpr[rd] = mfspr(SPRN_DSCR);
1055 /* Emulate the mtspr DSCR, rD. */
1056 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1057 PPC_INST_MTSPR_DSCR_USER) ||
1058 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1059 PPC_INST_MTSPR_DSCR)) &&
1060 cpu_has_feature(CPU_FTR_DSCR)) {
1061 PPC_WARN_EMULATED(mtdscr, regs);
1062 rd = (instword >> 21) & 0x1f;
1063 current->thread.dscr = regs->gpr[rd];
1064 current->thread.dscr_inherit = 1;
1065 mtspr(SPRN_DSCR, current->thread.dscr);
1073 int is_valid_bugaddr(unsigned long addr)
1075 return is_kernel_addr(addr);
1078 #ifdef CONFIG_MATH_EMULATION
1079 static int emulate_math(struct pt_regs *regs)
1082 extern int do_mathemu(struct pt_regs *regs);
1084 ret = do_mathemu(regs);
1086 PPC_WARN_EMULATED(math, regs);
1090 emulate_single_step(regs);
1094 code = __parse_fpscr(current->thread.fp_state.fpscr);
1095 _exception(SIGFPE, regs, code, regs->nip);
1099 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1106 static inline int emulate_math(struct pt_regs *regs) { return -1; }
1109 void program_check_exception(struct pt_regs *regs)
1111 enum ctx_state prev_state = exception_enter();
1112 unsigned int reason = get_reason(regs);
1114 /* We can now get here via a FP Unavailable exception if the core
1115 * has no FPU, in that case the reason flags will be 0 */
1117 if (reason & REASON_FP) {
1118 /* IEEE FP exception */
1122 if (reason & REASON_TRAP) {
1123 unsigned long bugaddr;
1124 /* Debugger is first in line to stop recursive faults in
1125 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1126 if (debugger_bpt(regs))
1129 if (kprobe_handler(regs))
1132 /* trap exception */
1133 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1137 bugaddr = regs->nip;
1139 * Fixup bugaddr for BUG_ON() in real mode
1141 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR))
1142 bugaddr += PAGE_OFFSET;
1144 if (!(regs->msr & MSR_PR) && /* not user-mode */
1145 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) {
1149 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1152 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1153 if (reason & REASON_TM) {
1154 /* This is a TM "Bad Thing Exception" program check.
1156 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1157 * transition in TM states.
1158 * - A trechkpt is attempted when transactional.
1159 * - A treclaim is attempted when non transactional.
1160 * - A tend is illegally attempted.
1161 * - writing a TM SPR when transactional.
1163 if (!user_mode(regs) &&
1164 report_bug(regs->nip, regs) == BUG_TRAP_TYPE_WARN) {
1168 /* If usermode caused this, it's done something illegal and
1169 * gets a SIGILL slap on the wrist. We call it an illegal
1170 * operand to distinguish from the instruction just being bad
1171 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1172 * illegal /placement/ of a valid instruction.
1174 if (user_mode(regs)) {
1175 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1178 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1179 "at %lx (msr 0x%x)\n", regs->nip, reason);
1180 die("Unrecoverable exception", regs, SIGABRT);
1186 * If we took the program check in the kernel skip down to sending a
1187 * SIGILL. The subsequent cases all relate to emulating instructions
1188 * which we should only do for userspace. We also do not want to enable
1189 * interrupts for kernel faults because that might lead to further
1190 * faults, and loose the context of the original exception.
1192 if (!user_mode(regs))
1195 /* We restore the interrupt state now */
1196 if (!arch_irq_disabled_regs(regs))
1199 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1200 * but there seems to be a hardware bug on the 405GP (RevD)
1201 * that means ESR is sometimes set incorrectly - either to
1202 * ESR_DST (!?) or 0. In the process of chasing this with the
1203 * hardware people - not sure if it can happen on any illegal
1204 * instruction or only on FP instructions, whether there is a
1205 * pattern to occurrences etc. -dgibson 31/Mar/2003
1207 if (!emulate_math(regs))
1210 /* Try to emulate it if we should. */
1211 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1212 switch (emulate_instruction(regs)) {
1215 emulate_single_step(regs);
1218 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1224 if (reason & REASON_PRIVILEGED)
1225 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1227 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1230 exception_exit(prev_state);
1232 NOKPROBE_SYMBOL(program_check_exception);
1235 * This occurs when running in hypervisor mode on POWER6 or later
1236 * and an illegal instruction is encountered.
1238 void emulation_assist_interrupt(struct pt_regs *regs)
1240 regs->msr |= REASON_ILLEGAL;
1241 program_check_exception(regs);
1243 NOKPROBE_SYMBOL(emulation_assist_interrupt);
1245 void alignment_exception(struct pt_regs *regs)
1247 enum ctx_state prev_state = exception_enter();
1248 int sig, code, fixed = 0;
1250 /* We restore the interrupt state now */
1251 if (!arch_irq_disabled_regs(regs))
1254 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1257 /* we don't implement logging of alignment exceptions */
1258 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1259 fixed = fix_alignment(regs);
1262 regs->nip += 4; /* skip over emulated instruction */
1263 emulate_single_step(regs);
1267 /* Operand address was bad */
1268 if (fixed == -EFAULT) {
1275 if (user_mode(regs))
1276 _exception(sig, regs, code, regs->dar);
1278 bad_page_fault(regs, regs->dar, sig);
1281 exception_exit(prev_state);
1284 void slb_miss_bad_addr(struct pt_regs *regs)
1286 enum ctx_state prev_state = exception_enter();
1288 if (user_mode(regs))
1289 _exception(SIGSEGV, regs, SEGV_BNDERR, regs->dar);
1291 bad_page_fault(regs, regs->dar, SIGSEGV);
1293 exception_exit(prev_state);
1296 void StackOverflow(struct pt_regs *regs)
1298 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n",
1299 current->comm, task_pid_nr(current), regs->gpr[1]);
1302 panic("kernel stack overflow");
1305 void nonrecoverable_exception(struct pt_regs *regs)
1307 printk(KERN_ERR "Non-recoverable exception at PC=%lx MSR=%lx\n",
1308 regs->nip, regs->msr);
1310 die("nonrecoverable exception", regs, SIGKILL);
1313 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1315 enum ctx_state prev_state = exception_enter();
1317 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1318 "%lx at %lx\n", regs->trap, regs->nip);
1319 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1321 exception_exit(prev_state);
1324 void altivec_unavailable_exception(struct pt_regs *regs)
1326 enum ctx_state prev_state = exception_enter();
1328 if (user_mode(regs)) {
1329 /* A user program has executed an altivec instruction,
1330 but this kernel doesn't support altivec. */
1331 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1335 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1336 "%lx at %lx\n", regs->trap, regs->nip);
1337 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1340 exception_exit(prev_state);
1343 void vsx_unavailable_exception(struct pt_regs *regs)
1345 if (user_mode(regs)) {
1346 /* A user program has executed an vsx instruction,
1347 but this kernel doesn't support vsx. */
1348 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1352 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1353 "%lx at %lx\n", regs->trap, regs->nip);
1354 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1358 static void tm_unavailable(struct pt_regs *regs)
1360 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1361 if (user_mode(regs)) {
1362 current->thread.load_tm++;
1363 regs->msr |= MSR_TM;
1365 tm_restore_sprs(¤t->thread);
1369 pr_emerg("Unrecoverable TM Unavailable Exception "
1370 "%lx at %lx\n", regs->trap, regs->nip);
1371 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT);
1374 void facility_unavailable_exception(struct pt_regs *regs)
1376 static char *facility_strings[] = {
1377 [FSCR_FP_LG] = "FPU",
1378 [FSCR_VECVSX_LG] = "VMX/VSX",
1379 [FSCR_DSCR_LG] = "DSCR",
1380 [FSCR_PM_LG] = "PMU SPRs",
1381 [FSCR_BHRB_LG] = "BHRB",
1382 [FSCR_TM_LG] = "TM",
1383 [FSCR_EBB_LG] = "EBB",
1384 [FSCR_TAR_LG] = "TAR",
1385 [FSCR_MSGP_LG] = "MSGP",
1386 [FSCR_SCV_LG] = "SCV",
1388 char *facility = "unknown";
1394 hv = (regs->trap == 0xf80);
1396 value = mfspr(SPRN_HFSCR);
1398 value = mfspr(SPRN_FSCR);
1400 status = value >> 56;
1401 if ((hv || status >= 2) &&
1402 (status < ARRAY_SIZE(facility_strings)) &&
1403 facility_strings[status])
1404 facility = facility_strings[status];
1406 /* We should not have taken this interrupt in kernel */
1407 if (!user_mode(regs)) {
1408 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n",
1409 facility, status, regs->nip);
1410 die("Unexpected facility unavailable exception", regs, SIGABRT);
1413 /* We restore the interrupt state now */
1414 if (!arch_irq_disabled_regs(regs))
1417 if (status == FSCR_DSCR_LG) {
1419 * User is accessing the DSCR register using the problem
1420 * state only SPR number (0x03) either through a mfspr or
1421 * a mtspr instruction. If it is a write attempt through
1422 * a mtspr, then we set the inherit bit. This also allows
1423 * the user to write or read the register directly in the
1424 * future by setting via the FSCR DSCR bit. But in case it
1425 * is a read DSCR attempt through a mfspr instruction, we
1426 * just emulate the instruction instead. This code path will
1427 * always emulate all the mfspr instructions till the user
1428 * has attempted at least one mtspr instruction. This way it
1429 * preserves the same behaviour when the user is accessing
1430 * the DSCR through privilege level only SPR number (0x11)
1431 * which is emulated through illegal instruction exception.
1432 * We always leave HFSCR DSCR set.
1434 if (get_user(instword, (u32 __user *)(regs->nip))) {
1435 pr_err("Failed to fetch the user instruction\n");
1439 /* Write into DSCR (mtspr 0x03, RS) */
1440 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1441 == PPC_INST_MTSPR_DSCR_USER) {
1442 rd = (instword >> 21) & 0x1f;
1443 current->thread.dscr = regs->gpr[rd];
1444 current->thread.dscr_inherit = 1;
1445 current->thread.fscr |= FSCR_DSCR;
1446 mtspr(SPRN_FSCR, current->thread.fscr);
1449 /* Read from DSCR (mfspr RT, 0x03) */
1450 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1451 == PPC_INST_MFSPR_DSCR_USER) {
1452 if (emulate_instruction(regs)) {
1453 pr_err("DSCR based mfspr emulation failed\n");
1457 emulate_single_step(regs);
1462 if (status == FSCR_TM_LG) {
1464 * If we're here then the hardware is TM aware because it
1465 * generated an exception with FSRM_TM set.
1467 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1468 * told us not to do TM, or the kernel is not built with TM
1471 * If both of those things are true, then userspace can spam the
1472 * console by triggering the printk() below just by continually
1473 * doing tbegin (or any TM instruction). So in that case just
1474 * send the process a SIGILL immediately.
1476 if (!cpu_has_feature(CPU_FTR_TM))
1479 tm_unavailable(regs);
1483 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1484 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr);
1487 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1491 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1493 void fp_unavailable_tm(struct pt_regs *regs)
1495 /* Note: This does not handle any kind of FP laziness. */
1497 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1498 regs->nip, regs->msr);
1500 /* We can only have got here if the task started using FP after
1501 * beginning the transaction. So, the transactional regs are just a
1502 * copy of the checkpointed ones. But, we still need to recheckpoint
1503 * as we're enabling FP for the process; it will return, abort the
1504 * transaction, and probably retry but now with FP enabled. So the
1505 * checkpointed FP registers need to be loaded.
1507 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1508 /* Reclaim didn't save out any FPRs to transact_fprs. */
1510 /* Enable FP for the task: */
1511 regs->msr |= (MSR_FP | current->thread.fpexc_mode);
1513 /* This loads and recheckpoints the FP registers from
1514 * thread.fpr[]. They will remain in registers after the
1515 * checkpoint so we don't need to reload them after.
1516 * If VMX is in use, the VRs now hold checkpointed values,
1517 * so we don't want to load the VRs from the thread_struct.
1519 tm_recheckpoint(¤t->thread, MSR_FP);
1521 /* If VMX is in use, get the transactional values back */
1522 if (regs->msr & MSR_VEC) {
1523 msr_check_and_set(MSR_VEC);
1524 load_vr_state(¤t->thread.vr_state);
1525 /* At this point all the VSX state is loaded, so enable it */
1526 regs->msr |= MSR_VSX;
1530 void altivec_unavailable_tm(struct pt_regs *regs)
1532 /* See the comments in fp_unavailable_tm(). This function operates
1536 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1538 regs->nip, regs->msr);
1539 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1540 regs->msr |= MSR_VEC;
1541 tm_recheckpoint(¤t->thread, MSR_VEC);
1542 current->thread.used_vr = 1;
1544 if (regs->msr & MSR_FP) {
1545 msr_check_and_set(MSR_FP);
1546 load_fp_state(¤t->thread.fp_state);
1547 regs->msr |= MSR_VSX;
1551 void vsx_unavailable_tm(struct pt_regs *regs)
1553 unsigned long orig_msr = regs->msr;
1555 /* See the comments in fp_unavailable_tm(). This works similarly,
1556 * though we're loading both FP and VEC registers in here.
1558 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1559 * regs. Either way, set MSR_VSX.
1562 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1564 regs->nip, regs->msr);
1566 current->thread.used_vsr = 1;
1568 /* If FP and VMX are already loaded, we have all the state we need */
1569 if ((orig_msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC)) {
1570 regs->msr |= MSR_VSX;
1574 /* This reclaims FP and/or VR regs if they're already enabled */
1575 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1577 regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
1580 /* This loads & recheckpoints FP and VRs; but we have
1581 * to be sure not to overwrite previously-valid state.
1583 tm_recheckpoint(¤t->thread, regs->msr & ~orig_msr);
1585 msr_check_and_set(orig_msr & (MSR_FP | MSR_VEC));
1587 if (orig_msr & MSR_FP)
1588 load_fp_state(¤t->thread.fp_state);
1589 if (orig_msr & MSR_VEC)
1590 load_vr_state(¤t->thread.vr_state);
1592 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1594 void performance_monitor_exception(struct pt_regs *regs)
1596 __this_cpu_inc(irq_stat.pmu_irqs);
1601 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1602 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1606 * Determine the cause of the debug event, clear the
1607 * event flags and send a trap to the handler. Torez
1609 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1610 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1611 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1612 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1614 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status, TRAP_HWBKPT,
1617 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1618 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1619 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status, TRAP_HWBKPT,
1622 } else if (debug_status & DBSR_IAC1) {
1623 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1624 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1625 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status, TRAP_HWBKPT,
1628 } else if (debug_status & DBSR_IAC2) {
1629 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1630 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status, TRAP_HWBKPT,
1633 } else if (debug_status & DBSR_IAC3) {
1634 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1635 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1636 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status, TRAP_HWBKPT,
1639 } else if (debug_status & DBSR_IAC4) {
1640 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1641 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status, TRAP_HWBKPT,
1646 * At the point this routine was called, the MSR(DE) was turned off.
1647 * Check all other debug flags and see if that bit needs to be turned
1650 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1651 current->thread.debug.dbcr1))
1652 regs->msr |= MSR_DE;
1654 /* Make sure the IDM flag is off */
1655 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1658 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1661 void DebugException(struct pt_regs *regs, unsigned long debug_status)
1663 current->thread.debug.dbsr = debug_status;
1665 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1666 * on server, it stops on the target of the branch. In order to simulate
1667 * the server behaviour, we thus restart right away with a single step
1668 * instead of stopping here when hitting a BT
1670 if (debug_status & DBSR_BT) {
1671 regs->msr &= ~MSR_DE;
1674 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1675 /* Clear the BT event */
1676 mtspr(SPRN_DBSR, DBSR_BT);
1678 /* Do the single step trick only when coming from userspace */
1679 if (user_mode(regs)) {
1680 current->thread.debug.dbcr0 &= ~DBCR0_BT;
1681 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1682 regs->msr |= MSR_DE;
1686 if (kprobe_post_handler(regs))
1689 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1690 5, SIGTRAP) == NOTIFY_STOP) {
1693 if (debugger_sstep(regs))
1695 } else if (debug_status & DBSR_IC) { /* Instruction complete */
1696 regs->msr &= ~MSR_DE;
1698 /* Disable instruction completion */
1699 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
1700 /* Clear the instruction completion event */
1701 mtspr(SPRN_DBSR, DBSR_IC);
1703 if (kprobe_post_handler(regs))
1706 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1707 5, SIGTRAP) == NOTIFY_STOP) {
1711 if (debugger_sstep(regs))
1714 if (user_mode(regs)) {
1715 current->thread.debug.dbcr0 &= ~DBCR0_IC;
1716 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1717 current->thread.debug.dbcr1))
1718 regs->msr |= MSR_DE;
1720 /* Make sure the IDM bit is off */
1721 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1724 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1726 handle_debug(regs, debug_status);
1728 NOKPROBE_SYMBOL(DebugException);
1729 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
1731 #if !defined(CONFIG_TAU_INT)
1732 void TAUException(struct pt_regs *regs)
1734 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
1735 regs->nip, regs->msr, regs->trap, print_tainted());
1737 #endif /* CONFIG_INT_TAU */
1739 #ifdef CONFIG_ALTIVEC
1740 void altivec_assist_exception(struct pt_regs *regs)
1744 if (!user_mode(regs)) {
1745 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
1746 " at %lx\n", regs->nip);
1747 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
1750 flush_altivec_to_thread(current);
1752 PPC_WARN_EMULATED(altivec, regs);
1753 err = emulate_altivec(regs);
1755 regs->nip += 4; /* skip emulated instruction */
1756 emulate_single_step(regs);
1760 if (err == -EFAULT) {
1761 /* got an error reading the instruction */
1762 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1764 /* didn't recognize the instruction */
1765 /* XXX quick hack for now: set the non-Java bit in the VSCR */
1766 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
1767 "in %s at %lx\n", current->comm, regs->nip);
1768 current->thread.vr_state.vscr.u[3] |= 0x10000;
1771 #endif /* CONFIG_ALTIVEC */
1773 #ifdef CONFIG_FSL_BOOKE
1774 void CacheLockingException(struct pt_regs *regs, unsigned long address,
1775 unsigned long error_code)
1777 /* We treat cache locking instructions from the user
1778 * as priv ops, in the future we could try to do
1781 if (error_code & (ESR_DLK|ESR_ILK))
1782 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1785 #endif /* CONFIG_FSL_BOOKE */
1788 void SPEFloatingPointException(struct pt_regs *regs)
1790 extern int do_spe_mathemu(struct pt_regs *regs);
1791 unsigned long spefscr;
1796 flush_spe_to_thread(current);
1798 spefscr = current->thread.spefscr;
1799 fpexc_mode = current->thread.fpexc_mode;
1801 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
1804 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
1807 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
1809 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
1812 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
1815 err = do_spe_mathemu(regs);
1817 regs->nip += 4; /* skip emulated instruction */
1818 emulate_single_step(regs);
1822 if (err == -EFAULT) {
1823 /* got an error reading the instruction */
1824 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1825 } else if (err == -EINVAL) {
1826 /* didn't recognize the instruction */
1827 printk(KERN_ERR "unrecognized spe instruction "
1828 "in %s at %lx\n", current->comm, regs->nip);
1830 _exception(SIGFPE, regs, code, regs->nip);
1836 void SPEFloatingPointRoundException(struct pt_regs *regs)
1838 extern int speround_handler(struct pt_regs *regs);
1842 if (regs->msr & MSR_SPE)
1843 giveup_spe(current);
1847 err = speround_handler(regs);
1849 regs->nip += 4; /* skip emulated instruction */
1850 emulate_single_step(regs);
1854 if (err == -EFAULT) {
1855 /* got an error reading the instruction */
1856 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
1857 } else if (err == -EINVAL) {
1858 /* didn't recognize the instruction */
1859 printk(KERN_ERR "unrecognized spe instruction "
1860 "in %s at %lx\n", current->comm, regs->nip);
1862 _exception(SIGFPE, regs, 0, regs->nip);
1869 * We enter here if we get an unrecoverable exception, that is, one
1870 * that happened at a point where the RI (recoverable interrupt) bit
1871 * in the MSR is 0. This indicates that SRR0/1 are live, and that
1872 * we therefore lost state by taking this exception.
1874 void unrecoverable_exception(struct pt_regs *regs)
1876 printk(KERN_EMERG "Unrecoverable exception %lx at %lx\n",
1877 regs->trap, regs->nip);
1878 die("Unrecoverable exception", regs, SIGABRT);
1880 NOKPROBE_SYMBOL(unrecoverable_exception);
1882 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
1884 * Default handler for a Watchdog exception,
1885 * spins until a reboot occurs
1887 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
1889 /* Generic WatchdogHandler, implement your own */
1890 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
1894 void WatchdogException(struct pt_regs *regs)
1896 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
1897 WatchdogHandler(regs);
1902 * We enter here if we discover during exception entry that we are
1903 * running in supervisor mode with a userspace value in the stack pointer.
1905 void kernel_bad_stack(struct pt_regs *regs)
1907 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
1908 regs->gpr[1], regs->nip);
1909 die("Bad kernel stack pointer", regs, SIGABRT);
1911 NOKPROBE_SYMBOL(kernel_bad_stack);
1913 void __init trap_init(void)
1918 #ifdef CONFIG_PPC_EMULATED_STATS
1920 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
1922 struct ppc_emulated ppc_emulated = {
1923 #ifdef CONFIG_ALTIVEC
1924 WARN_EMULATED_SETUP(altivec),
1926 WARN_EMULATED_SETUP(dcba),
1927 WARN_EMULATED_SETUP(dcbz),
1928 WARN_EMULATED_SETUP(fp_pair),
1929 WARN_EMULATED_SETUP(isel),
1930 WARN_EMULATED_SETUP(mcrxr),
1931 WARN_EMULATED_SETUP(mfpvr),
1932 WARN_EMULATED_SETUP(multiple),
1933 WARN_EMULATED_SETUP(popcntb),
1934 WARN_EMULATED_SETUP(spe),
1935 WARN_EMULATED_SETUP(string),
1936 WARN_EMULATED_SETUP(sync),
1937 WARN_EMULATED_SETUP(unaligned),
1938 #ifdef CONFIG_MATH_EMULATION
1939 WARN_EMULATED_SETUP(math),
1942 WARN_EMULATED_SETUP(vsx),
1945 WARN_EMULATED_SETUP(mfdscr),
1946 WARN_EMULATED_SETUP(mtdscr),
1947 WARN_EMULATED_SETUP(lq_stq),
1951 u32 ppc_warn_emulated;
1953 void ppc_warn_emulated_print(const char *type)
1955 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
1959 static int __init ppc_warn_emulated_init(void)
1961 struct dentry *dir, *d;
1963 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
1965 if (!powerpc_debugfs_root)
1968 dir = debugfs_create_dir("emulated_instructions",
1969 powerpc_debugfs_root);
1973 d = debugfs_create_u32("do_warn", S_IRUGO | S_IWUSR, dir,
1974 &ppc_warn_emulated);
1978 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
1979 d = debugfs_create_u32(entries[i].name, S_IRUGO | S_IWUSR, dir,
1980 (u32 *)&entries[i].val.counter);
1988 debugfs_remove_recursive(dir);
1992 device_initcall(ppc_warn_emulated_init);
1994 #endif /* CONFIG_PPC_EMULATED_STATS */