1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Copyright 2007-2010 Freescale Semiconductor, Inc.
6 * Modified by Cort Dougan (cort@cs.nmt.edu)
7 * and Paul Mackerras (paulus@samba.org)
11 * This file handles the architecture-dependent parts of hardware exceptions
14 #include <linux/errno.h>
15 #include <linux/sched.h>
16 #include <linux/sched/debug.h>
17 #include <linux/kernel.h>
19 #include <linux/pkeys.h>
20 #include <linux/stddef.h>
21 #include <linux/unistd.h>
22 #include <linux/ptrace.h>
23 #include <linux/user.h>
24 #include <linux/interrupt.h>
25 #include <linux/init.h>
26 #include <linux/extable.h>
27 #include <linux/module.h> /* print_modules */
28 #include <linux/prctl.h>
29 #include <linux/delay.h>
30 #include <linux/kprobes.h>
31 #include <linux/kexec.h>
32 #include <linux/backlight.h>
33 #include <linux/bug.h>
34 #include <linux/kdebug.h>
35 #include <linux/ratelimit.h>
36 #include <linux/context_tracking.h>
37 #include <linux/smp.h>
38 #include <linux/console.h>
39 #include <linux/kmsg_dump.h>
41 #include <asm/emulated_ops.h>
42 #include <asm/pgtable.h>
43 #include <linux/uaccess.h>
44 #include <asm/debugfs.h>
46 #include <asm/machdep.h>
50 #ifdef CONFIG_PMAC_BACKLIGHT
51 #include <asm/backlight.h>
54 #include <asm/firmware.h>
55 #include <asm/processor.h>
58 #include <asm/kexec.h>
59 #include <asm/ppc-opcode.h>
61 #include <asm/fadump.h>
62 #include <asm/switch_to.h>
64 #include <asm/debug.h>
65 #include <asm/asm-prototypes.h>
67 #include <sysdev/fsl_pci.h>
68 #include <asm/kprobes.h>
69 #include <asm/stacktrace.h>
72 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC_CORE)
73 int (*__debugger)(struct pt_regs *regs) __read_mostly;
74 int (*__debugger_ipi)(struct pt_regs *regs) __read_mostly;
75 int (*__debugger_bpt)(struct pt_regs *regs) __read_mostly;
76 int (*__debugger_sstep)(struct pt_regs *regs) __read_mostly;
77 int (*__debugger_iabr_match)(struct pt_regs *regs) __read_mostly;
78 int (*__debugger_break_match)(struct pt_regs *regs) __read_mostly;
79 int (*__debugger_fault_handler)(struct pt_regs *regs) __read_mostly;
81 EXPORT_SYMBOL(__debugger);
82 EXPORT_SYMBOL(__debugger_ipi);
83 EXPORT_SYMBOL(__debugger_bpt);
84 EXPORT_SYMBOL(__debugger_sstep);
85 EXPORT_SYMBOL(__debugger_iabr_match);
86 EXPORT_SYMBOL(__debugger_break_match);
87 EXPORT_SYMBOL(__debugger_fault_handler);
90 /* Transactional Memory trap debug */
92 #define TM_DEBUG(x...) printk(KERN_INFO x)
94 #define TM_DEBUG(x...) do { } while(0)
97 static const char *signame(int signr)
100 case SIGBUS: return "bus error";
101 case SIGFPE: return "floating point exception";
102 case SIGILL: return "illegal instruction";
103 case SIGSEGV: return "segfault";
104 case SIGTRAP: return "unhandled trap";
107 return "unknown signal";
111 * Trap & Exception support
114 #ifdef CONFIG_PMAC_BACKLIGHT
115 static void pmac_backlight_unblank(void)
117 mutex_lock(&pmac_backlight_mutex);
118 if (pmac_backlight) {
119 struct backlight_properties *props;
121 props = &pmac_backlight->props;
122 props->brightness = props->max_brightness;
123 props->power = FB_BLANK_UNBLANK;
124 backlight_update_status(pmac_backlight);
126 mutex_unlock(&pmac_backlight_mutex);
129 static inline void pmac_backlight_unblank(void) { }
133 * If oops/die is expected to crash the machine, return true here.
135 * This should not be expected to be 100% accurate, there may be
136 * notifiers registered or other unexpected conditions that may bring
137 * down the kernel. Or if the current process in the kernel is holding
138 * locks or has other critical state, the kernel may become effectively
141 bool die_will_crash(void)
143 if (should_fadump_crash())
145 if (kexec_should_crash(current))
147 if (in_interrupt() || panic_on_oops ||
148 !current->pid || is_global_init(current))
154 static arch_spinlock_t die_lock = __ARCH_SPIN_LOCK_UNLOCKED;
155 static int die_owner = -1;
156 static unsigned int die_nest_count;
157 static int die_counter;
159 extern void panic_flush_kmsg_start(void)
162 * These are mostly taken from kernel/panic.c, but tries to do
163 * relatively minimal work. Don't use delay functions (TB may
164 * be broken), don't crash dump (need to set a firmware log),
165 * don't run notifiers. We do want to get some information to
172 extern void panic_flush_kmsg_end(void)
174 printk_safe_flush_on_panic();
175 kmsg_dump(KMSG_DUMP_PANIC);
178 console_flush_on_panic(CONSOLE_FLUSH_PENDING);
181 static unsigned long oops_begin(struct pt_regs *regs)
188 /* racy, but better than risking deadlock. */
189 raw_local_irq_save(flags);
190 cpu = smp_processor_id();
191 if (!arch_spin_trylock(&die_lock)) {
192 if (cpu == die_owner)
193 /* nested oops. should stop eventually */;
195 arch_spin_lock(&die_lock);
201 if (machine_is(powermac))
202 pmac_backlight_unblank();
205 NOKPROBE_SYMBOL(oops_begin);
207 static void oops_end(unsigned long flags, struct pt_regs *regs,
211 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
215 if (!die_nest_count) {
216 /* Nest count reaches zero, release the lock. */
218 arch_spin_unlock(&die_lock);
220 raw_local_irq_restore(flags);
223 * system_reset_excption handles debugger, crash dump, panic, for 0x100
225 if (TRAP(regs) == 0x100)
228 crash_fadump(regs, "die oops");
230 if (kexec_should_crash(current))
237 * While our oops output is serialised by a spinlock, output
238 * from panic() called below can race and corrupt it. If we
239 * know we are going to panic, delay for 1 second so we have a
240 * chance to get clean backtraces from all CPUs that are oopsing.
242 if (in_interrupt() || panic_on_oops || !current->pid ||
243 is_global_init(current)) {
244 mdelay(MSEC_PER_SEC);
248 panic("Fatal exception");
249 make_task_dead(signr);
251 NOKPROBE_SYMBOL(oops_end);
253 static char *get_mmu_str(void)
255 if (early_radix_enabled())
257 if (early_mmu_has_feature(MMU_FTR_HPTE_TABLE))
262 static int __die(const char *str, struct pt_regs *regs, long err)
264 printk("Oops: %s, sig: %ld [#%d]\n", str, err, ++die_counter);
266 printk("%s PAGE_SIZE=%luK%s%s%s%s%s%s %s\n",
267 IS_ENABLED(CONFIG_CPU_LITTLE_ENDIAN) ? "LE" : "BE",
268 PAGE_SIZE / 1024, get_mmu_str(),
269 IS_ENABLED(CONFIG_PREEMPT) ? " PREEMPT" : "",
270 IS_ENABLED(CONFIG_SMP) ? " SMP" : "",
271 IS_ENABLED(CONFIG_SMP) ? (" NR_CPUS=" __stringify(NR_CPUS)) : "",
272 debug_pagealloc_enabled() ? " DEBUG_PAGEALLOC" : "",
273 IS_ENABLED(CONFIG_NUMA) ? " NUMA" : "",
274 ppc_md.name ? ppc_md.name : "");
276 if (notify_die(DIE_OOPS, str, regs, err, 255, SIGSEGV) == NOTIFY_STOP)
284 NOKPROBE_SYMBOL(__die);
286 void die(const char *str, struct pt_regs *regs, long err)
291 * system_reset_excption handles debugger, crash dump, panic, for 0x100
293 if (TRAP(regs) != 0x100) {
298 flags = oops_begin(regs);
299 if (__die(str, regs, err))
301 oops_end(flags, regs, err);
303 NOKPROBE_SYMBOL(die);
305 void user_single_step_report(struct pt_regs *regs)
307 force_sig_fault(SIGTRAP, TRAP_TRACE, (void __user *)regs->nip);
310 static void show_signal_msg(int signr, struct pt_regs *regs, int code,
313 static DEFINE_RATELIMIT_STATE(rs, DEFAULT_RATELIMIT_INTERVAL,
314 DEFAULT_RATELIMIT_BURST);
316 if (!show_unhandled_signals)
319 if (!unhandled_signal(current, signr))
322 if (!__ratelimit(&rs))
325 pr_info("%s[%d]: %s (%d) at %lx nip %lx lr %lx code %x",
326 current->comm, current->pid, signame(signr), signr,
327 addr, regs->nip, regs->link, code);
329 print_vma_addr(KERN_CONT " in ", regs->nip);
333 show_user_instructions(regs);
336 static bool exception_common(int signr, struct pt_regs *regs, int code,
339 if (!user_mode(regs)) {
340 die("Exception in kernel mode", regs, signr);
344 show_signal_msg(signr, regs, code, addr);
346 if (arch_irqs_disabled() && !arch_irq_disabled_regs(regs))
349 current->thread.trap_nr = code;
352 * Save all the pkey registers AMR/IAMR/UAMOR. Eg: Core dumps need
353 * to capture the content, if the task gets killed.
355 thread_pkey_regs_save(¤t->thread);
360 void _exception_pkey(struct pt_regs *regs, unsigned long addr, int key)
362 if (!exception_common(SIGSEGV, regs, SEGV_PKUERR, addr))
365 force_sig_pkuerr((void __user *) addr, key);
368 void _exception(int signr, struct pt_regs *regs, int code, unsigned long addr)
370 if (!exception_common(signr, regs, code, addr))
373 force_sig_fault(signr, code, (void __user *)addr);
377 * The interrupt architecture has a quirk in that the HV interrupts excluding
378 * the NMIs (0x100 and 0x200) do not clear MSR[RI] at entry. The first thing
379 * that an interrupt handler must do is save off a GPR into a scratch register,
380 * and all interrupts on POWERNV (HV=1) use the HSPRG1 register as scratch.
381 * Therefore an NMI can clobber an HV interrupt's live HSPRG1 without noticing
382 * that it is non-reentrant, which leads to random data corruption.
384 * The solution is for NMI interrupts in HV mode to check if they originated
385 * from these critical HV interrupt regions. If so, then mark them not
388 * An alternative would be for HV NMIs to use SPRG for scratch to avoid the
389 * HSPRG1 clobber, however this would cause guest SPRG to be clobbered. Linux
390 * guests should always have MSR[RI]=0 when its scratch SPRG is in use, so
391 * that would work. However any other guest OS that may have the SPRG live
392 * and MSR[RI]=1 could encounter silent corruption.
394 * Builds that do not support KVM could take this second option to increase
395 * the recoverability of NMIs.
397 void hv_nmi_check_nonrecoverable(struct pt_regs *regs)
399 #ifdef CONFIG_PPC_POWERNV
400 unsigned long kbase = (unsigned long)_stext;
401 unsigned long nip = regs->nip;
403 if (!(regs->msr & MSR_RI))
405 if (!(regs->msr & MSR_HV))
407 if (regs->msr & MSR_PR)
411 * Now test if the interrupt has hit a range that may be using
412 * HSPRG1 without having RI=0 (i.e., an HSRR interrupt). The
413 * problem ranges all run un-relocated. Test real and virt modes
414 * at the same time by droping the high bit of the nip (virt mode
415 * entry points still have the +0x4000 offset).
417 nip &= ~0xc000000000000000ULL;
418 if ((nip >= 0x500 && nip < 0x600) || (nip >= 0x4500 && nip < 0x4600))
420 if ((nip >= 0x980 && nip < 0xa00) || (nip >= 0x4980 && nip < 0x4a00))
422 if ((nip >= 0xe00 && nip < 0xec0) || (nip >= 0x4e00 && nip < 0x4ec0))
424 if ((nip >= 0xf80 && nip < 0xfa0) || (nip >= 0x4f80 && nip < 0x4fa0))
427 /* Trampoline code runs un-relocated so subtract kbase. */
428 if (nip >= (unsigned long)(start_real_trampolines - kbase) &&
429 nip < (unsigned long)(end_real_trampolines - kbase))
431 if (nip >= (unsigned long)(start_virt_trampolines - kbase) &&
432 nip < (unsigned long)(end_virt_trampolines - kbase))
437 regs->msr &= ~MSR_RI;
441 void system_reset_exception(struct pt_regs *regs)
443 unsigned long hsrr0, hsrr1;
444 bool nested = in_nmi();
445 bool saved_hsrrs = false;
448 * Avoid crashes in case of nested NMI exceptions. Recoverability
449 * is determined by RI and in_nmi
455 * System reset can interrupt code where HSRRs are live and MSR[RI]=1.
456 * The system reset interrupt itself may clobber HSRRs (e.g., to call
457 * OPAL), so save them here and restore them before returning.
459 * Machine checks don't need to save HSRRs, as the real mode handler
460 * is careful to avoid them, and the regular handler is not delivered
463 if (cpu_has_feature(CPU_FTR_HVMODE)) {
464 hsrr0 = mfspr(SPRN_HSRR0);
465 hsrr1 = mfspr(SPRN_HSRR1);
469 hv_nmi_check_nonrecoverable(regs);
471 __this_cpu_inc(irq_stat.sreset_irqs);
473 /* See if any machine dependent calls */
474 if (ppc_md.system_reset_exception) {
475 if (ppc_md.system_reset_exception(regs))
482 kmsg_dump(KMSG_DUMP_OOPS);
484 * A system reset is a request to dump, so we always send
485 * it through the crashdump code (if fadump or kdump are
488 crash_fadump(regs, "System Reset");
493 * We aren't the primary crash CPU. We need to send it
494 * to a holding pattern to avoid it ending up in the panic
497 crash_kexec_secondary(regs);
500 * No debugger or crash dump registered, print logs then
503 die("System Reset", regs, SIGABRT);
505 mdelay(2*MSEC_PER_SEC); /* Wait a little while for others to print */
506 add_taint(TAINT_DIE, LOCKDEP_NOW_UNRELIABLE);
507 nmi_panic(regs, "System Reset");
510 #ifdef CONFIG_PPC_BOOK3S_64
511 BUG_ON(get_paca()->in_nmi == 0);
512 if (get_paca()->in_nmi > 1)
513 die("Unrecoverable nested System Reset", regs, SIGABRT);
515 /* Must die if the interrupt is not recoverable */
516 if (!(regs->msr & MSR_RI)) {
517 /* For the reason explained in die_mce, nmi_exit before die */
519 die("Unrecoverable System Reset", regs, SIGABRT);
523 mtspr(SPRN_HSRR0, hsrr0);
524 mtspr(SPRN_HSRR1, hsrr1);
530 /* What should we do here? We could issue a shutdown or hard reset. */
534 * I/O accesses can cause machine checks on powermacs.
535 * Check if the NIP corresponds to the address of a sync
536 * instruction for which there is an entry in the exception
538 * Note that the 601 only takes a machine check on TEA
539 * (transfer error ack) signal assertion, and does not
540 * set any of the top 16 bits of SRR1.
543 static inline int check_io_access(struct pt_regs *regs)
546 unsigned long msr = regs->msr;
547 const struct exception_table_entry *entry;
548 unsigned int *nip = (unsigned int *)regs->nip;
550 if (((msr & 0xffff0000) == 0 || (msr & (0x80000 | 0x40000)))
551 && (entry = search_exception_tables(regs->nip)) != NULL) {
553 * Check that it's a sync instruction, or somewhere
554 * in the twi; isync; nop sequence that inb/inw/inl uses.
555 * As the address is in the exception table
556 * we should be able to read the instr there.
557 * For the debug message, we look at the preceding
560 if (*nip == PPC_INST_NOP)
562 else if (*nip == PPC_INST_ISYNC)
564 if (*nip == PPC_INST_SYNC || (*nip >> 26) == OP_TRAP) {
568 rb = (*nip >> 11) & 0x1f;
569 printk(KERN_DEBUG "%s bad port %lx at %p\n",
570 (*nip & 0x100)? "OUT to": "IN from",
571 regs->gpr[rb] - _IO_BASE, nip);
573 regs->nip = extable_fixup(entry);
577 #endif /* CONFIG_PPC32 */
581 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
582 /* On 4xx, the reason for the machine check or program exception
584 #define get_reason(regs) ((regs)->dsisr)
585 #define REASON_FP ESR_FP
586 #define REASON_ILLEGAL (ESR_PIL | ESR_PUO)
587 #define REASON_PRIVILEGED ESR_PPR
588 #define REASON_TRAP ESR_PTR
590 /* single-step stuff */
591 #define single_stepping(regs) (current->thread.debug.dbcr0 & DBCR0_IC)
592 #define clear_single_step(regs) (current->thread.debug.dbcr0 &= ~DBCR0_IC)
593 #define clear_br_trace(regs) do {} while(0)
595 /* On non-4xx, the reason for the machine check or program
596 exception is in the MSR. */
597 #define get_reason(regs) ((regs)->msr)
598 #define REASON_TM SRR1_PROGTM
599 #define REASON_FP SRR1_PROGFPE
600 #define REASON_ILLEGAL SRR1_PROGILL
601 #define REASON_PRIVILEGED SRR1_PROGPRIV
602 #define REASON_TRAP SRR1_PROGTRAP
604 #define single_stepping(regs) ((regs)->msr & MSR_SE)
605 #define clear_single_step(regs) ((regs)->msr &= ~MSR_SE)
606 #define clear_br_trace(regs) ((regs)->msr &= ~MSR_BE)
609 #if defined(CONFIG_E500)
610 int machine_check_e500mc(struct pt_regs *regs)
612 unsigned long mcsr = mfspr(SPRN_MCSR);
613 unsigned long pvr = mfspr(SPRN_PVR);
614 unsigned long reason = mcsr;
617 if (reason & MCSR_LD) {
618 recoverable = fsl_rio_mcheck_exception(regs);
619 if (recoverable == 1)
623 printk("Machine check in kernel mode.\n");
624 printk("Caused by (from MCSR=%lx): ", reason);
626 if (reason & MCSR_MCP)
627 pr_cont("Machine Check Signal\n");
629 if (reason & MCSR_ICPERR) {
630 pr_cont("Instruction Cache Parity Error\n");
633 * This is recoverable by invalidating the i-cache.
635 mtspr(SPRN_L1CSR1, mfspr(SPRN_L1CSR1) | L1CSR1_ICFI);
636 while (mfspr(SPRN_L1CSR1) & L1CSR1_ICFI)
640 * This will generally be accompanied by an instruction
641 * fetch error report -- only treat MCSR_IF as fatal
642 * if it wasn't due to an L1 parity error.
647 if (reason & MCSR_DCPERR_MC) {
648 pr_cont("Data Cache Parity Error\n");
651 * In write shadow mode we auto-recover from the error, but it
652 * may still get logged and cause a machine check. We should
653 * only treat the non-write shadow case as non-recoverable.
655 /* On e6500 core, L1 DCWS (Data cache write shadow mode) bit
656 * is not implemented but L1 data cache always runs in write
657 * shadow mode. Hence on data cache parity errors HW will
658 * automatically invalidate the L1 Data Cache.
660 if (PVR_VER(pvr) != PVR_VER_E6500) {
661 if (!(mfspr(SPRN_L1CSR2) & L1CSR2_DCWS))
666 if (reason & MCSR_L2MMU_MHIT) {
667 pr_cont("Hit on multiple TLB entries\n");
671 if (reason & MCSR_NMI)
672 pr_cont("Non-maskable interrupt\n");
674 if (reason & MCSR_IF) {
675 pr_cont("Instruction Fetch Error Report\n");
679 if (reason & MCSR_LD) {
680 pr_cont("Load Error Report\n");
684 if (reason & MCSR_ST) {
685 pr_cont("Store Error Report\n");
689 if (reason & MCSR_LDG) {
690 pr_cont("Guarded Load Error Report\n");
694 if (reason & MCSR_TLBSYNC)
695 pr_cont("Simultaneous tlbsync operations\n");
697 if (reason & MCSR_BSL2_ERR) {
698 pr_cont("Level 2 Cache Error\n");
702 if (reason & MCSR_MAV) {
705 addr = mfspr(SPRN_MCAR);
706 addr |= (u64)mfspr(SPRN_MCARU) << 32;
708 pr_cont("Machine Check %s Address: %#llx\n",
709 reason & MCSR_MEA ? "Effective" : "Physical", addr);
713 mtspr(SPRN_MCSR, mcsr);
714 return mfspr(SPRN_MCSR) == 0 && recoverable;
717 int machine_check_e500(struct pt_regs *regs)
719 unsigned long reason = mfspr(SPRN_MCSR);
721 if (reason & MCSR_BUS_RBERR) {
722 if (fsl_rio_mcheck_exception(regs))
724 if (fsl_pci_mcheck_exception(regs))
728 printk("Machine check in kernel mode.\n");
729 printk("Caused by (from MCSR=%lx): ", reason);
731 if (reason & MCSR_MCP)
732 pr_cont("Machine Check Signal\n");
733 if (reason & MCSR_ICPERR)
734 pr_cont("Instruction Cache Parity Error\n");
735 if (reason & MCSR_DCP_PERR)
736 pr_cont("Data Cache Push Parity Error\n");
737 if (reason & MCSR_DCPERR)
738 pr_cont("Data Cache Parity Error\n");
739 if (reason & MCSR_BUS_IAERR)
740 pr_cont("Bus - Instruction Address Error\n");
741 if (reason & MCSR_BUS_RAERR)
742 pr_cont("Bus - Read Address Error\n");
743 if (reason & MCSR_BUS_WAERR)
744 pr_cont("Bus - Write Address Error\n");
745 if (reason & MCSR_BUS_IBERR)
746 pr_cont("Bus - Instruction Data Error\n");
747 if (reason & MCSR_BUS_RBERR)
748 pr_cont("Bus - Read Data Bus Error\n");
749 if (reason & MCSR_BUS_WBERR)
750 pr_cont("Bus - Write Data Bus Error\n");
751 if (reason & MCSR_BUS_IPERR)
752 pr_cont("Bus - Instruction Parity Error\n");
753 if (reason & MCSR_BUS_RPERR)
754 pr_cont("Bus - Read Parity Error\n");
759 int machine_check_generic(struct pt_regs *regs)
763 #elif defined(CONFIG_E200)
764 int machine_check_e200(struct pt_regs *regs)
766 unsigned long reason = mfspr(SPRN_MCSR);
768 printk("Machine check in kernel mode.\n");
769 printk("Caused by (from MCSR=%lx): ", reason);
771 if (reason & MCSR_MCP)
772 pr_cont("Machine Check Signal\n");
773 if (reason & MCSR_CP_PERR)
774 pr_cont("Cache Push Parity Error\n");
775 if (reason & MCSR_CPERR)
776 pr_cont("Cache Parity Error\n");
777 if (reason & MCSR_EXCP_ERR)
778 pr_cont("ISI, ITLB, or Bus Error on first instruction fetch for an exception handler\n");
779 if (reason & MCSR_BUS_IRERR)
780 pr_cont("Bus - Read Bus Error on instruction fetch\n");
781 if (reason & MCSR_BUS_DRERR)
782 pr_cont("Bus - Read Bus Error on data load\n");
783 if (reason & MCSR_BUS_WRERR)
784 pr_cont("Bus - Write Bus Error on buffered store or cache line push\n");
788 #elif defined(CONFIG_PPC32)
789 int machine_check_generic(struct pt_regs *regs)
791 unsigned long reason = regs->msr;
793 printk("Machine check in kernel mode.\n");
794 printk("Caused by (from SRR1=%lx): ", reason);
795 switch (reason & 0x601F0000) {
797 pr_cont("Machine check signal\n");
799 case 0: /* for 601 */
801 case 0x140000: /* 7450 MSS error and TEA */
802 pr_cont("Transfer error ack signal\n");
805 pr_cont("Data parity error signal\n");
808 pr_cont("Address parity error signal\n");
811 pr_cont("L1 Data Cache error\n");
814 pr_cont("L1 Instruction Cache error\n");
817 pr_cont("L2 data cache parity error\n");
820 pr_cont("Unknown values in msr\n");
824 #endif /* everything else */
826 void machine_check_exception(struct pt_regs *regs)
829 bool nested = in_nmi();
833 __this_cpu_inc(irq_stat.mce_exceptions);
835 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_NOW_UNRELIABLE);
837 /* See if any machine dependent calls. In theory, we would want
838 * to call the CPU first, and call the ppc_md. one if the CPU
839 * one returns a positive number. However there is existing code
840 * that assumes the board gets a first chance, so let's keep it
841 * that way for now and fix things later. --BenH.
843 if (ppc_md.machine_check_exception)
844 recover = ppc_md.machine_check_exception(regs);
845 else if (cur_cpu_spec->machine_check)
846 recover = cur_cpu_spec->machine_check(regs);
851 if (debugger_fault_handler(regs))
854 if (check_io_access(regs))
860 die("Machine check", regs, SIGBUS);
862 /* Must die if the interrupt is not recoverable */
863 if (!(regs->msr & MSR_RI))
864 die("Unrecoverable Machine check", regs, SIGBUS);
873 void SMIException(struct pt_regs *regs)
875 die("System Management Interrupt", regs, SIGABRT);
879 static void p9_hmi_special_emu(struct pt_regs *regs)
881 unsigned int ra, rb, t, i, sel, instr, rc;
882 const void __user *addr;
883 u8 vbuf[16] __aligned(16), *vdst;
884 unsigned long ea, msr, msr_mask;
887 if (__get_user_inatomic(instr, (unsigned int __user *)regs->nip))
891 * lxvb16x opcode: 0x7c0006d8
892 * lxvd2x opcode: 0x7c000698
893 * lxvh8x opcode: 0x7c000658
894 * lxvw4x opcode: 0x7c000618
896 if ((instr & 0xfc00073e) != 0x7c000618) {
897 pr_devel("HMI vec emu: not vector CI %i:%s[%d] nip=%016lx"
899 smp_processor_id(), current->comm, current->pid,
904 /* Grab vector registers into the task struct */
905 msr = regs->msr; /* Grab msr before we flush the bits */
906 flush_vsx_to_thread(current);
907 enable_kernel_altivec();
910 * Is userspace running with a different endian (this is rare but
913 swap = (msr & MSR_LE) != (MSR_KERNEL & MSR_LE);
915 /* Decode the instruction */
916 ra = (instr >> 16) & 0x1f;
917 rb = (instr >> 11) & 0x1f;
918 t = (instr >> 21) & 0x1f;
920 vdst = (u8 *)¤t->thread.vr_state.vr[t];
922 vdst = (u8 *)¤t->thread.fp_state.fpr[t][0];
924 /* Grab the vector address */
925 ea = regs->gpr[rb] + (ra ? regs->gpr[ra] : 0);
928 addr = (__force const void __user *)ea;
931 if (!access_ok(addr, 16)) {
932 pr_devel("HMI vec emu: bad access %i:%s[%d] nip=%016lx"
933 " instr=%08x addr=%016lx\n",
934 smp_processor_id(), current->comm, current->pid,
935 regs->nip, instr, (unsigned long)addr);
939 /* Read the vector */
941 if ((unsigned long)addr & 0xfUL)
943 rc = __copy_from_user_inatomic(vbuf, addr, 16);
945 __get_user_atomic_128_aligned(vbuf, addr, rc);
947 pr_devel("HMI vec emu: page fault %i:%s[%d] nip=%016lx"
948 " instr=%08x addr=%016lx\n",
949 smp_processor_id(), current->comm, current->pid,
950 regs->nip, instr, (unsigned long)addr);
954 pr_devel("HMI vec emu: emulated vector CI %i:%s[%d] nip=%016lx"
955 " instr=%08x addr=%016lx\n",
956 smp_processor_id(), current->comm, current->pid, regs->nip,
957 instr, (unsigned long) addr);
959 /* Grab instruction "selector" */
960 sel = (instr >> 6) & 3;
963 * Check to make sure the facility is actually enabled. This
964 * could happen if we get a false positive hit.
966 * lxvd2x/lxvw4x always check MSR VSX sel = 0,2
967 * lxvh8x/lxvb16x check MSR VSX or VEC depending on VSR used sel = 1,3
970 if ((sel & 1) && (instr & 1)) /* lxvh8x & lxvb16x + VSR >= 32 */
972 if (!(msr & msr_mask)) {
973 pr_devel("HMI vec emu: MSR fac clear %i:%s[%d] nip=%016lx"
974 " instr=%08x msr:%016lx\n",
975 smp_processor_id(), current->comm, current->pid,
976 regs->nip, instr, msr);
980 /* Do logging here before we modify sel based on endian */
983 PPC_WARN_EMULATED(lxvw4x, regs);
986 PPC_WARN_EMULATED(lxvh8x, regs);
989 PPC_WARN_EMULATED(lxvd2x, regs);
991 case 3: /* lxvb16x */
992 PPC_WARN_EMULATED(lxvb16x, regs);
996 #ifdef __LITTLE_ENDIAN__
998 * An LE kernel stores the vector in the task struct as an LE
999 * byte array (effectively swapping both the components and
1000 * the content of the components). Those instructions expect
1001 * the components to remain in ascending address order, so we
1004 * If we are running a BE user space, the expectation is that
1005 * of a simple memcpy, so forcing the emulation to look like
1006 * a lxvb16x should do the trick.
1012 case 0: /* lxvw4x */
1013 for (i = 0; i < 4; i++)
1014 ((u32 *)vdst)[i] = ((u32 *)vbuf)[3-i];
1016 case 1: /* lxvh8x */
1017 for (i = 0; i < 8; i++)
1018 ((u16 *)vdst)[i] = ((u16 *)vbuf)[7-i];
1020 case 2: /* lxvd2x */
1021 for (i = 0; i < 2; i++)
1022 ((u64 *)vdst)[i] = ((u64 *)vbuf)[1-i];
1024 case 3: /* lxvb16x */
1025 for (i = 0; i < 16; i++)
1026 vdst[i] = vbuf[15-i];
1029 #else /* __LITTLE_ENDIAN__ */
1030 /* On a big endian kernel, a BE userspace only needs a memcpy */
1034 /* Otherwise, we need to swap the content of the components */
1036 case 0: /* lxvw4x */
1037 for (i = 0; i < 4; i++)
1038 ((u32 *)vdst)[i] = cpu_to_le32(((u32 *)vbuf)[i]);
1040 case 1: /* lxvh8x */
1041 for (i = 0; i < 8; i++)
1042 ((u16 *)vdst)[i] = cpu_to_le16(((u16 *)vbuf)[i]);
1044 case 2: /* lxvd2x */
1045 for (i = 0; i < 2; i++)
1046 ((u64 *)vdst)[i] = cpu_to_le64(((u64 *)vbuf)[i]);
1048 case 3: /* lxvb16x */
1049 memcpy(vdst, vbuf, 16);
1052 #endif /* !__LITTLE_ENDIAN__ */
1054 /* Go to next instruction */
1057 #endif /* CONFIG_VSX */
1059 void handle_hmi_exception(struct pt_regs *regs)
1061 struct pt_regs *old_regs;
1063 old_regs = set_irq_regs(regs);
1067 /* Real mode flagged P9 special emu is needed */
1068 if (local_paca->hmi_p9_special_emu) {
1069 local_paca->hmi_p9_special_emu = 0;
1072 * We don't want to take page faults while doing the
1073 * emulation, we just replay the instruction if necessary.
1075 pagefault_disable();
1076 p9_hmi_special_emu(regs);
1079 #endif /* CONFIG_VSX */
1081 if (ppc_md.handle_hmi_exception)
1082 ppc_md.handle_hmi_exception(regs);
1085 set_irq_regs(old_regs);
1088 void unknown_exception(struct pt_regs *regs)
1090 enum ctx_state prev_state = exception_enter();
1092 printk("Bad trap at PC: %lx, SR: %lx, vector=%lx\n",
1093 regs->nip, regs->msr, regs->trap);
1095 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1097 exception_exit(prev_state);
1100 void instruction_breakpoint_exception(struct pt_regs *regs)
1102 enum ctx_state prev_state = exception_enter();
1104 if (notify_die(DIE_IABR_MATCH, "iabr_match", regs, 5,
1105 5, SIGTRAP) == NOTIFY_STOP)
1107 if (debugger_iabr_match(regs))
1109 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1112 exception_exit(prev_state);
1115 void RunModeException(struct pt_regs *regs)
1117 _exception(SIGTRAP, regs, TRAP_UNK, 0);
1120 void single_step_exception(struct pt_regs *regs)
1122 enum ctx_state prev_state = exception_enter();
1124 clear_single_step(regs);
1125 clear_br_trace(regs);
1127 if (kprobe_post_handler(regs))
1130 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
1131 5, SIGTRAP) == NOTIFY_STOP)
1133 if (debugger_sstep(regs))
1136 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
1139 exception_exit(prev_state);
1141 NOKPROBE_SYMBOL(single_step_exception);
1144 * After we have successfully emulated an instruction, we have to
1145 * check if the instruction was being single-stepped, and if so,
1146 * pretend we got a single-step exception. This was pointed out
1147 * by Kumar Gala. -- paulus
1149 static void emulate_single_step(struct pt_regs *regs)
1151 if (single_stepping(regs))
1152 single_step_exception(regs);
1155 static inline int __parse_fpscr(unsigned long fpscr)
1157 int ret = FPE_FLTUNK;
1159 /* Invalid operation */
1160 if ((fpscr & FPSCR_VE) && (fpscr & FPSCR_VX))
1164 else if ((fpscr & FPSCR_OE) && (fpscr & FPSCR_OX))
1168 else if ((fpscr & FPSCR_UE) && (fpscr & FPSCR_UX))
1171 /* Divide by zero */
1172 else if ((fpscr & FPSCR_ZE) && (fpscr & FPSCR_ZX))
1175 /* Inexact result */
1176 else if ((fpscr & FPSCR_XE) && (fpscr & FPSCR_XX))
1182 static void parse_fpe(struct pt_regs *regs)
1186 flush_fp_to_thread(current);
1188 code = __parse_fpscr(current->thread.fp_state.fpscr);
1190 _exception(SIGFPE, regs, code, regs->nip);
1194 * Illegal instruction emulation support. Originally written to
1195 * provide the PVR to user applications using the mfspr rd, PVR.
1196 * Return non-zero if we can't emulate, or -EFAULT if the associated
1197 * memory access caused an access fault. Return zero on success.
1199 * There are a couple of ways to do this, either "decode" the instruction
1200 * or directly match lots of bits. In this case, matching lots of
1201 * bits is faster and easier.
1204 static int emulate_string_inst(struct pt_regs *regs, u32 instword)
1206 u8 rT = (instword >> 21) & 0x1f;
1207 u8 rA = (instword >> 16) & 0x1f;
1208 u8 NB_RB = (instword >> 11) & 0x1f;
1213 /* Early out if we are an invalid form of lswx */
1214 if ((instword & PPC_INST_STRING_MASK) == PPC_INST_LSWX)
1215 if ((rT == rA) || (rT == NB_RB))
1218 EA = (rA == 0) ? 0 : regs->gpr[rA];
1220 switch (instword & PPC_INST_STRING_MASK) {
1222 case PPC_INST_STSWX:
1224 num_bytes = regs->xer & 0x7f;
1227 case PPC_INST_STSWI:
1228 num_bytes = (NB_RB == 0) ? 32 : NB_RB;
1234 while (num_bytes != 0)
1237 u32 shift = 8 * (3 - (pos & 0x3));
1239 /* if process is 32-bit, clear upper 32 bits of EA */
1240 if ((regs->msr & MSR_64BIT) == 0)
1243 switch ((instword & PPC_INST_STRING_MASK)) {
1246 if (get_user(val, (u8 __user *)EA))
1248 /* first time updating this reg,
1252 regs->gpr[rT] |= val << shift;
1254 case PPC_INST_STSWI:
1255 case PPC_INST_STSWX:
1256 val = regs->gpr[rT] >> shift;
1257 if (put_user(val, (u8 __user *)EA))
1261 /* move EA to next address */
1265 /* manage our position within the register */
1276 static int emulate_popcntb_inst(struct pt_regs *regs, u32 instword)
1281 ra = (instword >> 16) & 0x1f;
1282 rs = (instword >> 21) & 0x1f;
1284 tmp = regs->gpr[rs];
1285 tmp = tmp - ((tmp >> 1) & 0x5555555555555555ULL);
1286 tmp = (tmp & 0x3333333333333333ULL) + ((tmp >> 2) & 0x3333333333333333ULL);
1287 tmp = (tmp + (tmp >> 4)) & 0x0f0f0f0f0f0f0f0fULL;
1288 regs->gpr[ra] = tmp;
1293 static int emulate_isel(struct pt_regs *regs, u32 instword)
1295 u8 rT = (instword >> 21) & 0x1f;
1296 u8 rA = (instword >> 16) & 0x1f;
1297 u8 rB = (instword >> 11) & 0x1f;
1298 u8 BC = (instword >> 6) & 0x1f;
1302 tmp = (rA == 0) ? 0 : regs->gpr[rA];
1303 bit = (regs->ccr >> (31 - BC)) & 0x1;
1305 regs->gpr[rT] = bit ? tmp : regs->gpr[rB];
1310 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1311 static inline bool tm_abort_check(struct pt_regs *regs, int cause)
1313 /* If we're emulating a load/store in an active transaction, we cannot
1314 * emulate it as the kernel operates in transaction suspended context.
1315 * We need to abort the transaction. This creates a persistent TM
1316 * abort so tell the user what caused it with a new code.
1318 if (MSR_TM_TRANSACTIONAL(regs->msr)) {
1326 static inline bool tm_abort_check(struct pt_regs *regs, int reason)
1332 static int emulate_instruction(struct pt_regs *regs)
1337 if (!user_mode(regs))
1339 CHECK_FULL_REGS(regs);
1341 if (get_user(instword, (u32 __user *)(regs->nip)))
1344 /* Emulate the mfspr rD, PVR. */
1345 if ((instword & PPC_INST_MFSPR_PVR_MASK) == PPC_INST_MFSPR_PVR) {
1346 PPC_WARN_EMULATED(mfpvr, regs);
1347 rd = (instword >> 21) & 0x1f;
1348 regs->gpr[rd] = mfspr(SPRN_PVR);
1352 /* Emulating the dcba insn is just a no-op. */
1353 if ((instword & PPC_INST_DCBA_MASK) == PPC_INST_DCBA) {
1354 PPC_WARN_EMULATED(dcba, regs);
1358 /* Emulate the mcrxr insn. */
1359 if ((instword & PPC_INST_MCRXR_MASK) == PPC_INST_MCRXR) {
1360 int shift = (instword >> 21) & 0x1c;
1361 unsigned long msk = 0xf0000000UL >> shift;
1363 PPC_WARN_EMULATED(mcrxr, regs);
1364 regs->ccr = (regs->ccr & ~msk) | ((regs->xer >> shift) & msk);
1365 regs->xer &= ~0xf0000000UL;
1369 /* Emulate load/store string insn. */
1370 if ((instword & PPC_INST_STRING_GEN_MASK) == PPC_INST_STRING) {
1371 if (tm_abort_check(regs,
1372 TM_CAUSE_EMULATE | TM_CAUSE_PERSISTENT))
1374 PPC_WARN_EMULATED(string, regs);
1375 return emulate_string_inst(regs, instword);
1378 /* Emulate the popcntb (Population Count Bytes) instruction. */
1379 if ((instword & PPC_INST_POPCNTB_MASK) == PPC_INST_POPCNTB) {
1380 PPC_WARN_EMULATED(popcntb, regs);
1381 return emulate_popcntb_inst(regs, instword);
1384 /* Emulate isel (Integer Select) instruction */
1385 if ((instword & PPC_INST_ISEL_MASK) == PPC_INST_ISEL) {
1386 PPC_WARN_EMULATED(isel, regs);
1387 return emulate_isel(regs, instword);
1390 /* Emulate sync instruction variants */
1391 if ((instword & PPC_INST_SYNC_MASK) == PPC_INST_SYNC) {
1392 PPC_WARN_EMULATED(sync, regs);
1393 asm volatile("sync");
1398 /* Emulate the mfspr rD, DSCR. */
1399 if ((((instword & PPC_INST_MFSPR_DSCR_USER_MASK) ==
1400 PPC_INST_MFSPR_DSCR_USER) ||
1401 ((instword & PPC_INST_MFSPR_DSCR_MASK) ==
1402 PPC_INST_MFSPR_DSCR)) &&
1403 cpu_has_feature(CPU_FTR_DSCR)) {
1404 PPC_WARN_EMULATED(mfdscr, regs);
1405 rd = (instword >> 21) & 0x1f;
1406 regs->gpr[rd] = mfspr(SPRN_DSCR);
1409 /* Emulate the mtspr DSCR, rD. */
1410 if ((((instword & PPC_INST_MTSPR_DSCR_USER_MASK) ==
1411 PPC_INST_MTSPR_DSCR_USER) ||
1412 ((instword & PPC_INST_MTSPR_DSCR_MASK) ==
1413 PPC_INST_MTSPR_DSCR)) &&
1414 cpu_has_feature(CPU_FTR_DSCR)) {
1415 PPC_WARN_EMULATED(mtdscr, regs);
1416 rd = (instword >> 21) & 0x1f;
1417 current->thread.dscr = regs->gpr[rd];
1418 current->thread.dscr_inherit = 1;
1419 mtspr(SPRN_DSCR, current->thread.dscr);
1427 #ifdef CONFIG_GENERIC_BUG
1428 int is_valid_bugaddr(unsigned long addr)
1430 return is_kernel_addr(addr);
1434 #ifdef CONFIG_MATH_EMULATION
1435 static int emulate_math(struct pt_regs *regs)
1438 extern int do_mathemu(struct pt_regs *regs);
1440 ret = do_mathemu(regs);
1442 PPC_WARN_EMULATED(math, regs);
1446 emulate_single_step(regs);
1450 code = __parse_fpscr(current->thread.fp_state.fpscr);
1451 _exception(SIGFPE, regs, code, regs->nip);
1455 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1462 static inline int emulate_math(struct pt_regs *regs) { return -1; }
1465 void program_check_exception(struct pt_regs *regs)
1467 enum ctx_state prev_state = exception_enter();
1468 unsigned int reason = get_reason(regs);
1470 /* We can now get here via a FP Unavailable exception if the core
1471 * has no FPU, in that case the reason flags will be 0 */
1473 if (reason & REASON_FP) {
1474 /* IEEE FP exception */
1478 if (reason & REASON_TRAP) {
1479 unsigned long bugaddr;
1480 /* Debugger is first in line to stop recursive faults in
1481 * rcu_lock, notify_die, or atomic_notifier_call_chain */
1482 if (debugger_bpt(regs))
1485 if (kprobe_handler(regs))
1488 /* trap exception */
1489 if (notify_die(DIE_BPT, "breakpoint", regs, 5, 5, SIGTRAP)
1493 bugaddr = regs->nip;
1495 * Fixup bugaddr for BUG_ON() in real mode
1497 if (!is_kernel_addr(bugaddr) && !(regs->msr & MSR_IR))
1498 bugaddr += PAGE_OFFSET;
1500 if (!(regs->msr & MSR_PR) && /* not user-mode */
1501 report_bug(bugaddr, regs) == BUG_TRAP_TYPE_WARN) {
1505 _exception(SIGTRAP, regs, TRAP_BRKPT, regs->nip);
1508 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1509 if (reason & REASON_TM) {
1510 /* This is a TM "Bad Thing Exception" program check.
1512 * - An rfid/hrfid/mtmsrd attempts to cause an illegal
1513 * transition in TM states.
1514 * - A trechkpt is attempted when transactional.
1515 * - A treclaim is attempted when non transactional.
1516 * - A tend is illegally attempted.
1517 * - writing a TM SPR when transactional.
1519 * If usermode caused this, it's done something illegal and
1520 * gets a SIGILL slap on the wrist. We call it an illegal
1521 * operand to distinguish from the instruction just being bad
1522 * (e.g. executing a 'tend' on a CPU without TM!); it's an
1523 * illegal /placement/ of a valid instruction.
1525 if (user_mode(regs)) {
1526 _exception(SIGILL, regs, ILL_ILLOPN, regs->nip);
1529 printk(KERN_EMERG "Unexpected TM Bad Thing exception "
1530 "at %lx (msr 0x%lx) tm_scratch=%llx\n",
1531 regs->nip, regs->msr, get_paca()->tm_scratch);
1532 die("Unrecoverable exception", regs, SIGABRT);
1538 * If we took the program check in the kernel skip down to sending a
1539 * SIGILL. The subsequent cases all relate to emulating instructions
1540 * which we should only do for userspace. We also do not want to enable
1541 * interrupts for kernel faults because that might lead to further
1542 * faults, and loose the context of the original exception.
1544 if (!user_mode(regs))
1547 /* We restore the interrupt state now */
1548 if (!arch_irq_disabled_regs(regs))
1551 /* (reason & REASON_ILLEGAL) would be the obvious thing here,
1552 * but there seems to be a hardware bug on the 405GP (RevD)
1553 * that means ESR is sometimes set incorrectly - either to
1554 * ESR_DST (!?) or 0. In the process of chasing this with the
1555 * hardware people - not sure if it can happen on any illegal
1556 * instruction or only on FP instructions, whether there is a
1557 * pattern to occurrences etc. -dgibson 31/Mar/2003
1559 if (!emulate_math(regs))
1562 /* Try to emulate it if we should. */
1563 if (reason & (REASON_ILLEGAL | REASON_PRIVILEGED)) {
1564 switch (emulate_instruction(regs)) {
1567 emulate_single_step(regs);
1570 _exception(SIGSEGV, regs, SEGV_MAPERR, regs->nip);
1576 if (reason & REASON_PRIVILEGED)
1577 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
1579 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1582 exception_exit(prev_state);
1584 NOKPROBE_SYMBOL(program_check_exception);
1587 * This occurs when running in hypervisor mode on POWER6 or later
1588 * and an illegal instruction is encountered.
1590 void emulation_assist_interrupt(struct pt_regs *regs)
1592 regs->msr |= REASON_ILLEGAL;
1593 program_check_exception(regs);
1595 NOKPROBE_SYMBOL(emulation_assist_interrupt);
1597 void alignment_exception(struct pt_regs *regs)
1599 enum ctx_state prev_state = exception_enter();
1600 int sig, code, fixed = 0;
1602 /* We restore the interrupt state now */
1603 if (!arch_irq_disabled_regs(regs))
1606 if (tm_abort_check(regs, TM_CAUSE_ALIGNMENT | TM_CAUSE_PERSISTENT))
1609 /* we don't implement logging of alignment exceptions */
1610 if (!(current->thread.align_ctl & PR_UNALIGN_SIGBUS))
1611 fixed = fix_alignment(regs);
1614 regs->nip += 4; /* skip over emulated instruction */
1615 emulate_single_step(regs);
1619 /* Operand address was bad */
1620 if (fixed == -EFAULT) {
1627 if (user_mode(regs))
1628 _exception(sig, regs, code, regs->dar);
1630 bad_page_fault(regs, regs->dar, sig);
1633 exception_exit(prev_state);
1636 void StackOverflow(struct pt_regs *regs)
1638 pr_crit("Kernel stack overflow in process %s[%d], r1=%lx\n",
1639 current->comm, task_pid_nr(current), regs->gpr[1]);
1642 panic("kernel stack overflow");
1645 void kernel_fp_unavailable_exception(struct pt_regs *regs)
1647 enum ctx_state prev_state = exception_enter();
1649 printk(KERN_EMERG "Unrecoverable FP Unavailable Exception "
1650 "%lx at %lx\n", regs->trap, regs->nip);
1651 die("Unrecoverable FP Unavailable Exception", regs, SIGABRT);
1653 exception_exit(prev_state);
1656 void altivec_unavailable_exception(struct pt_regs *regs)
1658 enum ctx_state prev_state = exception_enter();
1660 if (user_mode(regs)) {
1661 /* A user program has executed an altivec instruction,
1662 but this kernel doesn't support altivec. */
1663 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1667 printk(KERN_EMERG "Unrecoverable VMX/Altivec Unavailable Exception "
1668 "%lx at %lx\n", regs->trap, regs->nip);
1669 die("Unrecoverable VMX/Altivec Unavailable Exception", regs, SIGABRT);
1672 exception_exit(prev_state);
1675 void vsx_unavailable_exception(struct pt_regs *regs)
1677 if (user_mode(regs)) {
1678 /* A user program has executed an vsx instruction,
1679 but this kernel doesn't support vsx. */
1680 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1684 printk(KERN_EMERG "Unrecoverable VSX Unavailable Exception "
1685 "%lx at %lx\n", regs->trap, regs->nip);
1686 die("Unrecoverable VSX Unavailable Exception", regs, SIGABRT);
1690 static void tm_unavailable(struct pt_regs *regs)
1692 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1693 if (user_mode(regs)) {
1694 current->thread.load_tm++;
1695 regs->msr |= MSR_TM;
1697 tm_restore_sprs(¤t->thread);
1701 pr_emerg("Unrecoverable TM Unavailable Exception "
1702 "%lx at %lx\n", regs->trap, regs->nip);
1703 die("Unrecoverable TM Unavailable Exception", regs, SIGABRT);
1706 void facility_unavailable_exception(struct pt_regs *regs)
1708 static char *facility_strings[] = {
1709 [FSCR_FP_LG] = "FPU",
1710 [FSCR_VECVSX_LG] = "VMX/VSX",
1711 [FSCR_DSCR_LG] = "DSCR",
1712 [FSCR_PM_LG] = "PMU SPRs",
1713 [FSCR_BHRB_LG] = "BHRB",
1714 [FSCR_TM_LG] = "TM",
1715 [FSCR_EBB_LG] = "EBB",
1716 [FSCR_TAR_LG] = "TAR",
1717 [FSCR_MSGP_LG] = "MSGP",
1718 [FSCR_SCV_LG] = "SCV",
1720 char *facility = "unknown";
1726 hv = (TRAP(regs) == 0xf80);
1728 value = mfspr(SPRN_HFSCR);
1730 value = mfspr(SPRN_FSCR);
1732 status = value >> 56;
1733 if ((hv || status >= 2) &&
1734 (status < ARRAY_SIZE(facility_strings)) &&
1735 facility_strings[status])
1736 facility = facility_strings[status];
1738 /* We should not have taken this interrupt in kernel */
1739 if (!user_mode(regs)) {
1740 pr_emerg("Facility '%s' unavailable (%d) exception in kernel mode at %lx\n",
1741 facility, status, regs->nip);
1742 die("Unexpected facility unavailable exception", regs, SIGABRT);
1745 /* We restore the interrupt state now */
1746 if (!arch_irq_disabled_regs(regs))
1749 if (status == FSCR_DSCR_LG) {
1751 * User is accessing the DSCR register using the problem
1752 * state only SPR number (0x03) either through a mfspr or
1753 * a mtspr instruction. If it is a write attempt through
1754 * a mtspr, then we set the inherit bit. This also allows
1755 * the user to write or read the register directly in the
1756 * future by setting via the FSCR DSCR bit. But in case it
1757 * is a read DSCR attempt through a mfspr instruction, we
1758 * just emulate the instruction instead. This code path will
1759 * always emulate all the mfspr instructions till the user
1760 * has attempted at least one mtspr instruction. This way it
1761 * preserves the same behaviour when the user is accessing
1762 * the DSCR through privilege level only SPR number (0x11)
1763 * which is emulated through illegal instruction exception.
1764 * We always leave HFSCR DSCR set.
1766 if (get_user(instword, (u32 __user *)(regs->nip))) {
1767 pr_err("Failed to fetch the user instruction\n");
1771 /* Write into DSCR (mtspr 0x03, RS) */
1772 if ((instword & PPC_INST_MTSPR_DSCR_USER_MASK)
1773 == PPC_INST_MTSPR_DSCR_USER) {
1774 rd = (instword >> 21) & 0x1f;
1775 current->thread.dscr = regs->gpr[rd];
1776 current->thread.dscr_inherit = 1;
1777 current->thread.fscr |= FSCR_DSCR;
1778 mtspr(SPRN_FSCR, current->thread.fscr);
1781 /* Read from DSCR (mfspr RT, 0x03) */
1782 if ((instword & PPC_INST_MFSPR_DSCR_USER_MASK)
1783 == PPC_INST_MFSPR_DSCR_USER) {
1784 if (emulate_instruction(regs)) {
1785 pr_err("DSCR based mfspr emulation failed\n");
1789 emulate_single_step(regs);
1794 if (status == FSCR_TM_LG) {
1796 * If we're here then the hardware is TM aware because it
1797 * generated an exception with FSRM_TM set.
1799 * If cpu_has_feature(CPU_FTR_TM) is false, then either firmware
1800 * told us not to do TM, or the kernel is not built with TM
1803 * If both of those things are true, then userspace can spam the
1804 * console by triggering the printk() below just by continually
1805 * doing tbegin (or any TM instruction). So in that case just
1806 * send the process a SIGILL immediately.
1808 if (!cpu_has_feature(CPU_FTR_TM))
1811 tm_unavailable(regs);
1815 pr_err_ratelimited("%sFacility '%s' unavailable (%d), exception at 0x%lx, MSR=%lx\n",
1816 hv ? "Hypervisor " : "", facility, status, regs->nip, regs->msr);
1819 _exception(SIGILL, regs, ILL_ILLOPC, regs->nip);
1823 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1825 void fp_unavailable_tm(struct pt_regs *regs)
1827 /* Note: This does not handle any kind of FP laziness. */
1829 TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
1830 regs->nip, regs->msr);
1832 /* We can only have got here if the task started using FP after
1833 * beginning the transaction. So, the transactional regs are just a
1834 * copy of the checkpointed ones. But, we still need to recheckpoint
1835 * as we're enabling FP for the process; it will return, abort the
1836 * transaction, and probably retry but now with FP enabled. So the
1837 * checkpointed FP registers need to be loaded.
1839 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1842 * Reclaim initially saved out bogus (lazy) FPRs to ckfp_state, and
1843 * then it was overwrite by the thr->fp_state by tm_reclaim_thread().
1845 * At this point, ck{fp,vr}_state contains the exact values we want to
1849 /* Enable FP for the task: */
1850 current->thread.load_fp = 1;
1853 * Recheckpoint all the checkpointed ckpt, ck{fp, vr}_state registers.
1855 tm_recheckpoint(¤t->thread);
1858 void altivec_unavailable_tm(struct pt_regs *regs)
1860 /* See the comments in fp_unavailable_tm(). This function operates
1864 TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
1866 regs->nip, regs->msr);
1867 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1868 current->thread.load_vec = 1;
1869 tm_recheckpoint(¤t->thread);
1870 current->thread.used_vr = 1;
1873 void vsx_unavailable_tm(struct pt_regs *regs)
1875 /* See the comments in fp_unavailable_tm(). This works similarly,
1876 * though we're loading both FP and VEC registers in here.
1878 * If FP isn't in use, load FP regs. If VEC isn't in use, load VEC
1879 * regs. Either way, set MSR_VSX.
1882 TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
1884 regs->nip, regs->msr);
1886 current->thread.used_vsr = 1;
1888 /* This reclaims FP and/or VR regs if they're already enabled */
1889 tm_reclaim_current(TM_CAUSE_FAC_UNAV);
1891 current->thread.load_vec = 1;
1892 current->thread.load_fp = 1;
1894 tm_recheckpoint(¤t->thread);
1896 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1898 void performance_monitor_exception(struct pt_regs *regs)
1900 __this_cpu_inc(irq_stat.pmu_irqs);
1905 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1906 static void handle_debug(struct pt_regs *regs, unsigned long debug_status)
1910 * Determine the cause of the debug event, clear the
1911 * event flags and send a trap to the handler. Torez
1913 if (debug_status & (DBSR_DAC1R | DBSR_DAC1W)) {
1914 dbcr_dac(current) &= ~(DBCR_DAC1R | DBCR_DAC1W);
1915 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
1916 current->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
1918 do_send_trap(regs, mfspr(SPRN_DAC1), debug_status,
1921 } else if (debug_status & (DBSR_DAC2R | DBSR_DAC2W)) {
1922 dbcr_dac(current) &= ~(DBCR_DAC2R | DBCR_DAC2W);
1923 do_send_trap(regs, mfspr(SPRN_DAC2), debug_status,
1926 } else if (debug_status & DBSR_IAC1) {
1927 current->thread.debug.dbcr0 &= ~DBCR0_IAC1;
1928 dbcr_iac_range(current) &= ~DBCR_IAC12MODE;
1929 do_send_trap(regs, mfspr(SPRN_IAC1), debug_status,
1932 } else if (debug_status & DBSR_IAC2) {
1933 current->thread.debug.dbcr0 &= ~DBCR0_IAC2;
1934 do_send_trap(regs, mfspr(SPRN_IAC2), debug_status,
1937 } else if (debug_status & DBSR_IAC3) {
1938 current->thread.debug.dbcr0 &= ~DBCR0_IAC3;
1939 dbcr_iac_range(current) &= ~DBCR_IAC34MODE;
1940 do_send_trap(regs, mfspr(SPRN_IAC3), debug_status,
1943 } else if (debug_status & DBSR_IAC4) {
1944 current->thread.debug.dbcr0 &= ~DBCR0_IAC4;
1945 do_send_trap(regs, mfspr(SPRN_IAC4), debug_status,
1950 * At the point this routine was called, the MSR(DE) was turned off.
1951 * Check all other debug flags and see if that bit needs to be turned
1954 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
1955 current->thread.debug.dbcr1))
1956 regs->msr |= MSR_DE;
1958 /* Make sure the IDM flag is off */
1959 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
1962 mtspr(SPRN_DBCR0, current->thread.debug.dbcr0);
1965 void DebugException(struct pt_regs *regs, unsigned long debug_status)
1967 current->thread.debug.dbsr = debug_status;
1969 /* Hack alert: On BookE, Branch Taken stops on the branch itself, while
1970 * on server, it stops on the target of the branch. In order to simulate
1971 * the server behaviour, we thus restart right away with a single step
1972 * instead of stopping here when hitting a BT
1974 if (debug_status & DBSR_BT) {
1975 regs->msr &= ~MSR_DE;
1978 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_BT);
1979 /* Clear the BT event */
1980 mtspr(SPRN_DBSR, DBSR_BT);
1982 /* Do the single step trick only when coming from userspace */
1983 if (user_mode(regs)) {
1984 current->thread.debug.dbcr0 &= ~DBCR0_BT;
1985 current->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
1986 regs->msr |= MSR_DE;
1990 if (kprobe_post_handler(regs))
1993 if (notify_die(DIE_SSTEP, "block_step", regs, 5,
1994 5, SIGTRAP) == NOTIFY_STOP) {
1997 if (debugger_sstep(regs))
1999 } else if (debug_status & DBSR_IC) { /* Instruction complete */
2000 regs->msr &= ~MSR_DE;
2002 /* Disable instruction completion */
2003 mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR0_IC);
2004 /* Clear the instruction completion event */
2005 mtspr(SPRN_DBSR, DBSR_IC);
2007 if (kprobe_post_handler(regs))
2010 if (notify_die(DIE_SSTEP, "single_step", regs, 5,
2011 5, SIGTRAP) == NOTIFY_STOP) {
2015 if (debugger_sstep(regs))
2018 if (user_mode(regs)) {
2019 current->thread.debug.dbcr0 &= ~DBCR0_IC;
2020 if (DBCR_ACTIVE_EVENTS(current->thread.debug.dbcr0,
2021 current->thread.debug.dbcr1))
2022 regs->msr |= MSR_DE;
2024 /* Make sure the IDM bit is off */
2025 current->thread.debug.dbcr0 &= ~DBCR0_IDM;
2028 _exception(SIGTRAP, regs, TRAP_TRACE, regs->nip);
2030 handle_debug(regs, debug_status);
2032 NOKPROBE_SYMBOL(DebugException);
2033 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2035 #if !defined(CONFIG_TAU_INT)
2036 void TAUException(struct pt_regs *regs)
2038 printk("TAU trap at PC: %lx, MSR: %lx, vector=%lx %s\n",
2039 regs->nip, regs->msr, regs->trap, print_tainted());
2041 #endif /* CONFIG_INT_TAU */
2043 #ifdef CONFIG_ALTIVEC
2044 void altivec_assist_exception(struct pt_regs *regs)
2048 if (!user_mode(regs)) {
2049 printk(KERN_EMERG "VMX/Altivec assist exception in kernel mode"
2050 " at %lx\n", regs->nip);
2051 die("Kernel VMX/Altivec assist exception", regs, SIGILL);
2054 flush_altivec_to_thread(current);
2056 PPC_WARN_EMULATED(altivec, regs);
2057 err = emulate_altivec(regs);
2059 regs->nip += 4; /* skip emulated instruction */
2060 emulate_single_step(regs);
2064 if (err == -EFAULT) {
2065 /* got an error reading the instruction */
2066 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2068 /* didn't recognize the instruction */
2069 /* XXX quick hack for now: set the non-Java bit in the VSCR */
2070 printk_ratelimited(KERN_ERR "Unrecognized altivec instruction "
2071 "in %s at %lx\n", current->comm, regs->nip);
2072 current->thread.vr_state.vscr.u[3] |= 0x10000;
2075 #endif /* CONFIG_ALTIVEC */
2077 #ifdef CONFIG_FSL_BOOKE
2078 void CacheLockingException(struct pt_regs *regs, unsigned long address,
2079 unsigned long error_code)
2081 /* We treat cache locking instructions from the user
2082 * as priv ops, in the future we could try to do
2085 if (error_code & (ESR_DLK|ESR_ILK))
2086 _exception(SIGILL, regs, ILL_PRVOPC, regs->nip);
2089 #endif /* CONFIG_FSL_BOOKE */
2092 void SPEFloatingPointException(struct pt_regs *regs)
2094 extern int do_spe_mathemu(struct pt_regs *regs);
2095 unsigned long spefscr;
2097 int code = FPE_FLTUNK;
2100 /* We restore the interrupt state now */
2101 if (!arch_irq_disabled_regs(regs))
2104 flush_spe_to_thread(current);
2106 spefscr = current->thread.spefscr;
2107 fpexc_mode = current->thread.fpexc_mode;
2109 if ((spefscr & SPEFSCR_FOVF) && (fpexc_mode & PR_FP_EXC_OVF)) {
2112 else if ((spefscr & SPEFSCR_FUNF) && (fpexc_mode & PR_FP_EXC_UND)) {
2115 else if ((spefscr & SPEFSCR_FDBZ) && (fpexc_mode & PR_FP_EXC_DIV))
2117 else if ((spefscr & SPEFSCR_FINV) && (fpexc_mode & PR_FP_EXC_INV)) {
2120 else if ((spefscr & (SPEFSCR_FG | SPEFSCR_FX)) && (fpexc_mode & PR_FP_EXC_RES))
2123 err = do_spe_mathemu(regs);
2125 regs->nip += 4; /* skip emulated instruction */
2126 emulate_single_step(regs);
2130 if (err == -EFAULT) {
2131 /* got an error reading the instruction */
2132 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2133 } else if (err == -EINVAL) {
2134 /* didn't recognize the instruction */
2135 printk(KERN_ERR "unrecognized spe instruction "
2136 "in %s at %lx\n", current->comm, regs->nip);
2138 _exception(SIGFPE, regs, code, regs->nip);
2144 void SPEFloatingPointRoundException(struct pt_regs *regs)
2146 extern int speround_handler(struct pt_regs *regs);
2149 /* We restore the interrupt state now */
2150 if (!arch_irq_disabled_regs(regs))
2154 if (regs->msr & MSR_SPE)
2155 giveup_spe(current);
2159 err = speround_handler(regs);
2161 regs->nip += 4; /* skip emulated instruction */
2162 emulate_single_step(regs);
2166 if (err == -EFAULT) {
2167 /* got an error reading the instruction */
2168 _exception(SIGSEGV, regs, SEGV_ACCERR, regs->nip);
2169 } else if (err == -EINVAL) {
2170 /* didn't recognize the instruction */
2171 printk(KERN_ERR "unrecognized spe instruction "
2172 "in %s at %lx\n", current->comm, regs->nip);
2174 _exception(SIGFPE, regs, FPE_FLTUNK, regs->nip);
2181 * We enter here if we get an unrecoverable exception, that is, one
2182 * that happened at a point where the RI (recoverable interrupt) bit
2183 * in the MSR is 0. This indicates that SRR0/1 are live, and that
2184 * we therefore lost state by taking this exception.
2186 void unrecoverable_exception(struct pt_regs *regs)
2188 pr_emerg("Unrecoverable exception %lx at %lx (msr=%lx)\n",
2189 regs->trap, regs->nip, regs->msr);
2190 die("Unrecoverable exception", regs, SIGABRT);
2192 NOKPROBE_SYMBOL(unrecoverable_exception);
2194 #if defined(CONFIG_BOOKE_WDT) || defined(CONFIG_40x)
2196 * Default handler for a Watchdog exception,
2197 * spins until a reboot occurs
2199 void __attribute__ ((weak)) WatchdogHandler(struct pt_regs *regs)
2201 /* Generic WatchdogHandler, implement your own */
2202 mtspr(SPRN_TCR, mfspr(SPRN_TCR)&(~TCR_WIE));
2206 void WatchdogException(struct pt_regs *regs)
2208 printk (KERN_EMERG "PowerPC Book-E Watchdog Exception\n");
2209 WatchdogHandler(regs);
2214 * We enter here if we discover during exception entry that we are
2215 * running in supervisor mode with a userspace value in the stack pointer.
2217 void kernel_bad_stack(struct pt_regs *regs)
2219 printk(KERN_EMERG "Bad kernel stack pointer %lx at %lx\n",
2220 regs->gpr[1], regs->nip);
2221 die("Bad kernel stack pointer", regs, SIGABRT);
2223 NOKPROBE_SYMBOL(kernel_bad_stack);
2225 void __init trap_init(void)
2230 #ifdef CONFIG_PPC_EMULATED_STATS
2232 #define WARN_EMULATED_SETUP(type) .type = { .name = #type }
2234 struct ppc_emulated ppc_emulated = {
2235 #ifdef CONFIG_ALTIVEC
2236 WARN_EMULATED_SETUP(altivec),
2238 WARN_EMULATED_SETUP(dcba),
2239 WARN_EMULATED_SETUP(dcbz),
2240 WARN_EMULATED_SETUP(fp_pair),
2241 WARN_EMULATED_SETUP(isel),
2242 WARN_EMULATED_SETUP(mcrxr),
2243 WARN_EMULATED_SETUP(mfpvr),
2244 WARN_EMULATED_SETUP(multiple),
2245 WARN_EMULATED_SETUP(popcntb),
2246 WARN_EMULATED_SETUP(spe),
2247 WARN_EMULATED_SETUP(string),
2248 WARN_EMULATED_SETUP(sync),
2249 WARN_EMULATED_SETUP(unaligned),
2250 #ifdef CONFIG_MATH_EMULATION
2251 WARN_EMULATED_SETUP(math),
2254 WARN_EMULATED_SETUP(vsx),
2257 WARN_EMULATED_SETUP(mfdscr),
2258 WARN_EMULATED_SETUP(mtdscr),
2259 WARN_EMULATED_SETUP(lq_stq),
2260 WARN_EMULATED_SETUP(lxvw4x),
2261 WARN_EMULATED_SETUP(lxvh8x),
2262 WARN_EMULATED_SETUP(lxvd2x),
2263 WARN_EMULATED_SETUP(lxvb16x),
2267 u32 ppc_warn_emulated;
2269 void ppc_warn_emulated_print(const char *type)
2271 pr_warn_ratelimited("%s used emulated %s instruction\n", current->comm,
2275 static int __init ppc_warn_emulated_init(void)
2277 struct dentry *dir, *d;
2279 struct ppc_emulated_entry *entries = (void *)&ppc_emulated;
2281 if (!powerpc_debugfs_root)
2284 dir = debugfs_create_dir("emulated_instructions",
2285 powerpc_debugfs_root);
2289 d = debugfs_create_u32("do_warn", 0644, dir,
2290 &ppc_warn_emulated);
2294 for (i = 0; i < sizeof(ppc_emulated)/sizeof(*entries); i++) {
2295 d = debugfs_create_u32(entries[i].name, 0644, dir,
2296 (u32 *)&entries[i].val.counter);
2304 debugfs_remove_recursive(dir);
2308 device_initcall(ppc_warn_emulated_init);
2310 #endif /* CONFIG_PPC_EMULATED_STATS */