2 * Transactional memory support routines to reclaim and recheckpoint
3 * transactional process state.
5 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
8 #include <asm/asm-offsets.h>
9 #include <asm/ppc_asm.h>
10 #include <asm/ppc-opcode.h>
11 #include <asm/ptrace.h>
16 /* See fpu.S, this is borrowed from there */
17 #define __SAVE_32FPRS_VSRS(n,c,base) \
20 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
21 SAVE_32FPRS(n,base); \
23 2: SAVE_32VSRS(n,c,base); \
25 #define __REST_32FPRS_VSRS(n,c,base) \
28 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
29 REST_32FPRS(n,base); \
31 2: REST_32VSRS(n,c,base); \
34 #define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
35 #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
37 #define SAVE_32FPRS_VSRS(n,c,base) \
38 __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
39 #define REST_32FPRS_VSRS(n,c,base) \
40 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
42 /* Stack frame offsets for local variables. */
43 #define TM_FRAME_L0 TM_FRAME_SIZE-16
44 #define TM_FRAME_L1 TM_FRAME_SIZE-8
47 /* In order to access the TM SPRs, TM must be enabled. So, do so: */
60 std r0, THREAD_TM_TFHAR(r3)
62 std r0, THREAD_TM_TEXASR(r3)
64 std r0, THREAD_TM_TFIAR(r3)
67 _GLOBAL(tm_restore_sprs)
68 ld r0, THREAD_TM_TFHAR(r3)
70 ld r0, THREAD_TM_TEXASR(r3)
72 ld r0, THREAD_TM_TFIAR(r3)
76 /* Passed an 8-bit failure cause as first argument. */
81 /* void tm_reclaim(struct thread_struct *thread,
82 * unsigned long orig_msr,
85 * - Performs a full reclaim. This destroys outstanding
86 * transactions and updates thread->regs.tm_ckpt_* with the
87 * original checkpointed state. Note that thread->regs is
89 * - FP regs are written back to thread->transact_fpr before
90 * reclaiming. These are the transactional (current) versions.
92 * Purpose is to both abort transactions of, and preserve the state of,
93 * a transactions at a context switch. We preserve/restore both sets of process
94 * state to restore them when the thread's scheduled again. We continue in
95 * userland as though nothing happened, but when the transaction is resumed
96 * they will abort back to the checkpointed state we save out here.
98 * Call with IRQs off, stacks get all out of sync for some periods in here!
106 stdu r1, -TM_FRAME_SIZE(r1)
108 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
110 std r3, STK_PARAM(R3)(r1)
111 std r4, STK_PARAM(R4)(r1)
114 /* We need to setup MSR for VSX register save instructions. */
119 ori r16, r16, MSR_EE /* IRQs hard off */
121 oris r15, r15, MSR_VEC@h
124 oris r15,r15, MSR_VSX@h
125 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
128 std r14, TM_FRAME_L0(r1)
130 /* Do sanity check on MSR to make sure we are suspended */
131 li r7, (MSR_TS_S)@higher
135 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
137 /* Stash the stack pointer away for use after reclaim */
140 /* Clear MSR RI since we are about to change r1, EE is already off. */
146 * At this point we can't take an SLB miss since we have MSR_RI
147 * off. Load only to/from the stack/paca which are in SLB bolted regions
148 * until we turn MSR RI back on.
150 * The moment we treclaim, ALL of our GPRs will switch
151 * to user register state. (FPRs, CCR etc. also!)
152 * Use an sprg and a tm_scratch in the PACA to shuffle.
154 TRECLAIM(R5) /* Cause in r5 */
156 /* ******************** GPRs ******************** */
157 /* Stash the checkpointed r13 away in the scratch SPR and get the real
163 /* Stash the checkpointed r1 away in paca tm_scratch and get the real
166 std r1, PACATMSCRATCH(r13)
169 std r11, GPR11(r1) /* Temporary stash */
172 * Move the saved user r1 to the kernel stack in case PACATMSCRATCH is
173 * clobbered by an exception once we turn on MSR_RI below.
175 ld r11, PACATMSCRATCH(r13)
179 * Store r13 away so we can free up the scratch SPR for the SLB fault
180 * handler (needed once we start accessing the thread_struct).
185 /* Reset MSR RI so we can take SLB faults again */
189 /* Store the PPR in r11 and reset to decent value */
193 /* Now get some more GPRS free */
194 std r7, GPR7(r1) /* Temporary stash */
195 std r12, GPR12(r1) /* '' '' '' */
196 ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
198 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
200 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
202 /* Make r7 look like an exception frame so that we
203 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
205 subi r7, r7, STACK_FRAME_OVERHEAD
207 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
208 SAVE_GPR(0, r7) /* user r0 */
209 SAVE_GPR(2, r7) /* user r2 */
210 SAVE_4GPRS(3, r7) /* user r3-r6 */
211 SAVE_GPR(8, r7) /* user r8 */
212 SAVE_GPR(9, r7) /* user r9 */
213 SAVE_GPR(10, r7) /* user r10 */
214 ld r3, GPR1(r1) /* user r1 */
215 ld r4, GPR7(r1) /* user r7 */
216 ld r5, GPR11(r1) /* user r11 */
217 ld r6, GPR12(r1) /* user r12 */
218 ld r8, GPR13(r1) /* user r13 */
225 SAVE_NVGPRS(r7) /* user r14-r31 */
227 /* ******************** NIP ******************** */
229 std r3, _NIP(r7) /* Returns to failhandler */
230 /* The checkpointed NIP is ignored when rescheduling/rechkpting,
231 * but is used in signal return to 'wind back' to the abort handler.
234 /* ******************** CR,LR,CCR,MSR ********** */
246 /* ******************** TAR, DSCR ********** */
250 std r3, THREAD_TM_TAR(r12)
251 std r4, THREAD_TM_DSCR(r12)
253 /* MSR and flags: We don't change CRs, and we don't need to alter
258 /* ******************** FPR/VR/VSRs ************
259 * After reclaiming, capture the checkpointed FPRs/VRs /if used/.
261 * (If VSX used, FP and VMX are implied. Or, we don't need to look
262 * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
264 * We're passed the thread's MSR as the second parameter
266 * We enabled VEC/FP/VSX in the msr above, so we can execute these
269 ld r4, STK_PARAM(R4)(r1) /* Second parameter, MSR * */
271 andis. r0, r4, MSR_VEC@h
274 addi r7, r3, THREAD_CKVRSTATE
275 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
280 mfspr r0, SPRN_VRSAVE
281 std r0, THREAD_CKVRSAVE(r3)
286 addi r7, r3, THREAD_CKFPSTATE
287 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
290 stfd fr0,FPSTATE_FPSCR(r7)
294 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've
295 * been updated by the treclaim, to explain to userland the failure
298 mfspr r0, SPRN_TEXASR
301 std r0, THREAD_TM_TEXASR(r12)
302 std r3, THREAD_TM_TFHAR(r12)
303 std r4, THREAD_TM_TFIAR(r12)
305 /* AMR is checkpointed too, but is unsupported by Linux. */
307 /* Restore original MSR/IRQ state & clear TM mode */
308 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
311 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
316 addi r1, r1, TM_FRAME_SIZE
323 /* Load CPU's default DSCR */
324 ld r0, PACA_DSCR_DEFAULT(r13)
330 /* void tm_recheckpoint(struct thread_struct *thread,
331 * unsigned long orig_msr)
332 * - Restore the checkpointed register state saved by tm_reclaim
333 * when we switch_to a process.
335 * Call with IRQs off, stacks get all out of sync for
336 * some periods in here!
338 _GLOBAL(__tm_recheckpoint)
344 stdu r1, -TM_FRAME_SIZE(r1)
346 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
347 * This is used for backing up the NVGPRs:
351 /* Load complete register state from ts_ckpt* registers */
353 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
355 /* Make r7 look like an exception frame so that we
356 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
358 subi r7, r7, STACK_FRAME_OVERHEAD
361 /* R4 = original MSR to indicate whether thread used FP/Vector etc. */
363 /* Enable FP/vec in MSR if necessary! */
367 beq restore_gprs /* if neither, skip both */
371 oris r5, r5, MSR_VSX@h
372 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
374 or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
377 #ifdef CONFIG_ALTIVEC
379 * FP and VEC registers: These are recheckpointed from
380 * thread.ckfp_state and thread.ckvr_state respectively. The
381 * thread.fp_state[] version holds the 'live' (transactional)
382 * and will be loaded subsequently by any FPUnavailable trap.
384 andis. r0, r4, MSR_VEC@h
387 addi r8, r3, THREAD_CKVRSTATE
391 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
393 ld r5, THREAD_CKVRSAVE(r3)
394 mtspr SPRN_VRSAVE, r5
400 addi r8, r3, THREAD_CKFPSTATE
401 lfd fr0, FPSTATE_FPSCR(r8)
403 REST_32FPRS_VSRS(0, R4, R8)
406 mtmsr r6 /* FP/Vec off again! */
410 /* ******************** CR,LR,CCR,MSR ********** */
419 /* ******************** TAR ******************** */
420 ld r4, THREAD_TM_TAR(r3)
423 /* Load up the PPR and DSCR in GPRs only at this stage */
424 ld r5, THREAD_TM_DSCR(r3)
425 ld r6, THREAD_TM_PPR(r3)
427 REST_GPR(0, r7) /* GPR0 */
428 REST_2GPRS(2, r7) /* GPR2-3 */
429 REST_GPR(4, r7) /* GPR4 */
430 REST_4GPRS(8, r7) /* GPR8-11 */
431 REST_2GPRS(12, r7) /* GPR12-13 */
433 REST_NVGPRS(r7) /* GPR14-31 */
435 /* Load up PPR and DSCR here so we don't run with user values for long
440 /* Do final sanity check on TEXASR to make sure FS is set. Do this
441 * here before we load up the userspace r1 so any bugs we hit will get
443 mfspr r5, SPRN_TEXASR
448 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
450 /* Do final sanity check on MSR to make sure we are not transactional
454 li r5, (MSR_TS_MASK)@higher
458 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
467 * Store r1 and r5 on the stack so that we can access them
468 * after we clear MSR RI.
478 /* Clear MSR RI since we are about to change r1. EE is already off */
484 * At this point we can't take an SLB miss since we have MSR_RI
485 * off. Load only to/from the stack/paca which are in SLB bolted regions
486 * until we turn MSR RI back on.
493 /* Commit register state as checkpointed state: */
498 /* Our transactional state has now changed.
500 * Now just get out of here. Transactional (current) state will be
501 * updated once restore is called on the return path in the _switch-ed
508 /* R1 is restored, so we are recoverable again. EE is still off */
514 addi r1, r1, TM_FRAME_SIZE
521 /* Load CPU's default DSCR */
522 ld r0, PACA_DSCR_DEFAULT(r13)
527 /* ****************************************************************** */