1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Transactional memory support routines to reclaim and recheckpoint
4 * transactional process state.
6 * Copyright 2012 Matt Evans & Michael Neuling, IBM Corporation.
9 #include <asm/asm-offsets.h>
10 #include <asm/ppc_asm.h>
11 #include <asm/ppc-opcode.h>
12 #include <asm/ptrace.h>
17 /* See fpu.S, this is borrowed from there */
18 #define __SAVE_32FPRS_VSRS(n,c,base) \
21 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
22 SAVE_32FPRS(n,base); \
24 2: SAVE_32VSRS(n,c,base); \
26 #define __REST_32FPRS_VSRS(n,c,base) \
29 END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
30 REST_32FPRS(n,base); \
32 2: REST_32VSRS(n,c,base); \
35 #define __SAVE_32FPRS_VSRS(n,c,base) SAVE_32FPRS(n, base)
36 #define __REST_32FPRS_VSRS(n,c,base) REST_32FPRS(n, base)
38 #define SAVE_32FPRS_VSRS(n,c,base) \
39 __SAVE_32FPRS_VSRS(n,__REG_##c,__REG_##base)
40 #define REST_32FPRS_VSRS(n,c,base) \
41 __REST_32FPRS_VSRS(n,__REG_##c,__REG_##base)
43 /* Stack frame offsets for local variables. */
44 #define TM_FRAME_L0 TM_FRAME_SIZE-16
45 #define TM_FRAME_L1 TM_FRAME_SIZE-8
48 /* In order to access the TM SPRs, TM must be enabled. So, do so: */
61 std r0, THREAD_TM_TFHAR(r3)
63 std r0, THREAD_TM_TEXASR(r3)
65 std r0, THREAD_TM_TFIAR(r3)
68 _GLOBAL(tm_restore_sprs)
69 ld r0, THREAD_TM_TFHAR(r3)
71 ld r0, THREAD_TM_TEXASR(r3)
73 ld r0, THREAD_TM_TFIAR(r3)
77 /* Passed an 8-bit failure cause as first argument. */
82 /* void tm_reclaim(struct thread_struct *thread,
83 * unsigned long orig_msr,
86 * - Performs a full reclaim. This destroys outstanding
87 * transactions and updates thread->regs.tm_ckpt_* with the
88 * original checkpointed state. Note that thread->regs is
90 * - FP regs are written back to thread->transact_fpr before
91 * reclaiming. These are the transactional (current) versions.
93 * Purpose is to both abort transactions of, and preserve the state of,
94 * a transactions at a context switch. We preserve/restore both sets of process
95 * state to restore them when the thread's scheduled again. We continue in
96 * userland as though nothing happened, but when the transaction is resumed
97 * they will abort back to the checkpointed state we save out here.
99 * Call with IRQs off, stacks get all out of sync for some periods in here!
107 stdu r1, -TM_FRAME_SIZE(r1)
109 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD]. */
111 std r3, STK_PARAM(R3)(r1)
112 std r4, STK_PARAM(R4)(r1)
115 /* We need to setup MSR for VSX register save instructions. */
120 ori r16, r16, MSR_EE /* IRQs hard off */
122 oris r15, r15, MSR_VEC@h
125 oris r15,r15, MSR_VSX@h
126 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
129 std r14, TM_FRAME_L0(r1)
131 /* Do sanity check on MSR to make sure we are suspended */
132 li r7, (MSR_TS_S)@higher
136 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
138 /* Stash the stack pointer away for use after reclaim */
141 /* Clear MSR RI since we are about to change r1, EE is already off. */
147 * At this point we can't take an SLB miss since we have MSR_RI
148 * off. Load only to/from the stack/paca which are in SLB bolted regions
149 * until we turn MSR RI back on.
151 * The moment we treclaim, ALL of our GPRs will switch
152 * to user register state. (FPRs, CCR etc. also!)
153 * Use an sprg and a tm_scratch in the PACA to shuffle.
155 TRECLAIM(R5) /* Cause in r5 */
157 /* ******************** GPRs ******************** */
158 /* Stash the checkpointed r13 away in the scratch SPR and get the real
164 /* Stash the checkpointed r1 away in paca tm_scratch and get the real
167 std r1, PACATMSCRATCH(r13)
170 std r11, GPR11(r1) /* Temporary stash */
173 * Move the saved user r1 to the kernel stack in case PACATMSCRATCH is
174 * clobbered by an exception once we turn on MSR_RI below.
176 ld r11, PACATMSCRATCH(r13)
180 * Store r13 away so we can free up the scratch SPR for the SLB fault
181 * handler (needed once we start accessing the thread_struct).
186 /* Reset MSR RI so we can take SLB faults again */
190 /* Store the PPR in r11 and reset to decent value */
194 /* Now get some more GPRS free */
195 std r7, GPR7(r1) /* Temporary stash */
196 std r12, GPR12(r1) /* '' '' '' */
197 ld r12, STK_PARAM(R3)(r1) /* Param 0, thread_struct * */
199 std r11, THREAD_TM_PPR(r12) /* Store PPR and free r11 */
201 addi r7, r12, PT_CKPT_REGS /* Thread's ckpt_regs */
203 /* Make r7 look like an exception frame so that we
204 * can use the neat GPRx(n) macros. r7 is NOT a pt_regs ptr!
206 subi r7, r7, STACK_FRAME_OVERHEAD
208 /* Sync the userland GPRs 2-12, 14-31 to thread->regs: */
209 SAVE_GPR(0, r7) /* user r0 */
210 SAVE_GPR(2, r7) /* user r2 */
211 SAVE_4GPRS(3, r7) /* user r3-r6 */
212 SAVE_GPR(8, r7) /* user r8 */
213 SAVE_GPR(9, r7) /* user r9 */
214 SAVE_GPR(10, r7) /* user r10 */
215 ld r3, GPR1(r1) /* user r1 */
216 ld r4, GPR7(r1) /* user r7 */
217 ld r5, GPR11(r1) /* user r11 */
218 ld r6, GPR12(r1) /* user r12 */
219 ld r8, GPR13(r1) /* user r13 */
226 SAVE_NVGPRS(r7) /* user r14-r31 */
228 /* ******************** NIP ******************** */
230 std r3, _NIP(r7) /* Returns to failhandler */
231 /* The checkpointed NIP is ignored when rescheduling/rechkpting,
232 * but is used in signal return to 'wind back' to the abort handler.
235 /* ******************** CR,LR,CCR,MSR ********** */
247 /* ******************** TAR, DSCR ********** */
251 std r3, THREAD_TM_TAR(r12)
252 std r4, THREAD_TM_DSCR(r12)
254 /* MSR and flags: We don't change CRs, and we don't need to alter
259 /* ******************** FPR/VR/VSRs ************
260 * After reclaiming, capture the checkpointed FPRs/VRs /if used/.
262 * (If VSX used, FP and VMX are implied. Or, we don't need to look
263 * at MSR.VSX as copying FP regs if .FP, vector regs if .VMX covers it.)
265 * We're passed the thread's MSR as the second parameter
267 * We enabled VEC/FP/VSX in the msr above, so we can execute these
270 ld r4, STK_PARAM(R4)(r1) /* Second parameter, MSR * */
272 andis. r0, r4, MSR_VEC@h
275 addi r7, r3, THREAD_CKVRSTATE
276 SAVE_32VRS(0, r6, r7) /* r6 scratch, r7 transact vr state */
281 mfspr r0, SPRN_VRSAVE
282 std r0, THREAD_CKVRSAVE(r3)
287 addi r7, r3, THREAD_CKFPSTATE
288 SAVE_32FPRS_VSRS(0, R6, R7) /* r6 scratch, r7 transact fp state */
291 stfd fr0,FPSTATE_FPSCR(r7)
295 /* TM regs, incl TEXASR -- these live in thread_struct. Note they've
296 * been updated by the treclaim, to explain to userland the failure
299 mfspr r0, SPRN_TEXASR
302 std r0, THREAD_TM_TEXASR(r12)
303 std r3, THREAD_TM_TFHAR(r12)
304 std r4, THREAD_TM_TFIAR(r12)
306 /* AMR is checkpointed too, but is unsupported by Linux. */
308 /* Restore original MSR/IRQ state & clear TM mode */
309 ld r14, TM_FRAME_L0(r1) /* Orig MSR */
312 rldimi r14, r15, MSR_TS_LG, (63-MSR_TS_LG)-1
317 addi r1, r1, TM_FRAME_SIZE
324 /* Load CPU's default DSCR */
325 ld r0, PACA_DSCR_DEFAULT(r13)
331 /* void __tm_recheckpoint(struct thread_struct *thread,
332 * unsigned long orig_msr)
333 * - Restore the checkpointed register state saved by tm_reclaim
334 * when we switch_to a process.
336 * Call with IRQs off, stacks get all out of sync for
337 * some periods in here!
339 _GLOBAL(__tm_recheckpoint)
345 stdu r1, -TM_FRAME_SIZE(r1)
347 /* We've a struct pt_regs at [r1+STACK_FRAME_OVERHEAD].
348 * This is used for backing up the NVGPRs:
352 /* Load complete register state from ts_ckpt* registers */
354 addi r7, r3, PT_CKPT_REGS /* Thread's ckpt_regs */
356 /* Make r7 look like an exception frame so that we
357 * can use the neat GPRx(n) macros. r7 is now NOT a pt_regs ptr!
359 subi r7, r7, STACK_FRAME_OVERHEAD
362 /* R4 = original MSR to indicate whether thread used FP/Vector etc. */
364 /* Enable FP/vec in MSR if necessary! */
368 beq restore_gprs /* if neither, skip both */
372 oris r5, r5, MSR_VSX@h
373 END_FTR_SECTION_IFSET(CPU_FTR_VSX)
375 or r5, r6, r5 /* Set MSR.FP+.VSX/.VEC */
378 #ifdef CONFIG_ALTIVEC
380 * FP and VEC registers: These are recheckpointed from
381 * thread.ckfp_state and thread.ckvr_state respectively. The
382 * thread.fp_state[] version holds the 'live' (transactional)
383 * and will be loaded subsequently by any FPUnavailable trap.
385 andis. r0, r4, MSR_VEC@h
388 addi r8, r3, THREAD_CKVRSTATE
392 REST_32VRS(0, r5, r8) /* r5 scratch, r8 ptr */
394 ld r5, THREAD_CKVRSAVE(r3)
395 mtspr SPRN_VRSAVE, r5
401 addi r8, r3, THREAD_CKFPSTATE
402 lfd fr0, FPSTATE_FPSCR(r8)
404 REST_32FPRS_VSRS(0, R4, R8)
407 mtmsr r6 /* FP/Vec off again! */
411 /* ******************** CR,LR,CCR,MSR ********** */
420 /* ******************** TAR ******************** */
421 ld r4, THREAD_TM_TAR(r3)
424 /* Load up the PPR and DSCR in GPRs only at this stage */
425 ld r5, THREAD_TM_DSCR(r3)
426 ld r6, THREAD_TM_PPR(r3)
428 REST_GPR(0, r7) /* GPR0 */
429 REST_2GPRS(2, r7) /* GPR2-3 */
430 REST_GPR(4, r7) /* GPR4 */
431 REST_4GPRS(8, r7) /* GPR8-11 */
432 REST_2GPRS(12, r7) /* GPR12-13 */
434 REST_NVGPRS(r7) /* GPR14-31 */
436 /* Load up PPR and DSCR here so we don't run with user values for long
441 /* Do final sanity check on TEXASR to make sure FS is set. Do this
442 * here before we load up the userspace r1 so any bugs we hit will get
444 mfspr r5, SPRN_TEXASR
449 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
451 /* Do final sanity check on MSR to make sure we are not transactional
455 li r5, (MSR_TS_MASK)@higher
459 EMIT_BUG_ENTRY 1b,__FILE__,__LINE__,0
468 * Store r1 and r5 on the stack so that we can access them
469 * after we clear MSR RI.
479 /* Clear MSR RI since we are about to change r1. EE is already off */
485 * At this point we can't take an SLB miss since we have MSR_RI
486 * off. Load only to/from the stack/paca which are in SLB bolted regions
487 * until we turn MSR RI back on.
494 /* Commit register state as checkpointed state: */
499 /* Our transactional state has now changed.
501 * Now just get out of here. Transactional (current) state will be
502 * updated once restore is called on the return path in the _switch-ed
509 /* R1 is restored, so we are recoverable again. EE is still off */
515 addi r1, r1, TM_FRAME_SIZE
522 /* Load CPU's default DSCR */
523 ld r0, PACA_DSCR_DEFAULT(r13)
528 /* ****************************************************************** */