1 #include <linux/device.h>
4 #include <linux/percpu.h>
5 #include <linux/init.h>
6 #include <linux/sched.h>
7 #include <linux/export.h>
8 #include <linux/nodemask.h>
9 #include <linux/cpumask.h>
10 #include <linux/notifier.h>
12 #include <asm/current.h>
13 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/hvcall.h>
17 #include <asm/machdep.h>
20 #include <asm/firmware.h>
22 #include "cacheinfo.h"
26 #include <asm/lppaca.h>
29 static DEFINE_PER_CPU(struct cpu, cpu_devices);
34 * Snooze delay has not been hooked up since 3fa8cad82b94 ("powerpc/pseries/cpuidle:
35 * smt-snooze-delay cleanup.") and has been broken even longer. As was foretold in
38 * "ppc64_util currently utilises it. Once we fix ppc64_util, propose to clean
39 * up the kernel code."
41 * powerpc-utils stopped using it as of 1.3.8. At some point in the future this
42 * code should be removed.
45 static ssize_t store_smt_snooze_delay(struct device *dev,
46 struct device_attribute *attr,
50 pr_warn_once("%s (%d) stored to unsupported smt_snooze_delay, which has no effect.\n",
51 current->comm, current->pid);
55 static ssize_t show_smt_snooze_delay(struct device *dev,
56 struct device_attribute *attr,
59 pr_warn_once("%s (%d) read from unsupported smt_snooze_delay\n",
60 current->comm, current->pid);
61 return sprintf(buf, "100\n");
64 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
65 store_smt_snooze_delay);
67 static int __init setup_smt_snooze_delay(char *str)
69 if (!cpu_has_feature(CPU_FTR_SMT))
72 pr_warn("smt-snooze-delay command line option has no effect\n");
75 __setup("smt-snooze-delay=", setup_smt_snooze_delay);
77 #endif /* CONFIG_PPC64 */
79 #ifdef CONFIG_PPC_FSL_BOOK3E
83 static u64 altivec_idle_wt;
85 static unsigned int get_idle_ticks_bit(u64 ns)
90 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
92 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
100 static void do_show_pwrmgtcr0(void *val)
104 *value = mfspr(SPRN_PWRMGTCR0);
107 static ssize_t show_pw20_state(struct device *dev,
108 struct device_attribute *attr, char *buf)
111 unsigned int cpu = dev->id;
113 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
115 value &= PWRMGTCR0_PW20_WAIT;
117 return sprintf(buf, "%u\n", value ? 1 : 0);
120 static void do_store_pw20_state(void *val)
125 pw20_state = mfspr(SPRN_PWRMGTCR0);
128 pw20_state |= PWRMGTCR0_PW20_WAIT;
130 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
132 mtspr(SPRN_PWRMGTCR0, pw20_state);
135 static ssize_t store_pw20_state(struct device *dev,
136 struct device_attribute *attr,
137 const char *buf, size_t count)
140 unsigned int cpu = dev->id;
142 if (kstrtou32(buf, 0, &value))
148 smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
153 static ssize_t show_pw20_wait_time(struct device *dev,
154 struct device_attribute *attr, char *buf)
160 unsigned int cpu = dev->id;
163 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
164 value = (value & PWRMGTCR0_PW20_ENT) >>
165 PWRMGTCR0_PW20_ENT_SHIFT;
167 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
168 /* convert ms to ns */
169 if (tb_ticks_per_usec > 1000) {
170 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
174 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
176 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
182 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
185 static void set_pw20_wait_entry_bit(void *val)
190 pw20_idle = mfspr(SPRN_PWRMGTCR0);
192 /* Set Automatic PW20 Core Idle Count */
194 pw20_idle &= ~PWRMGTCR0_PW20_ENT;
197 pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
199 mtspr(SPRN_PWRMGTCR0, pw20_idle);
202 static ssize_t store_pw20_wait_time(struct device *dev,
203 struct device_attribute *attr,
204 const char *buf, size_t count)
209 unsigned int cpu = dev->id;
211 if (kstrtou64(buf, 0, &value))
217 entry_bit = get_idle_ticks_bit(value);
218 if (entry_bit > MAX_BIT)
223 smp_call_function_single(cpu, set_pw20_wait_entry_bit,
229 static ssize_t show_altivec_idle(struct device *dev,
230 struct device_attribute *attr, char *buf)
233 unsigned int cpu = dev->id;
235 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
237 value &= PWRMGTCR0_AV_IDLE_PD_EN;
239 return sprintf(buf, "%u\n", value ? 1 : 0);
242 static void do_store_altivec_idle(void *val)
247 altivec_idle = mfspr(SPRN_PWRMGTCR0);
250 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
252 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
254 mtspr(SPRN_PWRMGTCR0, altivec_idle);
257 static ssize_t store_altivec_idle(struct device *dev,
258 struct device_attribute *attr,
259 const char *buf, size_t count)
262 unsigned int cpu = dev->id;
264 if (kstrtou32(buf, 0, &value))
270 smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
275 static ssize_t show_altivec_idle_wait_time(struct device *dev,
276 struct device_attribute *attr, char *buf)
282 unsigned int cpu = dev->id;
284 if (!altivec_idle_wt) {
285 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
286 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
287 PWRMGTCR0_AV_IDLE_CNT_SHIFT;
289 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
290 /* convert ms to ns */
291 if (tb_ticks_per_usec > 1000) {
292 time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
296 time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
298 time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
301 time = altivec_idle_wt;
304 return sprintf(buf, "%llu\n", time > 0 ? time : 0);
307 static void set_altivec_idle_wait_entry_bit(void *val)
312 altivec_idle = mfspr(SPRN_PWRMGTCR0);
314 /* Set Automatic AltiVec Idle Count */
316 altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
319 altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
321 mtspr(SPRN_PWRMGTCR0, altivec_idle);
324 static ssize_t store_altivec_idle_wait_time(struct device *dev,
325 struct device_attribute *attr,
326 const char *buf, size_t count)
331 unsigned int cpu = dev->id;
333 if (kstrtou64(buf, 0, &value))
339 entry_bit = get_idle_ticks_bit(value);
340 if (entry_bit > MAX_BIT)
343 altivec_idle_wt = value;
345 smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
352 * Enable/Disable interface:
353 * 0, disable. 1, enable.
355 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
356 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
359 * Set wait time interface:(Nanosecond)
360 * Example: Base on TBfreq is 41MHZ.
364 * 196~390(ns): TB[60]
365 * 391~780(ns): TB[59]
366 * 781~1560(ns): TB[58]
369 static DEVICE_ATTR(pw20_wait_time, 0600,
371 store_pw20_wait_time);
372 static DEVICE_ATTR(altivec_idle_wait_time, 0600,
373 show_altivec_idle_wait_time,
374 store_altivec_idle_wait_time);
378 * Enabling PMCs will slow partition context switch times so we only do
379 * it the first time we write to the PMCs.
382 static DEFINE_PER_CPU(char, pmcs_enabled);
384 void ppc_enable_pmcs(void)
386 ppc_set_pmu_inuse(1);
388 /* Only need to enable them once */
389 if (__this_cpu_read(pmcs_enabled))
392 __this_cpu_write(pmcs_enabled, 1);
394 if (ppc_md.enable_pmcs)
395 ppc_md.enable_pmcs();
397 EXPORT_SYMBOL(ppc_enable_pmcs);
399 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
400 static void read_##NAME(void *val) \
402 *(unsigned long *)val = mfspr(ADDRESS); \
404 static void write_##NAME(void *val) \
407 mtspr(ADDRESS, *(unsigned long *)val); \
410 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
411 static ssize_t show_##NAME(struct device *dev, \
412 struct device_attribute *attr, \
415 struct cpu *cpu = container_of(dev, struct cpu, dev); \
417 smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1); \
418 return sprintf(buf, "%lx\n", val); \
420 static ssize_t __used \
421 store_##NAME(struct device *dev, struct device_attribute *attr, \
422 const char *buf, size_t count) \
424 struct cpu *cpu = container_of(dev, struct cpu, dev); \
426 int ret = sscanf(buf, "%lx", &val); \
429 smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
433 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
434 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
435 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
436 #define SYSFS_SPRSETUP(NAME, ADDRESS) \
437 __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
438 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
440 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
441 __SYSFS_SPRSETUP_SHOW_STORE(NAME)
443 /* Let's define all possible registers, we'll only hook up the ones
444 * that are implemented on the current processor
447 #if defined(CONFIG_PPC64)
448 #define HAS_PPC_PMC_CLASSIC 1
449 #define HAS_PPC_PMC_IBM 1
450 #define HAS_PPC_PMC_PA6T 1
451 #elif defined(CONFIG_6xx)
452 #define HAS_PPC_PMC_CLASSIC 1
453 #define HAS_PPC_PMC_IBM 1
454 #define HAS_PPC_PMC_G4 1
458 #ifdef HAS_PPC_PMC_CLASSIC
459 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
460 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
461 SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
462 SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
463 SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
464 SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
465 SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
466 SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
468 #ifdef HAS_PPC_PMC_G4
469 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
473 SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
474 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
476 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
477 SYSFS_SPRSETUP(purr, SPRN_PURR);
478 SYSFS_SPRSETUP(spurr, SPRN_SPURR);
479 SYSFS_SPRSETUP(pir, SPRN_PIR);
482 Lets only enable read for phyp resources and
483 enable write when needed with a separate function.
484 Lets be conservative and default to pseries.
486 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
487 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
488 static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
489 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
492 * This is the system wide DSCR register default value. Any
493 * change to this default value through the sysfs interface
494 * will update all per cpu DSCR default values across the
495 * system stored in their respective PACA structures.
497 static unsigned long dscr_default;
500 * read_dscr() - Fetch the cpu specific DSCR default
501 * @val: Returned cpu specific DSCR default value
503 * This function returns the per cpu DSCR default value
504 * for any cpu which is contained in it's PACA structure.
506 static void read_dscr(void *val)
508 *(unsigned long *)val = get_paca()->dscr_default;
513 * write_dscr() - Update the cpu specific DSCR default
514 * @val: New cpu specific DSCR default value to update
516 * This function updates the per cpu DSCR default value
517 * for any cpu which is contained in it's PACA structure.
519 static void write_dscr(void *val)
521 get_paca()->dscr_default = *(unsigned long *)val;
522 if (!current->thread.dscr_inherit) {
523 current->thread.dscr = *(unsigned long *)val;
524 mtspr(SPRN_DSCR, *(unsigned long *)val);
528 SYSFS_SPRSETUP_SHOW_STORE(dscr);
529 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
531 static void add_write_permission_dev_attr(struct device_attribute *attr)
533 attr->attr.mode |= 0200;
537 * show_dscr_default() - Fetch the system wide DSCR default
538 * @dev: Device structure
539 * @attr: Device attribute structure
540 * @buf: Interface buffer
542 * This function returns the system wide DSCR default value.
544 static ssize_t show_dscr_default(struct device *dev,
545 struct device_attribute *attr, char *buf)
547 return sprintf(buf, "%lx\n", dscr_default);
551 * store_dscr_default() - Update the system wide DSCR default
552 * @dev: Device structure
553 * @attr: Device attribute structure
554 * @buf: Interface buffer
555 * @count: Size of the update
557 * This function updates the system wide DSCR default value.
559 static ssize_t __used store_dscr_default(struct device *dev,
560 struct device_attribute *attr, const char *buf,
566 ret = sscanf(buf, "%lx", &val);
571 on_each_cpu(write_dscr, &val, 1);
576 static DEVICE_ATTR(dscr_default, 0600,
577 show_dscr_default, store_dscr_default);
579 static void sysfs_create_dscr_default(void)
582 if (cpu_has_feature(CPU_FTR_DSCR))
583 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
585 #endif /* CONFIG_PPC64 */
587 #ifdef HAS_PPC_PMC_PA6T
588 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
589 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
590 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
591 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
592 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
593 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
594 #ifdef CONFIG_DEBUG_KERNEL
595 SYSFS_SPRSETUP(hid0, SPRN_HID0);
596 SYSFS_SPRSETUP(hid1, SPRN_HID1);
597 SYSFS_SPRSETUP(hid4, SPRN_HID4);
598 SYSFS_SPRSETUP(hid5, SPRN_HID5);
599 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
600 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
601 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
602 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
603 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
604 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
605 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
606 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
607 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
608 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
609 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
610 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
611 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
612 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
613 SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
614 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
615 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
616 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
617 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
618 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
619 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
620 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
621 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
622 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
623 #endif /* CONFIG_DEBUG_KERNEL */
624 #endif /* HAS_PPC_PMC_PA6T */
626 #ifdef HAS_PPC_PMC_IBM
627 static struct device_attribute ibm_common_attrs[] = {
628 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
629 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
631 #endif /* HAS_PPC_PMC_G4 */
633 #ifdef HAS_PPC_PMC_G4
634 static struct device_attribute g4_common_attrs[] = {
635 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
636 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
637 __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
639 #endif /* HAS_PPC_PMC_G4 */
641 static struct device_attribute classic_pmc_attrs[] = {
642 __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
643 __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
644 __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
645 __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
646 __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
647 __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
649 __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
650 __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
654 #ifdef HAS_PPC_PMC_PA6T
655 static struct device_attribute pa6t_attrs[] = {
656 __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
657 __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
658 __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
659 __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
660 __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
661 __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
662 __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
663 __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
664 #ifdef CONFIG_DEBUG_KERNEL
665 __ATTR(hid0, 0600, show_hid0, store_hid0),
666 __ATTR(hid1, 0600, show_hid1, store_hid1),
667 __ATTR(hid4, 0600, show_hid4, store_hid4),
668 __ATTR(hid5, 0600, show_hid5, store_hid5),
669 __ATTR(ima0, 0600, show_ima0, store_ima0),
670 __ATTR(ima1, 0600, show_ima1, store_ima1),
671 __ATTR(ima2, 0600, show_ima2, store_ima2),
672 __ATTR(ima3, 0600, show_ima3, store_ima3),
673 __ATTR(ima4, 0600, show_ima4, store_ima4),
674 __ATTR(ima5, 0600, show_ima5, store_ima5),
675 __ATTR(ima6, 0600, show_ima6, store_ima6),
676 __ATTR(ima7, 0600, show_ima7, store_ima7),
677 __ATTR(ima8, 0600, show_ima8, store_ima8),
678 __ATTR(ima9, 0600, show_ima9, store_ima9),
679 __ATTR(imaat, 0600, show_imaat, store_imaat),
680 __ATTR(btcr, 0600, show_btcr, store_btcr),
681 __ATTR(pccr, 0600, show_pccr, store_pccr),
682 __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
683 __ATTR(der, 0600, show_der, store_der),
684 __ATTR(mer, 0600, show_mer, store_mer),
685 __ATTR(ber, 0600, show_ber, store_ber),
686 __ATTR(ier, 0600, show_ier, store_ier),
687 __ATTR(sier, 0600, show_sier, store_sier),
688 __ATTR(siar, 0600, show_siar, store_siar),
689 __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
690 __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
691 __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
692 __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
693 #endif /* CONFIG_DEBUG_KERNEL */
695 #endif /* HAS_PPC_PMC_PA6T */
696 #endif /* HAS_PPC_PMC_CLASSIC */
698 static int register_cpu_online(unsigned int cpu)
700 struct cpu *c = &per_cpu(cpu_devices, cpu);
701 struct device *s = &c->dev;
702 struct device_attribute *attrs, *pmc_attrs;
705 /* For cpus present at boot a reference was already grabbed in register_cpu() */
707 s->of_node = of_get_cpu_node(cpu, NULL);
710 if (cpu_has_feature(CPU_FTR_SMT))
711 device_create_file(s, &dev_attr_smt_snooze_delay);
715 switch (cur_cpu_spec->pmc_type) {
716 #ifdef HAS_PPC_PMC_IBM
718 attrs = ibm_common_attrs;
719 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
720 pmc_attrs = classic_pmc_attrs;
722 #endif /* HAS_PPC_PMC_IBM */
723 #ifdef HAS_PPC_PMC_G4
725 attrs = g4_common_attrs;
726 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
727 pmc_attrs = classic_pmc_attrs;
729 #endif /* HAS_PPC_PMC_G4 */
730 #ifdef HAS_PPC_PMC_PA6T
732 /* PA Semi starts counting at PMC0 */
734 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
737 #endif /* HAS_PPC_PMC_PA6T */
744 for (i = 0; i < nattrs; i++)
745 device_create_file(s, &attrs[i]);
748 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
749 device_create_file(s, &pmc_attrs[i]);
752 if (cpu_has_feature(CPU_FTR_MMCRA))
753 device_create_file(s, &dev_attr_mmcra);
755 if (cpu_has_feature(CPU_FTR_PURR)) {
756 if (!firmware_has_feature(FW_FEATURE_LPAR))
757 add_write_permission_dev_attr(&dev_attr_purr);
758 device_create_file(s, &dev_attr_purr);
761 if (cpu_has_feature(CPU_FTR_SPURR))
762 device_create_file(s, &dev_attr_spurr);
764 if (cpu_has_feature(CPU_FTR_DSCR))
765 device_create_file(s, &dev_attr_dscr);
767 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
768 device_create_file(s, &dev_attr_pir);
769 #endif /* CONFIG_PPC64 */
771 #ifdef CONFIG_PPC_FSL_BOOK3E
772 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
773 device_create_file(s, &dev_attr_pw20_state);
774 device_create_file(s, &dev_attr_pw20_wait_time);
776 device_create_file(s, &dev_attr_altivec_idle);
777 device_create_file(s, &dev_attr_altivec_idle_wait_time);
780 cacheinfo_cpu_online(cpu);
784 #ifdef CONFIG_HOTPLUG_CPU
785 static int unregister_cpu_online(unsigned int cpu)
787 struct cpu *c = &per_cpu(cpu_devices, cpu);
788 struct device *s = &c->dev;
789 struct device_attribute *attrs, *pmc_attrs;
792 BUG_ON(!c->hotpluggable);
795 if (cpu_has_feature(CPU_FTR_SMT))
796 device_remove_file(s, &dev_attr_smt_snooze_delay);
800 switch (cur_cpu_spec->pmc_type) {
801 #ifdef HAS_PPC_PMC_IBM
803 attrs = ibm_common_attrs;
804 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
805 pmc_attrs = classic_pmc_attrs;
807 #endif /* HAS_PPC_PMC_IBM */
808 #ifdef HAS_PPC_PMC_G4
810 attrs = g4_common_attrs;
811 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
812 pmc_attrs = classic_pmc_attrs;
814 #endif /* HAS_PPC_PMC_G4 */
815 #ifdef HAS_PPC_PMC_PA6T
817 /* PA Semi starts counting at PMC0 */
819 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
822 #endif /* HAS_PPC_PMC_PA6T */
829 for (i = 0; i < nattrs; i++)
830 device_remove_file(s, &attrs[i]);
833 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
834 device_remove_file(s, &pmc_attrs[i]);
837 if (cpu_has_feature(CPU_FTR_MMCRA))
838 device_remove_file(s, &dev_attr_mmcra);
840 if (cpu_has_feature(CPU_FTR_PURR))
841 device_remove_file(s, &dev_attr_purr);
843 if (cpu_has_feature(CPU_FTR_SPURR))
844 device_remove_file(s, &dev_attr_spurr);
846 if (cpu_has_feature(CPU_FTR_DSCR))
847 device_remove_file(s, &dev_attr_dscr);
849 if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
850 device_remove_file(s, &dev_attr_pir);
851 #endif /* CONFIG_PPC64 */
853 #ifdef CONFIG_PPC_FSL_BOOK3E
854 if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
855 device_remove_file(s, &dev_attr_pw20_state);
856 device_remove_file(s, &dev_attr_pw20_wait_time);
858 device_remove_file(s, &dev_attr_altivec_idle);
859 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
862 cacheinfo_cpu_offline(cpu);
863 of_node_put(s->of_node);
867 #else /* !CONFIG_HOTPLUG_CPU */
868 #define unregister_cpu_online NULL
871 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
872 ssize_t arch_cpu_probe(const char *buf, size_t count)
874 if (ppc_md.cpu_probe)
875 return ppc_md.cpu_probe(buf, count);
880 ssize_t arch_cpu_release(const char *buf, size_t count)
882 if (ppc_md.cpu_release)
883 return ppc_md.cpu_release(buf, count);
887 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
889 static DEFINE_MUTEX(cpu_mutex);
891 int cpu_add_dev_attr(struct device_attribute *attr)
895 mutex_lock(&cpu_mutex);
897 for_each_possible_cpu(cpu) {
898 device_create_file(get_cpu_device(cpu), attr);
901 mutex_unlock(&cpu_mutex);
904 EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
906 int cpu_add_dev_attr_group(struct attribute_group *attrs)
912 mutex_lock(&cpu_mutex);
914 for_each_possible_cpu(cpu) {
915 dev = get_cpu_device(cpu);
916 ret = sysfs_create_group(&dev->kobj, attrs);
920 mutex_unlock(&cpu_mutex);
923 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
926 void cpu_remove_dev_attr(struct device_attribute *attr)
930 mutex_lock(&cpu_mutex);
932 for_each_possible_cpu(cpu) {
933 device_remove_file(get_cpu_device(cpu), attr);
936 mutex_unlock(&cpu_mutex);
938 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
940 void cpu_remove_dev_attr_group(struct attribute_group *attrs)
945 mutex_lock(&cpu_mutex);
947 for_each_possible_cpu(cpu) {
948 dev = get_cpu_device(cpu);
949 sysfs_remove_group(&dev->kobj, attrs);
952 mutex_unlock(&cpu_mutex);
954 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
960 static void register_nodes(void)
964 for (i = 0; i < MAX_NUMNODES; i++)
965 register_one_node(i);
968 int sysfs_add_device_to_node(struct device *dev, int nid)
970 struct node *node = node_devices[nid];
971 return sysfs_create_link(&node->dev.kobj, &dev->kobj,
972 kobject_name(&dev->kobj));
974 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
976 void sysfs_remove_device_from_node(struct device *dev, int nid)
978 struct node *node = node_devices[nid];
979 sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
981 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
984 static void register_nodes(void)
991 /* Only valid if CPU is present. */
992 static ssize_t show_physical_id(struct device *dev,
993 struct device_attribute *attr, char *buf)
995 struct cpu *cpu = container_of(dev, struct cpu, dev);
997 return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
999 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1001 static int __init topology_init(void)
1007 for_each_possible_cpu(cpu) {
1008 struct cpu *c = &per_cpu(cpu_devices, cpu);
1011 * For now, we just see if the system supports making
1012 * the RTAS calls for CPU hotplug. But, there may be a
1013 * more comprehensive way to do this for an individual
1014 * CPU. For instance, the boot cpu might never be valid
1018 c->hotpluggable = 1;
1020 if (cpu_online(cpu) || c->hotpluggable) {
1021 register_cpu(c, cpu);
1023 device_create_file(&c->dev, &dev_attr_physical_id);
1026 r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
1027 register_cpu_online, unregister_cpu_online);
1030 sysfs_create_dscr_default();
1031 #endif /* CONFIG_PPC64 */
1035 subsys_initcall(topology_init);