arch/powerpc/kernel/sysfs.c

   1 #include <linux/device.h>
   2 #include <linux/cpu.h>
   3 #include <linux/smp.h>
   4 #include <linux/percpu.h>
   5 #include <linux/init.h>
   6 #include <linux/sched.h>
   7 #include <linux/export.h>
   8 #include <linux/nodemask.h>
   9 #include <linux/cpumask.h>
  10 #include <linux/notifier.h>
  11
  12 #include <asm/current.h>
  13 #include <asm/processor.h>
  14 #include <asm/cputable.h>
  15 #include <asm/hvcall.h>
  16 #include <asm/prom.h>
  17 #include <asm/machdep.h>
  18 #include <asm/smp.h>
  19 #include <asm/pmc.h>
  20 #include <asm/firmware.h>
  21
  22 #include "cacheinfo.h"
  23 #include "setup.h"
  24
  25 #ifdef CONFIG_PPC64
  26 #include <asm/paca.h>
  27 #include <asm/lppaca.h>
  28 #endif
  29
  30 static DEFINE_PER_CPU(struct cpu, cpu_devices);
  31
  32 #ifdef CONFIG_PPC64
  33
  34 /*
  35  * Snooze delay has not been hooked up since 3fa8cad82b94 ("powerpc/pseries/cpuidle:
  36  * smt-snooze-delay cleanup.") and has been broken even longer. As was foretold in
  37  * 2014:
  38  *
  39  *  "ppc64_util currently utilises it. Once we fix ppc64_util, propose to clean
  40  *  up the kernel code."
  41  *
  42  * powerpc-utils stopped using it as of 1.3.8. At some point in the future this
  43  * code should be removed.
  44  */
  45
  46 static ssize_t store_smt_snooze_delay(struct device *dev,
  47                                       struct device_attribute *attr,
  48                                       const char *buf,
  49                                       size_t count)
  50 {
  51         pr_warn_once("%s (%d) stored to unsupported smt_snooze_delay, which has no effect.\n",
  52                      current->comm, current->pid);
  53         return count;
  54 }
  55
  56 static ssize_t show_smt_snooze_delay(struct device *dev,
  57                                      struct device_attribute *attr,
  58                                      char *buf)
  59 {
  60         pr_warn_once("%s (%d) read from unsupported smt_snooze_delay\n",
  61                      current->comm, current->pid);
  62         return sprintf(buf, "100\n");
  63 }
  64
  65 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
  66                    store_smt_snooze_delay);
  67
  68 static int __init setup_smt_snooze_delay(char *str)
  69 {
  70         if (!cpu_has_feature(CPU_FTR_SMT))
  71                 return 1;
  72
  73         pr_warn("smt-snooze-delay command line option has no effect\n");
  74         return 1;
  75 }
  76 __setup("smt-snooze-delay=", setup_smt_snooze_delay);
  77
  78 #endif /* CONFIG_PPC64 */
  79
  80 #ifdef CONFIG_PPC_FSL_BOOK3E
  81 #define MAX_BIT                         63
  82
  83 static u64 pw20_wt;
  84 static u64 altivec_idle_wt;
  85
  86 static unsigned int get_idle_ticks_bit(u64 ns)
  87 {
  88         u64 cycle;
  89
  90         if (ns >= 10000)
  91                 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
  92         else
  93                 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
  94
  95         if (!cycle)
  96                 return 0;
  97
  98         return ilog2(cycle);
  99 }
 100
 101 static void do_show_pwrmgtcr0(void *val)
 102 {
 103         u32 *value = val;
 104
 105         *value = mfspr(SPRN_PWRMGTCR0);
 106 }
 107
 108 static ssize_t show_pw20_state(struct device *dev,
 109                                 struct device_attribute *attr, char *buf)
 110 {
 111         u32 value;
 112         unsigned int cpu = dev->id;
 113
 114         smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 115
 116         value &= PWRMGTCR0_PW20_WAIT;
 117
 118         return sprintf(buf, "%u\n", value ? 1 : 0);
 119 }
 120
 121 static void do_store_pw20_state(void *val)
 122 {
 123         u32 *value = val;
 124         u32 pw20_state;
 125
 126         pw20_state = mfspr(SPRN_PWRMGTCR0);
 127
 128         if (*value)
 129                 pw20_state |= PWRMGTCR0_PW20_WAIT;
 130         else
 131                 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
 132
 133         mtspr(SPRN_PWRMGTCR0, pw20_state);
 134 }
 135
 136 static ssize_t store_pw20_state(struct device *dev,
 137                                 struct device_attribute *attr,
 138                                 const char *buf, size_t count)
 139 {
 140         u32 value;
 141         unsigned int cpu = dev->id;
 142
 143         if (kstrtou32(buf, 0, &value))
 144                 return -EINVAL;
 145
 146         if (value > 1)
 147                 return -EINVAL;
 148
 149         smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
 150
 151         return count;
 152 }
 153
 154 static ssize_t show_pw20_wait_time(struct device *dev,
 155                                 struct device_attribute *attr, char *buf)
 156 {
 157         u32 value;
 158         u64 tb_cycle = 1;
 159         u64 time;
 160
 161         unsigned int cpu = dev->id;
 162
 163         if (!pw20_wt) {
 164                 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 165                 value = (value & PWRMGTCR0_PW20_ENT) >>
 166                                         PWRMGTCR0_PW20_ENT_SHIFT;
 167
 168                 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 169                 /* convert ms to ns */
 170                 if (tb_ticks_per_usec > 1000) {
 171                         time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 172                 } else {
 173                         u32 rem_us;
 174
 175                         time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 176                                                 &rem_us);
 177                         time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 178                 }
 179         } else {
 180                 time = pw20_wt;
 181         }
 182
 183         return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 184 }
 185
 186 static void set_pw20_wait_entry_bit(void *val)
 187 {
 188         u32 *value = val;
 189         u32 pw20_idle;
 190
 191         pw20_idle = mfspr(SPRN_PWRMGTCR0);
 192
 193         /* Set Automatic PW20 Core Idle Count */
 194         /* clear count */
 195         pw20_idle &= ~PWRMGTCR0_PW20_ENT;
 196
 197         /* set count */
 198         pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
 199
 200         mtspr(SPRN_PWRMGTCR0, pw20_idle);
 201 }
 202
 203 static ssize_t store_pw20_wait_time(struct device *dev,
 204                                 struct device_attribute *attr,
 205                                 const char *buf, size_t count)
 206 {
 207         u32 entry_bit;
 208         u64 value;
 209
 210         unsigned int cpu = dev->id;
 211
 212         if (kstrtou64(buf, 0, &value))
 213                 return -EINVAL;
 214
 215         if (!value)
 216                 return -EINVAL;
 217
 218         entry_bit = get_idle_ticks_bit(value);
 219         if (entry_bit > MAX_BIT)
 220                 return -EINVAL;
 221
 222         pw20_wt = value;
 223
 224         smp_call_function_single(cpu, set_pw20_wait_entry_bit,
 225                                 &entry_bit, 1);
 226
 227         return count;
 228 }
 229
 230 static ssize_t show_altivec_idle(struct device *dev,
 231                                 struct device_attribute *attr, char *buf)
 232 {
 233         u32 value;
 234         unsigned int cpu = dev->id;
 235
 236         smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 237
 238         value &= PWRMGTCR0_AV_IDLE_PD_EN;
 239
 240         return sprintf(buf, "%u\n", value ? 1 : 0);
 241 }
 242
 243 static void do_store_altivec_idle(void *val)
 244 {
 245         u32 *value = val;
 246         u32 altivec_idle;
 247
 248         altivec_idle = mfspr(SPRN_PWRMGTCR0);
 249
 250         if (*value)
 251                 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
 252         else
 253                 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
 254
 255         mtspr(SPRN_PWRMGTCR0, altivec_idle);
 256 }
 257
 258 static ssize_t store_altivec_idle(struct device *dev,
 259                                 struct device_attribute *attr,
 260                                 const char *buf, size_t count)
 261 {
 262         u32 value;
 263         unsigned int cpu = dev->id;
 264
 265         if (kstrtou32(buf, 0, &value))
 266                 return -EINVAL;
 267
 268         if (value > 1)
 269                 return -EINVAL;
 270
 271         smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
 272
 273         return count;
 274 }
 275
 276 static ssize_t show_altivec_idle_wait_time(struct device *dev,
 277                                 struct device_attribute *attr, char *buf)
 278 {
 279         u32 value;
 280         u64 tb_cycle = 1;
 281         u64 time;
 282
 283         unsigned int cpu = dev->id;
 284
 285         if (!altivec_idle_wt) {
 286                 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 287                 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
 288                                         PWRMGTCR0_AV_IDLE_CNT_SHIFT;
 289
 290                 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 291                 /* convert ms to ns */
 292                 if (tb_ticks_per_usec > 1000) {
 293                         time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 294                 } else {
 295                         u32 rem_us;
 296
 297                         time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 298                                                 &rem_us);
 299                         time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 300                 }
 301         } else {
 302                 time = altivec_idle_wt;
 303         }
 304
 305         return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 306 }
 307
 308 static void set_altivec_idle_wait_entry_bit(void *val)
 309 {
 310         u32 *value = val;
 311         u32 altivec_idle;
 312
 313         altivec_idle = mfspr(SPRN_PWRMGTCR0);
 314
 315         /* Set Automatic AltiVec Idle Count */
 316         /* clear count */
 317         altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
 318
 319         /* set count */
 320         altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
 321
 322         mtspr(SPRN_PWRMGTCR0, altivec_idle);
 323 }
 324
 325 static ssize_t store_altivec_idle_wait_time(struct device *dev,
 326                                 struct device_attribute *attr,
 327                                 const char *buf, size_t count)
 328 {
 329         u32 entry_bit;
 330         u64 value;
 331
 332         unsigned int cpu = dev->id;
 333
 334         if (kstrtou64(buf, 0, &value))
 335                 return -EINVAL;
 336
 337         if (!value)
 338                 return -EINVAL;
 339
 340         entry_bit = get_idle_ticks_bit(value);
 341         if (entry_bit > MAX_BIT)
 342                 return -EINVAL;
 343
 344         altivec_idle_wt = value;
 345
 346         smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
 347                                 &entry_bit, 1);
 348
 349         return count;
 350 }
 351
 352 /*
 353  * Enable/Disable interface:
 354  * 0, disable. 1, enable.
 355  */
 356 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
 357 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
 358
 359 /*
 360  * Set wait time interface:(Nanosecond)
 361  * Example: Base on TBfreq is 41MHZ.
 362  * 1~48(ns): TB[63]
 363  * 49~97(ns): TB[62]
 364  * 98~195(ns): TB[61]
 365  * 196~390(ns): TB[60]
 366  * 391~780(ns): TB[59]
 367  * 781~1560(ns): TB[58]
 368  * ...
 369  */
 370 static DEVICE_ATTR(pw20_wait_time, 0600,
 371                         show_pw20_wait_time,
 372                         store_pw20_wait_time);
 373 static DEVICE_ATTR(altivec_idle_wait_time, 0600,
 374                         show_altivec_idle_wait_time,
 375                         store_altivec_idle_wait_time);
 376 #endif
 377
 378 /*
 379  * Enabling PMCs will slow partition context switch times so we only do
 380  * it the first time we write to the PMCs.
 381  */
 382
 383 static DEFINE_PER_CPU(char, pmcs_enabled);
 384
 385 void ppc_enable_pmcs(void)
 386 {
 387         ppc_set_pmu_inuse(1);
 388
 389         /* Only need to enable them once */
 390         if (__this_cpu_read(pmcs_enabled))
 391                 return;
 392
 393         __this_cpu_write(pmcs_enabled, 1);
 394
 395         if (ppc_md.enable_pmcs)
 396                 ppc_md.enable_pmcs();
 397 }
 398 EXPORT_SYMBOL(ppc_enable_pmcs);
 399
 400 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
 401 static void read_##NAME(void *val) \
 402 { \
 403         *(unsigned long *)val = mfspr(ADDRESS); \
 404 } \
 405 static void write_##NAME(void *val) \
 406 { \
 407         EXTRA; \
 408         mtspr(ADDRESS, *(unsigned long *)val);  \
 409 }
 410
 411 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 412 static ssize_t show_##NAME(struct device *dev, \
 413                         struct device_attribute *attr, \
 414                         char *buf) \
 415 { \
 416         struct cpu *cpu = container_of(dev, struct cpu, dev); \
 417         unsigned long val; \
 418         smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1);    \
 419         return sprintf(buf, "%lx\n", val); \
 420 } \
 421 static ssize_t __used \
 422         store_##NAME(struct device *dev, struct device_attribute *attr, \
 423                         const char *buf, size_t count) \
 424 { \
 425         struct cpu *cpu = container_of(dev, struct cpu, dev); \
 426         unsigned long val; \
 427         int ret = sscanf(buf, "%lx", &val); \
 428         if (ret != 1) \
 429                 return -EINVAL; \
 430         smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
 431         return count; \
 432 }
 433
 434 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
 435         __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
 436         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 437 #define SYSFS_SPRSETUP(NAME, ADDRESS) \
 438         __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
 439         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 440
 441 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 442         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 443
 444 /* Let's define all possible registers, we'll only hook up the ones
 445  * that are implemented on the current processor
 446  */
 447
 448 #if defined(CONFIG_PPC64)
 449 #define HAS_PPC_PMC_CLASSIC     1
 450 #define HAS_PPC_PMC_IBM         1
 451 #define HAS_PPC_PMC_PA6T        1
 452 #elif defined(CONFIG_6xx)
 453 #define HAS_PPC_PMC_CLASSIC     1
 454 #define HAS_PPC_PMC_IBM         1
 455 #define HAS_PPC_PMC_G4          1
 456 #endif
 457
 458
 459 #ifdef HAS_PPC_PMC_CLASSIC
 460 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
 461 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
 462 SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
 463 SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
 464 SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
 465 SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
 466 SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
 467 SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
 468
 469 #ifdef HAS_PPC_PMC_G4
 470 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
 471 #endif
 472
 473 #ifdef CONFIG_PPC64
 474 SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
 475 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
 476
 477 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
 478 SYSFS_SPRSETUP(purr, SPRN_PURR);
 479 SYSFS_SPRSETUP(spurr, SPRN_SPURR);
 480 SYSFS_SPRSETUP(pir, SPRN_PIR);
 481 SYSFS_SPRSETUP(tscr, SPRN_TSCR);
 482
 483 /*
 484   Lets only enable read for phyp resources and
 485   enable write when needed with a separate function.
 486   Lets be conservative and default to pseries.
 487 */
 488 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
 489 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
 490 static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
 491 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
 492 static DEVICE_ATTR(tscr, 0600, show_tscr, store_tscr);
 493
 494 /*
 495  * This is the system wide DSCR register default value. Any
 496  * change to this default value through the sysfs interface
 497  * will update all per cpu DSCR default values across the
 498  * system stored in their respective PACA structures.
 499  */
 500 static unsigned long dscr_default;
 501
 502 /**
 503  * read_dscr() - Fetch the cpu specific DSCR default
 504  * @val:        Returned cpu specific DSCR default value
 505  *
 506  * This function returns the per cpu DSCR default value
 507  * for any cpu which is contained in it's PACA structure.
 508  */
 509 static void read_dscr(void *val)
 510 {
 511         *(unsigned long *)val = get_paca()->dscr_default;
 512 }
 513
 514
 515 /**
 516  * write_dscr() - Update the cpu specific DSCR default
 517  * @val:        New cpu specific DSCR default value to update
 518  *
 519  * This function updates the per cpu DSCR default value
 520  * for any cpu which is contained in it's PACA structure.
 521  */
 522 static void write_dscr(void *val)
 523 {
 524         get_paca()->dscr_default = *(unsigned long *)val;
 525         if (!current->thread.dscr_inherit) {
 526                 current->thread.dscr = *(unsigned long *)val;
 527                 mtspr(SPRN_DSCR, *(unsigned long *)val);
 528         }
 529 }
 530
 531 SYSFS_SPRSETUP_SHOW_STORE(dscr);
 532 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
 533
 534 static void add_write_permission_dev_attr(struct device_attribute *attr)
 535 {
 536         attr->attr.mode |= 0200;
 537 }
 538
 539 /**
 540  * show_dscr_default() - Fetch the system wide DSCR default
 541  * @dev:        Device structure
 542  * @attr:       Device attribute structure
 543  * @buf:        Interface buffer
 544  *
 545  * This function returns the system wide DSCR default value.
 546  */
 547 static ssize_t show_dscr_default(struct device *dev,
 548                 struct device_attribute *attr, char *buf)
 549 {
 550         return sprintf(buf, "%lx\n", dscr_default);
 551 }
 552
 553 /**
 554  * store_dscr_default() - Update the system wide DSCR default
 555  * @dev:        Device structure
 556  * @attr:       Device attribute structure
 557  * @buf:        Interface buffer
 558  * @count:      Size of the update
 559  *
 560  * This function updates the system wide DSCR default value.
 561  */
 562 static ssize_t __used store_dscr_default(struct device *dev,
 563                 struct device_attribute *attr, const char *buf,
 564                 size_t count)
 565 {
 566         unsigned long val;
 567         int ret = 0;
 568
 569         ret = sscanf(buf, "%lx", &val);
 570         if (ret != 1)
 571                 return -EINVAL;
 572         dscr_default = val;
 573
 574         on_each_cpu(write_dscr, &val, 1);
 575
 576         return count;
 577 }
 578
 579 static DEVICE_ATTR(dscr_default, 0600,
 580                 show_dscr_default, store_dscr_default);
 581
 582 static void sysfs_create_dscr_default(void)
 583 {
 584         if (cpu_has_feature(CPU_FTR_DSCR)) {
 585                 int err = 0;
 586                 int cpu;
 587
 588                 dscr_default = spr_default_dscr;
 589                 for_each_possible_cpu(cpu)
 590                         paca_ptrs[cpu]->dscr_default = dscr_default;
 591
 592                 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
 593         }
 594 }
 595
 596 #endif /* CONFIG_PPC64 */
 597
 598 #ifdef HAS_PPC_PMC_PA6T
 599 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
 600 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
 601 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
 602 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
 603 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
 604 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
 605 #ifdef CONFIG_DEBUG_KERNEL
 606 SYSFS_SPRSETUP(hid0, SPRN_HID0);
 607 SYSFS_SPRSETUP(hid1, SPRN_HID1);
 608 SYSFS_SPRSETUP(hid4, SPRN_HID4);
 609 SYSFS_SPRSETUP(hid5, SPRN_HID5);
 610 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
 611 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
 612 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
 613 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
 614 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
 615 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
 616 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
 617 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
 618 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
 619 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
 620 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
 621 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
 622 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
 623 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
 624 SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
 625 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
 626 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
 627 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
 628 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
 629 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
 630 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
 631 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
 632 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
 633 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
 634 #endif /* CONFIG_DEBUG_KERNEL */
 635 #endif /* HAS_PPC_PMC_PA6T */
 636
 637 #ifdef HAS_PPC_PMC_IBM
 638 static struct device_attribute ibm_common_attrs[] = {
 639         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 640         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 641 };
 642 #endif /* HAS_PPC_PMC_G4 */
 643
 644 #ifdef HAS_PPC_PMC_G4
 645 static struct device_attribute g4_common_attrs[] = {
 646         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 647         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 648         __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
 649 };
 650 #endif /* HAS_PPC_PMC_G4 */
 651
 652 static struct device_attribute classic_pmc_attrs[] = {
 653         __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
 654         __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
 655         __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
 656         __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
 657         __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
 658         __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
 659 #ifdef CONFIG_PPC64
 660         __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
 661         __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
 662 #endif
 663 };
 664
 665 #ifdef HAS_PPC_PMC_PA6T
 666 static struct device_attribute pa6t_attrs[] = {
 667         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 668         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 669         __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
 670         __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
 671         __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
 672         __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
 673         __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
 674         __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
 675 #ifdef CONFIG_DEBUG_KERNEL
 676         __ATTR(hid0, 0600, show_hid0, store_hid0),
 677         __ATTR(hid1, 0600, show_hid1, store_hid1),
 678         __ATTR(hid4, 0600, show_hid4, store_hid4),
 679         __ATTR(hid5, 0600, show_hid5, store_hid5),
 680         __ATTR(ima0, 0600, show_ima0, store_ima0),
 681         __ATTR(ima1, 0600, show_ima1, store_ima1),
 682         __ATTR(ima2, 0600, show_ima2, store_ima2),
 683         __ATTR(ima3, 0600, show_ima3, store_ima3),
 684         __ATTR(ima4, 0600, show_ima4, store_ima4),
 685         __ATTR(ima5, 0600, show_ima5, store_ima5),
 686         __ATTR(ima6, 0600, show_ima6, store_ima6),
 687         __ATTR(ima7, 0600, show_ima7, store_ima7),
 688         __ATTR(ima8, 0600, show_ima8, store_ima8),
 689         __ATTR(ima9, 0600, show_ima9, store_ima9),
 690         __ATTR(imaat, 0600, show_imaat, store_imaat),
 691         __ATTR(btcr, 0600, show_btcr, store_btcr),
 692         __ATTR(pccr, 0600, show_pccr, store_pccr),
 693         __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
 694         __ATTR(der, 0600, show_der, store_der),
 695         __ATTR(mer, 0600, show_mer, store_mer),
 696         __ATTR(ber, 0600, show_ber, store_ber),
 697         __ATTR(ier, 0600, show_ier, store_ier),
 698         __ATTR(sier, 0600, show_sier, store_sier),
 699         __ATTR(siar, 0600, show_siar, store_siar),
 700         __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
 701         __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
 702         __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
 703         __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
 704 #endif /* CONFIG_DEBUG_KERNEL */
 705 };
 706 #endif /* HAS_PPC_PMC_PA6T */
 707 #endif /* HAS_PPC_PMC_CLASSIC */
 708
 709 static int register_cpu_online(unsigned int cpu)
 710 {
 711         struct cpu *c = &per_cpu(cpu_devices, cpu);
 712         struct device *s = &c->dev;
 713         struct device_attribute *attrs, *pmc_attrs;
 714         int i, nattrs;
 715
 716         /* For cpus present at boot a reference was already grabbed in register_cpu() */
 717         if (!s->of_node)
 718                 s->of_node = of_get_cpu_node(cpu, NULL);
 719
 720 #ifdef CONFIG_PPC64
 721         if (cpu_has_feature(CPU_FTR_SMT))
 722                 device_create_file(s, &dev_attr_smt_snooze_delay);
 723 #endif
 724
 725         /* PMC stuff */
 726         switch (cur_cpu_spec->pmc_type) {
 727 #ifdef HAS_PPC_PMC_IBM
 728         case PPC_PMC_IBM:
 729                 attrs = ibm_common_attrs;
 730                 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
 731                 pmc_attrs = classic_pmc_attrs;
 732                 break;
 733 #endif /* HAS_PPC_PMC_IBM */
 734 #ifdef HAS_PPC_PMC_G4
 735         case PPC_PMC_G4:
 736                 attrs = g4_common_attrs;
 737                 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
 738                 pmc_attrs = classic_pmc_attrs;
 739                 break;
 740 #endif /* HAS_PPC_PMC_G4 */
 741 #ifdef HAS_PPC_PMC_PA6T
 742         case PPC_PMC_PA6T:
 743                 /* PA Semi starts counting at PMC0 */
 744                 attrs = pa6t_attrs;
 745                 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
 746                 pmc_attrs = NULL;
 747                 break;
 748 #endif /* HAS_PPC_PMC_PA6T */
 749         default:
 750                 attrs = NULL;
 751                 nattrs = 0;
 752                 pmc_attrs = NULL;
 753         }
 754
 755         for (i = 0; i < nattrs; i++)
 756                 device_create_file(s, &attrs[i]);
 757
 758         if (pmc_attrs)
 759                 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 760                         device_create_file(s, &pmc_attrs[i]);
 761
 762 #ifdef CONFIG_PPC64
 763         if (cpu_has_feature(CPU_FTR_MMCRA))
 764                 device_create_file(s, &dev_attr_mmcra);
 765
 766         if (cpu_has_feature(CPU_FTR_PURR)) {
 767                 if (!firmware_has_feature(FW_FEATURE_LPAR))
 768                         add_write_permission_dev_attr(&dev_attr_purr);
 769                 device_create_file(s, &dev_attr_purr);
 770         }
 771
 772         if (cpu_has_feature(CPU_FTR_SPURR))
 773                 device_create_file(s, &dev_attr_spurr);
 774
 775         if (cpu_has_feature(CPU_FTR_DSCR))
 776                 device_create_file(s, &dev_attr_dscr);
 777
 778         if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
 779                 device_create_file(s, &dev_attr_pir);
 780
 781         if (cpu_has_feature(CPU_FTR_ARCH_206) &&
 782                 !firmware_has_feature(FW_FEATURE_LPAR))
 783                 device_create_file(s, &dev_attr_tscr);
 784 #endif /* CONFIG_PPC64 */
 785
 786 #ifdef CONFIG_PPC_FSL_BOOK3E
 787         if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
 788                 device_create_file(s, &dev_attr_pw20_state);
 789                 device_create_file(s, &dev_attr_pw20_wait_time);
 790
 791                 device_create_file(s, &dev_attr_altivec_idle);
 792                 device_create_file(s, &dev_attr_altivec_idle_wait_time);
 793         }
 794 #endif
 795         cacheinfo_cpu_online(cpu);
 796         return 0;
 797 }
 798
 799 #ifdef CONFIG_HOTPLUG_CPU
 800 static int unregister_cpu_online(unsigned int cpu)
 801 {
 802         struct cpu *c = &per_cpu(cpu_devices, cpu);
 803         struct device *s = &c->dev;
 804         struct device_attribute *attrs, *pmc_attrs;
 805         int i, nattrs;
 806
 807         BUG_ON(!c->hotpluggable);
 808
 809 #ifdef CONFIG_PPC64
 810         if (cpu_has_feature(CPU_FTR_SMT))
 811                 device_remove_file(s, &dev_attr_smt_snooze_delay);
 812 #endif
 813
 814         /* PMC stuff */
 815         switch (cur_cpu_spec->pmc_type) {
 816 #ifdef HAS_PPC_PMC_IBM
 817         case PPC_PMC_IBM:
 818                 attrs = ibm_common_attrs;
 819                 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
 820                 pmc_attrs = classic_pmc_attrs;
 821                 break;
 822 #endif /* HAS_PPC_PMC_IBM */
 823 #ifdef HAS_PPC_PMC_G4
 824         case PPC_PMC_G4:
 825                 attrs = g4_common_attrs;
 826                 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
 827                 pmc_attrs = classic_pmc_attrs;
 828                 break;
 829 #endif /* HAS_PPC_PMC_G4 */
 830 #ifdef HAS_PPC_PMC_PA6T
 831         case PPC_PMC_PA6T:
 832                 /* PA Semi starts counting at PMC0 */
 833                 attrs = pa6t_attrs;
 834                 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
 835                 pmc_attrs = NULL;
 836                 break;
 837 #endif /* HAS_PPC_PMC_PA6T */
 838         default:
 839                 attrs = NULL;
 840                 nattrs = 0;
 841                 pmc_attrs = NULL;
 842         }
 843
 844         for (i = 0; i < nattrs; i++)
 845                 device_remove_file(s, &attrs[i]);
 846
 847         if (pmc_attrs)
 848                 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 849                         device_remove_file(s, &pmc_attrs[i]);
 850
 851 #ifdef CONFIG_PPC64
 852         if (cpu_has_feature(CPU_FTR_MMCRA))
 853                 device_remove_file(s, &dev_attr_mmcra);
 854
 855         if (cpu_has_feature(CPU_FTR_PURR))
 856                 device_remove_file(s, &dev_attr_purr);
 857
 858         if (cpu_has_feature(CPU_FTR_SPURR))
 859                 device_remove_file(s, &dev_attr_spurr);
 860
 861         if (cpu_has_feature(CPU_FTR_DSCR))
 862                 device_remove_file(s, &dev_attr_dscr);
 863
 864         if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
 865                 device_remove_file(s, &dev_attr_pir);
 866
 867         if (cpu_has_feature(CPU_FTR_ARCH_206) &&
 868                 !firmware_has_feature(FW_FEATURE_LPAR))
 869                 device_remove_file(s, &dev_attr_tscr);
 870 #endif /* CONFIG_PPC64 */
 871
 872 #ifdef CONFIG_PPC_FSL_BOOK3E
 873         if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
 874                 device_remove_file(s, &dev_attr_pw20_state);
 875                 device_remove_file(s, &dev_attr_pw20_wait_time);
 876
 877                 device_remove_file(s, &dev_attr_altivec_idle);
 878                 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
 879         }
 880 #endif
 881         cacheinfo_cpu_offline(cpu);
 882         of_node_put(s->of_node);
 883         s->of_node = NULL;
 884         return 0;
 885 }
 886 #else /* !CONFIG_HOTPLUG_CPU */
 887 #define unregister_cpu_online NULL
 888 #endif
 889
 890 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
 891 ssize_t arch_cpu_probe(const char *buf, size_t count)
 892 {
 893         if (ppc_md.cpu_probe)
 894                 return ppc_md.cpu_probe(buf, count);
 895
 896         return -EINVAL;
 897 }
 898
 899 ssize_t arch_cpu_release(const char *buf, size_t count)
 900 {
 901         if (ppc_md.cpu_release)
 902                 return ppc_md.cpu_release(buf, count);
 903
 904         return -EINVAL;
 905 }
 906 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
 907
 908 static DEFINE_MUTEX(cpu_mutex);
 909
 910 int cpu_add_dev_attr(struct device_attribute *attr)
 911 {
 912         int cpu;
 913
 914         mutex_lock(&cpu_mutex);
 915
 916         for_each_possible_cpu(cpu) {
 917                 device_create_file(get_cpu_device(cpu), attr);
 918         }
 919
 920         mutex_unlock(&cpu_mutex);
 921         return 0;
 922 }
 923 EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
 924
 925 int cpu_add_dev_attr_group(struct attribute_group *attrs)
 926 {
 927         int cpu;
 928         struct device *dev;
 929         int ret;
 930
 931         mutex_lock(&cpu_mutex);
 932
 933         for_each_possible_cpu(cpu) {
 934                 dev = get_cpu_device(cpu);
 935                 ret = sysfs_create_group(&dev->kobj, attrs);
 936                 WARN_ON(ret != 0);
 937         }
 938
 939         mutex_unlock(&cpu_mutex);
 940         return 0;
 941 }
 942 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
 943
 944
 945 void cpu_remove_dev_attr(struct device_attribute *attr)
 946 {
 947         int cpu;
 948
 949         mutex_lock(&cpu_mutex);
 950
 951         for_each_possible_cpu(cpu) {
 952                 device_remove_file(get_cpu_device(cpu), attr);
 953         }
 954
 955         mutex_unlock(&cpu_mutex);
 956 }
 957 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
 958
 959 void cpu_remove_dev_attr_group(struct attribute_group *attrs)
 960 {
 961         int cpu;
 962         struct device *dev;
 963
 964         mutex_lock(&cpu_mutex);
 965
 966         for_each_possible_cpu(cpu) {
 967                 dev = get_cpu_device(cpu);
 968                 sysfs_remove_group(&dev->kobj, attrs);
 969         }
 970
 971         mutex_unlock(&cpu_mutex);
 972 }
 973 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
 974
 975
 976 /* NUMA stuff */
 977
 978 #ifdef CONFIG_NUMA
 979 static void register_nodes(void)
 980 {
 981         int i;
 982
 983         for (i = 0; i < MAX_NUMNODES; i++)
 984                 register_one_node(i);
 985 }
 986
 987 int sysfs_add_device_to_node(struct device *dev, int nid)
 988 {
 989         struct node *node = node_devices[nid];
 990         return sysfs_create_link(&node->dev.kobj, &dev->kobj,
 991                         kobject_name(&dev->kobj));
 992 }
 993 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
 994
 995 void sysfs_remove_device_from_node(struct device *dev, int nid)
 996 {
 997         struct node *node = node_devices[nid];
 998         sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
 999 }
1000 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
1001
1002 #else
1003 static void register_nodes(void)
1004 {
1005         return;
1006 }
1007
1008 #endif
1009
1010 /* Only valid if CPU is present. */
1011 static ssize_t show_physical_id(struct device *dev,
1012                                 struct device_attribute *attr, char *buf)
1013 {
1014         struct cpu *cpu = container_of(dev, struct cpu, dev);
1015
1016         return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1017 }
1018 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1019
1020 static int __init topology_init(void)
1021 {
1022         int cpu, r;
1023
1024         register_nodes();
1025
1026         for_each_possible_cpu(cpu) {
1027                 struct cpu *c = &per_cpu(cpu_devices, cpu);
1028
1029                 /*
1030                  * For now, we just see if the system supports making
1031                  * the RTAS calls for CPU hotplug.  But, there may be a
1032                  * more comprehensive way to do this for an individual
1033                  * CPU.  For instance, the boot cpu might never be valid
1034                  * for hotplugging.
1035                  */
1036                 if (ppc_md.cpu_die)
1037                         c->hotpluggable = 1;
1038
1039                 if (cpu_online(cpu) || c->hotpluggable) {
1040                         register_cpu(c, cpu);
1041
1042                         device_create_file(&c->dev, &dev_attr_physical_id);
1043                 }
1044         }
1045         r = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "powerpc/topology:online",
1046                               register_cpu_online, unregister_cpu_online);
1047         WARN_ON(r < 0);
1048 #ifdef CONFIG_PPC64
1049         sysfs_create_dscr_default();
1050 #endif /* CONFIG_PPC64 */
1051
1052         return 0;
1053 }
1054 subsys_initcall(topology_init);