arch/powerpc/kernel/sysfs.c

   1 #include <linux/device.h>
   2 #include <linux/cpu.h>
   3 #include <linux/smp.h>
   4 #include <linux/percpu.h>
   5 #include <linux/init.h>
   6 #include <linux/sched.h>
   7 #include <linux/export.h>
   8 #include <linux/nodemask.h>
   9 #include <linux/cpumask.h>
  10 #include <linux/notifier.h>
  11
  12 #include <asm/current.h>
  13 #include <asm/processor.h>
  14 #include <asm/cputable.h>
  15 #include <asm/hvcall.h>
  16 #include <asm/prom.h>
  17 #include <asm/machdep.h>
  18 #include <asm/smp.h>
  19 #include <asm/pmc.h>
  20 #include <asm/firmware.h>
  21
  22 #include "cacheinfo.h"
  23
  24 #ifdef CONFIG_PPC64
  25 #include <asm/paca.h>
  26 #include <asm/lppaca.h>
  27 #endif
  28
  29 static DEFINE_PER_CPU(struct cpu, cpu_devices);
  30
  31 #ifdef CONFIG_PPC64
  32
  33 /*
  34  * Snooze delay has not been hooked up since 3fa8cad82b94 ("powerpc/pseries/cpuidle:
  35  * smt-snooze-delay cleanup.") and has been broken even longer. As was foretold in
  36  * 2014:
  37  *
  38  *  "ppc64_util currently utilises it. Once we fix ppc64_util, propose to clean
  39  *  up the kernel code."
  40  *
  41  * powerpc-utils stopped using it as of 1.3.8. At some point in the future this
  42  * code should be removed.
  43  */
  44
  45 static ssize_t store_smt_snooze_delay(struct device *dev,
  46                                       struct device_attribute *attr,
  47                                       const char *buf,
  48                                       size_t count)
  49 {
  50         pr_warn_once("%s (%d) stored to unsupported smt_snooze_delay, which has no effect.\n",
  51                      current->comm, current->pid);
  52         return count;
  53 }
  54
  55 static ssize_t show_smt_snooze_delay(struct device *dev,
  56                                      struct device_attribute *attr,
  57                                      char *buf)
  58 {
  59         pr_warn_once("%s (%d) read from unsupported smt_snooze_delay\n",
  60                      current->comm, current->pid);
  61         return sprintf(buf, "100\n");
  62 }
  63
  64 static DEVICE_ATTR(smt_snooze_delay, 0644, show_smt_snooze_delay,
  65                    store_smt_snooze_delay);
  66
  67 static int __init setup_smt_snooze_delay(char *str)
  68 {
  69         if (!cpu_has_feature(CPU_FTR_SMT))
  70                 return 1;
  71
  72         pr_warn("smt-snooze-delay command line option has no effect\n");
  73         return 1;
  74 }
  75 __setup("smt-snooze-delay=", setup_smt_snooze_delay);
  76
  77 #endif /* CONFIG_PPC64 */
  78
  79 #ifdef CONFIG_PPC_FSL_BOOK3E
  80 #define MAX_BIT                         63
  81
  82 static u64 pw20_wt;
  83 static u64 altivec_idle_wt;
  84
  85 static unsigned int get_idle_ticks_bit(u64 ns)
  86 {
  87         u64 cycle;
  88
  89         if (ns >= 10000)
  90                 cycle = div_u64(ns + 500, 1000) * tb_ticks_per_usec;
  91         else
  92                 cycle = div_u64(ns * tb_ticks_per_usec, 1000);
  93
  94         if (!cycle)
  95                 return 0;
  96
  97         return ilog2(cycle);
  98 }
  99
 100 static void do_show_pwrmgtcr0(void *val)
 101 {
 102         u32 *value = val;
 103
 104         *value = mfspr(SPRN_PWRMGTCR0);
 105 }
 106
 107 static ssize_t show_pw20_state(struct device *dev,
 108                                 struct device_attribute *attr, char *buf)
 109 {
 110         u32 value;
 111         unsigned int cpu = dev->id;
 112
 113         smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 114
 115         value &= PWRMGTCR0_PW20_WAIT;
 116
 117         return sprintf(buf, "%u\n", value ? 1 : 0);
 118 }
 119
 120 static void do_store_pw20_state(void *val)
 121 {
 122         u32 *value = val;
 123         u32 pw20_state;
 124
 125         pw20_state = mfspr(SPRN_PWRMGTCR0);
 126
 127         if (*value)
 128                 pw20_state |= PWRMGTCR0_PW20_WAIT;
 129         else
 130                 pw20_state &= ~PWRMGTCR0_PW20_WAIT;
 131
 132         mtspr(SPRN_PWRMGTCR0, pw20_state);
 133 }
 134
 135 static ssize_t store_pw20_state(struct device *dev,
 136                                 struct device_attribute *attr,
 137                                 const char *buf, size_t count)
 138 {
 139         u32 value;
 140         unsigned int cpu = dev->id;
 141
 142         if (kstrtou32(buf, 0, &value))
 143                 return -EINVAL;
 144
 145         if (value > 1)
 146                 return -EINVAL;
 147
 148         smp_call_function_single(cpu, do_store_pw20_state, &value, 1);
 149
 150         return count;
 151 }
 152
 153 static ssize_t show_pw20_wait_time(struct device *dev,
 154                                 struct device_attribute *attr, char *buf)
 155 {
 156         u32 value;
 157         u64 tb_cycle = 1;
 158         u64 time;
 159
 160         unsigned int cpu = dev->id;
 161
 162         if (!pw20_wt) {
 163                 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 164                 value = (value & PWRMGTCR0_PW20_ENT) >>
 165                                         PWRMGTCR0_PW20_ENT_SHIFT;
 166
 167                 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 168                 /* convert ms to ns */
 169                 if (tb_ticks_per_usec > 1000) {
 170                         time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 171                 } else {
 172                         u32 rem_us;
 173
 174                         time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 175                                                 &rem_us);
 176                         time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 177                 }
 178         } else {
 179                 time = pw20_wt;
 180         }
 181
 182         return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 183 }
 184
 185 static void set_pw20_wait_entry_bit(void *val)
 186 {
 187         u32 *value = val;
 188         u32 pw20_idle;
 189
 190         pw20_idle = mfspr(SPRN_PWRMGTCR0);
 191
 192         /* Set Automatic PW20 Core Idle Count */
 193         /* clear count */
 194         pw20_idle &= ~PWRMGTCR0_PW20_ENT;
 195
 196         /* set count */
 197         pw20_idle |= ((MAX_BIT - *value) << PWRMGTCR0_PW20_ENT_SHIFT);
 198
 199         mtspr(SPRN_PWRMGTCR0, pw20_idle);
 200 }
 201
 202 static ssize_t store_pw20_wait_time(struct device *dev,
 203                                 struct device_attribute *attr,
 204                                 const char *buf, size_t count)
 205 {
 206         u32 entry_bit;
 207         u64 value;
 208
 209         unsigned int cpu = dev->id;
 210
 211         if (kstrtou64(buf, 0, &value))
 212                 return -EINVAL;
 213
 214         if (!value)
 215                 return -EINVAL;
 216
 217         entry_bit = get_idle_ticks_bit(value);
 218         if (entry_bit > MAX_BIT)
 219                 return -EINVAL;
 220
 221         pw20_wt = value;
 222
 223         smp_call_function_single(cpu, set_pw20_wait_entry_bit,
 224                                 &entry_bit, 1);
 225
 226         return count;
 227 }
 228
 229 static ssize_t show_altivec_idle(struct device *dev,
 230                                 struct device_attribute *attr, char *buf)
 231 {
 232         u32 value;
 233         unsigned int cpu = dev->id;
 234
 235         smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 236
 237         value &= PWRMGTCR0_AV_IDLE_PD_EN;
 238
 239         return sprintf(buf, "%u\n", value ? 1 : 0);
 240 }
 241
 242 static void do_store_altivec_idle(void *val)
 243 {
 244         u32 *value = val;
 245         u32 altivec_idle;
 246
 247         altivec_idle = mfspr(SPRN_PWRMGTCR0);
 248
 249         if (*value)
 250                 altivec_idle |= PWRMGTCR0_AV_IDLE_PD_EN;
 251         else
 252                 altivec_idle &= ~PWRMGTCR0_AV_IDLE_PD_EN;
 253
 254         mtspr(SPRN_PWRMGTCR0, altivec_idle);
 255 }
 256
 257 static ssize_t store_altivec_idle(struct device *dev,
 258                                 struct device_attribute *attr,
 259                                 const char *buf, size_t count)
 260 {
 261         u32 value;
 262         unsigned int cpu = dev->id;
 263
 264         if (kstrtou32(buf, 0, &value))
 265                 return -EINVAL;
 266
 267         if (value > 1)
 268                 return -EINVAL;
 269
 270         smp_call_function_single(cpu, do_store_altivec_idle, &value, 1);
 271
 272         return count;
 273 }
 274
 275 static ssize_t show_altivec_idle_wait_time(struct device *dev,
 276                                 struct device_attribute *attr, char *buf)
 277 {
 278         u32 value;
 279         u64 tb_cycle = 1;
 280         u64 time;
 281
 282         unsigned int cpu = dev->id;
 283
 284         if (!altivec_idle_wt) {
 285                 smp_call_function_single(cpu, do_show_pwrmgtcr0, &value, 1);
 286                 value = (value & PWRMGTCR0_AV_IDLE_CNT) >>
 287                                         PWRMGTCR0_AV_IDLE_CNT_SHIFT;
 288
 289                 tb_cycle = (tb_cycle << (MAX_BIT - value + 1));
 290                 /* convert ms to ns */
 291                 if (tb_ticks_per_usec > 1000) {
 292                         time = div_u64(tb_cycle, tb_ticks_per_usec / 1000);
 293                 } else {
 294                         u32 rem_us;
 295
 296                         time = div_u64_rem(tb_cycle, tb_ticks_per_usec,
 297                                                 &rem_us);
 298                         time = time * 1000 + rem_us * 1000 / tb_ticks_per_usec;
 299                 }
 300         } else {
 301                 time = altivec_idle_wt;
 302         }
 303
 304         return sprintf(buf, "%llu\n", time > 0 ? time : 0);
 305 }
 306
 307 static void set_altivec_idle_wait_entry_bit(void *val)
 308 {
 309         u32 *value = val;
 310         u32 altivec_idle;
 311
 312         altivec_idle = mfspr(SPRN_PWRMGTCR0);
 313
 314         /* Set Automatic AltiVec Idle Count */
 315         /* clear count */
 316         altivec_idle &= ~PWRMGTCR0_AV_IDLE_CNT;
 317
 318         /* set count */
 319         altivec_idle |= ((MAX_BIT - *value) << PWRMGTCR0_AV_IDLE_CNT_SHIFT);
 320
 321         mtspr(SPRN_PWRMGTCR0, altivec_idle);
 322 }
 323
 324 static ssize_t store_altivec_idle_wait_time(struct device *dev,
 325                                 struct device_attribute *attr,
 326                                 const char *buf, size_t count)
 327 {
 328         u32 entry_bit;
 329         u64 value;
 330
 331         unsigned int cpu = dev->id;
 332
 333         if (kstrtou64(buf, 0, &value))
 334                 return -EINVAL;
 335
 336         if (!value)
 337                 return -EINVAL;
 338
 339         entry_bit = get_idle_ticks_bit(value);
 340         if (entry_bit > MAX_BIT)
 341                 return -EINVAL;
 342
 343         altivec_idle_wt = value;
 344
 345         smp_call_function_single(cpu, set_altivec_idle_wait_entry_bit,
 346                                 &entry_bit, 1);
 347
 348         return count;
 349 }
 350
 351 /*
 352  * Enable/Disable interface:
 353  * 0, disable. 1, enable.
 354  */
 355 static DEVICE_ATTR(pw20_state, 0600, show_pw20_state, store_pw20_state);
 356 static DEVICE_ATTR(altivec_idle, 0600, show_altivec_idle, store_altivec_idle);
 357
 358 /*
 359  * Set wait time interface:(Nanosecond)
 360  * Example: Base on TBfreq is 41MHZ.
 361  * 1~48(ns): TB[63]
 362  * 49~97(ns): TB[62]
 363  * 98~195(ns): TB[61]
 364  * 196~390(ns): TB[60]
 365  * 391~780(ns): TB[59]
 366  * 781~1560(ns): TB[58]
 367  * ...
 368  */
 369 static DEVICE_ATTR(pw20_wait_time, 0600,
 370                         show_pw20_wait_time,
 371                         store_pw20_wait_time);
 372 static DEVICE_ATTR(altivec_idle_wait_time, 0600,
 373                         show_altivec_idle_wait_time,
 374                         store_altivec_idle_wait_time);
 375 #endif
 376
 377 /*
 378  * Enabling PMCs will slow partition context switch times so we only do
 379  * it the first time we write to the PMCs.
 380  */
 381
 382 static DEFINE_PER_CPU(char, pmcs_enabled);
 383
 384 void ppc_enable_pmcs(void)
 385 {
 386         ppc_set_pmu_inuse(1);
 387
 388         /* Only need to enable them once */
 389         if (__this_cpu_read(pmcs_enabled))
 390                 return;
 391
 392         __this_cpu_write(pmcs_enabled, 1);
 393
 394         if (ppc_md.enable_pmcs)
 395                 ppc_md.enable_pmcs();
 396 }
 397 EXPORT_SYMBOL(ppc_enable_pmcs);
 398
 399 #define __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, EXTRA) \
 400 static void read_##NAME(void *val) \
 401 { \
 402         *(unsigned long *)val = mfspr(ADDRESS); \
 403 } \
 404 static void write_##NAME(void *val) \
 405 { \
 406         EXTRA; \
 407         mtspr(ADDRESS, *(unsigned long *)val);  \
 408 }
 409
 410 #define __SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 411 static ssize_t show_##NAME(struct device *dev, \
 412                         struct device_attribute *attr, \
 413                         char *buf) \
 414 { \
 415         struct cpu *cpu = container_of(dev, struct cpu, dev); \
 416         unsigned long val; \
 417         smp_call_function_single(cpu->dev.id, read_##NAME, &val, 1);    \
 418         return sprintf(buf, "%lx\n", val); \
 419 } \
 420 static ssize_t __used \
 421         store_##NAME(struct device *dev, struct device_attribute *attr, \
 422                         const char *buf, size_t count) \
 423 { \
 424         struct cpu *cpu = container_of(dev, struct cpu, dev); \
 425         unsigned long val; \
 426         int ret = sscanf(buf, "%lx", &val); \
 427         if (ret != 1) \
 428                 return -EINVAL; \
 429         smp_call_function_single(cpu->dev.id, write_##NAME, &val, 1); \
 430         return count; \
 431 }
 432
 433 #define SYSFS_PMCSETUP(NAME, ADDRESS) \
 434         __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ppc_enable_pmcs()) \
 435         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 436 #define SYSFS_SPRSETUP(NAME, ADDRESS) \
 437         __SYSFS_SPRSETUP_READ_WRITE(NAME, ADDRESS, ) \
 438         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 439
 440 #define SYSFS_SPRSETUP_SHOW_STORE(NAME) \
 441         __SYSFS_SPRSETUP_SHOW_STORE(NAME)
 442
 443 /* Let's define all possible registers, we'll only hook up the ones
 444  * that are implemented on the current processor
 445  */
 446
 447 #if defined(CONFIG_PPC64)
 448 #define HAS_PPC_PMC_CLASSIC     1
 449 #define HAS_PPC_PMC_IBM         1
 450 #define HAS_PPC_PMC_PA6T        1
 451 #elif defined(CONFIG_6xx)
 452 #define HAS_PPC_PMC_CLASSIC     1
 453 #define HAS_PPC_PMC_IBM         1
 454 #define HAS_PPC_PMC_G4          1
 455 #endif
 456
 457
 458 #ifdef HAS_PPC_PMC_CLASSIC
 459 SYSFS_PMCSETUP(mmcr0, SPRN_MMCR0);
 460 SYSFS_PMCSETUP(mmcr1, SPRN_MMCR1);
 461 SYSFS_PMCSETUP(pmc1, SPRN_PMC1);
 462 SYSFS_PMCSETUP(pmc2, SPRN_PMC2);
 463 SYSFS_PMCSETUP(pmc3, SPRN_PMC3);
 464 SYSFS_PMCSETUP(pmc4, SPRN_PMC4);
 465 SYSFS_PMCSETUP(pmc5, SPRN_PMC5);
 466 SYSFS_PMCSETUP(pmc6, SPRN_PMC6);
 467
 468 #ifdef HAS_PPC_PMC_G4
 469 SYSFS_PMCSETUP(mmcr2, SPRN_MMCR2);
 470 #endif
 471
 472 #ifdef CONFIG_PPC64
 473 SYSFS_PMCSETUP(pmc7, SPRN_PMC7);
 474 SYSFS_PMCSETUP(pmc8, SPRN_PMC8);
 475
 476 SYSFS_PMCSETUP(mmcra, SPRN_MMCRA);
 477 SYSFS_SPRSETUP(purr, SPRN_PURR);
 478 SYSFS_SPRSETUP(spurr, SPRN_SPURR);
 479 SYSFS_SPRSETUP(pir, SPRN_PIR);
 480
 481 /*
 482   Lets only enable read for phyp resources and
 483   enable write when needed with a separate function.
 484   Lets be conservative and default to pseries.
 485 */
 486 static DEVICE_ATTR(mmcra, 0600, show_mmcra, store_mmcra);
 487 static DEVICE_ATTR(spurr, 0400, show_spurr, NULL);
 488 static DEVICE_ATTR(purr, 0400, show_purr, store_purr);
 489 static DEVICE_ATTR(pir, 0400, show_pir, NULL);
 490
 491 /*
 492  * This is the system wide DSCR register default value. Any
 493  * change to this default value through the sysfs interface
 494  * will update all per cpu DSCR default values across the
 495  * system stored in their respective PACA structures.
 496  */
 497 static unsigned long dscr_default;
 498
 499 /**
 500  * read_dscr() - Fetch the cpu specific DSCR default
 501  * @val:        Returned cpu specific DSCR default value
 502  *
 503  * This function returns the per cpu DSCR default value
 504  * for any cpu which is contained in it's PACA structure.
 505  */
 506 static void read_dscr(void *val)
 507 {
 508         *(unsigned long *)val = get_paca()->dscr_default;
 509 }
 510
 511
 512 /**
 513  * write_dscr() - Update the cpu specific DSCR default
 514  * @val:        New cpu specific DSCR default value to update
 515  *
 516  * This function updates the per cpu DSCR default value
 517  * for any cpu which is contained in it's PACA structure.
 518  */
 519 static void write_dscr(void *val)
 520 {
 521         get_paca()->dscr_default = *(unsigned long *)val;
 522         if (!current->thread.dscr_inherit) {
 523                 current->thread.dscr = *(unsigned long *)val;
 524                 mtspr(SPRN_DSCR, *(unsigned long *)val);
 525         }
 526 }
 527
 528 SYSFS_SPRSETUP_SHOW_STORE(dscr);
 529 static DEVICE_ATTR(dscr, 0600, show_dscr, store_dscr);
 530
 531 static void add_write_permission_dev_attr(struct device_attribute *attr)
 532 {
 533         attr->attr.mode |= 0200;
 534 }
 535
 536 /**
 537  * show_dscr_default() - Fetch the system wide DSCR default
 538  * @dev:        Device structure
 539  * @attr:       Device attribute structure
 540  * @buf:        Interface buffer
 541  *
 542  * This function returns the system wide DSCR default value.
 543  */
 544 static ssize_t show_dscr_default(struct device *dev,
 545                 struct device_attribute *attr, char *buf)
 546 {
 547         return sprintf(buf, "%lx\n", dscr_default);
 548 }
 549
 550 /**
 551  * store_dscr_default() - Update the system wide DSCR default
 552  * @dev:        Device structure
 553  * @attr:       Device attribute structure
 554  * @buf:        Interface buffer
 555  * @count:      Size of the update
 556  *
 557  * This function updates the system wide DSCR default value.
 558  */
 559 static ssize_t __used store_dscr_default(struct device *dev,
 560                 struct device_attribute *attr, const char *buf,
 561                 size_t count)
 562 {
 563         unsigned long val;
 564         int ret = 0;
 565
 566         ret = sscanf(buf, "%lx", &val);
 567         if (ret != 1)
 568                 return -EINVAL;
 569         dscr_default = val;
 570
 571         on_each_cpu(write_dscr, &val, 1);
 572
 573         return count;
 574 }
 575
 576 static DEVICE_ATTR(dscr_default, 0600,
 577                 show_dscr_default, store_dscr_default);
 578
 579 static void sysfs_create_dscr_default(void)
 580 {
 581         int err = 0;
 582         if (cpu_has_feature(CPU_FTR_DSCR))
 583                 err = device_create_file(cpu_subsys.dev_root, &dev_attr_dscr_default);
 584 }
 585 #endif /* CONFIG_PPC64 */
 586
 587 #ifdef HAS_PPC_PMC_PA6T
 588 SYSFS_PMCSETUP(pa6t_pmc0, SPRN_PA6T_PMC0);
 589 SYSFS_PMCSETUP(pa6t_pmc1, SPRN_PA6T_PMC1);
 590 SYSFS_PMCSETUP(pa6t_pmc2, SPRN_PA6T_PMC2);
 591 SYSFS_PMCSETUP(pa6t_pmc3, SPRN_PA6T_PMC3);
 592 SYSFS_PMCSETUP(pa6t_pmc4, SPRN_PA6T_PMC4);
 593 SYSFS_PMCSETUP(pa6t_pmc5, SPRN_PA6T_PMC5);
 594 #ifdef CONFIG_DEBUG_KERNEL
 595 SYSFS_SPRSETUP(hid0, SPRN_HID0);
 596 SYSFS_SPRSETUP(hid1, SPRN_HID1);
 597 SYSFS_SPRSETUP(hid4, SPRN_HID4);
 598 SYSFS_SPRSETUP(hid5, SPRN_HID5);
 599 SYSFS_SPRSETUP(ima0, SPRN_PA6T_IMA0);
 600 SYSFS_SPRSETUP(ima1, SPRN_PA6T_IMA1);
 601 SYSFS_SPRSETUP(ima2, SPRN_PA6T_IMA2);
 602 SYSFS_SPRSETUP(ima3, SPRN_PA6T_IMA3);
 603 SYSFS_SPRSETUP(ima4, SPRN_PA6T_IMA4);
 604 SYSFS_SPRSETUP(ima5, SPRN_PA6T_IMA5);
 605 SYSFS_SPRSETUP(ima6, SPRN_PA6T_IMA6);
 606 SYSFS_SPRSETUP(ima7, SPRN_PA6T_IMA7);
 607 SYSFS_SPRSETUP(ima8, SPRN_PA6T_IMA8);
 608 SYSFS_SPRSETUP(ima9, SPRN_PA6T_IMA9);
 609 SYSFS_SPRSETUP(imaat, SPRN_PA6T_IMAAT);
 610 SYSFS_SPRSETUP(btcr, SPRN_PA6T_BTCR);
 611 SYSFS_SPRSETUP(pccr, SPRN_PA6T_PCCR);
 612 SYSFS_SPRSETUP(rpccr, SPRN_PA6T_RPCCR);
 613 SYSFS_SPRSETUP(der, SPRN_PA6T_DER);
 614 SYSFS_SPRSETUP(mer, SPRN_PA6T_MER);
 615 SYSFS_SPRSETUP(ber, SPRN_PA6T_BER);
 616 SYSFS_SPRSETUP(ier, SPRN_PA6T_IER);
 617 SYSFS_SPRSETUP(sier, SPRN_PA6T_SIER);
 618 SYSFS_SPRSETUP(siar, SPRN_PA6T_SIAR);
 619 SYSFS_SPRSETUP(tsr0, SPRN_PA6T_TSR0);
 620 SYSFS_SPRSETUP(tsr1, SPRN_PA6T_TSR1);
 621 SYSFS_SPRSETUP(tsr2, SPRN_PA6T_TSR2);
 622 SYSFS_SPRSETUP(tsr3, SPRN_PA6T_TSR3);
 623 #endif /* CONFIG_DEBUG_KERNEL */
 624 #endif /* HAS_PPC_PMC_PA6T */
 625
 626 #ifdef HAS_PPC_PMC_IBM
 627 static struct device_attribute ibm_common_attrs[] = {
 628         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 629         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 630 };
 631 #endif /* HAS_PPC_PMC_G4 */
 632
 633 #ifdef HAS_PPC_PMC_G4
 634 static struct device_attribute g4_common_attrs[] = {
 635         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 636         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 637         __ATTR(mmcr2, 0600, show_mmcr2, store_mmcr2),
 638 };
 639 #endif /* HAS_PPC_PMC_G4 */
 640
 641 static struct device_attribute classic_pmc_attrs[] = {
 642         __ATTR(pmc1, 0600, show_pmc1, store_pmc1),
 643         __ATTR(pmc2, 0600, show_pmc2, store_pmc2),
 644         __ATTR(pmc3, 0600, show_pmc3, store_pmc3),
 645         __ATTR(pmc4, 0600, show_pmc4, store_pmc4),
 646         __ATTR(pmc5, 0600, show_pmc5, store_pmc5),
 647         __ATTR(pmc6, 0600, show_pmc6, store_pmc6),
 648 #ifdef CONFIG_PPC64
 649         __ATTR(pmc7, 0600, show_pmc7, store_pmc7),
 650         __ATTR(pmc8, 0600, show_pmc8, store_pmc8),
 651 #endif
 652 };
 653
 654 #ifdef HAS_PPC_PMC_PA6T
 655 static struct device_attribute pa6t_attrs[] = {
 656         __ATTR(mmcr0, 0600, show_mmcr0, store_mmcr0),
 657         __ATTR(mmcr1, 0600, show_mmcr1, store_mmcr1),
 658         __ATTR(pmc0, 0600, show_pa6t_pmc0, store_pa6t_pmc0),
 659         __ATTR(pmc1, 0600, show_pa6t_pmc1, store_pa6t_pmc1),
 660         __ATTR(pmc2, 0600, show_pa6t_pmc2, store_pa6t_pmc2),
 661         __ATTR(pmc3, 0600, show_pa6t_pmc3, store_pa6t_pmc3),
 662         __ATTR(pmc4, 0600, show_pa6t_pmc4, store_pa6t_pmc4),
 663         __ATTR(pmc5, 0600, show_pa6t_pmc5, store_pa6t_pmc5),
 664 #ifdef CONFIG_DEBUG_KERNEL
 665         __ATTR(hid0, 0600, show_hid0, store_hid0),
 666         __ATTR(hid1, 0600, show_hid1, store_hid1),
 667         __ATTR(hid4, 0600, show_hid4, store_hid4),
 668         __ATTR(hid5, 0600, show_hid5, store_hid5),
 669         __ATTR(ima0, 0600, show_ima0, store_ima0),
 670         __ATTR(ima1, 0600, show_ima1, store_ima1),
 671         __ATTR(ima2, 0600, show_ima2, store_ima2),
 672         __ATTR(ima3, 0600, show_ima3, store_ima3),
 673         __ATTR(ima4, 0600, show_ima4, store_ima4),
 674         __ATTR(ima5, 0600, show_ima5, store_ima5),
 675         __ATTR(ima6, 0600, show_ima6, store_ima6),
 676         __ATTR(ima7, 0600, show_ima7, store_ima7),
 677         __ATTR(ima8, 0600, show_ima8, store_ima8),
 678         __ATTR(ima9, 0600, show_ima9, store_ima9),
 679         __ATTR(imaat, 0600, show_imaat, store_imaat),
 680         __ATTR(btcr, 0600, show_btcr, store_btcr),
 681         __ATTR(pccr, 0600, show_pccr, store_pccr),
 682         __ATTR(rpccr, 0600, show_rpccr, store_rpccr),
 683         __ATTR(der, 0600, show_der, store_der),
 684         __ATTR(mer, 0600, show_mer, store_mer),
 685         __ATTR(ber, 0600, show_ber, store_ber),
 686         __ATTR(ier, 0600, show_ier, store_ier),
 687         __ATTR(sier, 0600, show_sier, store_sier),
 688         __ATTR(siar, 0600, show_siar, store_siar),
 689         __ATTR(tsr0, 0600, show_tsr0, store_tsr0),
 690         __ATTR(tsr1, 0600, show_tsr1, store_tsr1),
 691         __ATTR(tsr2, 0600, show_tsr2, store_tsr2),
 692         __ATTR(tsr3, 0600, show_tsr3, store_tsr3),
 693 #endif /* CONFIG_DEBUG_KERNEL */
 694 };
 695 #endif /* HAS_PPC_PMC_PA6T */
 696 #endif /* HAS_PPC_PMC_CLASSIC */
 697
 698 static void register_cpu_online(unsigned int cpu)
 699 {
 700         struct cpu *c = &per_cpu(cpu_devices, cpu);
 701         struct device *s = &c->dev;
 702         struct device_attribute *attrs, *pmc_attrs;
 703         int i, nattrs;
 704
 705 #ifdef CONFIG_PPC64
 706         if (cpu_has_feature(CPU_FTR_SMT))
 707                 device_create_file(s, &dev_attr_smt_snooze_delay);
 708 #endif
 709
 710         /* PMC stuff */
 711         switch (cur_cpu_spec->pmc_type) {
 712 #ifdef HAS_PPC_PMC_IBM
 713         case PPC_PMC_IBM:
 714                 attrs = ibm_common_attrs;
 715                 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
 716                 pmc_attrs = classic_pmc_attrs;
 717                 break;
 718 #endif /* HAS_PPC_PMC_IBM */
 719 #ifdef HAS_PPC_PMC_G4
 720         case PPC_PMC_G4:
 721                 attrs = g4_common_attrs;
 722                 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
 723                 pmc_attrs = classic_pmc_attrs;
 724                 break;
 725 #endif /* HAS_PPC_PMC_G4 */
 726 #ifdef HAS_PPC_PMC_PA6T
 727         case PPC_PMC_PA6T:
 728                 /* PA Semi starts counting at PMC0 */
 729                 attrs = pa6t_attrs;
 730                 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
 731                 pmc_attrs = NULL;
 732                 break;
 733 #endif /* HAS_PPC_PMC_PA6T */
 734         default:
 735                 attrs = NULL;
 736                 nattrs = 0;
 737                 pmc_attrs = NULL;
 738         }
 739
 740         for (i = 0; i < nattrs; i++)
 741                 device_create_file(s, &attrs[i]);
 742
 743         if (pmc_attrs)
 744                 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 745                         device_create_file(s, &pmc_attrs[i]);
 746
 747 #ifdef CONFIG_PPC64
 748         if (cpu_has_feature(CPU_FTR_MMCRA))
 749                 device_create_file(s, &dev_attr_mmcra);
 750
 751         if (cpu_has_feature(CPU_FTR_PURR)) {
 752                 if (!firmware_has_feature(FW_FEATURE_LPAR))
 753                         add_write_permission_dev_attr(&dev_attr_purr);
 754                 device_create_file(s, &dev_attr_purr);
 755         }
 756
 757         if (cpu_has_feature(CPU_FTR_SPURR))
 758                 device_create_file(s, &dev_attr_spurr);
 759
 760         if (cpu_has_feature(CPU_FTR_DSCR))
 761                 device_create_file(s, &dev_attr_dscr);
 762
 763         if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
 764                 device_create_file(s, &dev_attr_pir);
 765 #endif /* CONFIG_PPC64 */
 766
 767 #ifdef CONFIG_PPC_FSL_BOOK3E
 768         if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
 769                 device_create_file(s, &dev_attr_pw20_state);
 770                 device_create_file(s, &dev_attr_pw20_wait_time);
 771
 772                 device_create_file(s, &dev_attr_altivec_idle);
 773                 device_create_file(s, &dev_attr_altivec_idle_wait_time);
 774         }
 775 #endif
 776         cacheinfo_cpu_online(cpu);
 777 }
 778
 779 #ifdef CONFIG_HOTPLUG_CPU
 780 static void unregister_cpu_online(unsigned int cpu)
 781 {
 782         struct cpu *c = &per_cpu(cpu_devices, cpu);
 783         struct device *s = &c->dev;
 784         struct device_attribute *attrs, *pmc_attrs;
 785         int i, nattrs;
 786
 787         BUG_ON(!c->hotpluggable);
 788
 789 #ifdef CONFIG_PPC64
 790         if (cpu_has_feature(CPU_FTR_SMT))
 791                 device_remove_file(s, &dev_attr_smt_snooze_delay);
 792 #endif
 793
 794         /* PMC stuff */
 795         switch (cur_cpu_spec->pmc_type) {
 796 #ifdef HAS_PPC_PMC_IBM
 797         case PPC_PMC_IBM:
 798                 attrs = ibm_common_attrs;
 799                 nattrs = sizeof(ibm_common_attrs) / sizeof(struct device_attribute);
 800                 pmc_attrs = classic_pmc_attrs;
 801                 break;
 802 #endif /* HAS_PPC_PMC_IBM */
 803 #ifdef HAS_PPC_PMC_G4
 804         case PPC_PMC_G4:
 805                 attrs = g4_common_attrs;
 806                 nattrs = sizeof(g4_common_attrs) / sizeof(struct device_attribute);
 807                 pmc_attrs = classic_pmc_attrs;
 808                 break;
 809 #endif /* HAS_PPC_PMC_G4 */
 810 #ifdef HAS_PPC_PMC_PA6T
 811         case PPC_PMC_PA6T:
 812                 /* PA Semi starts counting at PMC0 */
 813                 attrs = pa6t_attrs;
 814                 nattrs = sizeof(pa6t_attrs) / sizeof(struct device_attribute);
 815                 pmc_attrs = NULL;
 816                 break;
 817 #endif /* HAS_PPC_PMC_PA6T */
 818         default:
 819                 attrs = NULL;
 820                 nattrs = 0;
 821                 pmc_attrs = NULL;
 822         }
 823
 824         for (i = 0; i < nattrs; i++)
 825                 device_remove_file(s, &attrs[i]);
 826
 827         if (pmc_attrs)
 828                 for (i = 0; i < cur_cpu_spec->num_pmcs; i++)
 829                         device_remove_file(s, &pmc_attrs[i]);
 830
 831 #ifdef CONFIG_PPC64
 832         if (cpu_has_feature(CPU_FTR_MMCRA))
 833                 device_remove_file(s, &dev_attr_mmcra);
 834
 835         if (cpu_has_feature(CPU_FTR_PURR))
 836                 device_remove_file(s, &dev_attr_purr);
 837
 838         if (cpu_has_feature(CPU_FTR_SPURR))
 839                 device_remove_file(s, &dev_attr_spurr);
 840
 841         if (cpu_has_feature(CPU_FTR_DSCR))
 842                 device_remove_file(s, &dev_attr_dscr);
 843
 844         if (cpu_has_feature(CPU_FTR_PPCAS_ARCH_V2))
 845                 device_remove_file(s, &dev_attr_pir);
 846 #endif /* CONFIG_PPC64 */
 847
 848 #ifdef CONFIG_PPC_FSL_BOOK3E
 849         if (PVR_VER(cur_cpu_spec->pvr_value) == PVR_VER_E6500) {
 850                 device_remove_file(s, &dev_attr_pw20_state);
 851                 device_remove_file(s, &dev_attr_pw20_wait_time);
 852
 853                 device_remove_file(s, &dev_attr_altivec_idle);
 854                 device_remove_file(s, &dev_attr_altivec_idle_wait_time);
 855         }
 856 #endif
 857         cacheinfo_cpu_offline(cpu);
 858 }
 859
 860 #ifdef CONFIG_ARCH_CPU_PROBE_RELEASE
 861 ssize_t arch_cpu_probe(const char *buf, size_t count)
 862 {
 863         if (ppc_md.cpu_probe)
 864                 return ppc_md.cpu_probe(buf, count);
 865
 866         return -EINVAL;
 867 }
 868
 869 ssize_t arch_cpu_release(const char *buf, size_t count)
 870 {
 871         if (ppc_md.cpu_release)
 872                 return ppc_md.cpu_release(buf, count);
 873
 874         return -EINVAL;
 875 }
 876 #endif /* CONFIG_ARCH_CPU_PROBE_RELEASE */
 877
 878 #endif /* CONFIG_HOTPLUG_CPU */
 879
 880 static int sysfs_cpu_notify(struct notifier_block *self,
 881                                       unsigned long action, void *hcpu)
 882 {
 883         unsigned int cpu = (unsigned int)(long)hcpu;
 884
 885         switch (action) {
 886         case CPU_ONLINE:
 887         case CPU_ONLINE_FROZEN:
 888                 register_cpu_online(cpu);
 889                 break;
 890 #ifdef CONFIG_HOTPLUG_CPU
 891         case CPU_DEAD:
 892         case CPU_DEAD_FROZEN:
 893                 unregister_cpu_online(cpu);
 894                 break;
 895 #endif
 896         }
 897         return NOTIFY_OK;
 898 }
 899
 900 static struct notifier_block sysfs_cpu_nb = {
 901         .notifier_call  = sysfs_cpu_notify,
 902 };
 903
 904 static DEFINE_MUTEX(cpu_mutex);
 905
 906 int cpu_add_dev_attr(struct device_attribute *attr)
 907 {
 908         int cpu;
 909
 910         mutex_lock(&cpu_mutex);
 911
 912         for_each_possible_cpu(cpu) {
 913                 device_create_file(get_cpu_device(cpu), attr);
 914         }
 915
 916         mutex_unlock(&cpu_mutex);
 917         return 0;
 918 }
 919 EXPORT_SYMBOL_GPL(cpu_add_dev_attr);
 920
 921 int cpu_add_dev_attr_group(struct attribute_group *attrs)
 922 {
 923         int cpu;
 924         struct device *dev;
 925         int ret;
 926
 927         mutex_lock(&cpu_mutex);
 928
 929         for_each_possible_cpu(cpu) {
 930                 dev = get_cpu_device(cpu);
 931                 ret = sysfs_create_group(&dev->kobj, attrs);
 932                 WARN_ON(ret != 0);
 933         }
 934
 935         mutex_unlock(&cpu_mutex);
 936         return 0;
 937 }
 938 EXPORT_SYMBOL_GPL(cpu_add_dev_attr_group);
 939
 940
 941 void cpu_remove_dev_attr(struct device_attribute *attr)
 942 {
 943         int cpu;
 944
 945         mutex_lock(&cpu_mutex);
 946
 947         for_each_possible_cpu(cpu) {
 948                 device_remove_file(get_cpu_device(cpu), attr);
 949         }
 950
 951         mutex_unlock(&cpu_mutex);
 952 }
 953 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr);
 954
 955 void cpu_remove_dev_attr_group(struct attribute_group *attrs)
 956 {
 957         int cpu;
 958         struct device *dev;
 959
 960         mutex_lock(&cpu_mutex);
 961
 962         for_each_possible_cpu(cpu) {
 963                 dev = get_cpu_device(cpu);
 964                 sysfs_remove_group(&dev->kobj, attrs);
 965         }
 966
 967         mutex_unlock(&cpu_mutex);
 968 }
 969 EXPORT_SYMBOL_GPL(cpu_remove_dev_attr_group);
 970
 971
 972 /* NUMA stuff */
 973
 974 #ifdef CONFIG_NUMA
 975 static void register_nodes(void)
 976 {
 977         int i;
 978
 979         for (i = 0; i < MAX_NUMNODES; i++)
 980                 register_one_node(i);
 981 }
 982
 983 int sysfs_add_device_to_node(struct device *dev, int nid)
 984 {
 985         struct node *node = node_devices[nid];
 986         return sysfs_create_link(&node->dev.kobj, &dev->kobj,
 987                         kobject_name(&dev->kobj));
 988 }
 989 EXPORT_SYMBOL_GPL(sysfs_add_device_to_node);
 990
 991 void sysfs_remove_device_from_node(struct device *dev, int nid)
 992 {
 993         struct node *node = node_devices[nid];
 994         sysfs_remove_link(&node->dev.kobj, kobject_name(&dev->kobj));
 995 }
 996 EXPORT_SYMBOL_GPL(sysfs_remove_device_from_node);
 997
 998 #else
 999 static void register_nodes(void)
1000 {
1001         return;
1002 }
1003
1004 #endif
1005
1006 /* Only valid if CPU is present. */
1007 static ssize_t show_physical_id(struct device *dev,
1008                                 struct device_attribute *attr, char *buf)
1009 {
1010         struct cpu *cpu = container_of(dev, struct cpu, dev);
1011
1012         return sprintf(buf, "%d\n", get_hard_smp_processor_id(cpu->dev.id));
1013 }
1014 static DEVICE_ATTR(physical_id, 0444, show_physical_id, NULL);
1015
1016 static int __init topology_init(void)
1017 {
1018         int cpu;
1019
1020         register_nodes();
1021
1022         cpu_notifier_register_begin();
1023
1024         for_each_possible_cpu(cpu) {
1025                 struct cpu *c = &per_cpu(cpu_devices, cpu);
1026
1027                 /*
1028                  * For now, we just see if the system supports making
1029                  * the RTAS calls for CPU hotplug.  But, there may be a
1030                  * more comprehensive way to do this for an individual
1031                  * CPU.  For instance, the boot cpu might never be valid
1032                  * for hotplugging.
1033                  */
1034                 if (ppc_md.cpu_die)
1035                         c->hotpluggable = 1;
1036
1037                 if (cpu_online(cpu) || c->hotpluggable) {
1038                         register_cpu(c, cpu);
1039
1040                         device_create_file(&c->dev, &dev_attr_physical_id);
1041                 }
1042
1043                 if (cpu_online(cpu))
1044                         register_cpu_online(cpu);
1045         }
1046
1047         __register_cpu_notifier(&sysfs_cpu_nb);
1048
1049         cpu_notifier_register_done();
1050
1051 #ifdef CONFIG_PPC64
1052         sysfs_create_dscr_default();
1053 #endif /* CONFIG_PPC64 */
1054
1055         return 0;
1056 }
1057 subsys_initcall(topology_init);