1 /* SPDX-License-Identifier: GPL-2.0 */
2 #include <linux/threads.h>
3 #include <asm/processor.h>
5 #include <asm/cputable.h>
6 #include <asm/thread_info.h>
7 #include <asm/ppc_asm.h>
8 #include <asm/asm-offsets.h>
12 * Structure for storing CPU registers on the save area.
18 #define SL_SPRG0 0x10 /* 4 sprg's */
39 #define SL_R12 0xb4 /* r12 to r31 */
40 #define SL_SIZE (SL_R12 + 80)
45 _GLOBAL(swsusp_save_area)
52 _GLOBAL(swsusp_arch_suspend)
54 lis r11,swsusp_save_area@h
55 ori r11,r11,swsusp_save_area@l
71 /* Get a stable timebase and save it */
84 stw r4,SL_SPRG0+4(r11)
86 stw r4,SL_SPRG0+8(r11)
88 stw r4,SL_SPRG0+12(r11)
94 stw r4,SL_DBAT0+4(r11)
98 stw r4,SL_DBAT1+4(r11)
102 stw r4,SL_DBAT2+4(r11)
106 stw r4,SL_DBAT3+4(r11)
110 stw r4,SL_IBAT0+4(r11)
114 stw r4,SL_IBAT1+4(r11)
118 stw r4,SL_IBAT2+4(r11)
122 stw r4,SL_IBAT3+4(r11)
124 BEGIN_MMU_FTR_SECTION
128 stw r4,SL_DBAT4+4(r11)
132 stw r4,SL_DBAT5+4(r11)
136 stw r4,SL_DBAT6+4(r11)
140 stw r4,SL_DBAT7+4(r11)
144 stw r4,SL_IBAT4+4(r11)
148 stw r4,SL_IBAT5+4(r11)
152 stw r4,SL_IBAT6+4(r11)
156 stw r4,SL_IBAT7+4(r11)
157 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
160 /* Backup various CPU config stuffs */
163 /* Call the low level suspend stuff (we should probably have made
168 /* Restore LR from the save area */
169 lis r11,swsusp_save_area@h
170 ori r11,r11,swsusp_save_area@l
178 _GLOBAL(swsusp_arch_resume)
180 #ifdef CONFIG_ALTIVEC
181 /* Stop pending alitvec streams and memory accesses */
184 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
188 /* Disable MSR:DR to make sure we don't take a TLB or
189 * hash miss during the copy, as our hash table will
190 * for a while be unusable. For .text, we assume we are
191 * covered by a BAT. This works only for non-G5 at this
192 * point. G5 will need a better approach, possibly using
193 * a small temporary hash table filled with large mappings,
194 * disabling the MMU completely isn't a good option for
195 * performance reasons.
196 * (Note that 750's may have the same performance issue as
197 * the G5 in this case, we should investigate using moving
198 * BATs for these CPUs)
202 rlwinm r0,r0,0,28,26 /* clear MSR_DR */
207 /* Load ptr the list of pages to copy in r3 */
208 lis r11,(restore_pblist - KERNELBASE)@h
209 ori r11,r11,restore_pblist@l
212 /* Copy the pages. This is a very basic implementation, to
213 * be replaced by something more cache efficient */
218 lwz r11,pbe_address(r3) /* source */
220 lwz r10,pbe_orig_address(r3) /* destination */
238 /* Do a very simple cache flush/inval of the L1 to ensure
239 * coherency of the icache
251 /* Now flush those cache lines */
261 /* Ok, we are now running with the kernel data of the old
262 * kernel fully restored. We can get to the save area
263 * easily now. As for the rest of the code, it assumes the
264 * loader kernel and the booted one are exactly identical
266 lis r11,swsusp_save_area@h
267 ori r11,r11,swsusp_save_area@l
271 /* Restore various CPU config stuffs */
272 bl __restore_cpu_setup
274 /* Restore the BATs, and SDR1. Then we can turn on the MMU.
275 * This is a bit hairy as we are running out of those BATs,
276 * but first, our code is probably in the icache, and we are
277 * writing the same value to the BAT, so that should be fine,
278 * though a better solution will have to be found long-term
284 lwz r4,SL_SPRG0+4(r11)
286 lwz r4,SL_SPRG0+8(r11)
288 lwz r4,SL_SPRG0+12(r11)
294 lwz r4,SL_DBAT0+4(r11)
298 lwz r4,SL_DBAT1+4(r11)
302 lwz r4,SL_DBAT2+4(r11)
306 lwz r4,SL_DBAT3+4(r11)
310 lwz r4,SL_IBAT0+4(r11)
314 lwz r4,SL_IBAT1+4(r11)
318 lwz r4,SL_IBAT2+4(r11)
322 lwz r4,SL_IBAT3+4(r11)
324 BEGIN_MMU_FTR_SECTION
327 lwz r4,SL_DBAT4+4(r11)
331 lwz r4,SL_DBAT5+4(r11)
335 lwz r4,SL_DBAT6+4(r11)
339 lwz r4,SL_DBAT7+4(r11)
343 lwz r4,SL_IBAT4+4(r11)
347 lwz r4,SL_IBAT5+4(r11)
351 lwz r4,SL_IBAT6+4(r11)
355 lwz r4,SL_IBAT7+4(r11)
357 END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS)
362 1: addic. r4,r4,-0x1000
367 /* restore the MSR and turn on the MMU */
380 /* Kick decrementer */
384 /* Restore the callee-saved registers and return */
393 // XXX Note: we don't really need to call swsusp_resume
398 /* FIXME:This construct is actually not useful since we don't shut
399 * down the instruction MMU, we could just flip back MSR-DR on.