1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Written by Cort Dougan (cort@cs.nmt.edu) borrowing a great
6 * deal of code from the sparc and intel versions.
8 * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
10 * PowerPC-64 Support added by Dave Engebretsen, Peter Bergner, and
11 * Mike Corrigan {engebret|bergner|mikec}@us.ibm.com
16 #include <linux/kernel.h>
17 #include <linux/export.h>
18 #include <linux/sched/mm.h>
19 #include <linux/sched/task_stack.h>
20 #include <linux/sched/topology.h>
21 #include <linux/smp.h>
22 #include <linux/interrupt.h>
23 #include <linux/delay.h>
24 #include <linux/init.h>
25 #include <linux/spinlock.h>
26 #include <linux/cache.h>
27 #include <linux/err.h>
28 #include <linux/device.h>
29 #include <linux/cpu.h>
30 #include <linux/notifier.h>
31 #include <linux/topology.h>
32 #include <linux/profile.h>
33 #include <linux/processor.h>
34 #include <linux/random.h>
35 #include <linux/stackprotector.h>
36 #include <linux/pgtable.h>
37 #include <linux/clockchips.h>
38 #include <linux/kexec.h>
40 #include <asm/ptrace.h>
41 #include <linux/atomic.h>
43 #include <asm/hw_irq.h>
44 #include <asm/kvm_ppc.h>
45 #include <asm/dbell.h>
49 #include <asm/machdep.h>
50 #include <asm/cputhreads.h>
51 #include <asm/cputable.h>
53 #include <asm/vdso_datapage.h>
58 #include <asm/debug.h>
59 #include <asm/cpu_has_feature.h>
60 #include <asm/ftrace.h>
62 #include <asm/fadump.h>
66 #define DBG(fmt...) udbg_printf(fmt)
71 #ifdef CONFIG_HOTPLUG_CPU
72 /* State of each CPU during hotplug phases */
73 static DEFINE_PER_CPU(int, cpu_state) = { 0 };
76 struct task_struct *secondary_current;
78 bool coregroup_enabled;
79 bool thread_group_shares_l2;
80 bool thread_group_shares_l3;
82 DEFINE_PER_CPU(cpumask_var_t, cpu_sibling_map);
83 DEFINE_PER_CPU(cpumask_var_t, cpu_smallcore_map);
84 DEFINE_PER_CPU(cpumask_var_t, cpu_l2_cache_map);
85 DEFINE_PER_CPU(cpumask_var_t, cpu_core_map);
86 static DEFINE_PER_CPU(cpumask_var_t, cpu_coregroup_map);
88 EXPORT_PER_CPU_SYMBOL(cpu_sibling_map);
89 EXPORT_PER_CPU_SYMBOL(cpu_l2_cache_map);
90 EXPORT_PER_CPU_SYMBOL(cpu_core_map);
91 EXPORT_SYMBOL_GPL(has_big_cores);
94 #ifdef CONFIG_SCHED_SMT
102 #define MAX_THREAD_LIST_SIZE 8
103 #define THREAD_GROUP_SHARE_L1 1
104 #define THREAD_GROUP_SHARE_L2_L3 2
105 struct thread_groups {
106 unsigned int property;
107 unsigned int nr_groups;
108 unsigned int threads_per_group;
109 unsigned int thread_list[MAX_THREAD_LIST_SIZE];
112 /* Maximum number of properties that groups of threads within a core can share */
113 #define MAX_THREAD_GROUP_PROPERTIES 2
115 struct thread_groups_list {
116 unsigned int nr_properties;
117 struct thread_groups property_tgs[MAX_THREAD_GROUP_PROPERTIES];
120 static struct thread_groups_list tgl[NR_CPUS] __initdata;
122 * On big-cores system, thread_group_l1_cache_map for each CPU corresponds to
123 * the set its siblings that share the L1-cache.
125 DEFINE_PER_CPU(cpumask_var_t, thread_group_l1_cache_map);
128 * On some big-cores system, thread_group_l2_cache_map for each CPU
129 * corresponds to the set its siblings within the core that share the
132 DEFINE_PER_CPU(cpumask_var_t, thread_group_l2_cache_map);
135 * On P10, thread_group_l3_cache_map for each CPU is equal to the
136 * thread_group_l2_cache_map
138 DEFINE_PER_CPU(cpumask_var_t, thread_group_l3_cache_map);
140 /* SMP operations for this machine */
141 struct smp_ops_t *smp_ops;
143 /* Can't be static due to PowerMac hackery */
144 volatile unsigned int cpu_callin_map[NR_CPUS];
146 int smt_enabled_at_boot = 1;
149 * Returns 1 if the specified cpu should be brought up during boot.
150 * Used to inhibit booting threads if they've been disabled or
151 * limited on the command line
153 int smp_generic_cpu_bootable(unsigned int nr)
155 /* Special case - we inhibit secondary thread startup
156 * during boot if the user requests it.
158 if (system_state < SYSTEM_RUNNING && cpu_has_feature(CPU_FTR_SMT)) {
159 if (!smt_enabled_at_boot && cpu_thread_in_core(nr) != 0)
161 if (smt_enabled_at_boot
162 && cpu_thread_in_core(nr) >= smt_enabled_at_boot)
171 int smp_generic_kick_cpu(int nr)
173 if (nr < 0 || nr >= nr_cpu_ids)
177 * The processor is currently spinning, waiting for the
178 * cpu_start field to become non-zero After we set cpu_start,
179 * the processor will continue on to secondary_start
181 if (!paca_ptrs[nr]->cpu_start) {
182 paca_ptrs[nr]->cpu_start = 1;
187 #ifdef CONFIG_HOTPLUG_CPU
189 * Ok it's not there, so it might be soft-unplugged, let's
190 * try to bring it back
192 generic_set_cpu_up(nr);
194 smp_send_reschedule(nr);
195 #endif /* CONFIG_HOTPLUG_CPU */
199 #endif /* CONFIG_PPC64 */
201 static irqreturn_t call_function_action(int irq, void *data)
203 generic_smp_call_function_interrupt();
207 static irqreturn_t reschedule_action(int irq, void *data)
213 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
214 static irqreturn_t tick_broadcast_ipi_action(int irq, void *data)
216 timer_broadcast_interrupt();
221 #ifdef CONFIG_NMI_IPI
222 static irqreturn_t nmi_ipi_action(int irq, void *data)
224 smp_handle_nmi_ipi(get_irq_regs());
229 static irq_handler_t smp_ipi_action[] = {
230 [PPC_MSG_CALL_FUNCTION] = call_function_action,
231 [PPC_MSG_RESCHEDULE] = reschedule_action,
232 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
233 [PPC_MSG_TICK_BROADCAST] = tick_broadcast_ipi_action,
235 #ifdef CONFIG_NMI_IPI
236 [PPC_MSG_NMI_IPI] = nmi_ipi_action,
241 * The NMI IPI is a fallback and not truly non-maskable. It is simpler
242 * than going through the call function infrastructure, and strongly
243 * serialized, so it is more appropriate for debugging.
245 const char *smp_ipi_name[] = {
246 [PPC_MSG_CALL_FUNCTION] = "ipi call function",
247 [PPC_MSG_RESCHEDULE] = "ipi reschedule",
248 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
249 [PPC_MSG_TICK_BROADCAST] = "ipi tick-broadcast",
251 #ifdef CONFIG_NMI_IPI
252 [PPC_MSG_NMI_IPI] = "nmi ipi",
256 /* optional function to request ipi, for controllers with >= 4 ipis */
257 int smp_request_message_ipi(int virq, int msg)
261 if (msg < 0 || msg > PPC_MSG_NMI_IPI)
263 #ifndef CONFIG_NMI_IPI
264 if (msg == PPC_MSG_NMI_IPI)
268 err = request_irq(virq, smp_ipi_action[msg],
269 IRQF_PERCPU | IRQF_NO_THREAD | IRQF_NO_SUSPEND,
270 smp_ipi_name[msg], NULL);
271 WARN(err < 0, "unable to request_irq %d for %s (rc %d)\n",
272 virq, smp_ipi_name[msg], err);
277 #ifdef CONFIG_PPC_SMP_MUXED_IPI
278 struct cpu_messages {
279 long messages; /* current messages */
281 static DEFINE_PER_CPU_SHARED_ALIGNED(struct cpu_messages, ipi_message);
283 void smp_muxed_ipi_set_message(int cpu, int msg)
285 struct cpu_messages *info = &per_cpu(ipi_message, cpu);
286 char *message = (char *)&info->messages;
289 * Order previous accesses before accesses in the IPI handler.
295 void smp_muxed_ipi_message_pass(int cpu, int msg)
297 smp_muxed_ipi_set_message(cpu, msg);
300 * cause_ipi functions are required to include a full barrier
301 * before doing whatever causes the IPI.
303 smp_ops->cause_ipi(cpu);
306 #ifdef __BIG_ENDIAN__
307 #define IPI_MESSAGE(A) (1uL << ((BITS_PER_LONG - 8) - 8 * (A)))
309 #define IPI_MESSAGE(A) (1uL << (8 * (A)))
312 irqreturn_t smp_ipi_demux(void)
314 mb(); /* order any irq clear */
316 return smp_ipi_demux_relaxed();
319 /* sync-free variant. Callers should ensure synchronization */
320 irqreturn_t smp_ipi_demux_relaxed(void)
322 struct cpu_messages *info;
325 info = this_cpu_ptr(&ipi_message);
327 all = xchg(&info->messages, 0);
328 #if defined(CONFIG_KVM_XICS) && defined(CONFIG_KVM_BOOK3S_HV_POSSIBLE)
330 * Must check for PPC_MSG_RM_HOST_ACTION messages
331 * before PPC_MSG_CALL_FUNCTION messages because when
332 * a VM is destroyed, we call kick_all_cpus_sync()
333 * to ensure that any pending PPC_MSG_RM_HOST_ACTION
334 * messages have completed before we free any VCPUs.
336 if (all & IPI_MESSAGE(PPC_MSG_RM_HOST_ACTION))
337 kvmppc_xics_ipi_action();
339 if (all & IPI_MESSAGE(PPC_MSG_CALL_FUNCTION))
340 generic_smp_call_function_interrupt();
341 if (all & IPI_MESSAGE(PPC_MSG_RESCHEDULE))
343 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
344 if (all & IPI_MESSAGE(PPC_MSG_TICK_BROADCAST))
345 timer_broadcast_interrupt();
347 #ifdef CONFIG_NMI_IPI
348 if (all & IPI_MESSAGE(PPC_MSG_NMI_IPI))
349 nmi_ipi_action(0, NULL);
351 } while (info->messages);
355 #endif /* CONFIG_PPC_SMP_MUXED_IPI */
357 static inline void do_message_pass(int cpu, int msg)
359 if (smp_ops->message_pass)
360 smp_ops->message_pass(cpu, msg);
361 #ifdef CONFIG_PPC_SMP_MUXED_IPI
363 smp_muxed_ipi_message_pass(cpu, msg);
367 void smp_send_reschedule(int cpu)
370 do_message_pass(cpu, PPC_MSG_RESCHEDULE);
372 EXPORT_SYMBOL_GPL(smp_send_reschedule);
374 void arch_send_call_function_single_ipi(int cpu)
376 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
379 void arch_send_call_function_ipi_mask(const struct cpumask *mask)
383 for_each_cpu(cpu, mask)
384 do_message_pass(cpu, PPC_MSG_CALL_FUNCTION);
387 #ifdef CONFIG_NMI_IPI
392 * NMI IPIs may not be recoverable, so should not be used as ongoing part of
393 * a running system. They can be used for crash, debug, halt/reboot, etc.
395 * The IPI call waits with interrupts disabled until all targets enter the
396 * NMI handler, then returns. Subsequent IPIs can be issued before targets
397 * have returned from their handlers, so there is no guarantee about
398 * concurrency or re-entrancy.
400 * A new NMI can be issued before all targets exit the handler.
402 * The IPI call may time out without all targets entering the NMI handler.
403 * In that case, there is some logic to recover (and ignore subsequent
404 * NMI interrupts that may eventually be raised), but the platform interrupt
405 * handler may not be able to distinguish this from other exception causes,
406 * which may cause a crash.
409 static atomic_t __nmi_ipi_lock = ATOMIC_INIT(0);
410 static struct cpumask nmi_ipi_pending_mask;
411 static bool nmi_ipi_busy = false;
412 static void (*nmi_ipi_function)(struct pt_regs *) = NULL;
414 noinstr static void nmi_ipi_lock_start(unsigned long *flags)
416 raw_local_irq_save(*flags);
418 while (arch_atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1) {
419 raw_local_irq_restore(*flags);
420 spin_until_cond(arch_atomic_read(&__nmi_ipi_lock) == 0);
421 raw_local_irq_save(*flags);
426 noinstr static void nmi_ipi_lock(void)
428 while (arch_atomic_cmpxchg(&__nmi_ipi_lock, 0, 1) == 1)
429 spin_until_cond(arch_atomic_read(&__nmi_ipi_lock) == 0);
432 noinstr static void nmi_ipi_unlock(void)
435 WARN_ON(arch_atomic_read(&__nmi_ipi_lock) != 1);
436 arch_atomic_set(&__nmi_ipi_lock, 0);
439 noinstr static void nmi_ipi_unlock_end(unsigned long *flags)
442 raw_local_irq_restore(*flags);
446 * Platform NMI handler calls this to ack
448 noinstr int smp_handle_nmi_ipi(struct pt_regs *regs)
450 void (*fn)(struct pt_regs *) = NULL;
452 int me = raw_smp_processor_id();
456 * Unexpected NMIs are possible here because the interrupt may not
457 * be able to distinguish NMI IPIs from other types of NMIs, or
458 * because the caller may have timed out.
460 nmi_ipi_lock_start(&flags);
461 if (cpumask_test_cpu(me, &nmi_ipi_pending_mask)) {
462 cpumask_clear_cpu(me, &nmi_ipi_pending_mask);
463 fn = READ_ONCE(nmi_ipi_function);
467 nmi_ipi_unlock_end(&flags);
475 static void do_smp_send_nmi_ipi(int cpu, bool safe)
477 if (!safe && smp_ops->cause_nmi_ipi && smp_ops->cause_nmi_ipi(cpu))
481 do_message_pass(cpu, PPC_MSG_NMI_IPI);
485 for_each_online_cpu(c) {
486 if (c == raw_smp_processor_id())
488 do_message_pass(c, PPC_MSG_NMI_IPI);
494 * - cpu is the target CPU (must not be this CPU), or NMI_IPI_ALL_OTHERS.
495 * - fn is the target callback function.
496 * - delay_us > 0 is the delay before giving up waiting for targets to
497 * begin executing the handler, == 0 specifies indefinite delay.
499 static int __smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *),
500 u64 delay_us, bool safe)
503 int me = raw_smp_processor_id();
507 BUG_ON(cpu < 0 && cpu != NMI_IPI_ALL_OTHERS);
509 if (unlikely(!smp_ops))
512 nmi_ipi_lock_start(&flags);
513 while (nmi_ipi_busy) {
514 nmi_ipi_unlock_end(&flags);
515 spin_until_cond(!nmi_ipi_busy);
516 nmi_ipi_lock_start(&flags);
519 nmi_ipi_function = fn;
521 WARN_ON_ONCE(!cpumask_empty(&nmi_ipi_pending_mask));
525 cpumask_copy(&nmi_ipi_pending_mask, cpu_online_mask);
526 cpumask_clear_cpu(me, &nmi_ipi_pending_mask);
528 cpumask_set_cpu(cpu, &nmi_ipi_pending_mask);
533 /* Interrupts remain hard disabled */
535 do_smp_send_nmi_ipi(cpu, safe);
538 /* nmi_ipi_busy is set here, so unlock/lock is okay */
539 while (!cpumask_empty(&nmi_ipi_pending_mask)) {
550 if (!cpumask_empty(&nmi_ipi_pending_mask)) {
551 /* Timeout waiting for CPUs to call smp_handle_nmi_ipi */
553 cpumask_clear(&nmi_ipi_pending_mask);
556 nmi_ipi_function = NULL;
557 nmi_ipi_busy = false;
559 nmi_ipi_unlock_end(&flags);
564 int smp_send_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us)
566 return __smp_send_nmi_ipi(cpu, fn, delay_us, false);
569 int smp_send_safe_nmi_ipi(int cpu, void (*fn)(struct pt_regs *), u64 delay_us)
571 return __smp_send_nmi_ipi(cpu, fn, delay_us, true);
573 #endif /* CONFIG_NMI_IPI */
575 #ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
576 void tick_broadcast(const struct cpumask *mask)
580 for_each_cpu(cpu, mask)
581 do_message_pass(cpu, PPC_MSG_TICK_BROADCAST);
585 #ifdef CONFIG_DEBUGGER
586 static void debugger_ipi_callback(struct pt_regs *regs)
591 void smp_send_debugger_break(void)
593 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, debugger_ipi_callback, 1000000);
597 #ifdef CONFIG_KEXEC_CORE
598 void crash_send_ipi(void (*crash_ipi_callback)(struct pt_regs *))
602 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, crash_ipi_callback, 1000000);
603 if (kdump_in_progress() && crash_wake_offline) {
604 for_each_present_cpu(cpu) {
608 * crash_ipi_callback will wait for
609 * all cpus, including offline CPUs.
610 * We don't care about nmi_ipi_function.
611 * Offline cpus will jump straight into
612 * crash_ipi_callback, we can skip the
613 * entire NMI dance and waiting for
614 * cpus to clear pending mask, etc.
616 do_smp_send_nmi_ipi(cpu, false);
622 void crash_smp_send_stop(void)
624 static bool stopped = false;
627 * In case of fadump, register data for all CPUs is captured by f/w
628 * on ibm,os-term rtas call. Skip IPI callbacks to other CPUs before
629 * this rtas call to avoid tricky post processing of those CPUs'
632 if (should_fadump_crash())
640 #ifdef CONFIG_KEXEC_CORE
641 if (kexec_crash_image) {
642 crash_kexec_prepare();
650 #ifdef CONFIG_NMI_IPI
651 static void nmi_stop_this_cpu(struct pt_regs *regs)
654 * IRQs are already hard disabled by the smp_handle_nmi_ipi.
656 set_cpu_online(smp_processor_id(), false);
663 void smp_send_stop(void)
665 smp_send_nmi_ipi(NMI_IPI_ALL_OTHERS, nmi_stop_this_cpu, 1000000);
668 #else /* CONFIG_NMI_IPI */
670 static void stop_this_cpu(void *dummy)
675 * Offlining CPUs in stop_this_cpu can result in scheduler warnings,
676 * (see commit de6e5d38417e), but printk_safe_flush_on_panic() wants
677 * to know other CPUs are offline before it breaks locks to flush
678 * printk buffers, in case we panic()ed while holding the lock.
680 set_cpu_online(smp_processor_id(), false);
687 void smp_send_stop(void)
689 static bool stopped = false;
692 * Prevent waiting on csd lock from a previous smp_send_stop.
693 * This is racy, but in general callers try to do the right
694 * thing and only fire off one smp_send_stop (e.g., see
702 smp_call_function(stop_this_cpu, NULL, 0);
704 #endif /* CONFIG_NMI_IPI */
706 static struct task_struct *current_set[NR_CPUS];
708 static void smp_store_cpu_info(int id)
710 per_cpu(cpu_pvr, id) = mfspr(SPRN_PVR);
711 #ifdef CONFIG_PPC_E500
712 per_cpu(next_tlbcam_idx, id)
713 = (mfspr(SPRN_TLB1CFG) & TLBnCFG_N_ENTRY) - 1;
718 * Relationships between CPUs are maintained in a set of per-cpu cpumasks so
719 * rather than just passing around the cpumask we pass around a function that
720 * returns the that cpumask for the given CPU.
722 static void set_cpus_related(int i, int j, struct cpumask *(*get_cpumask)(int))
724 cpumask_set_cpu(i, get_cpumask(j));
725 cpumask_set_cpu(j, get_cpumask(i));
728 #ifdef CONFIG_HOTPLUG_CPU
729 static void set_cpus_unrelated(int i, int j,
730 struct cpumask *(*get_cpumask)(int))
732 cpumask_clear_cpu(i, get_cpumask(j));
733 cpumask_clear_cpu(j, get_cpumask(i));
738 * Extends set_cpus_related. Instead of setting one CPU at a time in
739 * dstmask, set srcmask at oneshot. dstmask should be super set of srcmask.
741 static void or_cpumasks_related(int i, int j, struct cpumask *(*srcmask)(int),
742 struct cpumask *(*dstmask)(int))
744 struct cpumask *mask;
748 for_each_cpu(k, srcmask(i))
749 cpumask_or(dstmask(k), dstmask(k), mask);
755 for_each_cpu(k, srcmask(j))
756 cpumask_or(dstmask(k), dstmask(k), mask);
760 * parse_thread_groups: Parses the "ibm,thread-groups" device tree
761 * property for the CPU device node @dn and stores
762 * the parsed output in the thread_groups_list
765 * @dn: The device node of the CPU device.
766 * @tglp: Pointer to a thread group list structure into which the parsed
767 * output of "ibm,thread-groups" is stored.
769 * ibm,thread-groups[0..N-1] array defines which group of threads in
770 * the CPU-device node can be grouped together based on the property.
772 * This array can represent thread groupings for multiple properties.
774 * ibm,thread-groups[i + 0] tells us the property based on which the
775 * threads are being grouped together. If this value is 1, it implies
776 * that the threads in the same group share L1, translation cache. If
777 * the value is 2, it implies that the threads in the same group share
780 * ibm,thread-groups[i+1] tells us how many such thread groups exist for the
781 * property ibm,thread-groups[i]
783 * ibm,thread-groups[i+2] tells us the number of threads in each such
785 * Suppose k = (ibm,thread-groups[i+1] * ibm,thread-groups[i+2]), then,
787 * ibm,thread-groups[i+3..i+k+2] (is the list of threads identified by
788 * "ibm,ppc-interrupt-server#s" arranged as per their membership in
792 * If "ibm,thread-groups" = [1,2,4,8,10,12,14,9,11,13,15,2,2,4,8,10,12,14,9,11,13,15]
793 * This can be decomposed up into two consecutive arrays:
794 * a) [1,2,4,8,10,12,14,9,11,13,15]
795 * b) [2,2,4,8,10,12,14,9,11,13,15]
799 * a) provides information of Property "1" being shared by "2" groups,
800 * each with "4" threads each. The "ibm,ppc-interrupt-server#s" of
801 * the first group is {8,10,12,14} and the
802 * "ibm,ppc-interrupt-server#s" of the second group is
803 * {9,11,13,15}. Property "1" is indicative of the thread in the
804 * group sharing L1 cache, translation cache and Instruction Data
807 * b) provides information of Property "2" being shared by "2" groups,
808 * each group with "4" threads. The "ibm,ppc-interrupt-server#s" of
809 * the first group is {8,10,12,14} and the
810 * "ibm,ppc-interrupt-server#s" of the second group is
811 * {9,11,13,15}. Property "2" indicates that the threads in each
812 * group share the L2-cache.
814 * Returns 0 on success, -EINVAL if the property does not exist,
815 * -ENODATA if property does not have a value, and -EOVERFLOW if the
816 * property data isn't large enough.
818 static int parse_thread_groups(struct device_node *dn,
819 struct thread_groups_list *tglp)
821 unsigned int property_idx = 0;
822 u32 *thread_group_array;
823 size_t total_threads;
828 count = of_property_count_u32_elems(dn, "ibm,thread-groups");
829 thread_group_array = kcalloc(count, sizeof(u32), GFP_KERNEL);
830 ret = of_property_read_u32_array(dn, "ibm,thread-groups",
831 thread_group_array, count);
835 while (i < count && property_idx < MAX_THREAD_GROUP_PROPERTIES) {
837 struct thread_groups *tg = &tglp->property_tgs[property_idx++];
839 tg->property = thread_group_array[i];
840 tg->nr_groups = thread_group_array[i + 1];
841 tg->threads_per_group = thread_group_array[i + 2];
842 total_threads = tg->nr_groups * tg->threads_per_group;
844 thread_list = &thread_group_array[i + 3];
846 for (j = 0; j < total_threads; j++)
847 tg->thread_list[j] = thread_list[j];
848 i = i + 3 + total_threads;
851 tglp->nr_properties = property_idx;
854 kfree(thread_group_array);
859 * get_cpu_thread_group_start : Searches the thread group in tg->thread_list
860 * that @cpu belongs to.
862 * @cpu : The logical CPU whose thread group is being searched.
863 * @tg : The thread-group structure of the CPU node which @cpu belongs
866 * Returns the index to tg->thread_list that points to the start
867 * of the thread_group that @cpu belongs to.
869 * Returns -1 if cpu doesn't belong to any of the groups pointed to by
872 static int get_cpu_thread_group_start(int cpu, struct thread_groups *tg)
874 int hw_cpu_id = get_hard_smp_processor_id(cpu);
877 for (i = 0; i < tg->nr_groups; i++) {
878 int group_start = i * tg->threads_per_group;
880 for (j = 0; j < tg->threads_per_group; j++) {
881 int idx = group_start + j;
883 if (tg->thread_list[idx] == hw_cpu_id)
891 static struct thread_groups *__init get_thread_groups(int cpu,
895 struct device_node *dn = of_get_cpu_node(cpu, NULL);
896 struct thread_groups_list *cpu_tgl = &tgl[cpu];
897 struct thread_groups *tg = NULL;
906 if (!cpu_tgl->nr_properties) {
907 *err = parse_thread_groups(dn, cpu_tgl);
912 for (i = 0; i < cpu_tgl->nr_properties; i++) {
913 if (cpu_tgl->property_tgs[i].property == group_property) {
914 tg = &cpu_tgl->property_tgs[i];
926 static int __init update_mask_from_threadgroup(cpumask_var_t *mask, struct thread_groups *tg,
927 int cpu, int cpu_group_start)
929 int first_thread = cpu_first_thread_sibling(cpu);
932 zalloc_cpumask_var_node(mask, GFP_KERNEL, cpu_to_node(cpu));
934 for (i = first_thread; i < first_thread + threads_per_core; i++) {
935 int i_group_start = get_cpu_thread_group_start(i, tg);
937 if (unlikely(i_group_start == -1)) {
942 if (i_group_start == cpu_group_start)
943 cpumask_set_cpu(i, *mask);
949 static int __init init_thread_group_cache_map(int cpu, int cache_property)
952 int cpu_group_start = -1, err = 0;
953 struct thread_groups *tg = NULL;
954 cpumask_var_t *mask = NULL;
956 if (cache_property != THREAD_GROUP_SHARE_L1 &&
957 cache_property != THREAD_GROUP_SHARE_L2_L3)
960 tg = get_thread_groups(cpu, cache_property, &err);
965 cpu_group_start = get_cpu_thread_group_start(cpu, tg);
967 if (unlikely(cpu_group_start == -1)) {
972 if (cache_property == THREAD_GROUP_SHARE_L1) {
973 mask = &per_cpu(thread_group_l1_cache_map, cpu);
974 update_mask_from_threadgroup(mask, tg, cpu, cpu_group_start);
976 else if (cache_property == THREAD_GROUP_SHARE_L2_L3) {
977 mask = &per_cpu(thread_group_l2_cache_map, cpu);
978 update_mask_from_threadgroup(mask, tg, cpu, cpu_group_start);
979 mask = &per_cpu(thread_group_l3_cache_map, cpu);
980 update_mask_from_threadgroup(mask, tg, cpu, cpu_group_start);
987 static bool shared_caches;
989 #ifdef CONFIG_SCHED_SMT
990 /* cpumask of CPUs with asymmetric SMT dependency */
991 static int powerpc_smt_flags(void)
993 int flags = SD_SHARE_CPUCAPACITY | SD_SHARE_PKG_RESOURCES;
995 if (cpu_has_feature(CPU_FTR_ASYM_SMT)) {
996 printk_once(KERN_INFO "Enabling Asymmetric SMT scheduling\n");
997 flags |= SD_ASYM_PACKING;
1004 * P9 has a slightly odd architecture where pairs of cores share an L2 cache.
1005 * This topology makes it *much* cheaper to migrate tasks between adjacent cores
1006 * since the migrated task remains cache hot. We want to take advantage of this
1007 * at the scheduler level so an extra topology level is required.
1009 static int powerpc_shared_cache_flags(void)
1011 return SD_SHARE_PKG_RESOURCES;
1015 * We can't just pass cpu_l2_cache_mask() directly because
1016 * returns a non-const pointer and the compiler barfs on that.
1018 static const struct cpumask *shared_cache_mask(int cpu)
1020 return per_cpu(cpu_l2_cache_map, cpu);
1023 #ifdef CONFIG_SCHED_SMT
1024 static const struct cpumask *smallcore_smt_mask(int cpu)
1026 return cpu_smallcore_mask(cpu);
1030 static struct cpumask *cpu_coregroup_mask(int cpu)
1032 return per_cpu(cpu_coregroup_map, cpu);
1035 static bool has_coregroup_support(void)
1037 return coregroup_enabled;
1040 static const struct cpumask *cpu_mc_mask(int cpu)
1042 return cpu_coregroup_mask(cpu);
1045 static struct sched_domain_topology_level powerpc_topology[] = {
1046 #ifdef CONFIG_SCHED_SMT
1047 { cpu_smt_mask, powerpc_smt_flags, SD_INIT_NAME(SMT) },
1049 { shared_cache_mask, powerpc_shared_cache_flags, SD_INIT_NAME(CACHE) },
1050 { cpu_mc_mask, SD_INIT_NAME(MC) },
1051 { cpu_cpu_mask, SD_INIT_NAME(DIE) },
1055 static int __init init_big_cores(void)
1059 for_each_possible_cpu(cpu) {
1060 int err = init_thread_group_cache_map(cpu, THREAD_GROUP_SHARE_L1);
1065 zalloc_cpumask_var_node(&per_cpu(cpu_smallcore_map, cpu),
1070 has_big_cores = true;
1072 for_each_possible_cpu(cpu) {
1073 int err = init_thread_group_cache_map(cpu, THREAD_GROUP_SHARE_L2_L3);
1079 thread_group_shares_l2 = true;
1080 thread_group_shares_l3 = true;
1081 pr_debug("L2/L3 cache only shared by the threads in the small core\n");
1086 void __init smp_prepare_cpus(unsigned int max_cpus)
1090 DBG("smp_prepare_cpus\n");
1093 * setup_cpu may need to be called on the boot cpu. We haven't
1094 * spun any cpus up but lets be paranoid.
1096 BUG_ON(boot_cpuid != smp_processor_id());
1098 /* Fixup boot cpu */
1099 smp_store_cpu_info(boot_cpuid);
1100 cpu_callin_map[boot_cpuid] = 1;
1102 for_each_possible_cpu(cpu) {
1103 zalloc_cpumask_var_node(&per_cpu(cpu_sibling_map, cpu),
1104 GFP_KERNEL, cpu_to_node(cpu));
1105 zalloc_cpumask_var_node(&per_cpu(cpu_l2_cache_map, cpu),
1106 GFP_KERNEL, cpu_to_node(cpu));
1107 zalloc_cpumask_var_node(&per_cpu(cpu_core_map, cpu),
1108 GFP_KERNEL, cpu_to_node(cpu));
1109 if (has_coregroup_support())
1110 zalloc_cpumask_var_node(&per_cpu(cpu_coregroup_map, cpu),
1111 GFP_KERNEL, cpu_to_node(cpu));
1115 * numa_node_id() works after this.
1117 if (cpu_present(cpu)) {
1118 set_cpu_numa_node(cpu, numa_cpu_lookup_table[cpu]);
1119 set_cpu_numa_mem(cpu,
1120 local_memory_node(numa_cpu_lookup_table[cpu]));
1125 /* Init the cpumasks so the boot CPU is related to itself */
1126 cpumask_set_cpu(boot_cpuid, cpu_sibling_mask(boot_cpuid));
1127 cpumask_set_cpu(boot_cpuid, cpu_l2_cache_mask(boot_cpuid));
1128 cpumask_set_cpu(boot_cpuid, cpu_core_mask(boot_cpuid));
1130 if (has_coregroup_support())
1131 cpumask_set_cpu(boot_cpuid, cpu_coregroup_mask(boot_cpuid));
1134 if (has_big_cores) {
1135 cpumask_set_cpu(boot_cpuid,
1136 cpu_smallcore_mask(boot_cpuid));
1139 if (cpu_to_chip_id(boot_cpuid) != -1) {
1140 int idx = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1143 * All threads of a core will all belong to the same core,
1144 * chip_id_lookup_table will have one entry per core.
1145 * Assumption: if boot_cpuid doesn't have a chip-id, then no
1146 * other CPUs, will also not have chip-id.
1148 chip_id_lookup_table = kcalloc(idx, sizeof(int), GFP_KERNEL);
1149 if (chip_id_lookup_table)
1150 memset(chip_id_lookup_table, -1, sizeof(int) * idx);
1153 if (smp_ops && smp_ops->probe)
1157 void smp_prepare_boot_cpu(void)
1159 BUG_ON(smp_processor_id() != boot_cpuid);
1161 paca_ptrs[boot_cpuid]->__current = current;
1163 set_numa_node(numa_cpu_lookup_table[boot_cpuid]);
1164 current_set[boot_cpuid] = current;
1167 #ifdef CONFIG_HOTPLUG_CPU
1169 int generic_cpu_disable(void)
1171 unsigned int cpu = smp_processor_id();
1173 if (cpu == boot_cpuid)
1176 set_cpu_online(cpu, false);
1178 vdso_data->processorCount--;
1180 /* Update affinity of all IRQs previously aimed at this CPU */
1181 irq_migrate_all_off_this_cpu();
1184 * Depending on the details of the interrupt controller, it's possible
1185 * that one of the interrupts we just migrated away from this CPU is
1186 * actually already pending on this CPU. If we leave it in that state
1187 * the interrupt will never be EOI'ed, and will never fire again. So
1188 * temporarily enable interrupts here, to allow any pending interrupt to
1189 * be received (and EOI'ed), before we take this CPU offline.
1193 local_irq_disable();
1198 void generic_cpu_die(unsigned int cpu)
1202 for (i = 0; i < 100; i++) {
1204 if (is_cpu_dead(cpu))
1208 printk(KERN_ERR "CPU%d didn't die...\n", cpu);
1211 void generic_set_cpu_dead(unsigned int cpu)
1213 per_cpu(cpu_state, cpu) = CPU_DEAD;
1217 * The cpu_state should be set to CPU_UP_PREPARE in kick_cpu(), otherwise
1218 * the cpu_state is always CPU_DEAD after calling generic_set_cpu_dead(),
1219 * which makes the delay in generic_cpu_die() not happen.
1221 void generic_set_cpu_up(unsigned int cpu)
1223 per_cpu(cpu_state, cpu) = CPU_UP_PREPARE;
1226 int generic_check_cpu_restart(unsigned int cpu)
1228 return per_cpu(cpu_state, cpu) == CPU_UP_PREPARE;
1231 int is_cpu_dead(unsigned int cpu)
1233 return per_cpu(cpu_state, cpu) == CPU_DEAD;
1236 static bool secondaries_inhibited(void)
1238 return kvm_hv_mode_active();
1241 #else /* HOTPLUG_CPU */
1243 #define secondaries_inhibited() 0
1247 static void cpu_idle_thread_init(unsigned int cpu, struct task_struct *idle)
1250 paca_ptrs[cpu]->__current = idle;
1251 paca_ptrs[cpu]->kstack = (unsigned long)task_stack_page(idle) +
1252 THREAD_SIZE - STACK_FRAME_OVERHEAD;
1254 task_thread_info(idle)->cpu = cpu;
1255 secondary_current = current_set[cpu] = idle;
1258 int __cpu_up(unsigned int cpu, struct task_struct *tidle)
1260 const unsigned long boot_spin_ms = 5 * MSEC_PER_SEC;
1261 const bool booting = system_state < SYSTEM_RUNNING;
1262 const unsigned long hp_spin_ms = 1;
1263 unsigned long deadline;
1265 const unsigned long spin_wait_ms = booting ? boot_spin_ms : hp_spin_ms;
1268 * Don't allow secondary threads to come online if inhibited
1270 if (threads_per_core > 1 && secondaries_inhibited() &&
1271 cpu_thread_in_subcore(cpu))
1274 if (smp_ops == NULL ||
1275 (smp_ops->cpu_bootable && !smp_ops->cpu_bootable(cpu)))
1278 cpu_idle_thread_init(cpu, tidle);
1281 * The platform might need to allocate resources prior to bringing
1284 if (smp_ops->prepare_cpu) {
1285 rc = smp_ops->prepare_cpu(cpu);
1290 /* Make sure callin-map entry is 0 (can be leftover a CPU
1293 cpu_callin_map[cpu] = 0;
1295 /* The information for processor bringup must
1296 * be written out to main store before we release
1302 DBG("smp: kicking cpu %d\n", cpu);
1303 rc = smp_ops->kick_cpu(cpu);
1305 pr_err("smp: failed starting cpu %d (rc %d)\n", cpu, rc);
1310 * At boot time, simply spin on the callin word until the
1313 * At run time, spin for an optimistic amount of time to avoid
1314 * sleeping in the common case.
1316 deadline = jiffies + msecs_to_jiffies(spin_wait_ms);
1317 spin_until_cond(cpu_callin_map[cpu] || time_is_before_jiffies(deadline));
1319 if (!cpu_callin_map[cpu] && system_state >= SYSTEM_RUNNING) {
1320 const unsigned long sleep_interval_us = 10 * USEC_PER_MSEC;
1321 const unsigned long sleep_wait_ms = 100 * MSEC_PER_SEC;
1323 deadline = jiffies + msecs_to_jiffies(sleep_wait_ms);
1324 while (!cpu_callin_map[cpu] && time_is_after_jiffies(deadline))
1325 fsleep(sleep_interval_us);
1328 if (!cpu_callin_map[cpu]) {
1329 printk(KERN_ERR "Processor %u is stuck.\n", cpu);
1333 DBG("Processor %u found.\n", cpu);
1335 if (smp_ops->give_timebase)
1336 smp_ops->give_timebase();
1338 /* Wait until cpu puts itself in the online & active maps */
1339 spin_until_cond(cpu_online(cpu));
1344 /* Return the value of the reg property corresponding to the given
1347 int cpu_to_core_id(int cpu)
1349 struct device_node *np;
1352 np = of_get_cpu_node(cpu, NULL);
1356 id = of_get_cpu_hwid(np, 0);
1361 EXPORT_SYMBOL_GPL(cpu_to_core_id);
1363 /* Helper routines for cpu to core mapping */
1364 int cpu_core_index_of_thread(int cpu)
1366 return cpu >> threads_shift;
1368 EXPORT_SYMBOL_GPL(cpu_core_index_of_thread);
1370 int cpu_first_thread_of_core(int core)
1372 return core << threads_shift;
1374 EXPORT_SYMBOL_GPL(cpu_first_thread_of_core);
1376 /* Must be called when no change can occur to cpu_present_mask,
1377 * i.e. during cpu online or offline.
1379 static struct device_node *cpu_to_l2cache(int cpu)
1381 struct device_node *np;
1382 struct device_node *cache;
1384 if (!cpu_present(cpu))
1387 np = of_get_cpu_node(cpu, NULL);
1391 cache = of_find_next_cache_node(np);
1398 static bool update_mask_by_l2(int cpu, cpumask_var_t *mask)
1400 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask;
1401 struct device_node *l2_cache, *np;
1405 submask_fn = cpu_smallcore_mask;
1408 * If the threads in a thread-group share L2 cache, then the
1409 * L2-mask can be obtained from thread_group_l2_cache_map.
1411 if (thread_group_shares_l2) {
1412 cpumask_set_cpu(cpu, cpu_l2_cache_mask(cpu));
1414 for_each_cpu(i, per_cpu(thread_group_l2_cache_map, cpu)) {
1416 set_cpus_related(i, cpu, cpu_l2_cache_mask);
1419 /* Verify that L1-cache siblings are a subset of L2 cache-siblings */
1420 if (!cpumask_equal(submask_fn(cpu), cpu_l2_cache_mask(cpu)) &&
1421 !cpumask_subset(submask_fn(cpu), cpu_l2_cache_mask(cpu))) {
1422 pr_warn_once("CPU %d : Inconsistent L1 and L2 cache siblings\n",
1429 l2_cache = cpu_to_l2cache(cpu);
1430 if (!l2_cache || !*mask) {
1431 /* Assume only core siblings share cache with this CPU */
1432 for_each_cpu(i, cpu_sibling_mask(cpu))
1433 set_cpus_related(cpu, i, cpu_l2_cache_mask);
1438 cpumask_and(*mask, cpu_online_mask, cpu_cpu_mask(cpu));
1440 /* Update l2-cache mask with all the CPUs that are part of submask */
1441 or_cpumasks_related(cpu, cpu, submask_fn, cpu_l2_cache_mask);
1443 /* Skip all CPUs already part of current CPU l2-cache mask */
1444 cpumask_andnot(*mask, *mask, cpu_l2_cache_mask(cpu));
1446 for_each_cpu(i, *mask) {
1448 * when updating the marks the current CPU has not been marked
1449 * online, but we need to update the cache masks
1451 np = cpu_to_l2cache(i);
1453 /* Skip all CPUs already part of current CPU l2-cache */
1454 if (np == l2_cache) {
1455 or_cpumasks_related(cpu, i, submask_fn, cpu_l2_cache_mask);
1456 cpumask_andnot(*mask, *mask, submask_fn(i));
1458 cpumask_andnot(*mask, *mask, cpu_l2_cache_mask(i));
1463 of_node_put(l2_cache);
1468 #ifdef CONFIG_HOTPLUG_CPU
1469 static void remove_cpu_from_masks(int cpu)
1471 struct cpumask *(*mask_fn)(int) = cpu_sibling_mask;
1474 unmap_cpu_from_node(cpu);
1477 mask_fn = cpu_l2_cache_mask;
1479 for_each_cpu(i, mask_fn(cpu)) {
1480 set_cpus_unrelated(cpu, i, cpu_l2_cache_mask);
1481 set_cpus_unrelated(cpu, i, cpu_sibling_mask);
1483 set_cpus_unrelated(cpu, i, cpu_smallcore_mask);
1486 for_each_cpu(i, cpu_core_mask(cpu))
1487 set_cpus_unrelated(cpu, i, cpu_core_mask);
1489 if (has_coregroup_support()) {
1490 for_each_cpu(i, cpu_coregroup_mask(cpu))
1491 set_cpus_unrelated(cpu, i, cpu_coregroup_mask);
1496 static inline void add_cpu_to_smallcore_masks(int cpu)
1503 cpumask_set_cpu(cpu, cpu_smallcore_mask(cpu));
1505 for_each_cpu(i, per_cpu(thread_group_l1_cache_map, cpu)) {
1507 set_cpus_related(i, cpu, cpu_smallcore_mask);
1511 static void update_coregroup_mask(int cpu, cpumask_var_t *mask)
1513 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask;
1514 int coregroup_id = cpu_to_coregroup_id(cpu);
1518 submask_fn = cpu_l2_cache_mask;
1521 /* Assume only siblings are part of this CPU's coregroup */
1522 for_each_cpu(i, submask_fn(cpu))
1523 set_cpus_related(cpu, i, cpu_coregroup_mask);
1528 cpumask_and(*mask, cpu_online_mask, cpu_cpu_mask(cpu));
1530 /* Update coregroup mask with all the CPUs that are part of submask */
1531 or_cpumasks_related(cpu, cpu, submask_fn, cpu_coregroup_mask);
1533 /* Skip all CPUs already part of coregroup mask */
1534 cpumask_andnot(*mask, *mask, cpu_coregroup_mask(cpu));
1536 for_each_cpu(i, *mask) {
1537 /* Skip all CPUs not part of this coregroup */
1538 if (coregroup_id == cpu_to_coregroup_id(i)) {
1539 or_cpumasks_related(cpu, i, submask_fn, cpu_coregroup_mask);
1540 cpumask_andnot(*mask, *mask, submask_fn(i));
1542 cpumask_andnot(*mask, *mask, cpu_coregroup_mask(i));
1547 static void add_cpu_to_masks(int cpu)
1549 struct cpumask *(*submask_fn)(int) = cpu_sibling_mask;
1550 int first_thread = cpu_first_thread_sibling(cpu);
1557 * This CPU will not be in the online mask yet so we need to manually
1558 * add it to it's own thread sibling mask.
1560 map_cpu_to_node(cpu, cpu_to_node(cpu));
1561 cpumask_set_cpu(cpu, cpu_sibling_mask(cpu));
1562 cpumask_set_cpu(cpu, cpu_core_mask(cpu));
1564 for (i = first_thread; i < first_thread + threads_per_core; i++)
1566 set_cpus_related(i, cpu, cpu_sibling_mask);
1568 add_cpu_to_smallcore_masks(cpu);
1570 /* In CPU-hotplug path, hence use GFP_ATOMIC */
1571 ret = alloc_cpumask_var_node(&mask, GFP_ATOMIC, cpu_to_node(cpu));
1572 update_mask_by_l2(cpu, &mask);
1574 if (has_coregroup_support())
1575 update_coregroup_mask(cpu, &mask);
1577 if (chip_id_lookup_table && ret)
1578 chip_id = cpu_to_chip_id(cpu);
1581 submask_fn = cpu_l2_cache_mask;
1583 /* Update core_mask with all the CPUs that are part of submask */
1584 or_cpumasks_related(cpu, cpu, submask_fn, cpu_core_mask);
1586 /* Skip all CPUs already part of current CPU core mask */
1587 cpumask_andnot(mask, cpu_online_mask, cpu_core_mask(cpu));
1589 /* If chip_id is -1; limit the cpu_core_mask to within DIE*/
1591 cpumask_and(mask, mask, cpu_cpu_mask(cpu));
1593 for_each_cpu(i, mask) {
1594 if (chip_id == cpu_to_chip_id(i)) {
1595 or_cpumasks_related(cpu, i, submask_fn, cpu_core_mask);
1596 cpumask_andnot(mask, mask, submask_fn(i));
1598 cpumask_andnot(mask, mask, cpu_core_mask(i));
1602 free_cpumask_var(mask);
1605 /* Activate a secondary processor. */
1606 void start_secondary(void *unused)
1608 unsigned int cpu = raw_smp_processor_id();
1610 /* PPC64 calls setup_kup() in early_setup_secondary() */
1611 if (IS_ENABLED(CONFIG_PPC32))
1615 current->active_mm = &init_mm;
1617 smp_store_cpu_info(cpu);
1618 set_dec(tb_ticks_per_jiffy);
1619 rcu_cpu_starting(cpu);
1620 cpu_callin_map[cpu] = 1;
1622 if (smp_ops->setup_cpu)
1623 smp_ops->setup_cpu(cpu);
1624 if (smp_ops->take_timebase)
1625 smp_ops->take_timebase();
1627 secondary_cpu_time_init();
1630 if (system_state == SYSTEM_RUNNING)
1631 vdso_data->processorCount++;
1635 set_numa_node(numa_cpu_lookup_table[cpu]);
1636 set_numa_mem(local_memory_node(numa_cpu_lookup_table[cpu]));
1638 /* Update topology CPU masks */
1639 add_cpu_to_masks(cpu);
1642 * Check for any shared caches. Note that this must be done on a
1643 * per-core basis because one core in the pair might be disabled.
1645 if (!shared_caches) {
1646 struct cpumask *(*sibling_mask)(int) = cpu_sibling_mask;
1647 struct cpumask *mask = cpu_l2_cache_mask(cpu);
1650 sibling_mask = cpu_smallcore_mask;
1652 if (cpumask_weight(mask) > cpumask_weight(sibling_mask(cpu)))
1653 shared_caches = true;
1657 notify_cpu_starting(cpu);
1658 set_cpu_online(cpu, true);
1660 boot_init_stack_canary();
1664 /* We can enable ftrace for secondary cpus now */
1665 this_cpu_enable_ftrace();
1667 cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
1672 static void __init fixup_topology(void)
1676 #ifdef CONFIG_SCHED_SMT
1677 if (has_big_cores) {
1678 pr_info("Big cores detected but using small core scheduling\n");
1679 powerpc_topology[smt_idx].mask = smallcore_smt_mask;
1683 if (!has_coregroup_support())
1684 powerpc_topology[mc_idx].mask = powerpc_topology[cache_idx].mask;
1687 * Try to consolidate topology levels here instead of
1688 * allowing scheduler to degenerate.
1689 * - Dont consolidate if masks are different.
1690 * - Dont consolidate if sd_flags exists and are different.
1692 for (i = 1; i <= die_idx; i++) {
1693 if (powerpc_topology[i].mask != powerpc_topology[i - 1].mask)
1696 if (powerpc_topology[i].sd_flags && powerpc_topology[i - 1].sd_flags &&
1697 powerpc_topology[i].sd_flags != powerpc_topology[i - 1].sd_flags)
1700 if (!powerpc_topology[i - 1].sd_flags)
1701 powerpc_topology[i - 1].sd_flags = powerpc_topology[i].sd_flags;
1703 powerpc_topology[i].mask = powerpc_topology[i + 1].mask;
1704 powerpc_topology[i].sd_flags = powerpc_topology[i + 1].sd_flags;
1705 #ifdef CONFIG_SCHED_DEBUG
1706 powerpc_topology[i].name = powerpc_topology[i + 1].name;
1711 void __init smp_cpus_done(unsigned int max_cpus)
1714 * We are running pinned to the boot CPU, see rest_init().
1716 if (smp_ops && smp_ops->setup_cpu)
1717 smp_ops->setup_cpu(boot_cpuid);
1719 if (smp_ops && smp_ops->bringup_done)
1720 smp_ops->bringup_done();
1722 dump_numa_cpu_topology();
1725 set_sched_topology(powerpc_topology);
1728 #ifdef CONFIG_HOTPLUG_CPU
1729 int __cpu_disable(void)
1731 int cpu = smp_processor_id();
1734 if (!smp_ops->cpu_disable)
1737 this_cpu_disable_ftrace();
1739 err = smp_ops->cpu_disable();
1743 /* Update sibling maps */
1744 remove_cpu_from_masks(cpu);
1749 void __cpu_die(unsigned int cpu)
1751 if (smp_ops->cpu_die)
1752 smp_ops->cpu_die(cpu);
1755 void arch_cpu_idle_dead(void)
1758 * Disable on the down path. This will be re-enabled by
1759 * start_secondary() via start_secondary_resume() below
1761 this_cpu_disable_ftrace();
1763 if (smp_ops->cpu_offline_self)
1764 smp_ops->cpu_offline_self();
1766 /* If we return, we re-enter start_secondary */
1767 start_secondary_resume();