arch/powerpc/kernel/ptrace.c

   1 /*
   2  *  PowerPC version
   3  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
   4  *
   5  *  Derived from "arch/m68k/kernel/ptrace.c"
   6  *  Copyright (C) 1994 by Hamish Macdonald
   7  *  Taken from linux/kernel/ptrace.c and modified for M680x0.
   8  *  linux/kernel/ptrace.c is by Ross Biro 1/23/92, edited by Linus Torvalds
   9  *
  10  * Modified by Cort Dougan (cort@hq.fsmlabs.com)
  11  * and Paul Mackerras (paulus@samba.org).
  12  *
  13  * This file is subject to the terms and conditions of the GNU General
  14  * Public License.  See the file README.legal in the main directory of
  15  * this archive for more details.
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/sched.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/errno.h>
  23 #include <linux/ptrace.h>
  24 #include <linux/regset.h>
  25 #include <linux/tracehook.h>
  26 #include <linux/elf.h>
  27 #include <linux/user.h>
  28 #include <linux/security.h>
  29 #include <linux/signal.h>
  30 #include <linux/seccomp.h>
  31 #include <linux/audit.h>
  32 #include <trace/syscall.h>
  33 #include <linux/hw_breakpoint.h>
  34 #include <linux/perf_event.h>
  35 #include <linux/context_tracking.h>
  36
  37 #include <linux/uaccess.h>
  38 #include <asm/page.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/switch_to.h>
  41 #include <asm/tm.h>
  42 #include <asm/asm-prototypes.h>
  43
  44 #define CREATE_TRACE_POINTS
  45 #include <trace/events/syscalls.h>
  46
  47 /*
  48  * The parameter save area on the stack is used to store arguments being passed
  49  * to callee function and is located at fixed offset from stack pointer.
  50  */
  51 #ifdef CONFIG_PPC32
  52 #define PARAMETER_SAVE_AREA_OFFSET      24  /* bytes */
  53 #else /* CONFIG_PPC32 */
  54 #define PARAMETER_SAVE_AREA_OFFSET      48  /* bytes */
  55 #endif
  56
  57 struct pt_regs_offset {
  58         const char *name;
  59         int offset;
  60 };
  61
  62 #define STR(s)  #s                      /* convert to string */
  63 #define REG_OFFSET_NAME(r) {.name = #r, .offset = offsetof(struct pt_regs, r)}
  64 #define GPR_OFFSET_NAME(num)    \
  65         {.name = STR(r##num), .offset = offsetof(struct pt_regs, gpr[num])}, \
  66         {.name = STR(gpr##num), .offset = offsetof(struct pt_regs, gpr[num])}
  67 #define REG_OFFSET_END {.name = NULL, .offset = 0}
  68
  69 #define TVSO(f) (offsetof(struct thread_vr_state, f))
  70 #define TFSO(f) (offsetof(struct thread_fp_state, f))
  71 #define TSO(f)  (offsetof(struct thread_struct, f))
  72
  73 static const struct pt_regs_offset regoffset_table[] = {
  74         GPR_OFFSET_NAME(0),
  75         GPR_OFFSET_NAME(1),
  76         GPR_OFFSET_NAME(2),
  77         GPR_OFFSET_NAME(3),
  78         GPR_OFFSET_NAME(4),
  79         GPR_OFFSET_NAME(5),
  80         GPR_OFFSET_NAME(6),
  81         GPR_OFFSET_NAME(7),
  82         GPR_OFFSET_NAME(8),
  83         GPR_OFFSET_NAME(9),
  84         GPR_OFFSET_NAME(10),
  85         GPR_OFFSET_NAME(11),
  86         GPR_OFFSET_NAME(12),
  87         GPR_OFFSET_NAME(13),
  88         GPR_OFFSET_NAME(14),
  89         GPR_OFFSET_NAME(15),
  90         GPR_OFFSET_NAME(16),
  91         GPR_OFFSET_NAME(17),
  92         GPR_OFFSET_NAME(18),
  93         GPR_OFFSET_NAME(19),
  94         GPR_OFFSET_NAME(20),
  95         GPR_OFFSET_NAME(21),
  96         GPR_OFFSET_NAME(22),
  97         GPR_OFFSET_NAME(23),
  98         GPR_OFFSET_NAME(24),
  99         GPR_OFFSET_NAME(25),
 100         GPR_OFFSET_NAME(26),
 101         GPR_OFFSET_NAME(27),
 102         GPR_OFFSET_NAME(28),
 103         GPR_OFFSET_NAME(29),
 104         GPR_OFFSET_NAME(30),
 105         GPR_OFFSET_NAME(31),
 106         REG_OFFSET_NAME(nip),
 107         REG_OFFSET_NAME(msr),
 108         REG_OFFSET_NAME(ctr),
 109         REG_OFFSET_NAME(link),
 110         REG_OFFSET_NAME(xer),
 111         REG_OFFSET_NAME(ccr),
 112 #ifdef CONFIG_PPC64
 113         REG_OFFSET_NAME(softe),
 114 #else
 115         REG_OFFSET_NAME(mq),
 116 #endif
 117         REG_OFFSET_NAME(trap),
 118         REG_OFFSET_NAME(dar),
 119         REG_OFFSET_NAME(dsisr),
 120         REG_OFFSET_END,
 121 };
 122
 123 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 124 static void flush_tmregs_to_thread(struct task_struct *tsk)
 125 {
 126         /*
 127          * If task is not current, it will have been flushed already to
 128          * it's thread_struct during __switch_to().
 129          *
 130          * A reclaim flushes ALL the state or if not in TM save TM SPRs
 131          * in the appropriate thread structures from live.
 132          */
 133
 134         if ((!cpu_has_feature(CPU_FTR_TM)) || (tsk != current))
 135                 return;
 136
 137         if (MSR_TM_SUSPENDED(mfmsr())) {
 138                 tm_reclaim_current(TM_CAUSE_SIGNAL);
 139         } else {
 140                 tm_enable();
 141                 tm_save_sprs(&(tsk->thread));
 142         }
 143 }
 144 #else
 145 static inline void flush_tmregs_to_thread(struct task_struct *tsk) { }
 146 #endif
 147
 148 /**
 149  * regs_query_register_offset() - query register offset from its name
 150  * @name:       the name of a register
 151  *
 152  * regs_query_register_offset() returns the offset of a register in struct
 153  * pt_regs from its name. If the name is invalid, this returns -EINVAL;
 154  */
 155 int regs_query_register_offset(const char *name)
 156 {
 157         const struct pt_regs_offset *roff;
 158         for (roff = regoffset_table; roff->name != NULL; roff++)
 159                 if (!strcmp(roff->name, name))
 160                         return roff->offset;
 161         return -EINVAL;
 162 }
 163
 164 /**
 165  * regs_query_register_name() - query register name from its offset
 166  * @offset:     the offset of a register in struct pt_regs.
 167  *
 168  * regs_query_register_name() returns the name of a register from its
 169  * offset in struct pt_regs. If the @offset is invalid, this returns NULL;
 170  */
 171 const char *regs_query_register_name(unsigned int offset)
 172 {
 173         const struct pt_regs_offset *roff;
 174         for (roff = regoffset_table; roff->name != NULL; roff++)
 175                 if (roff->offset == offset)
 176                         return roff->name;
 177         return NULL;
 178 }
 179
 180 /*
 181  * does not yet catch signals sent when the child dies.
 182  * in exit.c or in signal.c.
 183  */
 184
 185 /*
 186  * Set of msr bits that gdb can change on behalf of a process.
 187  */
 188 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 189 #define MSR_DEBUGCHANGE 0
 190 #else
 191 #define MSR_DEBUGCHANGE (MSR_SE | MSR_BE)
 192 #endif
 193
 194 /*
 195  * Max register writeable via put_reg
 196  */
 197 #ifdef CONFIG_PPC32
 198 #define PT_MAX_PUT_REG  PT_MQ
 199 #else
 200 #define PT_MAX_PUT_REG  PT_CCR
 201 #endif
 202
 203 static unsigned long get_user_msr(struct task_struct *task)
 204 {
 205         return task->thread.regs->msr | task->thread.fpexc_mode;
 206 }
 207
 208 static int set_user_msr(struct task_struct *task, unsigned long msr)
 209 {
 210         task->thread.regs->msr &= ~MSR_DEBUGCHANGE;
 211         task->thread.regs->msr |= msr & MSR_DEBUGCHANGE;
 212         return 0;
 213 }
 214
 215 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 216 static unsigned long get_user_ckpt_msr(struct task_struct *task)
 217 {
 218         return task->thread.ckpt_regs.msr | task->thread.fpexc_mode;
 219 }
 220
 221 static int set_user_ckpt_msr(struct task_struct *task, unsigned long msr)
 222 {
 223         task->thread.ckpt_regs.msr &= ~MSR_DEBUGCHANGE;
 224         task->thread.ckpt_regs.msr |= msr & MSR_DEBUGCHANGE;
 225         return 0;
 226 }
 227
 228 static int set_user_ckpt_trap(struct task_struct *task, unsigned long trap)
 229 {
 230         task->thread.ckpt_regs.trap = trap & 0xfff0;
 231         return 0;
 232 }
 233 #endif
 234
 235 #ifdef CONFIG_PPC64
 236 static int get_user_dscr(struct task_struct *task, unsigned long *data)
 237 {
 238         *data = task->thread.dscr;
 239         return 0;
 240 }
 241
 242 static int set_user_dscr(struct task_struct *task, unsigned long dscr)
 243 {
 244         task->thread.dscr = dscr;
 245         task->thread.dscr_inherit = 1;
 246         return 0;
 247 }
 248 #else
 249 static int get_user_dscr(struct task_struct *task, unsigned long *data)
 250 {
 251         return -EIO;
 252 }
 253
 254 static int set_user_dscr(struct task_struct *task, unsigned long dscr)
 255 {
 256         return -EIO;
 257 }
 258 #endif
 259
 260 /*
 261  * We prevent mucking around with the reserved area of trap
 262  * which are used internally by the kernel.
 263  */
 264 static int set_user_trap(struct task_struct *task, unsigned long trap)
 265 {
 266         task->thread.regs->trap = trap & 0xfff0;
 267         return 0;
 268 }
 269
 270 /*
 271  * Get contents of register REGNO in task TASK.
 272  */
 273 int ptrace_get_reg(struct task_struct *task, int regno, unsigned long *data)
 274 {
 275         if ((task->thread.regs == NULL) || !data)
 276                 return -EIO;
 277
 278         if (regno == PT_MSR) {
 279                 *data = get_user_msr(task);
 280                 return 0;
 281         }
 282
 283         if (regno == PT_DSCR)
 284                 return get_user_dscr(task, data);
 285
 286         if (regno < (sizeof(struct pt_regs) / sizeof(unsigned long))) {
 287                 *data = ((unsigned long *)task->thread.regs)[regno];
 288                 return 0;
 289         }
 290
 291         return -EIO;
 292 }
 293
 294 /*
 295  * Write contents of register REGNO in task TASK.
 296  */
 297 int ptrace_put_reg(struct task_struct *task, int regno, unsigned long data)
 298 {
 299         if (task->thread.regs == NULL)
 300                 return -EIO;
 301
 302         if (regno == PT_MSR)
 303                 return set_user_msr(task, data);
 304         if (regno == PT_TRAP)
 305                 return set_user_trap(task, data);
 306         if (regno == PT_DSCR)
 307                 return set_user_dscr(task, data);
 308
 309         if (regno <= PT_MAX_PUT_REG) {
 310                 ((unsigned long *)task->thread.regs)[regno] = data;
 311                 return 0;
 312         }
 313         return -EIO;
 314 }
 315
 316 static int gpr_get(struct task_struct *target, const struct user_regset *regset,
 317                    unsigned int pos, unsigned int count,
 318                    void *kbuf, void __user *ubuf)
 319 {
 320         int i, ret;
 321
 322         if (target->thread.regs == NULL)
 323                 return -EIO;
 324
 325         if (!FULL_REGS(target->thread.regs)) {
 326                 /* We have a partial register set.  Fill 14-31 with bogus values */
 327                 for (i = 14; i < 32; i++)
 328                         target->thread.regs->gpr[i] = NV_REG_POISON;
 329         }
 330
 331         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 332                                   target->thread.regs,
 333                                   0, offsetof(struct pt_regs, msr));
 334         if (!ret) {
 335                 unsigned long msr = get_user_msr(target);
 336                 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
 337                                           offsetof(struct pt_regs, msr),
 338                                           offsetof(struct pt_regs, msr) +
 339                                           sizeof(msr));
 340         }
 341
 342         BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
 343                      offsetof(struct pt_regs, msr) + sizeof(long));
 344
 345         if (!ret)
 346                 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 347                                           &target->thread.regs->orig_gpr3,
 348                                           offsetof(struct pt_regs, orig_gpr3),
 349                                           sizeof(struct pt_regs));
 350         if (!ret)
 351                 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
 352                                                sizeof(struct pt_regs), -1);
 353
 354         return ret;
 355 }
 356
 357 static int gpr_set(struct task_struct *target, const struct user_regset *regset,
 358                    unsigned int pos, unsigned int count,
 359                    const void *kbuf, const void __user *ubuf)
 360 {
 361         unsigned long reg;
 362         int ret;
 363
 364         if (target->thread.regs == NULL)
 365                 return -EIO;
 366
 367         CHECK_FULL_REGS(target->thread.regs);
 368
 369         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 370                                  target->thread.regs,
 371                                  0, PT_MSR * sizeof(reg));
 372
 373         if (!ret && count > 0) {
 374                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
 375                                          PT_MSR * sizeof(reg),
 376                                          (PT_MSR + 1) * sizeof(reg));
 377                 if (!ret)
 378                         ret = set_user_msr(target, reg);
 379         }
 380
 381         BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
 382                      offsetof(struct pt_regs, msr) + sizeof(long));
 383
 384         if (!ret)
 385                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 386                                          &target->thread.regs->orig_gpr3,
 387                                          PT_ORIG_R3 * sizeof(reg),
 388                                          (PT_MAX_PUT_REG + 1) * sizeof(reg));
 389
 390         if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
 391                 ret = user_regset_copyin_ignore(
 392                         &pos, &count, &kbuf, &ubuf,
 393                         (PT_MAX_PUT_REG + 1) * sizeof(reg),
 394                         PT_TRAP * sizeof(reg));
 395
 396         if (!ret && count > 0) {
 397                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
 398                                          PT_TRAP * sizeof(reg),
 399                                          (PT_TRAP + 1) * sizeof(reg));
 400                 if (!ret)
 401                         ret = set_user_trap(target, reg);
 402         }
 403
 404         if (!ret)
 405                 ret = user_regset_copyin_ignore(
 406                         &pos, &count, &kbuf, &ubuf,
 407                         (PT_TRAP + 1) * sizeof(reg), -1);
 408
 409         return ret;
 410 }
 411
 412 /*
 413  * Regardless of transactions, 'fp_state' holds the current running
 414  * value of all FPR registers and 'ckfp_state' holds the last checkpointed
 415  * value of all FPR registers for the current transaction.
 416  *
 417  * Userspace interface buffer layout:
 418  *
 419  * struct data {
 420  *      u64     fpr[32];
 421  *      u64     fpscr;
 422  * };
 423  */
 424 static int fpr_get(struct task_struct *target, const struct user_regset *regset,
 425                    unsigned int pos, unsigned int count,
 426                    void *kbuf, void __user *ubuf)
 427 {
 428 #ifdef CONFIG_VSX
 429         u64 buf[33];
 430         int i;
 431
 432         flush_fp_to_thread(target);
 433
 434         /* copy to local buffer then write that out */
 435         for (i = 0; i < 32 ; i++)
 436                 buf[i] = target->thread.TS_FPR(i);
 437         buf[32] = target->thread.fp_state.fpscr;
 438         return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
 439 #else
 440         BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
 441                      offsetof(struct thread_fp_state, fpr[32]));
 442
 443         flush_fp_to_thread(target);
 444
 445         return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 446                                    &target->thread.fp_state, 0, -1);
 447 #endif
 448 }
 449
 450 /*
 451  * Regardless of transactions, 'fp_state' holds the current running
 452  * value of all FPR registers and 'ckfp_state' holds the last checkpointed
 453  * value of all FPR registers for the current transaction.
 454  *
 455  * Userspace interface buffer layout:
 456  *
 457  * struct data {
 458  *      u64     fpr[32];
 459  *      u64     fpscr;
 460  * };
 461  *
 462  */
 463 static int fpr_set(struct task_struct *target, const struct user_regset *regset,
 464                    unsigned int pos, unsigned int count,
 465                    const void *kbuf, const void __user *ubuf)
 466 {
 467 #ifdef CONFIG_VSX
 468         u64 buf[33];
 469         int i;
 470
 471         flush_fp_to_thread(target);
 472
 473         for (i = 0; i < 32 ; i++)
 474                 buf[i] = target->thread.TS_FPR(i);
 475         buf[32] = target->thread.fp_state.fpscr;
 476
 477         /* copy to local buffer then write that out */
 478         i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
 479         if (i)
 480                 return i;
 481
 482         for (i = 0; i < 32 ; i++)
 483                 target->thread.TS_FPR(i) = buf[i];
 484         target->thread.fp_state.fpscr = buf[32];
 485         return 0;
 486 #else
 487         BUILD_BUG_ON(offsetof(struct thread_fp_state, fpscr) !=
 488                      offsetof(struct thread_fp_state, fpr[32]));
 489
 490         flush_fp_to_thread(target);
 491
 492         return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 493                                   &target->thread.fp_state, 0, -1);
 494 #endif
 495 }
 496
 497 #ifdef CONFIG_ALTIVEC
 498 /*
 499  * Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go.
 500  * The transfer totals 34 quadword.  Quadwords 0-31 contain the
 501  * corresponding vector registers.  Quadword 32 contains the vscr as the
 502  * last word (offset 12) within that quadword.  Quadword 33 contains the
 503  * vrsave as the first word (offset 0) within the quadword.
 504  *
 505  * This definition of the VMX state is compatible with the current PPC32
 506  * ptrace interface.  This allows signal handling and ptrace to use the
 507  * same structures.  This also simplifies the implementation of a bi-arch
 508  * (combined (32- and 64-bit) gdb.
 509  */
 510
 511 static int vr_active(struct task_struct *target,
 512                      const struct user_regset *regset)
 513 {
 514         flush_altivec_to_thread(target);
 515         return target->thread.used_vr ? regset->n : 0;
 516 }
 517
 518 /*
 519  * Regardless of transactions, 'vr_state' holds the current running
 520  * value of all the VMX registers and 'ckvr_state' holds the last
 521  * checkpointed value of all the VMX registers for the current
 522  * transaction to fall back on in case it aborts.
 523  *
 524  * Userspace interface buffer layout:
 525  *
 526  * struct data {
 527  *      vector128       vr[32];
 528  *      vector128       vscr;
 529  *      vector128       vrsave;
 530  * };
 531  */
 532 static int vr_get(struct task_struct *target, const struct user_regset *regset,
 533                   unsigned int pos, unsigned int count,
 534                   void *kbuf, void __user *ubuf)
 535 {
 536         int ret;
 537
 538         flush_altivec_to_thread(target);
 539
 540         BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
 541                      offsetof(struct thread_vr_state, vr[32]));
 542
 543         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 544                                   &target->thread.vr_state, 0,
 545                                   33 * sizeof(vector128));
 546         if (!ret) {
 547                 /*
 548                  * Copy out only the low-order word of vrsave.
 549                  */
 550                 int start, end;
 551                 union {
 552                         elf_vrreg_t reg;
 553                         u32 word;
 554                 } vrsave;
 555                 memset(&vrsave, 0, sizeof(vrsave));
 556
 557                 vrsave.word = target->thread.vrsave;
 558
 559                 start = 33 * sizeof(vector128);
 560                 end = start + sizeof(vrsave);
 561                 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
 562                                           start, end);
 563         }
 564
 565         return ret;
 566 }
 567
 568 /*
 569  * Regardless of transactions, 'vr_state' holds the current running
 570  * value of all the VMX registers and 'ckvr_state' holds the last
 571  * checkpointed value of all the VMX registers for the current
 572  * transaction to fall back on in case it aborts.
 573  *
 574  * Userspace interface buffer layout:
 575  *
 576  * struct data {
 577  *      vector128       vr[32];
 578  *      vector128       vscr;
 579  *      vector128       vrsave;
 580  * };
 581  */
 582 static int vr_set(struct task_struct *target, const struct user_regset *regset,
 583                   unsigned int pos, unsigned int count,
 584                   const void *kbuf, const void __user *ubuf)
 585 {
 586         int ret;
 587
 588         flush_altivec_to_thread(target);
 589
 590         BUILD_BUG_ON(offsetof(struct thread_vr_state, vscr) !=
 591                      offsetof(struct thread_vr_state, vr[32]));
 592
 593         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 594                                  &target->thread.vr_state, 0,
 595                                  33 * sizeof(vector128));
 596         if (!ret && count > 0) {
 597                 /*
 598                  * We use only the first word of vrsave.
 599                  */
 600                 int start, end;
 601                 union {
 602                         elf_vrreg_t reg;
 603                         u32 word;
 604                 } vrsave;
 605                 memset(&vrsave, 0, sizeof(vrsave));
 606
 607                 vrsave.word = target->thread.vrsave;
 608
 609                 start = 33 * sizeof(vector128);
 610                 end = start + sizeof(vrsave);
 611                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
 612                                          start, end);
 613                 if (!ret)
 614                         target->thread.vrsave = vrsave.word;
 615         }
 616
 617         return ret;
 618 }
 619 #endif /* CONFIG_ALTIVEC */
 620
 621 #ifdef CONFIG_VSX
 622 /*
 623  * Currently to set and and get all the vsx state, you need to call
 624  * the fp and VMX calls as well.  This only get/sets the lower 32
 625  * 128bit VSX registers.
 626  */
 627
 628 static int vsr_active(struct task_struct *target,
 629                       const struct user_regset *regset)
 630 {
 631         flush_vsx_to_thread(target);
 632         return target->thread.used_vsr ? regset->n : 0;
 633 }
 634
 635 /*
 636  * Regardless of transactions, 'fp_state' holds the current running
 637  * value of all FPR registers and 'ckfp_state' holds the last
 638  * checkpointed value of all FPR registers for the current
 639  * transaction.
 640  *
 641  * Userspace interface buffer layout:
 642  *
 643  * struct data {
 644  *      u64     vsx[32];
 645  * };
 646  */
 647 static int vsr_get(struct task_struct *target, const struct user_regset *regset,
 648                    unsigned int pos, unsigned int count,
 649                    void *kbuf, void __user *ubuf)
 650 {
 651         u64 buf[32];
 652         int ret, i;
 653
 654         flush_tmregs_to_thread(target);
 655         flush_fp_to_thread(target);
 656         flush_altivec_to_thread(target);
 657         flush_vsx_to_thread(target);
 658
 659         for (i = 0; i < 32 ; i++)
 660                 buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
 661
 662         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 663                                   buf, 0, 32 * sizeof(double));
 664
 665         return ret;
 666 }
 667
 668 /*
 669  * Regardless of transactions, 'fp_state' holds the current running
 670  * value of all FPR registers and 'ckfp_state' holds the last
 671  * checkpointed value of all FPR registers for the current
 672  * transaction.
 673  *
 674  * Userspace interface buffer layout:
 675  *
 676  * struct data {
 677  *      u64     vsx[32];
 678  * };
 679  */
 680 static int vsr_set(struct task_struct *target, const struct user_regset *regset,
 681                    unsigned int pos, unsigned int count,
 682                    const void *kbuf, const void __user *ubuf)
 683 {
 684         u64 buf[32];
 685         int ret,i;
 686
 687         flush_tmregs_to_thread(target);
 688         flush_fp_to_thread(target);
 689         flush_altivec_to_thread(target);
 690         flush_vsx_to_thread(target);
 691
 692         for (i = 0; i < 32 ; i++)
 693                 buf[i] = target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET];
 694
 695         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 696                                  buf, 0, 32 * sizeof(double));
 697         if (!ret)
 698                 for (i = 0; i < 32 ; i++)
 699                         target->thread.fp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i];
 700
 701         return ret;
 702 }
 703 #endif /* CONFIG_VSX */
 704
 705 #ifdef CONFIG_SPE
 706
 707 /*
 708  * For get_evrregs/set_evrregs functions 'data' has the following layout:
 709  *
 710  * struct {
 711  *   u32 evr[32];
 712  *   u64 acc;
 713  *   u32 spefscr;
 714  * }
 715  */
 716
 717 static int evr_active(struct task_struct *target,
 718                       const struct user_regset *regset)
 719 {
 720         flush_spe_to_thread(target);
 721         return target->thread.used_spe ? regset->n : 0;
 722 }
 723
 724 static int evr_get(struct task_struct *target, const struct user_regset *regset,
 725                    unsigned int pos, unsigned int count,
 726                    void *kbuf, void __user *ubuf)
 727 {
 728         int ret;
 729
 730         flush_spe_to_thread(target);
 731
 732         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 733                                   &target->thread.evr,
 734                                   0, sizeof(target->thread.evr));
 735
 736         BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
 737                      offsetof(struct thread_struct, spefscr));
 738
 739         if (!ret)
 740                 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 741                                           &target->thread.acc,
 742                                           sizeof(target->thread.evr), -1);
 743
 744         return ret;
 745 }
 746
 747 static int evr_set(struct task_struct *target, const struct user_regset *regset,
 748                    unsigned int pos, unsigned int count,
 749                    const void *kbuf, const void __user *ubuf)
 750 {
 751         int ret;
 752
 753         flush_spe_to_thread(target);
 754
 755         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 756                                  &target->thread.evr,
 757                                  0, sizeof(target->thread.evr));
 758
 759         BUILD_BUG_ON(offsetof(struct thread_struct, acc) + sizeof(u64) !=
 760                      offsetof(struct thread_struct, spefscr));
 761
 762         if (!ret)
 763                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 764                                          &target->thread.acc,
 765                                          sizeof(target->thread.evr), -1);
 766
 767         return ret;
 768 }
 769 #endif /* CONFIG_SPE */
 770
 771 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 772 /**
 773  * tm_cgpr_active - get active number of registers in CGPR
 774  * @target:     The target task.
 775  * @regset:     The user regset structure.
 776  *
 777  * This function checks for the active number of available
 778  * regisers in transaction checkpointed GPR category.
 779  */
 780 static int tm_cgpr_active(struct task_struct *target,
 781                           const struct user_regset *regset)
 782 {
 783         if (!cpu_has_feature(CPU_FTR_TM))
 784                 return -ENODEV;
 785
 786         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
 787                 return 0;
 788
 789         return regset->n;
 790 }
 791
 792 /**
 793  * tm_cgpr_get - get CGPR registers
 794  * @target:     The target task.
 795  * @regset:     The user regset structure.
 796  * @pos:        The buffer position.
 797  * @count:      Number of bytes to copy.
 798  * @kbuf:       Kernel buffer to copy from.
 799  * @ubuf:       User buffer to copy into.
 800  *
 801  * This function gets transaction checkpointed GPR registers.
 802  *
 803  * When the transaction is active, 'ckpt_regs' holds all the checkpointed
 804  * GPR register values for the current transaction to fall back on if it
 805  * aborts in between. This function gets those checkpointed GPR registers.
 806  * The userspace interface buffer layout is as follows.
 807  *
 808  * struct data {
 809  *      struct pt_regs ckpt_regs;
 810  * };
 811  */
 812 static int tm_cgpr_get(struct task_struct *target,
 813                         const struct user_regset *regset,
 814                         unsigned int pos, unsigned int count,
 815                         void *kbuf, void __user *ubuf)
 816 {
 817         int ret;
 818
 819         if (!cpu_has_feature(CPU_FTR_TM))
 820                 return -ENODEV;
 821
 822         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
 823                 return -ENODATA;
 824
 825         flush_tmregs_to_thread(target);
 826         flush_fp_to_thread(target);
 827         flush_altivec_to_thread(target);
 828
 829         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 830                                   &target->thread.ckpt_regs,
 831                                   0, offsetof(struct pt_regs, msr));
 832         if (!ret) {
 833                 unsigned long msr = get_user_ckpt_msr(target);
 834
 835                 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &msr,
 836                                           offsetof(struct pt_regs, msr),
 837                                           offsetof(struct pt_regs, msr) +
 838                                           sizeof(msr));
 839         }
 840
 841         BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
 842                      offsetof(struct pt_regs, msr) + sizeof(long));
 843
 844         if (!ret)
 845                 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
 846                                           &target->thread.ckpt_regs.orig_gpr3,
 847                                           offsetof(struct pt_regs, orig_gpr3),
 848                                           sizeof(struct pt_regs));
 849         if (!ret)
 850                 ret = user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
 851                                                sizeof(struct pt_regs), -1);
 852
 853         return ret;
 854 }
 855
 856 /*
 857  * tm_cgpr_set - set the CGPR registers
 858  * @target:     The target task.
 859  * @regset:     The user regset structure.
 860  * @pos:        The buffer position.
 861  * @count:      Number of bytes to copy.
 862  * @kbuf:       Kernel buffer to copy into.
 863  * @ubuf:       User buffer to copy from.
 864  *
 865  * This function sets in transaction checkpointed GPR registers.
 866  *
 867  * When the transaction is active, 'ckpt_regs' holds the checkpointed
 868  * GPR register values for the current transaction to fall back on if it
 869  * aborts in between. This function sets those checkpointed GPR registers.
 870  * The userspace interface buffer layout is as follows.
 871  *
 872  * struct data {
 873  *      struct pt_regs ckpt_regs;
 874  * };
 875  */
 876 static int tm_cgpr_set(struct task_struct *target,
 877                         const struct user_regset *regset,
 878                         unsigned int pos, unsigned int count,
 879                         const void *kbuf, const void __user *ubuf)
 880 {
 881         unsigned long reg;
 882         int ret;
 883
 884         if (!cpu_has_feature(CPU_FTR_TM))
 885                 return -ENODEV;
 886
 887         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
 888                 return -ENODATA;
 889
 890         flush_tmregs_to_thread(target);
 891         flush_fp_to_thread(target);
 892         flush_altivec_to_thread(target);
 893
 894         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 895                                  &target->thread.ckpt_regs,
 896                                  0, PT_MSR * sizeof(reg));
 897
 898         if (!ret && count > 0) {
 899                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
 900                                          PT_MSR * sizeof(reg),
 901                                          (PT_MSR + 1) * sizeof(reg));
 902                 if (!ret)
 903                         ret = set_user_ckpt_msr(target, reg);
 904         }
 905
 906         BUILD_BUG_ON(offsetof(struct pt_regs, orig_gpr3) !=
 907                      offsetof(struct pt_regs, msr) + sizeof(long));
 908
 909         if (!ret)
 910                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
 911                                          &target->thread.ckpt_regs.orig_gpr3,
 912                                          PT_ORIG_R3 * sizeof(reg),
 913                                          (PT_MAX_PUT_REG + 1) * sizeof(reg));
 914
 915         if (PT_MAX_PUT_REG + 1 < PT_TRAP && !ret)
 916                 ret = user_regset_copyin_ignore(
 917                         &pos, &count, &kbuf, &ubuf,
 918                         (PT_MAX_PUT_REG + 1) * sizeof(reg),
 919                         PT_TRAP * sizeof(reg));
 920
 921         if (!ret && count > 0) {
 922                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &reg,
 923                                          PT_TRAP * sizeof(reg),
 924                                          (PT_TRAP + 1) * sizeof(reg));
 925                 if (!ret)
 926                         ret = set_user_ckpt_trap(target, reg);
 927         }
 928
 929         if (!ret)
 930                 ret = user_regset_copyin_ignore(
 931                         &pos, &count, &kbuf, &ubuf,
 932                         (PT_TRAP + 1) * sizeof(reg), -1);
 933
 934         return ret;
 935 }
 936
 937 /**
 938  * tm_cfpr_active - get active number of registers in CFPR
 939  * @target:     The target task.
 940  * @regset:     The user regset structure.
 941  *
 942  * This function checks for the active number of available
 943  * regisers in transaction checkpointed FPR category.
 944  */
 945 static int tm_cfpr_active(struct task_struct *target,
 946                                 const struct user_regset *regset)
 947 {
 948         if (!cpu_has_feature(CPU_FTR_TM))
 949                 return -ENODEV;
 950
 951         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
 952                 return 0;
 953
 954         return regset->n;
 955 }
 956
 957 /**
 958  * tm_cfpr_get - get CFPR registers
 959  * @target:     The target task.
 960  * @regset:     The user regset structure.
 961  * @pos:        The buffer position.
 962  * @count:      Number of bytes to copy.
 963  * @kbuf:       Kernel buffer to copy from.
 964  * @ubuf:       User buffer to copy into.
 965  *
 966  * This function gets in transaction checkpointed FPR registers.
 967  *
 968  * When the transaction is active 'ckfp_state' holds the checkpointed
 969  * values for the current transaction to fall back on if it aborts
 970  * in between. This function gets those checkpointed FPR registers.
 971  * The userspace interface buffer layout is as follows.
 972  *
 973  * struct data {
 974  *      u64     fpr[32];
 975  *      u64     fpscr;
 976  *};
 977  */
 978 static int tm_cfpr_get(struct task_struct *target,
 979                         const struct user_regset *regset,
 980                         unsigned int pos, unsigned int count,
 981                         void *kbuf, void __user *ubuf)
 982 {
 983         u64 buf[33];
 984         int i;
 985
 986         if (!cpu_has_feature(CPU_FTR_TM))
 987                 return -ENODEV;
 988
 989         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
 990                 return -ENODATA;
 991
 992         flush_tmregs_to_thread(target);
 993         flush_fp_to_thread(target);
 994         flush_altivec_to_thread(target);
 995
 996         /* copy to local buffer then write that out */
 997         for (i = 0; i < 32 ; i++)
 998                 buf[i] = target->thread.TS_CKFPR(i);
 999         buf[32] = target->thread.ckfp_state.fpscr;
1000         return user_regset_copyout(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
1001 }
1002
1003 /**
1004  * tm_cfpr_set - set CFPR registers
1005  * @target:     The target task.
1006  * @regset:     The user regset structure.
1007  * @pos:        The buffer position.
1008  * @count:      Number of bytes to copy.
1009  * @kbuf:       Kernel buffer to copy into.
1010  * @ubuf:       User buffer to copy from.
1011  *
1012  * This function sets in transaction checkpointed FPR registers.
1013  *
1014  * When the transaction is active 'ckfp_state' holds the checkpointed
1015  * FPR register values for the current transaction to fall back on
1016  * if it aborts in between. This function sets these checkpointed
1017  * FPR registers. The userspace interface buffer layout is as follows.
1018  *
1019  * struct data {
1020  *      u64     fpr[32];
1021  *      u64     fpscr;
1022  *};
1023  */
1024 static int tm_cfpr_set(struct task_struct *target,
1025                         const struct user_regset *regset,
1026                         unsigned int pos, unsigned int count,
1027                         const void *kbuf, const void __user *ubuf)
1028 {
1029         u64 buf[33];
1030         int i;
1031
1032         if (!cpu_has_feature(CPU_FTR_TM))
1033                 return -ENODEV;
1034
1035         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1036                 return -ENODATA;
1037
1038         flush_tmregs_to_thread(target);
1039         flush_fp_to_thread(target);
1040         flush_altivec_to_thread(target);
1041
1042         for (i = 0; i < 32; i++)
1043                 buf[i] = target->thread.TS_CKFPR(i);
1044         buf[32] = target->thread.ckfp_state.fpscr;
1045
1046         /* copy to local buffer then write that out */
1047         i = user_regset_copyin(&pos, &count, &kbuf, &ubuf, buf, 0, -1);
1048         if (i)
1049                 return i;
1050         for (i = 0; i < 32 ; i++)
1051                 target->thread.TS_CKFPR(i) = buf[i];
1052         target->thread.ckfp_state.fpscr = buf[32];
1053         return 0;
1054 }
1055
1056 /**
1057  * tm_cvmx_active - get active number of registers in CVMX
1058  * @target:     The target task.
1059  * @regset:     The user regset structure.
1060  *
1061  * This function checks for the active number of available
1062  * regisers in checkpointed VMX category.
1063  */
1064 static int tm_cvmx_active(struct task_struct *target,
1065                                 const struct user_regset *regset)
1066 {
1067         if (!cpu_has_feature(CPU_FTR_TM))
1068                 return -ENODEV;
1069
1070         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1071                 return 0;
1072
1073         return regset->n;
1074 }
1075
1076 /**
1077  * tm_cvmx_get - get CMVX registers
1078  * @target:     The target task.
1079  * @regset:     The user regset structure.
1080  * @pos:        The buffer position.
1081  * @count:      Number of bytes to copy.
1082  * @kbuf:       Kernel buffer to copy from.
1083  * @ubuf:       User buffer to copy into.
1084  *
1085  * This function gets in transaction checkpointed VMX registers.
1086  *
1087  * When the transaction is active 'ckvr_state' and 'ckvrsave' hold
1088  * the checkpointed values for the current transaction to fall
1089  * back on if it aborts in between. The userspace interface buffer
1090  * layout is as follows.
1091  *
1092  * struct data {
1093  *      vector128       vr[32];
1094  *      vector128       vscr;
1095  *      vector128       vrsave;
1096  *};
1097  */
1098 static int tm_cvmx_get(struct task_struct *target,
1099                         const struct user_regset *regset,
1100                         unsigned int pos, unsigned int count,
1101                         void *kbuf, void __user *ubuf)
1102 {
1103         int ret;
1104
1105         BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32]));
1106
1107         if (!cpu_has_feature(CPU_FTR_TM))
1108                 return -ENODEV;
1109
1110         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1111                 return -ENODATA;
1112
1113         /* Flush the state */
1114         flush_tmregs_to_thread(target);
1115         flush_fp_to_thread(target);
1116         flush_altivec_to_thread(target);
1117
1118         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1119                                         &target->thread.ckvr_state, 0,
1120                                         33 * sizeof(vector128));
1121         if (!ret) {
1122                 /*
1123                  * Copy out only the low-order word of vrsave.
1124                  */
1125                 union {
1126                         elf_vrreg_t reg;
1127                         u32 word;
1128                 } vrsave;
1129                 memset(&vrsave, 0, sizeof(vrsave));
1130                 vrsave.word = target->thread.ckvrsave;
1131                 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf, &vrsave,
1132                                                 33 * sizeof(vector128), -1);
1133         }
1134
1135         return ret;
1136 }
1137
1138 /**
1139  * tm_cvmx_set - set CMVX registers
1140  * @target:     The target task.
1141  * @regset:     The user regset structure.
1142  * @pos:        The buffer position.
1143  * @count:      Number of bytes to copy.
1144  * @kbuf:       Kernel buffer to copy into.
1145  * @ubuf:       User buffer to copy from.
1146  *
1147  * This function sets in transaction checkpointed VMX registers.
1148  *
1149  * When the transaction is active 'ckvr_state' and 'ckvrsave' hold
1150  * the checkpointed values for the current transaction to fall
1151  * back on if it aborts in between. The userspace interface buffer
1152  * layout is as follows.
1153  *
1154  * struct data {
1155  *      vector128       vr[32];
1156  *      vector128       vscr;
1157  *      vector128       vrsave;
1158  *};
1159  */
1160 static int tm_cvmx_set(struct task_struct *target,
1161                         const struct user_regset *regset,
1162                         unsigned int pos, unsigned int count,
1163                         const void *kbuf, const void __user *ubuf)
1164 {
1165         int ret;
1166
1167         BUILD_BUG_ON(TVSO(vscr) != TVSO(vr[32]));
1168
1169         if (!cpu_has_feature(CPU_FTR_TM))
1170                 return -ENODEV;
1171
1172         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1173                 return -ENODATA;
1174
1175         flush_tmregs_to_thread(target);
1176         flush_fp_to_thread(target);
1177         flush_altivec_to_thread(target);
1178
1179         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1180                                         &target->thread.ckvr_state, 0,
1181                                         33 * sizeof(vector128));
1182         if (!ret && count > 0) {
1183                 /*
1184                  * We use only the low-order word of vrsave.
1185                  */
1186                 union {
1187                         elf_vrreg_t reg;
1188                         u32 word;
1189                 } vrsave;
1190                 memset(&vrsave, 0, sizeof(vrsave));
1191                 vrsave.word = target->thread.ckvrsave;
1192                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &vrsave,
1193                                                 33 * sizeof(vector128), -1);
1194                 if (!ret)
1195                         target->thread.ckvrsave = vrsave.word;
1196         }
1197
1198         return ret;
1199 }
1200
1201 /**
1202  * tm_cvsx_active - get active number of registers in CVSX
1203  * @target:     The target task.
1204  * @regset:     The user regset structure.
1205  *
1206  * This function checks for the active number of available
1207  * regisers in transaction checkpointed VSX category.
1208  */
1209 static int tm_cvsx_active(struct task_struct *target,
1210                                 const struct user_regset *regset)
1211 {
1212         if (!cpu_has_feature(CPU_FTR_TM))
1213                 return -ENODEV;
1214
1215         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1216                 return 0;
1217
1218         flush_vsx_to_thread(target);
1219         return target->thread.used_vsr ? regset->n : 0;
1220 }
1221
1222 /**
1223  * tm_cvsx_get - get CVSX registers
1224  * @target:     The target task.
1225  * @regset:     The user regset structure.
1226  * @pos:        The buffer position.
1227  * @count:      Number of bytes to copy.
1228  * @kbuf:       Kernel buffer to copy from.
1229  * @ubuf:       User buffer to copy into.
1230  *
1231  * This function gets in transaction checkpointed VSX registers.
1232  *
1233  * When the transaction is active 'ckfp_state' holds the checkpointed
1234  * values for the current transaction to fall back on if it aborts
1235  * in between. This function gets those checkpointed VSX registers.
1236  * The userspace interface buffer layout is as follows.
1237  *
1238  * struct data {
1239  *      u64     vsx[32];
1240  *};
1241  */
1242 static int tm_cvsx_get(struct task_struct *target,
1243                         const struct user_regset *regset,
1244                         unsigned int pos, unsigned int count,
1245                         void *kbuf, void __user *ubuf)
1246 {
1247         u64 buf[32];
1248         int ret, i;
1249
1250         if (!cpu_has_feature(CPU_FTR_TM))
1251                 return -ENODEV;
1252
1253         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1254                 return -ENODATA;
1255
1256         /* Flush the state */
1257         flush_tmregs_to_thread(target);
1258         flush_fp_to_thread(target);
1259         flush_altivec_to_thread(target);
1260         flush_vsx_to_thread(target);
1261
1262         for (i = 0; i < 32 ; i++)
1263                 buf[i] = target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET];
1264         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1265                                   buf, 0, 32 * sizeof(double));
1266
1267         return ret;
1268 }
1269
1270 /**
1271  * tm_cvsx_set - set CFPR registers
1272  * @target:     The target task.
1273  * @regset:     The user regset structure.
1274  * @pos:        The buffer position.
1275  * @count:      Number of bytes to copy.
1276  * @kbuf:       Kernel buffer to copy into.
1277  * @ubuf:       User buffer to copy from.
1278  *
1279  * This function sets in transaction checkpointed VSX registers.
1280  *
1281  * When the transaction is active 'ckfp_state' holds the checkpointed
1282  * VSX register values for the current transaction to fall back on
1283  * if it aborts in between. This function sets these checkpointed
1284  * FPR registers. The userspace interface buffer layout is as follows.
1285  *
1286  * struct data {
1287  *      u64     vsx[32];
1288  *};
1289  */
1290 static int tm_cvsx_set(struct task_struct *target,
1291                         const struct user_regset *regset,
1292                         unsigned int pos, unsigned int count,
1293                         const void *kbuf, const void __user *ubuf)
1294 {
1295         u64 buf[32];
1296         int ret, i;
1297
1298         if (!cpu_has_feature(CPU_FTR_TM))
1299                 return -ENODEV;
1300
1301         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1302                 return -ENODATA;
1303
1304         /* Flush the state */
1305         flush_tmregs_to_thread(target);
1306         flush_fp_to_thread(target);
1307         flush_altivec_to_thread(target);
1308         flush_vsx_to_thread(target);
1309
1310         for (i = 0; i < 32 ; i++)
1311                 buf[i] = target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET];
1312
1313         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1314                                  buf, 0, 32 * sizeof(double));
1315         if (!ret)
1316                 for (i = 0; i < 32 ; i++)
1317                         target->thread.ckfp_state.fpr[i][TS_VSRLOWOFFSET] = buf[i];
1318
1319         return ret;
1320 }
1321
1322 /**
1323  * tm_spr_active - get active number of registers in TM SPR
1324  * @target:     The target task.
1325  * @regset:     The user regset structure.
1326  *
1327  * This function checks the active number of available
1328  * regisers in the transactional memory SPR category.
1329  */
1330 static int tm_spr_active(struct task_struct *target,
1331                          const struct user_regset *regset)
1332 {
1333         if (!cpu_has_feature(CPU_FTR_TM))
1334                 return -ENODEV;
1335
1336         return regset->n;
1337 }
1338
1339 /**
1340  * tm_spr_get - get the TM related SPR registers
1341  * @target:     The target task.
1342  * @regset:     The user regset structure.
1343  * @pos:        The buffer position.
1344  * @count:      Number of bytes to copy.
1345  * @kbuf:       Kernel buffer to copy from.
1346  * @ubuf:       User buffer to copy into.
1347  *
1348  * This function gets transactional memory related SPR registers.
1349  * The userspace interface buffer layout is as follows.
1350  *
1351  * struct {
1352  *      u64             tm_tfhar;
1353  *      u64             tm_texasr;
1354  *      u64             tm_tfiar;
1355  * };
1356  */
1357 static int tm_spr_get(struct task_struct *target,
1358                       const struct user_regset *regset,
1359                       unsigned int pos, unsigned int count,
1360                       void *kbuf, void __user *ubuf)
1361 {
1362         int ret;
1363
1364         /* Build tests */
1365         BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
1366         BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
1367         BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
1368
1369         if (!cpu_has_feature(CPU_FTR_TM))
1370                 return -ENODEV;
1371
1372         /* Flush the states */
1373         flush_tmregs_to_thread(target);
1374         flush_fp_to_thread(target);
1375         flush_altivec_to_thread(target);
1376
1377         /* TFHAR register */
1378         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1379                                 &target->thread.tm_tfhar, 0, sizeof(u64));
1380
1381         /* TEXASR register */
1382         if (!ret)
1383                 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1384                                 &target->thread.tm_texasr, sizeof(u64),
1385                                 2 * sizeof(u64));
1386
1387         /* TFIAR register */
1388         if (!ret)
1389                 ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1390                                 &target->thread.tm_tfiar,
1391                                 2 * sizeof(u64), 3 * sizeof(u64));
1392         return ret;
1393 }
1394
1395 /**
1396  * tm_spr_set - set the TM related SPR registers
1397  * @target:     The target task.
1398  * @regset:     The user regset structure.
1399  * @pos:        The buffer position.
1400  * @count:      Number of bytes to copy.
1401  * @kbuf:       Kernel buffer to copy into.
1402  * @ubuf:       User buffer to copy from.
1403  *
1404  * This function sets transactional memory related SPR registers.
1405  * The userspace interface buffer layout is as follows.
1406  *
1407  * struct {
1408  *      u64             tm_tfhar;
1409  *      u64             tm_texasr;
1410  *      u64             tm_tfiar;
1411  * };
1412  */
1413 static int tm_spr_set(struct task_struct *target,
1414                       const struct user_regset *regset,
1415                       unsigned int pos, unsigned int count,
1416                       const void *kbuf, const void __user *ubuf)
1417 {
1418         int ret;
1419
1420         /* Build tests */
1421         BUILD_BUG_ON(TSO(tm_tfhar) + sizeof(u64) != TSO(tm_texasr));
1422         BUILD_BUG_ON(TSO(tm_texasr) + sizeof(u64) != TSO(tm_tfiar));
1423         BUILD_BUG_ON(TSO(tm_tfiar) + sizeof(u64) != TSO(ckpt_regs));
1424
1425         if (!cpu_has_feature(CPU_FTR_TM))
1426                 return -ENODEV;
1427
1428         /* Flush the states */
1429         flush_tmregs_to_thread(target);
1430         flush_fp_to_thread(target);
1431         flush_altivec_to_thread(target);
1432
1433         /* TFHAR register */
1434         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1435                                 &target->thread.tm_tfhar, 0, sizeof(u64));
1436
1437         /* TEXASR register */
1438         if (!ret)
1439                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1440                                 &target->thread.tm_texasr, sizeof(u64),
1441                                 2 * sizeof(u64));
1442
1443         /* TFIAR register */
1444         if (!ret)
1445                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1446                                 &target->thread.tm_tfiar,
1447                                  2 * sizeof(u64), 3 * sizeof(u64));
1448         return ret;
1449 }
1450
1451 static int tm_tar_active(struct task_struct *target,
1452                          const struct user_regset *regset)
1453 {
1454         if (!cpu_has_feature(CPU_FTR_TM))
1455                 return -ENODEV;
1456
1457         if (MSR_TM_ACTIVE(target->thread.regs->msr))
1458                 return regset->n;
1459
1460         return 0;
1461 }
1462
1463 static int tm_tar_get(struct task_struct *target,
1464                       const struct user_regset *regset,
1465                       unsigned int pos, unsigned int count,
1466                       void *kbuf, void __user *ubuf)
1467 {
1468         int ret;
1469
1470         if (!cpu_has_feature(CPU_FTR_TM))
1471                 return -ENODEV;
1472
1473         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1474                 return -ENODATA;
1475
1476         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1477                                 &target->thread.tm_tar, 0, sizeof(u64));
1478         return ret;
1479 }
1480
1481 static int tm_tar_set(struct task_struct *target,
1482                       const struct user_regset *regset,
1483                       unsigned int pos, unsigned int count,
1484                       const void *kbuf, const void __user *ubuf)
1485 {
1486         int ret;
1487
1488         if (!cpu_has_feature(CPU_FTR_TM))
1489                 return -ENODEV;
1490
1491         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1492                 return -ENODATA;
1493
1494         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1495                                 &target->thread.tm_tar, 0, sizeof(u64));
1496         return ret;
1497 }
1498
1499 static int tm_ppr_active(struct task_struct *target,
1500                          const struct user_regset *regset)
1501 {
1502         if (!cpu_has_feature(CPU_FTR_TM))
1503                 return -ENODEV;
1504
1505         if (MSR_TM_ACTIVE(target->thread.regs->msr))
1506                 return regset->n;
1507
1508         return 0;
1509 }
1510
1511
1512 static int tm_ppr_get(struct task_struct *target,
1513                       const struct user_regset *regset,
1514                       unsigned int pos, unsigned int count,
1515                       void *kbuf, void __user *ubuf)
1516 {
1517         int ret;
1518
1519         if (!cpu_has_feature(CPU_FTR_TM))
1520                 return -ENODEV;
1521
1522         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1523                 return -ENODATA;
1524
1525         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1526                                 &target->thread.tm_ppr, 0, sizeof(u64));
1527         return ret;
1528 }
1529
1530 static int tm_ppr_set(struct task_struct *target,
1531                       const struct user_regset *regset,
1532                       unsigned int pos, unsigned int count,
1533                       const void *kbuf, const void __user *ubuf)
1534 {
1535         int ret;
1536
1537         if (!cpu_has_feature(CPU_FTR_TM))
1538                 return -ENODEV;
1539
1540         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1541                 return -ENODATA;
1542
1543         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1544                                 &target->thread.tm_ppr, 0, sizeof(u64));
1545         return ret;
1546 }
1547
1548 static int tm_dscr_active(struct task_struct *target,
1549                          const struct user_regset *regset)
1550 {
1551         if (!cpu_has_feature(CPU_FTR_TM))
1552                 return -ENODEV;
1553
1554         if (MSR_TM_ACTIVE(target->thread.regs->msr))
1555                 return regset->n;
1556
1557         return 0;
1558 }
1559
1560 static int tm_dscr_get(struct task_struct *target,
1561                       const struct user_regset *regset,
1562                       unsigned int pos, unsigned int count,
1563                       void *kbuf, void __user *ubuf)
1564 {
1565         int ret;
1566
1567         if (!cpu_has_feature(CPU_FTR_TM))
1568                 return -ENODEV;
1569
1570         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1571                 return -ENODATA;
1572
1573         ret = user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1574                                 &target->thread.tm_dscr, 0, sizeof(u64));
1575         return ret;
1576 }
1577
1578 static int tm_dscr_set(struct task_struct *target,
1579                       const struct user_regset *regset,
1580                       unsigned int pos, unsigned int count,
1581                       const void *kbuf, const void __user *ubuf)
1582 {
1583         int ret;
1584
1585         if (!cpu_has_feature(CPU_FTR_TM))
1586                 return -ENODEV;
1587
1588         if (!MSR_TM_ACTIVE(target->thread.regs->msr))
1589                 return -ENODATA;
1590
1591         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1592                                 &target->thread.tm_dscr, 0, sizeof(u64));
1593         return ret;
1594 }
1595 #endif  /* CONFIG_PPC_TRANSACTIONAL_MEM */
1596
1597 #ifdef CONFIG_PPC64
1598 static int ppr_get(struct task_struct *target,
1599                       const struct user_regset *regset,
1600                       unsigned int pos, unsigned int count,
1601                       void *kbuf, void __user *ubuf)
1602 {
1603         return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1604                                    &target->thread.ppr, 0, sizeof(u64));
1605 }
1606
1607 static int ppr_set(struct task_struct *target,
1608                       const struct user_regset *regset,
1609                       unsigned int pos, unsigned int count,
1610                       const void *kbuf, const void __user *ubuf)
1611 {
1612         return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1613                                   &target->thread.ppr, 0, sizeof(u64));
1614 }
1615
1616 static int dscr_get(struct task_struct *target,
1617                       const struct user_regset *regset,
1618                       unsigned int pos, unsigned int count,
1619                       void *kbuf, void __user *ubuf)
1620 {
1621         return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1622                                    &target->thread.dscr, 0, sizeof(u64));
1623 }
1624 static int dscr_set(struct task_struct *target,
1625                       const struct user_regset *regset,
1626                       unsigned int pos, unsigned int count,
1627                       const void *kbuf, const void __user *ubuf)
1628 {
1629         return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1630                                   &target->thread.dscr, 0, sizeof(u64));
1631 }
1632 #endif
1633 #ifdef CONFIG_PPC_BOOK3S_64
1634 static int tar_get(struct task_struct *target,
1635                       const struct user_regset *regset,
1636                       unsigned int pos, unsigned int count,
1637                       void *kbuf, void __user *ubuf)
1638 {
1639         return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1640                                    &target->thread.tar, 0, sizeof(u64));
1641 }
1642 static int tar_set(struct task_struct *target,
1643                       const struct user_regset *regset,
1644                       unsigned int pos, unsigned int count,
1645                       const void *kbuf, const void __user *ubuf)
1646 {
1647         return user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1648                                   &target->thread.tar, 0, sizeof(u64));
1649 }
1650
1651 static int ebb_active(struct task_struct *target,
1652                          const struct user_regset *regset)
1653 {
1654         if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1655                 return -ENODEV;
1656
1657         if (target->thread.used_ebb)
1658                 return regset->n;
1659
1660         return 0;
1661 }
1662
1663 static int ebb_get(struct task_struct *target,
1664                       const struct user_regset *regset,
1665                       unsigned int pos, unsigned int count,
1666                       void *kbuf, void __user *ubuf)
1667 {
1668         /* Build tests */
1669         BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr));
1670         BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr));
1671
1672         if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1673                 return -ENODEV;
1674
1675         if (!target->thread.used_ebb)
1676                 return -ENODATA;
1677
1678         return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1679                         &target->thread.ebbrr, 0, 3 * sizeof(unsigned long));
1680 }
1681
1682 static int ebb_set(struct task_struct *target,
1683                       const struct user_regset *regset,
1684                       unsigned int pos, unsigned int count,
1685                       const void *kbuf, const void __user *ubuf)
1686 {
1687         int ret = 0;
1688
1689         /* Build tests */
1690         BUILD_BUG_ON(TSO(ebbrr) + sizeof(unsigned long) != TSO(ebbhr));
1691         BUILD_BUG_ON(TSO(ebbhr) + sizeof(unsigned long) != TSO(bescr));
1692
1693         if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1694                 return -ENODEV;
1695
1696         if (target->thread.used_ebb)
1697                 return -ENODATA;
1698
1699         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1700                         &target->thread.ebbrr, 0, sizeof(unsigned long));
1701
1702         if (!ret)
1703                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1704                         &target->thread.ebbhr, sizeof(unsigned long),
1705                         2 * sizeof(unsigned long));
1706
1707         if (!ret)
1708                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1709                         &target->thread.bescr,
1710                         2 * sizeof(unsigned long), 3 * sizeof(unsigned long));
1711
1712         return ret;
1713 }
1714 static int pmu_active(struct task_struct *target,
1715                          const struct user_regset *regset)
1716 {
1717         if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1718                 return -ENODEV;
1719
1720         return regset->n;
1721 }
1722
1723 static int pmu_get(struct task_struct *target,
1724                       const struct user_regset *regset,
1725                       unsigned int pos, unsigned int count,
1726                       void *kbuf, void __user *ubuf)
1727 {
1728         /* Build tests */
1729         BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar));
1730         BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier));
1731         BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2));
1732         BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0));
1733
1734         if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1735                 return -ENODEV;
1736
1737         return user_regset_copyout(&pos, &count, &kbuf, &ubuf,
1738                         &target->thread.siar, 0,
1739                         5 * sizeof(unsigned long));
1740 }
1741
1742 static int pmu_set(struct task_struct *target,
1743                       const struct user_regset *regset,
1744                       unsigned int pos, unsigned int count,
1745                       const void *kbuf, const void __user *ubuf)
1746 {
1747         int ret = 0;
1748
1749         /* Build tests */
1750         BUILD_BUG_ON(TSO(siar) + sizeof(unsigned long) != TSO(sdar));
1751         BUILD_BUG_ON(TSO(sdar) + sizeof(unsigned long) != TSO(sier));
1752         BUILD_BUG_ON(TSO(sier) + sizeof(unsigned long) != TSO(mmcr2));
1753         BUILD_BUG_ON(TSO(mmcr2) + sizeof(unsigned long) != TSO(mmcr0));
1754
1755         if (!cpu_has_feature(CPU_FTR_ARCH_207S))
1756                 return -ENODEV;
1757
1758         ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1759                         &target->thread.siar, 0,
1760                         sizeof(unsigned long));
1761
1762         if (!ret)
1763                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1764                         &target->thread.sdar, sizeof(unsigned long),
1765                         2 * sizeof(unsigned long));
1766
1767         if (!ret)
1768                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1769                         &target->thread.sier, 2 * sizeof(unsigned long),
1770                         3 * sizeof(unsigned long));
1771
1772         if (!ret)
1773                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1774                         &target->thread.mmcr2, 3 * sizeof(unsigned long),
1775                         4 * sizeof(unsigned long));
1776
1777         if (!ret)
1778                 ret = user_regset_copyin(&pos, &count, &kbuf, &ubuf,
1779                         &target->thread.mmcr0, 4 * sizeof(unsigned long),
1780                         5 * sizeof(unsigned long));
1781         return ret;
1782 }
1783 #endif
1784 /*
1785  * These are our native regset flavors.
1786  */
1787 enum powerpc_regset {
1788         REGSET_GPR,
1789         REGSET_FPR,
1790 #ifdef CONFIG_ALTIVEC
1791         REGSET_VMX,
1792 #endif
1793 #ifdef CONFIG_VSX
1794         REGSET_VSX,
1795 #endif
1796 #ifdef CONFIG_SPE
1797         REGSET_SPE,
1798 #endif
1799 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1800         REGSET_TM_CGPR,         /* TM checkpointed GPR registers */
1801         REGSET_TM_CFPR,         /* TM checkpointed FPR registers */
1802         REGSET_TM_CVMX,         /* TM checkpointed VMX registers */
1803         REGSET_TM_CVSX,         /* TM checkpointed VSX registers */
1804         REGSET_TM_SPR,          /* TM specific SPR registers */
1805         REGSET_TM_CTAR,         /* TM checkpointed TAR register */
1806         REGSET_TM_CPPR,         /* TM checkpointed PPR register */
1807         REGSET_TM_CDSCR,        /* TM checkpointed DSCR register */
1808 #endif
1809 #ifdef CONFIG_PPC64
1810         REGSET_PPR,             /* PPR register */
1811         REGSET_DSCR,            /* DSCR register */
1812 #endif
1813 #ifdef CONFIG_PPC_BOOK3S_64
1814         REGSET_TAR,             /* TAR register */
1815         REGSET_EBB,             /* EBB registers */
1816         REGSET_PMR,             /* Performance Monitor Registers */
1817 #endif
1818 };
1819
1820 static const struct user_regset native_regsets[] = {
1821         [REGSET_GPR] = {
1822                 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
1823                 .size = sizeof(long), .align = sizeof(long),
1824                 .get = gpr_get, .set = gpr_set
1825         },
1826         [REGSET_FPR] = {
1827                 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
1828                 .size = sizeof(double), .align = sizeof(double),
1829                 .get = fpr_get, .set = fpr_set
1830         },
1831 #ifdef CONFIG_ALTIVEC
1832         [REGSET_VMX] = {
1833                 .core_note_type = NT_PPC_VMX, .n = 34,
1834                 .size = sizeof(vector128), .align = sizeof(vector128),
1835                 .active = vr_active, .get = vr_get, .set = vr_set
1836         },
1837 #endif
1838 #ifdef CONFIG_VSX
1839         [REGSET_VSX] = {
1840                 .core_note_type = NT_PPC_VSX, .n = 32,
1841                 .size = sizeof(double), .align = sizeof(double),
1842                 .active = vsr_active, .get = vsr_get, .set = vsr_set
1843         },
1844 #endif
1845 #ifdef CONFIG_SPE
1846         [REGSET_SPE] = {
1847                 .core_note_type = NT_PPC_SPE, .n = 35,
1848                 .size = sizeof(u32), .align = sizeof(u32),
1849                 .active = evr_active, .get = evr_get, .set = evr_set
1850         },
1851 #endif
1852 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1853         [REGSET_TM_CGPR] = {
1854                 .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG,
1855                 .size = sizeof(long), .align = sizeof(long),
1856                 .active = tm_cgpr_active, .get = tm_cgpr_get, .set = tm_cgpr_set
1857         },
1858         [REGSET_TM_CFPR] = {
1859                 .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG,
1860                 .size = sizeof(double), .align = sizeof(double),
1861                 .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
1862         },
1863         [REGSET_TM_CVMX] = {
1864                 .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX,
1865                 .size = sizeof(vector128), .align = sizeof(vector128),
1866                 .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
1867         },
1868         [REGSET_TM_CVSX] = {
1869                 .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX,
1870                 .size = sizeof(double), .align = sizeof(double),
1871                 .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
1872         },
1873         [REGSET_TM_SPR] = {
1874                 .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
1875                 .size = sizeof(u64), .align = sizeof(u64),
1876                 .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
1877         },
1878         [REGSET_TM_CTAR] = {
1879                 .core_note_type = NT_PPC_TM_CTAR, .n = 1,
1880                 .size = sizeof(u64), .align = sizeof(u64),
1881                 .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
1882         },
1883         [REGSET_TM_CPPR] = {
1884                 .core_note_type = NT_PPC_TM_CPPR, .n = 1,
1885                 .size = sizeof(u64), .align = sizeof(u64),
1886                 .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
1887         },
1888         [REGSET_TM_CDSCR] = {
1889                 .core_note_type = NT_PPC_TM_CDSCR, .n = 1,
1890                 .size = sizeof(u64), .align = sizeof(u64),
1891                 .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
1892         },
1893 #endif
1894 #ifdef CONFIG_PPC64
1895         [REGSET_PPR] = {
1896                 .core_note_type = NT_PPC_PPR, .n = 1,
1897                 .size = sizeof(u64), .align = sizeof(u64),
1898                 .get = ppr_get, .set = ppr_set
1899         },
1900         [REGSET_DSCR] = {
1901                 .core_note_type = NT_PPC_DSCR, .n = 1,
1902                 .size = sizeof(u64), .align = sizeof(u64),
1903                 .get = dscr_get, .set = dscr_set
1904         },
1905 #endif
1906 #ifdef CONFIG_PPC_BOOK3S_64
1907         [REGSET_TAR] = {
1908                 .core_note_type = NT_PPC_TAR, .n = 1,
1909                 .size = sizeof(u64), .align = sizeof(u64),
1910                 .get = tar_get, .set = tar_set
1911         },
1912         [REGSET_EBB] = {
1913                 .core_note_type = NT_PPC_EBB, .n = ELF_NEBB,
1914                 .size = sizeof(u64), .align = sizeof(u64),
1915                 .active = ebb_active, .get = ebb_get, .set = ebb_set
1916         },
1917         [REGSET_PMR] = {
1918                 .core_note_type = NT_PPC_PMU, .n = ELF_NPMU,
1919                 .size = sizeof(u64), .align = sizeof(u64),
1920                 .active = pmu_active, .get = pmu_get, .set = pmu_set
1921         },
1922 #endif
1923 };
1924
1925 static const struct user_regset_view user_ppc_native_view = {
1926         .name = UTS_MACHINE, .e_machine = ELF_ARCH, .ei_osabi = ELF_OSABI,
1927         .regsets = native_regsets, .n = ARRAY_SIZE(native_regsets)
1928 };
1929
1930 #ifdef CONFIG_PPC64
1931 #include <linux/compat.h>
1932
1933 static int gpr32_get_common(struct task_struct *target,
1934                      const struct user_regset *regset,
1935                      unsigned int pos, unsigned int count,
1936                             void *kbuf, void __user *ubuf,
1937                             unsigned long *regs)
1938 {
1939         compat_ulong_t *k = kbuf;
1940         compat_ulong_t __user *u = ubuf;
1941         compat_ulong_t reg;
1942
1943         pos /= sizeof(reg);
1944         count /= sizeof(reg);
1945
1946         if (kbuf)
1947                 for (; count > 0 && pos < PT_MSR; --count)
1948                         *k++ = regs[pos++];
1949         else
1950                 for (; count > 0 && pos < PT_MSR; --count)
1951                         if (__put_user((compat_ulong_t) regs[pos++], u++))
1952                                 return -EFAULT;
1953
1954         if (count > 0 && pos == PT_MSR) {
1955                 reg = get_user_msr(target);
1956                 if (kbuf)
1957                         *k++ = reg;
1958                 else if (__put_user(reg, u++))
1959                         return -EFAULT;
1960                 ++pos;
1961                 --count;
1962         }
1963
1964         if (kbuf)
1965                 for (; count > 0 && pos < PT_REGS_COUNT; --count)
1966                         *k++ = regs[pos++];
1967         else
1968                 for (; count > 0 && pos < PT_REGS_COUNT; --count)
1969                         if (__put_user((compat_ulong_t) regs[pos++], u++))
1970                                 return -EFAULT;
1971
1972         kbuf = k;
1973         ubuf = u;
1974         pos *= sizeof(reg);
1975         count *= sizeof(reg);
1976         return user_regset_copyout_zero(&pos, &count, &kbuf, &ubuf,
1977                                         PT_REGS_COUNT * sizeof(reg), -1);
1978 }
1979
1980 static int gpr32_set_common(struct task_struct *target,
1981                      const struct user_regset *regset,
1982                      unsigned int pos, unsigned int count,
1983                      const void *kbuf, const void __user *ubuf,
1984                      unsigned long *regs)
1985 {
1986         const compat_ulong_t *k = kbuf;
1987         const compat_ulong_t __user *u = ubuf;
1988         compat_ulong_t reg;
1989
1990         pos /= sizeof(reg);
1991         count /= sizeof(reg);
1992
1993         if (kbuf)
1994                 for (; count > 0 && pos < PT_MSR; --count)
1995                         regs[pos++] = *k++;
1996         else
1997                 for (; count > 0 && pos < PT_MSR; --count) {
1998                         if (__get_user(reg, u++))
1999                                 return -EFAULT;
2000                         regs[pos++] = reg;
2001                 }
2002
2003
2004         if (count > 0 && pos == PT_MSR) {
2005                 if (kbuf)
2006                         reg = *k++;
2007                 else if (__get_user(reg, u++))
2008                         return -EFAULT;
2009                 set_user_msr(target, reg);
2010                 ++pos;
2011                 --count;
2012         }
2013
2014         if (kbuf) {
2015                 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count)
2016                         regs[pos++] = *k++;
2017                 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
2018                         ++k;
2019         } else {
2020                 for (; count > 0 && pos <= PT_MAX_PUT_REG; --count) {
2021                         if (__get_user(reg, u++))
2022                                 return -EFAULT;
2023                         regs[pos++] = reg;
2024                 }
2025                 for (; count > 0 && pos < PT_TRAP; --count, ++pos)
2026                         if (__get_user(reg, u++))
2027                                 return -EFAULT;
2028         }
2029
2030         if (count > 0 && pos == PT_TRAP) {
2031                 if (kbuf)
2032                         reg = *k++;
2033                 else if (__get_user(reg, u++))
2034                         return -EFAULT;
2035                 set_user_trap(target, reg);
2036                 ++pos;
2037                 --count;
2038         }
2039
2040         kbuf = k;
2041         ubuf = u;
2042         pos *= sizeof(reg);
2043         count *= sizeof(reg);
2044         return user_regset_copyin_ignore(&pos, &count, &kbuf, &ubuf,
2045                                          (PT_TRAP + 1) * sizeof(reg), -1);
2046 }
2047
2048 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2049 static int tm_cgpr32_get(struct task_struct *target,
2050                      const struct user_regset *regset,
2051                      unsigned int pos, unsigned int count,
2052                      void *kbuf, void __user *ubuf)
2053 {
2054         return gpr32_get_common(target, regset, pos, count, kbuf, ubuf,
2055                         &target->thread.ckpt_regs.gpr[0]);
2056 }
2057
2058 static int tm_cgpr32_set(struct task_struct *target,
2059                      const struct user_regset *regset,
2060                      unsigned int pos, unsigned int count,
2061                      const void *kbuf, const void __user *ubuf)
2062 {
2063         return gpr32_set_common(target, regset, pos, count, kbuf, ubuf,
2064                         &target->thread.ckpt_regs.gpr[0]);
2065 }
2066 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
2067
2068 static int gpr32_get(struct task_struct *target,
2069                      const struct user_regset *regset,
2070                      unsigned int pos, unsigned int count,
2071                      void *kbuf, void __user *ubuf)
2072 {
2073         int i;
2074
2075         if (target->thread.regs == NULL)
2076                 return -EIO;
2077
2078         if (!FULL_REGS(target->thread.regs)) {
2079                 /*
2080                  * We have a partial register set.
2081                  * Fill 14-31 with bogus values.
2082                  */
2083                 for (i = 14; i < 32; i++)
2084                         target->thread.regs->gpr[i] = NV_REG_POISON;
2085         }
2086         return gpr32_get_common(target, regset, pos, count, kbuf, ubuf,
2087                         &target->thread.regs->gpr[0]);
2088 }
2089
2090 static int gpr32_set(struct task_struct *target,
2091                      const struct user_regset *regset,
2092                      unsigned int pos, unsigned int count,
2093                      const void *kbuf, const void __user *ubuf)
2094 {
2095         if (target->thread.regs == NULL)
2096                 return -EIO;
2097
2098         CHECK_FULL_REGS(target->thread.regs);
2099         return gpr32_set_common(target, regset, pos, count, kbuf, ubuf,
2100                         &target->thread.regs->gpr[0]);
2101 }
2102
2103 /*
2104  * These are the regset flavors matching the CONFIG_PPC32 native set.
2105  */
2106 static const struct user_regset compat_regsets[] = {
2107         [REGSET_GPR] = {
2108                 .core_note_type = NT_PRSTATUS, .n = ELF_NGREG,
2109                 .size = sizeof(compat_long_t), .align = sizeof(compat_long_t),
2110                 .get = gpr32_get, .set = gpr32_set
2111         },
2112         [REGSET_FPR] = {
2113                 .core_note_type = NT_PRFPREG, .n = ELF_NFPREG,
2114                 .size = sizeof(double), .align = sizeof(double),
2115                 .get = fpr_get, .set = fpr_set
2116         },
2117 #ifdef CONFIG_ALTIVEC
2118         [REGSET_VMX] = {
2119                 .core_note_type = NT_PPC_VMX, .n = 34,
2120                 .size = sizeof(vector128), .align = sizeof(vector128),
2121                 .active = vr_active, .get = vr_get, .set = vr_set
2122         },
2123 #endif
2124 #ifdef CONFIG_SPE
2125         [REGSET_SPE] = {
2126                 .core_note_type = NT_PPC_SPE, .n = 35,
2127                 .size = sizeof(u32), .align = sizeof(u32),
2128                 .active = evr_active, .get = evr_get, .set = evr_set
2129         },
2130 #endif
2131 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
2132         [REGSET_TM_CGPR] = {
2133                 .core_note_type = NT_PPC_TM_CGPR, .n = ELF_NGREG,
2134                 .size = sizeof(long), .align = sizeof(long),
2135                 .active = tm_cgpr_active,
2136                 .get = tm_cgpr32_get, .set = tm_cgpr32_set
2137         },
2138         [REGSET_TM_CFPR] = {
2139                 .core_note_type = NT_PPC_TM_CFPR, .n = ELF_NFPREG,
2140                 .size = sizeof(double), .align = sizeof(double),
2141                 .active = tm_cfpr_active, .get = tm_cfpr_get, .set = tm_cfpr_set
2142         },
2143         [REGSET_TM_CVMX] = {
2144                 .core_note_type = NT_PPC_TM_CVMX, .n = ELF_NVMX,
2145                 .size = sizeof(vector128), .align = sizeof(vector128),
2146                 .active = tm_cvmx_active, .get = tm_cvmx_get, .set = tm_cvmx_set
2147         },
2148         [REGSET_TM_CVSX] = {
2149                 .core_note_type = NT_PPC_TM_CVSX, .n = ELF_NVSX,
2150                 .size = sizeof(double), .align = sizeof(double),
2151                 .active = tm_cvsx_active, .get = tm_cvsx_get, .set = tm_cvsx_set
2152         },
2153         [REGSET_TM_SPR] = {
2154                 .core_note_type = NT_PPC_TM_SPR, .n = ELF_NTMSPRREG,
2155                 .size = sizeof(u64), .align = sizeof(u64),
2156                 .active = tm_spr_active, .get = tm_spr_get, .set = tm_spr_set
2157         },
2158         [REGSET_TM_CTAR] = {
2159                 .core_note_type = NT_PPC_TM_CTAR, .n = 1,
2160                 .size = sizeof(u64), .align = sizeof(u64),
2161                 .active = tm_tar_active, .get = tm_tar_get, .set = tm_tar_set
2162         },
2163         [REGSET_TM_CPPR] = {
2164                 .core_note_type = NT_PPC_TM_CPPR, .n = 1,
2165                 .size = sizeof(u64), .align = sizeof(u64),
2166                 .active = tm_ppr_active, .get = tm_ppr_get, .set = tm_ppr_set
2167         },
2168         [REGSET_TM_CDSCR] = {
2169                 .core_note_type = NT_PPC_TM_CDSCR, .n = 1,
2170                 .size = sizeof(u64), .align = sizeof(u64),
2171                 .active = tm_dscr_active, .get = tm_dscr_get, .set = tm_dscr_set
2172         },
2173 #endif
2174 #ifdef CONFIG_PPC64
2175         [REGSET_PPR] = {
2176                 .core_note_type = NT_PPC_PPR, .n = 1,
2177                 .size = sizeof(u64), .align = sizeof(u64),
2178                 .get = ppr_get, .set = ppr_set
2179         },
2180         [REGSET_DSCR] = {
2181                 .core_note_type = NT_PPC_DSCR, .n = 1,
2182                 .size = sizeof(u64), .align = sizeof(u64),
2183                 .get = dscr_get, .set = dscr_set
2184         },
2185 #endif
2186 #ifdef CONFIG_PPC_BOOK3S_64
2187         [REGSET_TAR] = {
2188                 .core_note_type = NT_PPC_TAR, .n = 1,
2189                 .size = sizeof(u64), .align = sizeof(u64),
2190                 .get = tar_get, .set = tar_set
2191         },
2192         [REGSET_EBB] = {
2193                 .core_note_type = NT_PPC_EBB, .n = ELF_NEBB,
2194                 .size = sizeof(u64), .align = sizeof(u64),
2195                 .active = ebb_active, .get = ebb_get, .set = ebb_set
2196         },
2197 #endif
2198 };
2199
2200 static const struct user_regset_view user_ppc_compat_view = {
2201         .name = "ppc", .e_machine = EM_PPC, .ei_osabi = ELF_OSABI,
2202         .regsets = compat_regsets, .n = ARRAY_SIZE(compat_regsets)
2203 };
2204 #endif  /* CONFIG_PPC64 */
2205
2206 const struct user_regset_view *task_user_regset_view(struct task_struct *task)
2207 {
2208 #ifdef CONFIG_PPC64
2209         if (test_tsk_thread_flag(task, TIF_32BIT))
2210                 return &user_ppc_compat_view;
2211 #endif
2212         return &user_ppc_native_view;
2213 }
2214
2215
2216 void user_enable_single_step(struct task_struct *task)
2217 {
2218         struct pt_regs *regs = task->thread.regs;
2219
2220         if (regs != NULL) {
2221 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2222                 task->thread.debug.dbcr0 &= ~DBCR0_BT;
2223                 task->thread.debug.dbcr0 |= DBCR0_IDM | DBCR0_IC;
2224                 regs->msr |= MSR_DE;
2225 #else
2226                 regs->msr &= ~MSR_BE;
2227                 regs->msr |= MSR_SE;
2228 #endif
2229         }
2230         set_tsk_thread_flag(task, TIF_SINGLESTEP);
2231 }
2232
2233 void user_enable_block_step(struct task_struct *task)
2234 {
2235         struct pt_regs *regs = task->thread.regs;
2236
2237         if (regs != NULL) {
2238 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2239                 task->thread.debug.dbcr0 &= ~DBCR0_IC;
2240                 task->thread.debug.dbcr0 = DBCR0_IDM | DBCR0_BT;
2241                 regs->msr |= MSR_DE;
2242 #else
2243                 regs->msr &= ~MSR_SE;
2244                 regs->msr |= MSR_BE;
2245 #endif
2246         }
2247         set_tsk_thread_flag(task, TIF_SINGLESTEP);
2248 }
2249
2250 void user_disable_single_step(struct task_struct *task)
2251 {
2252         struct pt_regs *regs = task->thread.regs;
2253
2254         if (regs != NULL) {
2255 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2256                 /*
2257                  * The logic to disable single stepping should be as
2258                  * simple as turning off the Instruction Complete flag.
2259                  * And, after doing so, if all debug flags are off, turn
2260                  * off DBCR0(IDM) and MSR(DE) .... Torez
2261                  */
2262                 task->thread.debug.dbcr0 &= ~(DBCR0_IC|DBCR0_BT);
2263                 /*
2264                  * Test to see if any of the DBCR_ACTIVE_EVENTS bits are set.
2265                  */
2266                 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
2267                                         task->thread.debug.dbcr1)) {
2268                         /*
2269                          * All debug events were off.....
2270                          */
2271                         task->thread.debug.dbcr0 &= ~DBCR0_IDM;
2272                         regs->msr &= ~MSR_DE;
2273                 }
2274 #else
2275                 regs->msr &= ~(MSR_SE | MSR_BE);
2276 #endif
2277         }
2278         clear_tsk_thread_flag(task, TIF_SINGLESTEP);
2279 }
2280
2281 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2282 void ptrace_triggered(struct perf_event *bp,
2283                       struct perf_sample_data *data, struct pt_regs *regs)
2284 {
2285         struct perf_event_attr attr;
2286
2287         /*
2288          * Disable the breakpoint request here since ptrace has defined a
2289          * one-shot behaviour for breakpoint exceptions in PPC64.
2290          * The SIGTRAP signal is generated automatically for us in do_dabr().
2291          * We don't have to do anything about that here
2292          */
2293         attr = bp->attr;
2294         attr.disabled = true;
2295         modify_user_hw_breakpoint(bp, &attr);
2296 }
2297 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2298
2299 static int ptrace_set_debugreg(struct task_struct *task, unsigned long addr,
2300                                unsigned long data)
2301 {
2302 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2303         int ret;
2304         struct thread_struct *thread = &(task->thread);
2305         struct perf_event *bp;
2306         struct perf_event_attr attr;
2307 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2308 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2309         struct arch_hw_breakpoint hw_brk;
2310 #endif
2311
2312         /* For ppc64 we support one DABR and no IABR's at the moment (ppc64).
2313          *  For embedded processors we support one DAC and no IAC's at the
2314          *  moment.
2315          */
2316         if (addr > 0)
2317                 return -EINVAL;
2318
2319         /* The bottom 3 bits in dabr are flags */
2320         if ((data & ~0x7UL) >= TASK_SIZE)
2321                 return -EIO;
2322
2323 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2324         /* For processors using DABR (i.e. 970), the bottom 3 bits are flags.
2325          *  It was assumed, on previous implementations, that 3 bits were
2326          *  passed together with the data address, fitting the design of the
2327          *  DABR register, as follows:
2328          *
2329          *  bit 0: Read flag
2330          *  bit 1: Write flag
2331          *  bit 2: Breakpoint translation
2332          *
2333          *  Thus, we use them here as so.
2334          */
2335
2336         /* Ensure breakpoint translation bit is set */
2337         if (data && !(data & HW_BRK_TYPE_TRANSLATE))
2338                 return -EIO;
2339         hw_brk.address = data & (~HW_BRK_TYPE_DABR);
2340         hw_brk.type = (data & HW_BRK_TYPE_DABR) | HW_BRK_TYPE_PRIV_ALL;
2341         hw_brk.len = 8;
2342 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2343         bp = thread->ptrace_bps[0];
2344         if ((!data) || !(hw_brk.type & HW_BRK_TYPE_RDWR)) {
2345                 if (bp) {
2346                         unregister_hw_breakpoint(bp);
2347                         thread->ptrace_bps[0] = NULL;
2348                 }
2349                 return 0;
2350         }
2351         if (bp) {
2352                 attr = bp->attr;
2353                 attr.bp_addr = hw_brk.address;
2354                 arch_bp_generic_fields(hw_brk.type, &attr.bp_type);
2355
2356                 /* Enable breakpoint */
2357                 attr.disabled = false;
2358
2359                 ret =  modify_user_hw_breakpoint(bp, &attr);
2360                 if (ret) {
2361                         return ret;
2362                 }
2363                 thread->ptrace_bps[0] = bp;
2364                 thread->hw_brk = hw_brk;
2365                 return 0;
2366         }
2367
2368         /* Create a new breakpoint request if one doesn't exist already */
2369         hw_breakpoint_init(&attr);
2370         attr.bp_addr = hw_brk.address;
2371         attr.bp_len = 8;
2372         arch_bp_generic_fields(hw_brk.type,
2373                                &attr.bp_type);
2374
2375         thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
2376                                                ptrace_triggered, NULL, task);
2377         if (IS_ERR(bp)) {
2378                 thread->ptrace_bps[0] = NULL;
2379                 return PTR_ERR(bp);
2380         }
2381
2382 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2383         task->thread.hw_brk = hw_brk;
2384 #else /* CONFIG_PPC_ADV_DEBUG_REGS */
2385         /* As described above, it was assumed 3 bits were passed with the data
2386          *  address, but we will assume only the mode bits will be passed
2387          *  as to not cause alignment restrictions for DAC-based processors.
2388          */
2389
2390         /* DAC's hold the whole address without any mode flags */
2391         task->thread.debug.dac1 = data & ~0x3UL;
2392
2393         if (task->thread.debug.dac1 == 0) {
2394                 dbcr_dac(task) &= ~(DBCR_DAC1R | DBCR_DAC1W);
2395                 if (!DBCR_ACTIVE_EVENTS(task->thread.debug.dbcr0,
2396                                         task->thread.debug.dbcr1)) {
2397                         task->thread.regs->msr &= ~MSR_DE;
2398                         task->thread.debug.dbcr0 &= ~DBCR0_IDM;
2399                 }
2400                 return 0;
2401         }
2402
2403         /* Read or Write bits must be set */
2404
2405         if (!(data & 0x3UL))
2406                 return -EINVAL;
2407
2408         /* Set the Internal Debugging flag (IDM bit 1) for the DBCR0
2409            register */
2410         task->thread.debug.dbcr0 |= DBCR0_IDM;
2411
2412         /* Check for write and read flags and set DBCR0
2413            accordingly */
2414         dbcr_dac(task) &= ~(DBCR_DAC1R|DBCR_DAC1W);
2415         if (data & 0x1UL)
2416                 dbcr_dac(task) |= DBCR_DAC1R;
2417         if (data & 0x2UL)
2418                 dbcr_dac(task) |= DBCR_DAC1W;
2419         task->thread.regs->msr |= MSR_DE;
2420 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2421         return 0;
2422 }
2423
2424 /*
2425  * Called by kernel/ptrace.c when detaching..
2426  *
2427  * Make sure single step bits etc are not set.
2428  */
2429 void ptrace_disable(struct task_struct *child)
2430 {
2431         /* make sure the single step bit is not set. */
2432         user_disable_single_step(child);
2433 }
2434
2435 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2436 static long set_instruction_bp(struct task_struct *child,
2437                               struct ppc_hw_breakpoint *bp_info)
2438 {
2439         int slot;
2440         int slot1_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC1) != 0);
2441         int slot2_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC2) != 0);
2442         int slot3_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC3) != 0);
2443         int slot4_in_use = ((child->thread.debug.dbcr0 & DBCR0_IAC4) != 0);
2444
2445         if (dbcr_iac_range(child) & DBCR_IAC12MODE)
2446                 slot2_in_use = 1;
2447         if (dbcr_iac_range(child) & DBCR_IAC34MODE)
2448                 slot4_in_use = 1;
2449
2450         if (bp_info->addr >= TASK_SIZE)
2451                 return -EIO;
2452
2453         if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT) {
2454
2455                 /* Make sure range is valid. */
2456                 if (bp_info->addr2 >= TASK_SIZE)
2457                         return -EIO;
2458
2459                 /* We need a pair of IAC regsisters */
2460                 if ((!slot1_in_use) && (!slot2_in_use)) {
2461                         slot = 1;
2462                         child->thread.debug.iac1 = bp_info->addr;
2463                         child->thread.debug.iac2 = bp_info->addr2;
2464                         child->thread.debug.dbcr0 |= DBCR0_IAC1;
2465                         if (bp_info->addr_mode ==
2466                                         PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
2467                                 dbcr_iac_range(child) |= DBCR_IAC12X;
2468                         else
2469                                 dbcr_iac_range(child) |= DBCR_IAC12I;
2470 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2471                 } else if ((!slot3_in_use) && (!slot4_in_use)) {
2472                         slot = 3;
2473                         child->thread.debug.iac3 = bp_info->addr;
2474                         child->thread.debug.iac4 = bp_info->addr2;
2475                         child->thread.debug.dbcr0 |= DBCR0_IAC3;
2476                         if (bp_info->addr_mode ==
2477                                         PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
2478                                 dbcr_iac_range(child) |= DBCR_IAC34X;
2479                         else
2480                                 dbcr_iac_range(child) |= DBCR_IAC34I;
2481 #endif
2482                 } else
2483                         return -ENOSPC;
2484         } else {
2485                 /* We only need one.  If possible leave a pair free in
2486                  * case a range is needed later
2487                  */
2488                 if (!slot1_in_use) {
2489                         /*
2490                          * Don't use iac1 if iac1-iac2 are free and either
2491                          * iac3 or iac4 (but not both) are free
2492                          */
2493                         if (slot2_in_use || (slot3_in_use == slot4_in_use)) {
2494                                 slot = 1;
2495                                 child->thread.debug.iac1 = bp_info->addr;
2496                                 child->thread.debug.dbcr0 |= DBCR0_IAC1;
2497                                 goto out;
2498                         }
2499                 }
2500                 if (!slot2_in_use) {
2501                         slot = 2;
2502                         child->thread.debug.iac2 = bp_info->addr;
2503                         child->thread.debug.dbcr0 |= DBCR0_IAC2;
2504 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2505                 } else if (!slot3_in_use) {
2506                         slot = 3;
2507                         child->thread.debug.iac3 = bp_info->addr;
2508                         child->thread.debug.dbcr0 |= DBCR0_IAC3;
2509                 } else if (!slot4_in_use) {
2510                         slot = 4;
2511                         child->thread.debug.iac4 = bp_info->addr;
2512                         child->thread.debug.dbcr0 |= DBCR0_IAC4;
2513 #endif
2514                 } else
2515                         return -ENOSPC;
2516         }
2517 out:
2518         child->thread.debug.dbcr0 |= DBCR0_IDM;
2519         child->thread.regs->msr |= MSR_DE;
2520
2521         return slot;
2522 }
2523
2524 static int del_instruction_bp(struct task_struct *child, int slot)
2525 {
2526         switch (slot) {
2527         case 1:
2528                 if ((child->thread.debug.dbcr0 & DBCR0_IAC1) == 0)
2529                         return -ENOENT;
2530
2531                 if (dbcr_iac_range(child) & DBCR_IAC12MODE) {
2532                         /* address range - clear slots 1 & 2 */
2533                         child->thread.debug.iac2 = 0;
2534                         dbcr_iac_range(child) &= ~DBCR_IAC12MODE;
2535                 }
2536                 child->thread.debug.iac1 = 0;
2537                 child->thread.debug.dbcr0 &= ~DBCR0_IAC1;
2538                 break;
2539         case 2:
2540                 if ((child->thread.debug.dbcr0 & DBCR0_IAC2) == 0)
2541                         return -ENOENT;
2542
2543                 if (dbcr_iac_range(child) & DBCR_IAC12MODE)
2544                         /* used in a range */
2545                         return -EINVAL;
2546                 child->thread.debug.iac2 = 0;
2547                 child->thread.debug.dbcr0 &= ~DBCR0_IAC2;
2548                 break;
2549 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
2550         case 3:
2551                 if ((child->thread.debug.dbcr0 & DBCR0_IAC3) == 0)
2552                         return -ENOENT;
2553
2554                 if (dbcr_iac_range(child) & DBCR_IAC34MODE) {
2555                         /* address range - clear slots 3 & 4 */
2556                         child->thread.debug.iac4 = 0;
2557                         dbcr_iac_range(child) &= ~DBCR_IAC34MODE;
2558                 }
2559                 child->thread.debug.iac3 = 0;
2560                 child->thread.debug.dbcr0 &= ~DBCR0_IAC3;
2561                 break;
2562         case 4:
2563                 if ((child->thread.debug.dbcr0 & DBCR0_IAC4) == 0)
2564                         return -ENOENT;
2565
2566                 if (dbcr_iac_range(child) & DBCR_IAC34MODE)
2567                         /* Used in a range */
2568                         return -EINVAL;
2569                 child->thread.debug.iac4 = 0;
2570                 child->thread.debug.dbcr0 &= ~DBCR0_IAC4;
2571                 break;
2572 #endif
2573         default:
2574                 return -EINVAL;
2575         }
2576         return 0;
2577 }
2578
2579 static int set_dac(struct task_struct *child, struct ppc_hw_breakpoint *bp_info)
2580 {
2581         int byte_enable =
2582                 (bp_info->condition_mode >> PPC_BREAKPOINT_CONDITION_BE_SHIFT)
2583                 & 0xf;
2584         int condition_mode =
2585                 bp_info->condition_mode & PPC_BREAKPOINT_CONDITION_MODE;
2586         int slot;
2587
2588         if (byte_enable && (condition_mode == 0))
2589                 return -EINVAL;
2590
2591         if (bp_info->addr >= TASK_SIZE)
2592                 return -EIO;
2593
2594         if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0) {
2595                 slot = 1;
2596                 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2597                         dbcr_dac(child) |= DBCR_DAC1R;
2598                 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2599                         dbcr_dac(child) |= DBCR_DAC1W;
2600                 child->thread.debug.dac1 = (unsigned long)bp_info->addr;
2601 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2602                 if (byte_enable) {
2603                         child->thread.debug.dvc1 =
2604                                 (unsigned long)bp_info->condition_value;
2605                         child->thread.debug.dbcr2 |=
2606                                 ((byte_enable << DBCR2_DVC1BE_SHIFT) |
2607                                  (condition_mode << DBCR2_DVC1M_SHIFT));
2608                 }
2609 #endif
2610 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2611         } else if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
2612                 /* Both dac1 and dac2 are part of a range */
2613                 return -ENOSPC;
2614 #endif
2615         } else if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0) {
2616                 slot = 2;
2617                 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2618                         dbcr_dac(child) |= DBCR_DAC2R;
2619                 if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2620                         dbcr_dac(child) |= DBCR_DAC2W;
2621                 child->thread.debug.dac2 = (unsigned long)bp_info->addr;
2622 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2623                 if (byte_enable) {
2624                         child->thread.debug.dvc2 =
2625                                 (unsigned long)bp_info->condition_value;
2626                         child->thread.debug.dbcr2 |=
2627                                 ((byte_enable << DBCR2_DVC2BE_SHIFT) |
2628                                  (condition_mode << DBCR2_DVC2M_SHIFT));
2629                 }
2630 #endif
2631         } else
2632                 return -ENOSPC;
2633         child->thread.debug.dbcr0 |= DBCR0_IDM;
2634         child->thread.regs->msr |= MSR_DE;
2635
2636         return slot + 4;
2637 }
2638
2639 static int del_dac(struct task_struct *child, int slot)
2640 {
2641         if (slot == 1) {
2642                 if ((dbcr_dac(child) & (DBCR_DAC1R | DBCR_DAC1W)) == 0)
2643                         return -ENOENT;
2644
2645                 child->thread.debug.dac1 = 0;
2646                 dbcr_dac(child) &= ~(DBCR_DAC1R | DBCR_DAC1W);
2647 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2648                 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE) {
2649                         child->thread.debug.dac2 = 0;
2650                         child->thread.debug.dbcr2 &= ~DBCR2_DAC12MODE;
2651                 }
2652                 child->thread.debug.dbcr2 &= ~(DBCR2_DVC1M | DBCR2_DVC1BE);
2653 #endif
2654 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2655                 child->thread.debug.dvc1 = 0;
2656 #endif
2657         } else if (slot == 2) {
2658                 if ((dbcr_dac(child) & (DBCR_DAC2R | DBCR_DAC2W)) == 0)
2659                         return -ENOENT;
2660
2661 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2662                 if (child->thread.debug.dbcr2 & DBCR2_DAC12MODE)
2663                         /* Part of a range */
2664                         return -EINVAL;
2665                 child->thread.debug.dbcr2 &= ~(DBCR2_DVC2M | DBCR2_DVC2BE);
2666 #endif
2667 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
2668                 child->thread.debug.dvc2 = 0;
2669 #endif
2670                 child->thread.debug.dac2 = 0;
2671                 dbcr_dac(child) &= ~(DBCR_DAC2R | DBCR_DAC2W);
2672         } else
2673                 return -EINVAL;
2674
2675         return 0;
2676 }
2677 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
2678
2679 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2680 static int set_dac_range(struct task_struct *child,
2681                          struct ppc_hw_breakpoint *bp_info)
2682 {
2683         int mode = bp_info->addr_mode & PPC_BREAKPOINT_MODE_MASK;
2684
2685         /* We don't allow range watchpoints to be used with DVC */
2686         if (bp_info->condition_mode)
2687                 return -EINVAL;
2688
2689         /*
2690          * Best effort to verify the address range.  The user/supervisor bits
2691          * prevent trapping in kernel space, but let's fail on an obvious bad
2692          * range.  The simple test on the mask is not fool-proof, and any
2693          * exclusive range will spill over into kernel space.
2694          */
2695         if (bp_info->addr >= TASK_SIZE)
2696                 return -EIO;
2697         if (mode == PPC_BREAKPOINT_MODE_MASK) {
2698                 /*
2699                  * dac2 is a bitmask.  Don't allow a mask that makes a
2700                  * kernel space address from a valid dac1 value
2701                  */
2702                 if (~((unsigned long)bp_info->addr2) >= TASK_SIZE)
2703                         return -EIO;
2704         } else {
2705                 /*
2706                  * For range breakpoints, addr2 must also be a valid address
2707                  */
2708                 if (bp_info->addr2 >= TASK_SIZE)
2709                         return -EIO;
2710         }
2711
2712         if (child->thread.debug.dbcr0 &
2713             (DBCR0_DAC1R | DBCR0_DAC1W | DBCR0_DAC2R | DBCR0_DAC2W))
2714                 return -ENOSPC;
2715
2716         if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2717                 child->thread.debug.dbcr0 |= (DBCR0_DAC1R | DBCR0_IDM);
2718         if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2719                 child->thread.debug.dbcr0 |= (DBCR0_DAC1W | DBCR0_IDM);
2720         child->thread.debug.dac1 = bp_info->addr;
2721         child->thread.debug.dac2 = bp_info->addr2;
2722         if (mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
2723                 child->thread.debug.dbcr2  |= DBCR2_DAC12M;
2724         else if (mode == PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE)
2725                 child->thread.debug.dbcr2  |= DBCR2_DAC12MX;
2726         else    /* PPC_BREAKPOINT_MODE_MASK */
2727                 child->thread.debug.dbcr2  |= DBCR2_DAC12MM;
2728         child->thread.regs->msr |= MSR_DE;
2729
2730         return 5;
2731 }
2732 #endif /* CONFIG_PPC_ADV_DEBUG_DAC_RANGE */
2733
2734 static long ppc_set_hwdebug(struct task_struct *child,
2735                      struct ppc_hw_breakpoint *bp_info)
2736 {
2737 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2738         int len = 0;
2739         struct thread_struct *thread = &(child->thread);
2740         struct perf_event *bp;
2741         struct perf_event_attr attr;
2742 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2743 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
2744         struct arch_hw_breakpoint brk;
2745 #endif
2746
2747         if (bp_info->version != 1)
2748                 return -ENOTSUPP;
2749 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2750         /*
2751          * Check for invalid flags and combinations
2752          */
2753         if ((bp_info->trigger_type == 0) ||
2754             (bp_info->trigger_type & ~(PPC_BREAKPOINT_TRIGGER_EXECUTE |
2755                                        PPC_BREAKPOINT_TRIGGER_RW)) ||
2756             (bp_info->addr_mode & ~PPC_BREAKPOINT_MODE_MASK) ||
2757             (bp_info->condition_mode &
2758              ~(PPC_BREAKPOINT_CONDITION_MODE |
2759                PPC_BREAKPOINT_CONDITION_BE_ALL)))
2760                 return -EINVAL;
2761 #if CONFIG_PPC_ADV_DEBUG_DVCS == 0
2762         if (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
2763                 return -EINVAL;
2764 #endif
2765
2766         if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_EXECUTE) {
2767                 if ((bp_info->trigger_type != PPC_BREAKPOINT_TRIGGER_EXECUTE) ||
2768                     (bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE))
2769                         return -EINVAL;
2770                 return set_instruction_bp(child, bp_info);
2771         }
2772         if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
2773                 return set_dac(child, bp_info);
2774
2775 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2776         return set_dac_range(child, bp_info);
2777 #else
2778         return -EINVAL;
2779 #endif
2780 #else /* !CONFIG_PPC_ADV_DEBUG_DVCS */
2781         /*
2782          * We only support one data breakpoint
2783          */
2784         if ((bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_RW) == 0 ||
2785             (bp_info->trigger_type & ~PPC_BREAKPOINT_TRIGGER_RW) != 0 ||
2786             bp_info->condition_mode != PPC_BREAKPOINT_CONDITION_NONE)
2787                 return -EINVAL;
2788
2789         if ((unsigned long)bp_info->addr >= TASK_SIZE)
2790                 return -EIO;
2791
2792         brk.address = bp_info->addr & ~7UL;
2793         brk.type = HW_BRK_TYPE_TRANSLATE;
2794         brk.len = 8;
2795         if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_READ)
2796                 brk.type |= HW_BRK_TYPE_READ;
2797         if (bp_info->trigger_type & PPC_BREAKPOINT_TRIGGER_WRITE)
2798                 brk.type |= HW_BRK_TYPE_WRITE;
2799 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2800         /*
2801          * Check if the request is for 'range' breakpoints. We can
2802          * support it if range < 8 bytes.
2803          */
2804         if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE)
2805                 len = bp_info->addr2 - bp_info->addr;
2806         else if (bp_info->addr_mode == PPC_BREAKPOINT_MODE_EXACT)
2807                 len = 1;
2808         else
2809                 return -EINVAL;
2810         bp = thread->ptrace_bps[0];
2811         if (bp)
2812                 return -ENOSPC;
2813
2814         /* Create a new breakpoint request if one doesn't exist already */
2815         hw_breakpoint_init(&attr);
2816         attr.bp_addr = (unsigned long)bp_info->addr & ~HW_BREAKPOINT_ALIGN;
2817         attr.bp_len = len;
2818         arch_bp_generic_fields(brk.type, &attr.bp_type);
2819
2820         thread->ptrace_bps[0] = bp = register_user_hw_breakpoint(&attr,
2821                                                ptrace_triggered, NULL, child);
2822         if (IS_ERR(bp)) {
2823                 thread->ptrace_bps[0] = NULL;
2824                 return PTR_ERR(bp);
2825         }
2826
2827         return 1;
2828 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2829
2830         if (bp_info->addr_mode != PPC_BREAKPOINT_MODE_EXACT)
2831                 return -EINVAL;
2832
2833         if (child->thread.hw_brk.address)
2834                 return -ENOSPC;
2835
2836         child->thread.hw_brk = brk;
2837
2838         return 1;
2839 #endif /* !CONFIG_PPC_ADV_DEBUG_DVCS */
2840 }
2841
2842 static long ppc_del_hwdebug(struct task_struct *child, long data)
2843 {
2844 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2845         int ret = 0;
2846         struct thread_struct *thread = &(child->thread);
2847         struct perf_event *bp;
2848 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2849 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2850         int rc;
2851
2852         if (data <= 4)
2853                 rc = del_instruction_bp(child, (int)data);
2854         else
2855                 rc = del_dac(child, (int)data - 4);
2856
2857         if (!rc) {
2858                 if (!DBCR_ACTIVE_EVENTS(child->thread.debug.dbcr0,
2859                                         child->thread.debug.dbcr1)) {
2860                         child->thread.debug.dbcr0 &= ~DBCR0_IDM;
2861                         child->thread.regs->msr &= ~MSR_DE;
2862                 }
2863         }
2864         return rc;
2865 #else
2866         if (data != 1)
2867                 return -EINVAL;
2868
2869 #ifdef CONFIG_HAVE_HW_BREAKPOINT
2870         bp = thread->ptrace_bps[0];
2871         if (bp) {
2872                 unregister_hw_breakpoint(bp);
2873                 thread->ptrace_bps[0] = NULL;
2874         } else
2875                 ret = -ENOENT;
2876         return ret;
2877 #else /* CONFIG_HAVE_HW_BREAKPOINT */
2878         if (child->thread.hw_brk.address == 0)
2879                 return -ENOENT;
2880
2881         child->thread.hw_brk.address = 0;
2882         child->thread.hw_brk.type = 0;
2883 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
2884
2885         return 0;
2886 #endif
2887 }
2888
2889 long arch_ptrace(struct task_struct *child, long request,
2890                  unsigned long addr, unsigned long data)
2891 {
2892         int ret = -EPERM;
2893         void __user *datavp = (void __user *) data;
2894         unsigned long __user *datalp = datavp;
2895
2896         switch (request) {
2897         /* read the word at location addr in the USER area. */
2898         case PTRACE_PEEKUSR: {
2899                 unsigned long index, tmp;
2900
2901                 ret = -EIO;
2902                 /* convert to index and check */
2903 #ifdef CONFIG_PPC32
2904                 index = addr >> 2;
2905                 if ((addr & 3) || (index > PT_FPSCR)
2906                     || (child->thread.regs == NULL))
2907 #else
2908                 index = addr >> 3;
2909                 if ((addr & 7) || (index > PT_FPSCR))
2910 #endif
2911                         break;
2912
2913                 CHECK_FULL_REGS(child->thread.regs);
2914                 if (index < PT_FPR0) {
2915                         ret = ptrace_get_reg(child, (int) index, &tmp);
2916                         if (ret)
2917                                 break;
2918                 } else {
2919                         unsigned int fpidx = index - PT_FPR0;
2920
2921                         flush_fp_to_thread(child);
2922                         if (fpidx < (PT_FPSCR - PT_FPR0))
2923                                 if (IS_ENABLED(CONFIG_PPC32)) {
2924                                         // On 32-bit the index we are passed refers to 32-bit words
2925                                         tmp = ((u32 *)child->thread.fp_state.fpr)[fpidx];
2926                                 } else {
2927                                         memcpy(&tmp, &child->thread.TS_FPR(fpidx),
2928                                                sizeof(long));
2929                                 }
2930                         else
2931                                 tmp = child->thread.fp_state.fpscr;
2932                 }
2933                 ret = put_user(tmp, datalp);
2934                 break;
2935         }
2936
2937         /* write the word at location addr in the USER area */
2938         case PTRACE_POKEUSR: {
2939                 unsigned long index;
2940
2941                 ret = -EIO;
2942                 /* convert to index and check */
2943 #ifdef CONFIG_PPC32
2944                 index = addr >> 2;
2945                 if ((addr & 3) || (index > PT_FPSCR)
2946                     || (child->thread.regs == NULL))
2947 #else
2948                 index = addr >> 3;
2949                 if ((addr & 7) || (index > PT_FPSCR))
2950 #endif
2951                         break;
2952
2953                 CHECK_FULL_REGS(child->thread.regs);
2954                 if (index < PT_FPR0) {
2955                         ret = ptrace_put_reg(child, index, data);
2956                 } else {
2957                         unsigned int fpidx = index - PT_FPR0;
2958
2959                         flush_fp_to_thread(child);
2960                         if (fpidx < (PT_FPSCR - PT_FPR0))
2961                                 if (IS_ENABLED(CONFIG_PPC32)) {
2962                                         // On 32-bit the index we are passed refers to 32-bit words
2963                                         ((u32 *)child->thread.fp_state.fpr)[fpidx] = data;
2964                                 } else {
2965                                         memcpy(&child->thread.TS_FPR(fpidx), &data,
2966                                                sizeof(long));
2967                                 }
2968                         else
2969                                 child->thread.fp_state.fpscr = data;
2970                         ret = 0;
2971                 }
2972                 break;
2973         }
2974
2975         case PPC_PTRACE_GETHWDBGINFO: {
2976                 struct ppc_debug_info dbginfo;
2977
2978                 dbginfo.version = 1;
2979 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
2980                 dbginfo.num_instruction_bps = CONFIG_PPC_ADV_DEBUG_IACS;
2981                 dbginfo.num_data_bps = CONFIG_PPC_ADV_DEBUG_DACS;
2982                 dbginfo.num_condition_regs = CONFIG_PPC_ADV_DEBUG_DVCS;
2983                 dbginfo.data_bp_alignment = 4;
2984                 dbginfo.sizeof_condition = 4;
2985                 dbginfo.features = PPC_DEBUG_FEATURE_INSN_BP_RANGE |
2986                                    PPC_DEBUG_FEATURE_INSN_BP_MASK;
2987 #ifdef CONFIG_PPC_ADV_DEBUG_DAC_RANGE
2988                 dbginfo.features |=
2989                                    PPC_DEBUG_FEATURE_DATA_BP_RANGE |
2990                                    PPC_DEBUG_FEATURE_DATA_BP_MASK;
2991 #endif
2992 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
2993                 dbginfo.num_instruction_bps = 0;
2994                 dbginfo.num_data_bps = 1;
2995                 dbginfo.num_condition_regs = 0;
2996 #ifdef CONFIG_PPC64
2997                 dbginfo.data_bp_alignment = 8;
2998 #else
2999                 dbginfo.data_bp_alignment = 4;
3000 #endif
3001                 dbginfo.sizeof_condition = 0;
3002 #ifdef CONFIG_HAVE_HW_BREAKPOINT
3003                 dbginfo.features = PPC_DEBUG_FEATURE_DATA_BP_RANGE;
3004                 if (cpu_has_feature(CPU_FTR_DAWR))
3005                         dbginfo.features |= PPC_DEBUG_FEATURE_DATA_BP_DAWR;
3006 #else
3007                 dbginfo.features = 0;
3008 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
3009 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
3010
3011                 if (!access_ok(VERIFY_WRITE, datavp,
3012                                sizeof(struct ppc_debug_info)))
3013                         return -EFAULT;
3014                 ret = __copy_to_user(datavp, &dbginfo,
3015                                      sizeof(struct ppc_debug_info)) ?
3016                       -EFAULT : 0;
3017                 break;
3018         }
3019
3020         case PPC_PTRACE_SETHWDEBUG: {
3021                 struct ppc_hw_breakpoint bp_info;
3022
3023                 if (!access_ok(VERIFY_READ, datavp,
3024                                sizeof(struct ppc_hw_breakpoint)))
3025                         return -EFAULT;
3026                 ret = __copy_from_user(&bp_info, datavp,
3027                                        sizeof(struct ppc_hw_breakpoint)) ?
3028                       -EFAULT : 0;
3029                 if (!ret)
3030                         ret = ppc_set_hwdebug(child, &bp_info);
3031                 break;
3032         }
3033
3034         case PPC_PTRACE_DELHWDEBUG: {
3035                 ret = ppc_del_hwdebug(child, data);
3036                 break;
3037         }
3038
3039         case PTRACE_GET_DEBUGREG: {
3040 #ifndef CONFIG_PPC_ADV_DEBUG_REGS
3041                 unsigned long dabr_fake;
3042 #endif
3043                 ret = -EINVAL;
3044                 /* We only support one DABR and no IABRS at the moment */
3045                 if (addr > 0)
3046                         break;
3047 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
3048                 ret = put_user(child->thread.debug.dac1, datalp);
3049 #else
3050                 dabr_fake = ((child->thread.hw_brk.address & (~HW_BRK_TYPE_DABR)) |
3051                              (child->thread.hw_brk.type & HW_BRK_TYPE_DABR));
3052                 ret = put_user(dabr_fake, datalp);
3053 #endif
3054                 break;
3055         }
3056
3057         case PTRACE_SET_DEBUGREG:
3058                 ret = ptrace_set_debugreg(child, addr, data);
3059                 break;
3060
3061 #ifdef CONFIG_PPC64
3062         case PTRACE_GETREGS64:
3063 #endif
3064         case PTRACE_GETREGS:    /* Get all pt_regs from the child. */
3065                 return copy_regset_to_user(child, &user_ppc_native_view,
3066                                            REGSET_GPR,
3067                                            0, sizeof(struct pt_regs),
3068                                            datavp);
3069
3070 #ifdef CONFIG_PPC64
3071         case PTRACE_SETREGS64:
3072 #endif
3073         case PTRACE_SETREGS:    /* Set all gp regs in the child. */
3074                 return copy_regset_from_user(child, &user_ppc_native_view,
3075                                              REGSET_GPR,
3076                                              0, sizeof(struct pt_regs),
3077                                              datavp);
3078
3079         case PTRACE_GETFPREGS: /* Get the child FPU state (FPR0...31 + FPSCR) */
3080                 return copy_regset_to_user(child, &user_ppc_native_view,
3081                                            REGSET_FPR,
3082                                            0, sizeof(elf_fpregset_t),
3083                                            datavp);
3084
3085         case PTRACE_SETFPREGS: /* Set the child FPU state (FPR0...31 + FPSCR) */
3086                 return copy_regset_from_user(child, &user_ppc_native_view,
3087                                              REGSET_FPR,
3088                                              0, sizeof(elf_fpregset_t),
3089                                              datavp);
3090
3091 #ifdef CONFIG_ALTIVEC
3092         case PTRACE_GETVRREGS:
3093                 return copy_regset_to_user(child, &user_ppc_native_view,
3094                                            REGSET_VMX,
3095                                            0, (33 * sizeof(vector128) +
3096                                                sizeof(u32)),
3097                                            datavp);
3098
3099         case PTRACE_SETVRREGS:
3100                 return copy_regset_from_user(child, &user_ppc_native_view,
3101                                              REGSET_VMX,
3102                                              0, (33 * sizeof(vector128) +
3103                                                  sizeof(u32)),
3104                                              datavp);
3105 #endif
3106 #ifdef CONFIG_VSX
3107         case PTRACE_GETVSRREGS:
3108                 return copy_regset_to_user(child, &user_ppc_native_view,
3109                                            REGSET_VSX,
3110                                            0, 32 * sizeof(double),
3111                                            datavp);
3112
3113         case PTRACE_SETVSRREGS:
3114                 return copy_regset_from_user(child, &user_ppc_native_view,
3115                                              REGSET_VSX,
3116                                              0, 32 * sizeof(double),
3117                                              datavp);
3118 #endif
3119 #ifdef CONFIG_SPE
3120         case PTRACE_GETEVRREGS:
3121                 /* Get the child spe register state. */
3122                 return copy_regset_to_user(child, &user_ppc_native_view,
3123                                            REGSET_SPE, 0, 35 * sizeof(u32),
3124                                            datavp);
3125
3126         case PTRACE_SETEVRREGS:
3127                 /* Set the child spe register state. */
3128                 return copy_regset_from_user(child, &user_ppc_native_view,
3129                                              REGSET_SPE, 0, 35 * sizeof(u32),
3130                                              datavp);
3131 #endif
3132
3133         default:
3134                 ret = ptrace_request(child, request, addr, data);
3135                 break;
3136         }
3137         return ret;
3138 }
3139
3140 #ifdef CONFIG_SECCOMP
3141 static int do_seccomp(struct pt_regs *regs)
3142 {
3143         if (!test_thread_flag(TIF_SECCOMP))
3144                 return 0;
3145
3146         /*
3147          * The ABI we present to seccomp tracers is that r3 contains
3148          * the syscall return value and orig_gpr3 contains the first
3149          * syscall parameter. This is different to the ptrace ABI where
3150          * both r3 and orig_gpr3 contain the first syscall parameter.
3151          */
3152         regs->gpr[3] = -ENOSYS;
3153
3154         /*
3155          * We use the __ version here because we have already checked
3156          * TIF_SECCOMP. If this fails, there is nothing left to do, we
3157          * have already loaded -ENOSYS into r3, or seccomp has put
3158          * something else in r3 (via SECCOMP_RET_ERRNO/TRACE).
3159          */
3160         if (__secure_computing(NULL))
3161                 return -1;
3162
3163         /*
3164          * The syscall was allowed by seccomp, restore the register
3165          * state to what audit expects.
3166          * Note that we use orig_gpr3, which means a seccomp tracer can
3167          * modify the first syscall parameter (in orig_gpr3) and also
3168          * allow the syscall to proceed.
3169          */
3170         regs->gpr[3] = regs->orig_gpr3;
3171
3172         return 0;
3173 }
3174 #else
3175 static inline int do_seccomp(struct pt_regs *regs) { return 0; }
3176 #endif /* CONFIG_SECCOMP */
3177
3178 /**
3179  * do_syscall_trace_enter() - Do syscall tracing on kernel entry.
3180  * @regs: the pt_regs of the task to trace (current)
3181  *
3182  * Performs various types of tracing on syscall entry. This includes seccomp,
3183  * ptrace, syscall tracepoints and audit.
3184  *
3185  * The pt_regs are potentially visible to userspace via ptrace, so their
3186  * contents is ABI.
3187  *
3188  * One or more of the tracers may modify the contents of pt_regs, in particular
3189  * to modify arguments or even the syscall number itself.
3190  *
3191  * It's also possible that a tracer can choose to reject the system call. In
3192  * that case this function will return an illegal syscall number, and will put
3193  * an appropriate return value in regs->r3.
3194  *
3195  * Return: the (possibly changed) syscall number.
3196  */
3197 long do_syscall_trace_enter(struct pt_regs *regs)
3198 {
3199         user_exit();
3200
3201         /*
3202          * The tracer may decide to abort the syscall, if so tracehook
3203          * will return !0. Note that the tracer may also just change
3204          * regs->gpr[0] to an invalid syscall number, that is handled
3205          * below on the exit path.
3206          */
3207         if (test_thread_flag(TIF_SYSCALL_TRACE) &&
3208             tracehook_report_syscall_entry(regs))
3209                 goto skip;
3210
3211         /* Run seccomp after ptrace; allow it to set gpr[3]. */
3212         if (do_seccomp(regs))
3213                 return -1;
3214
3215         /* Avoid trace and audit when syscall is invalid. */
3216         if (regs->gpr[0] >= NR_syscalls)
3217                 goto skip;
3218
3219         if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
3220                 trace_sys_enter(regs, regs->gpr[0]);
3221
3222 #ifdef CONFIG_PPC64
3223         if (!is_32bit_task())
3224                 audit_syscall_entry(regs->gpr[0], regs->gpr[3], regs->gpr[4],
3225                                     regs->gpr[5], regs->gpr[6]);
3226         else
3227 #endif
3228                 audit_syscall_entry(regs->gpr[0],
3229                                     regs->gpr[3] & 0xffffffff,
3230                                     regs->gpr[4] & 0xffffffff,
3231                                     regs->gpr[5] & 0xffffffff,
3232                                     regs->gpr[6] & 0xffffffff);
3233
3234         /* Return the possibly modified but valid syscall number */
3235         return regs->gpr[0];
3236
3237 skip:
3238         /*
3239          * If we are aborting explicitly, or if the syscall number is
3240          * now invalid, set the return value to -ENOSYS.
3241          */
3242         regs->gpr[3] = -ENOSYS;
3243         return -1;
3244 }
3245
3246 void do_syscall_trace_leave(struct pt_regs *regs)
3247 {
3248         int step;
3249
3250         audit_syscall_exit(regs);
3251
3252         if (unlikely(test_thread_flag(TIF_SYSCALL_TRACEPOINT)))
3253                 trace_sys_exit(regs, regs->result);
3254
3255         step = test_thread_flag(TIF_SINGLESTEP);
3256         if (step || test_thread_flag(TIF_SYSCALL_TRACE))
3257                 tracehook_report_syscall_exit(regs, step);
3258
3259         user_enter();
3260 }