1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Derived from "arch/i386/kernel/process.c"
4 * Copyright (C) 1995 Linus Torvalds
6 * Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
7 * Paul Mackerras (paulus@cs.anu.edu.au)
10 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
13 #include <linux/errno.h>
14 #include <linux/sched.h>
15 #include <linux/sched/debug.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/task_stack.h>
18 #include <linux/kernel.h>
20 #include <linux/smp.h>
21 #include <linux/stddef.h>
22 #include <linux/unistd.h>
23 #include <linux/ptrace.h>
24 #include <linux/slab.h>
25 #include <linux/user.h>
26 #include <linux/elf.h>
27 #include <linux/prctl.h>
28 #include <linux/init_task.h>
29 #include <linux/export.h>
30 #include <linux/kallsyms.h>
31 #include <linux/mqueue.h>
32 #include <linux/hardirq.h>
33 #include <linux/utsname.h>
34 #include <linux/ftrace.h>
35 #include <linux/kernel_stat.h>
36 #include <linux/personality.h>
37 #include <linux/random.h>
38 #include <linux/hw_breakpoint.h>
39 #include <linux/uaccess.h>
40 #include <linux/elf-randomize.h>
41 #include <linux/pkeys.h>
42 #include <linux/seq_buf.h>
45 #include <asm/processor.h>
48 #include <asm/machdep.h>
50 #include <asm/runlatch.h>
51 #include <asm/syscalls.h>
52 #include <asm/switch_to.h>
54 #include <asm/debug.h>
56 #include <asm/firmware.h>
57 #include <asm/hw_irq.h>
59 #include <asm/code-patching.h>
61 #include <asm/livepatch.h>
62 #include <asm/cpu_has_feature.h>
63 #include <asm/asm-prototypes.h>
64 #include <asm/stacktrace.h>
65 #include <asm/hw_breakpoint.h>
67 #include <linux/kprobes.h>
68 #include <linux/kdebug.h>
70 /* Transactional Memory debug */
72 #define TM_DEBUG(x...) printk(KERN_INFO x)
74 #define TM_DEBUG(x...) do { } while(0)
77 extern unsigned long _get_SP(void);
79 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
81 * Are we running in "Suspend disabled" mode? If so we have to block any
82 * sigreturn that would get us into suspended state, and we also warn in some
83 * other paths that we should never reach with suspend disabled.
85 bool tm_suspend_disabled __ro_after_init = false;
87 static void check_if_tm_restore_required(struct task_struct *tsk)
90 * If we are saving the current thread's registers, and the
91 * thread is in a transactional state, set the TIF_RESTORE_TM
92 * bit so that we know to restore the registers before
93 * returning to userspace.
95 if (tsk == current && tsk->thread.regs &&
96 MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
97 !test_thread_flag(TIF_RESTORE_TM)) {
98 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
99 set_thread_flag(TIF_RESTORE_TM);
104 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
105 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
107 bool strict_msr_control;
108 EXPORT_SYMBOL(strict_msr_control);
110 static int __init enable_strict_msr_control(char *str)
112 strict_msr_control = true;
113 pr_info("Enabling strict facility control\n");
117 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
119 /* notrace because it's called by restore_math */
120 unsigned long notrace msr_check_and_set(unsigned long bits)
122 unsigned long oldmsr = mfmsr();
123 unsigned long newmsr;
125 newmsr = oldmsr | bits;
127 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
130 if (oldmsr != newmsr)
135 EXPORT_SYMBOL_GPL(msr_check_and_set);
137 /* notrace because it's called by restore_math */
138 void notrace __msr_check_and_clear(unsigned long bits)
140 unsigned long oldmsr = mfmsr();
141 unsigned long newmsr;
143 newmsr = oldmsr & ~bits;
145 if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
148 if (oldmsr != newmsr)
151 EXPORT_SYMBOL(__msr_check_and_clear);
153 #ifdef CONFIG_PPC_FPU
154 static void __giveup_fpu(struct task_struct *tsk)
159 msr = tsk->thread.regs->msr;
160 msr &= ~(MSR_FP|MSR_FE0|MSR_FE1);
161 if (cpu_has_feature(CPU_FTR_VSX))
163 tsk->thread.regs->msr = msr;
166 void giveup_fpu(struct task_struct *tsk)
168 check_if_tm_restore_required(tsk);
170 msr_check_and_set(MSR_FP);
172 msr_check_and_clear(MSR_FP);
174 EXPORT_SYMBOL(giveup_fpu);
177 * Make sure the floating-point register state in the
178 * the thread_struct is up to date for task tsk.
180 void flush_fp_to_thread(struct task_struct *tsk)
182 if (tsk->thread.regs) {
184 * We need to disable preemption here because if we didn't,
185 * another process could get scheduled after the regs->msr
186 * test but before we have finished saving the FP registers
187 * to the thread_struct. That process could take over the
188 * FPU, and then when we get scheduled again we would store
189 * bogus values for the remaining FP registers.
192 if (tsk->thread.regs->msr & MSR_FP) {
194 * This should only ever be called for current or
195 * for a stopped child process. Since we save away
196 * the FP register state on context switch,
197 * there is something wrong if a stopped child appears
198 * to still have its FP state in the CPU registers.
200 BUG_ON(tsk != current);
206 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
208 void enable_kernel_fp(void)
210 unsigned long cpumsr;
212 WARN_ON(preemptible());
214 cpumsr = msr_check_and_set(MSR_FP);
216 if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
217 check_if_tm_restore_required(current);
219 * If a thread has already been reclaimed then the
220 * checkpointed registers are on the CPU but have definitely
221 * been saved by the reclaim code. Don't need to and *cannot*
222 * giveup as this would save to the 'live' structure not the
223 * checkpointed structure.
225 if (!MSR_TM_ACTIVE(cpumsr) &&
226 MSR_TM_ACTIVE(current->thread.regs->msr))
228 __giveup_fpu(current);
231 EXPORT_SYMBOL(enable_kernel_fp);
233 static inline void __giveup_fpu(struct task_struct *tsk) { }
234 #endif /* CONFIG_PPC_FPU */
236 #ifdef CONFIG_ALTIVEC
237 static void __giveup_altivec(struct task_struct *tsk)
242 msr = tsk->thread.regs->msr;
244 if (cpu_has_feature(CPU_FTR_VSX))
246 tsk->thread.regs->msr = msr;
249 void giveup_altivec(struct task_struct *tsk)
251 check_if_tm_restore_required(tsk);
253 msr_check_and_set(MSR_VEC);
254 __giveup_altivec(tsk);
255 msr_check_and_clear(MSR_VEC);
257 EXPORT_SYMBOL(giveup_altivec);
259 void enable_kernel_altivec(void)
261 unsigned long cpumsr;
263 WARN_ON(preemptible());
265 cpumsr = msr_check_and_set(MSR_VEC);
267 if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
268 check_if_tm_restore_required(current);
270 * If a thread has already been reclaimed then the
271 * checkpointed registers are on the CPU but have definitely
272 * been saved by the reclaim code. Don't need to and *cannot*
273 * giveup as this would save to the 'live' structure not the
274 * checkpointed structure.
276 if (!MSR_TM_ACTIVE(cpumsr) &&
277 MSR_TM_ACTIVE(current->thread.regs->msr))
279 __giveup_altivec(current);
282 EXPORT_SYMBOL(enable_kernel_altivec);
285 * Make sure the VMX/Altivec register state in the
286 * the thread_struct is up to date for task tsk.
288 void flush_altivec_to_thread(struct task_struct *tsk)
290 if (tsk->thread.regs) {
292 if (tsk->thread.regs->msr & MSR_VEC) {
293 BUG_ON(tsk != current);
299 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
300 #endif /* CONFIG_ALTIVEC */
303 static void __giveup_vsx(struct task_struct *tsk)
305 unsigned long msr = tsk->thread.regs->msr;
308 * We should never be ssetting MSR_VSX without also setting
311 WARN_ON((msr & MSR_VSX) && !((msr & MSR_FP) && (msr & MSR_VEC)));
313 /* __giveup_fpu will clear MSR_VSX */
317 __giveup_altivec(tsk);
320 static void giveup_vsx(struct task_struct *tsk)
322 check_if_tm_restore_required(tsk);
324 msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
326 msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
329 void enable_kernel_vsx(void)
331 unsigned long cpumsr;
333 WARN_ON(preemptible());
335 cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
337 if (current->thread.regs &&
338 (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
339 check_if_tm_restore_required(current);
341 * If a thread has already been reclaimed then the
342 * checkpointed registers are on the CPU but have definitely
343 * been saved by the reclaim code. Don't need to and *cannot*
344 * giveup as this would save to the 'live' structure not the
345 * checkpointed structure.
347 if (!MSR_TM_ACTIVE(cpumsr) &&
348 MSR_TM_ACTIVE(current->thread.regs->msr))
350 __giveup_vsx(current);
353 EXPORT_SYMBOL(enable_kernel_vsx);
355 void flush_vsx_to_thread(struct task_struct *tsk)
357 if (tsk->thread.regs) {
359 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
360 BUG_ON(tsk != current);
366 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
367 #endif /* CONFIG_VSX */
370 void giveup_spe(struct task_struct *tsk)
372 check_if_tm_restore_required(tsk);
374 msr_check_and_set(MSR_SPE);
376 msr_check_and_clear(MSR_SPE);
378 EXPORT_SYMBOL(giveup_spe);
380 void enable_kernel_spe(void)
382 WARN_ON(preemptible());
384 msr_check_and_set(MSR_SPE);
386 if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
387 check_if_tm_restore_required(current);
388 __giveup_spe(current);
391 EXPORT_SYMBOL(enable_kernel_spe);
393 void flush_spe_to_thread(struct task_struct *tsk)
395 if (tsk->thread.regs) {
397 if (tsk->thread.regs->msr & MSR_SPE) {
398 BUG_ON(tsk != current);
399 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
405 #endif /* CONFIG_SPE */
407 static unsigned long msr_all_available;
409 static int __init init_msr_all_available(void)
411 if (IS_ENABLED(CONFIG_PPC_FPU))
412 msr_all_available |= MSR_FP;
413 if (cpu_has_feature(CPU_FTR_ALTIVEC))
414 msr_all_available |= MSR_VEC;
415 if (cpu_has_feature(CPU_FTR_VSX))
416 msr_all_available |= MSR_VSX;
417 if (cpu_has_feature(CPU_FTR_SPE))
418 msr_all_available |= MSR_SPE;
422 early_initcall(init_msr_all_available);
424 void giveup_all(struct task_struct *tsk)
426 unsigned long usermsr;
428 if (!tsk->thread.regs)
431 check_if_tm_restore_required(tsk);
433 usermsr = tsk->thread.regs->msr;
435 if ((usermsr & msr_all_available) == 0)
438 msr_check_and_set(msr_all_available);
440 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
442 if (usermsr & MSR_FP)
444 if (usermsr & MSR_VEC)
445 __giveup_altivec(tsk);
446 if (usermsr & MSR_SPE)
449 msr_check_and_clear(msr_all_available);
451 EXPORT_SYMBOL(giveup_all);
453 #ifdef CONFIG_PPC_BOOK3S_64
454 #ifdef CONFIG_PPC_FPU
455 static bool should_restore_fp(void)
457 if (current->thread.load_fp) {
458 current->thread.load_fp++;
464 static void do_restore_fp(void)
466 load_fp_state(¤t->thread.fp_state);
469 static bool should_restore_fp(void) { return false; }
470 static void do_restore_fp(void) { }
471 #endif /* CONFIG_PPC_FPU */
473 #ifdef CONFIG_ALTIVEC
474 static bool should_restore_altivec(void)
476 if (cpu_has_feature(CPU_FTR_ALTIVEC) && (current->thread.load_vec)) {
477 current->thread.load_vec++;
483 static void do_restore_altivec(void)
485 load_vr_state(¤t->thread.vr_state);
486 current->thread.used_vr = 1;
489 static bool should_restore_altivec(void) { return false; }
490 static void do_restore_altivec(void) { }
491 #endif /* CONFIG_ALTIVEC */
493 static bool should_restore_vsx(void)
495 if (cpu_has_feature(CPU_FTR_VSX))
500 static void do_restore_vsx(void)
502 current->thread.used_vsr = 1;
505 static void do_restore_vsx(void) { }
506 #endif /* CONFIG_VSX */
509 * The exception exit path calls restore_math() with interrupts hard disabled
510 * but the soft irq state not "reconciled". ftrace code that calls
511 * local_irq_save/restore causes warnings.
513 * Rather than complicate the exit path, just don't trace restore_math. This
514 * could be done by having ftrace entry code check for this un-reconciled
515 * condition where MSR[EE]=0 and PACA_IRQ_HARD_DIS is not set, and
516 * temporarily fix it up for the duration of the ftrace call.
518 void notrace restore_math(struct pt_regs *regs)
521 unsigned long new_msr = 0;
526 * new_msr tracks the facilities that are to be restored. Only reload
527 * if the bit is not set in the user MSR (if it is set, the registers
528 * are live for the user thread).
530 if ((!(msr & MSR_FP)) && should_restore_fp())
533 if ((!(msr & MSR_VEC)) && should_restore_altivec())
536 if ((!(msr & MSR_VSX)) && should_restore_vsx()) {
537 if (((msr | new_msr) & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC))
542 unsigned long fpexc_mode = 0;
544 msr_check_and_set(new_msr);
546 if (new_msr & MSR_FP) {
549 // This also covers VSX, because VSX implies FP
550 fpexc_mode = current->thread.fpexc_mode;
553 if (new_msr & MSR_VEC)
554 do_restore_altivec();
556 if (new_msr & MSR_VSX)
559 msr_check_and_clear(new_msr);
561 regs->msr |= new_msr | fpexc_mode;
564 #endif /* CONFIG_PPC_BOOK3S_64 */
566 static void save_all(struct task_struct *tsk)
568 unsigned long usermsr;
570 if (!tsk->thread.regs)
573 usermsr = tsk->thread.regs->msr;
575 if ((usermsr & msr_all_available) == 0)
578 msr_check_and_set(msr_all_available);
580 WARN_ON((usermsr & MSR_VSX) && !((usermsr & MSR_FP) && (usermsr & MSR_VEC)));
582 if (usermsr & MSR_FP)
585 if (usermsr & MSR_VEC)
588 if (usermsr & MSR_SPE)
591 msr_check_and_clear(msr_all_available);
592 thread_pkey_regs_save(&tsk->thread);
595 void flush_all_to_thread(struct task_struct *tsk)
597 if (tsk->thread.regs) {
599 BUG_ON(tsk != current);
601 if (tsk->thread.regs->msr & MSR_SPE)
602 tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
609 EXPORT_SYMBOL(flush_all_to_thread);
611 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
612 void do_send_trap(struct pt_regs *regs, unsigned long address,
613 unsigned long error_code, int breakpt)
615 current->thread.trap_nr = TRAP_HWBKPT;
616 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
617 11, SIGSEGV) == NOTIFY_STOP)
620 /* Deliver the signal to userspace */
621 force_sig_ptrace_errno_trap(breakpt, /* breakpoint or watchpoint id */
622 (void __user *)address);
624 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
626 static void do_break_handler(struct pt_regs *regs)
628 struct arch_hw_breakpoint null_brk = {0};
629 struct arch_hw_breakpoint *info;
630 struct ppc_inst instr = ppc_inst(0);
637 * If underneath hw supports only one watchpoint, we know it
638 * caused exception. 8xx also falls into this category.
640 if (nr_wp_slots() == 1) {
641 __set_breakpoint(0, &null_brk);
642 current->thread.hw_brk[0] = null_brk;
643 current->thread.hw_brk[0].flags |= HW_BRK_FLAG_DISABLED;
647 /* Otherwise findout which DAWR caused exception and disable it. */
648 wp_get_instr_detail(regs, &instr, &type, &size, &ea);
650 for (i = 0; i < nr_wp_slots(); i++) {
651 info = ¤t->thread.hw_brk[i];
655 if (wp_check_constraints(regs, instr, ea, type, size, info)) {
656 __set_breakpoint(i, &null_brk);
657 current->thread.hw_brk[i] = null_brk;
658 current->thread.hw_brk[i].flags |= HW_BRK_FLAG_DISABLED;
663 void do_break (struct pt_regs *regs, unsigned long address,
664 unsigned long error_code)
666 current->thread.trap_nr = TRAP_HWBKPT;
667 if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
668 11, SIGSEGV) == NOTIFY_STOP)
671 if (debugger_break_match(regs))
675 * We reach here only when watchpoint exception is generated by ptrace
676 * event (or hw is buggy!). Now if CONFIG_HAVE_HW_BREAKPOINT is set,
677 * watchpoint is already handled by hw_breakpoint_handler() so we don't
678 * have to do anything. But when CONFIG_HAVE_HW_BREAKPOINT is not set,
679 * we need to manually handle the watchpoint here.
681 if (!IS_ENABLED(CONFIG_HAVE_HW_BREAKPOINT))
682 do_break_handler(regs);
684 /* Deliver the signal to userspace */
685 force_sig_fault(SIGTRAP, TRAP_HWBKPT, (void __user *)address);
687 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
689 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk[HBP_NUM_MAX]);
691 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
693 * Set the debug registers back to their default "safe" values.
695 static void set_debug_reg_defaults(struct thread_struct *thread)
697 thread->debug.iac1 = thread->debug.iac2 = 0;
698 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
699 thread->debug.iac3 = thread->debug.iac4 = 0;
701 thread->debug.dac1 = thread->debug.dac2 = 0;
702 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
703 thread->debug.dvc1 = thread->debug.dvc2 = 0;
705 thread->debug.dbcr0 = 0;
708 * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
710 thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
711 DBCR1_IAC3US | DBCR1_IAC4US;
713 * Force Data Address Compare User/Supervisor bits to be User-only
714 * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
716 thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
718 thread->debug.dbcr1 = 0;
722 static void prime_debug_regs(struct debug_reg *debug)
725 * We could have inherited MSR_DE from userspace, since
726 * it doesn't get cleared on exception entry. Make sure
727 * MSR_DE is clear before we enable any debug events.
729 mtmsr(mfmsr() & ~MSR_DE);
731 mtspr(SPRN_IAC1, debug->iac1);
732 mtspr(SPRN_IAC2, debug->iac2);
733 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
734 mtspr(SPRN_IAC3, debug->iac3);
735 mtspr(SPRN_IAC4, debug->iac4);
737 mtspr(SPRN_DAC1, debug->dac1);
738 mtspr(SPRN_DAC2, debug->dac2);
739 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
740 mtspr(SPRN_DVC1, debug->dvc1);
741 mtspr(SPRN_DVC2, debug->dvc2);
743 mtspr(SPRN_DBCR0, debug->dbcr0);
744 mtspr(SPRN_DBCR1, debug->dbcr1);
746 mtspr(SPRN_DBCR2, debug->dbcr2);
750 * Unless neither the old or new thread are making use of the
751 * debug registers, set the debug registers from the values
752 * stored in the new thread.
754 void switch_booke_debug_regs(struct debug_reg *new_debug)
756 if ((current->thread.debug.dbcr0 & DBCR0_IDM)
757 || (new_debug->dbcr0 & DBCR0_IDM))
758 prime_debug_regs(new_debug);
760 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
761 #else /* !CONFIG_PPC_ADV_DEBUG_REGS */
762 #ifndef CONFIG_HAVE_HW_BREAKPOINT
763 static void set_breakpoint(int i, struct arch_hw_breakpoint *brk)
766 __set_breakpoint(i, brk);
770 static void set_debug_reg_defaults(struct thread_struct *thread)
773 struct arch_hw_breakpoint null_brk = {0};
775 for (i = 0; i < nr_wp_slots(); i++) {
776 thread->hw_brk[i] = null_brk;
777 if (ppc_breakpoint_available())
778 set_breakpoint(i, &thread->hw_brk[i]);
782 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
783 struct arch_hw_breakpoint *b)
785 if (a->address != b->address)
787 if (a->type != b->type)
789 if (a->len != b->len)
791 /* no need to check hw_len. it's calculated from address and len */
795 static void switch_hw_breakpoint(struct task_struct *new)
799 for (i = 0; i < nr_wp_slots(); i++) {
800 if (likely(hw_brk_match(this_cpu_ptr(¤t_brk[i]),
801 &new->thread.hw_brk[i])))
804 __set_breakpoint(i, &new->thread.hw_brk[i]);
807 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
808 #endif /* CONFIG_PPC_ADV_DEBUG_REGS */
810 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
811 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
813 mtspr(SPRN_DAC1, dabr);
814 if (IS_ENABLED(CONFIG_PPC_47x))
818 #elif defined(CONFIG_PPC_BOOK3S)
819 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
821 mtspr(SPRN_DABR, dabr);
822 if (cpu_has_feature(CPU_FTR_DABRX))
823 mtspr(SPRN_DABRX, dabrx);
827 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
833 static inline int set_dabr(struct arch_hw_breakpoint *brk)
835 unsigned long dabr, dabrx;
837 dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
838 dabrx = ((brk->type >> 3) & 0x7);
841 return ppc_md.set_dabr(dabr, dabrx);
843 return __set_dabr(dabr, dabrx);
846 static inline int set_breakpoint_8xx(struct arch_hw_breakpoint *brk)
848 unsigned long lctrl1 = LCTRL1_CTE_GT | LCTRL1_CTF_LT | LCTRL1_CRWE_RW |
850 unsigned long lctrl2 = LCTRL2_LW0EN | LCTRL2_LW0LADC | LCTRL2_SLW0EN;
851 unsigned long start_addr = ALIGN_DOWN(brk->address, HW_BREAKPOINT_SIZE);
852 unsigned long end_addr = ALIGN(brk->address + brk->len, HW_BREAKPOINT_SIZE);
855 lctrl2 |= LCTRL2_LW0LA_F;
856 else if (end_addr == 0)
857 lctrl2 |= LCTRL2_LW0LA_E;
859 lctrl2 |= LCTRL2_LW0LA_EandF;
861 mtspr(SPRN_LCTRL2, 0);
863 if ((brk->type & HW_BRK_TYPE_RDWR) == 0)
866 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_READ)
867 lctrl1 |= LCTRL1_CRWE_RO | LCTRL1_CRWF_RO;
868 if ((brk->type & HW_BRK_TYPE_RDWR) == HW_BRK_TYPE_WRITE)
869 lctrl1 |= LCTRL1_CRWE_WO | LCTRL1_CRWF_WO;
871 mtspr(SPRN_CMPE, start_addr - 1);
872 mtspr(SPRN_CMPF, end_addr);
873 mtspr(SPRN_LCTRL1, lctrl1);
874 mtspr(SPRN_LCTRL2, lctrl2);
879 void __set_breakpoint(int nr, struct arch_hw_breakpoint *brk)
881 memcpy(this_cpu_ptr(¤t_brk[nr]), brk, sizeof(*brk));
886 else if (IS_ENABLED(CONFIG_PPC_8xx))
887 set_breakpoint_8xx(brk);
888 else if (!cpu_has_feature(CPU_FTR_ARCH_207S))
892 // Shouldn't happen due to higher level checks
896 /* Check if we have DAWR or DABR hardware */
897 bool ppc_breakpoint_available(void)
900 return true; /* POWER8 DAWR or POWER9 forced DAWR */
901 if (cpu_has_feature(CPU_FTR_ARCH_207S))
902 return false; /* POWER9 with DAWR disabled */
903 /* DABR: Everything but POWER8 and POWER9 */
906 EXPORT_SYMBOL_GPL(ppc_breakpoint_available);
908 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
910 static inline bool tm_enabled(struct task_struct *tsk)
912 return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
915 static void tm_reclaim_thread(struct thread_struct *thr, uint8_t cause)
918 * Use the current MSR TM suspended bit to track if we have
919 * checkpointed state outstanding.
920 * On signal delivery, we'd normally reclaim the checkpointed
921 * state to obtain stack pointer (see:get_tm_stackpointer()).
922 * This will then directly return to userspace without going
923 * through __switch_to(). However, if the stack frame is bad,
924 * we need to exit this thread which calls __switch_to() which
925 * will again attempt to reclaim the already saved tm state.
926 * Hence we need to check that we've not already reclaimed
928 * We do this using the current MSR, rather tracking it in
929 * some specific thread_struct bit, as it has the additional
930 * benefit of checking for a potential TM bad thing exception.
932 if (!MSR_TM_SUSPENDED(mfmsr()))
935 giveup_all(container_of(thr, struct task_struct, thread));
937 tm_reclaim(thr, cause);
940 * If we are in a transaction and FP is off then we can't have
941 * used FP inside that transaction. Hence the checkpointed
942 * state is the same as the live state. We need to copy the
943 * live state to the checkpointed state so that when the
944 * transaction is restored, the checkpointed state is correct
945 * and the aborted transaction sees the correct state. We use
946 * ckpt_regs.msr here as that's what tm_reclaim will use to
947 * determine if it's going to write the checkpointed state or
948 * not. So either this will write the checkpointed registers,
949 * or reclaim will. Similarly for VMX.
951 if ((thr->ckpt_regs.msr & MSR_FP) == 0)
952 memcpy(&thr->ckfp_state, &thr->fp_state,
953 sizeof(struct thread_fp_state));
954 if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
955 memcpy(&thr->ckvr_state, &thr->vr_state,
956 sizeof(struct thread_vr_state));
959 void tm_reclaim_current(uint8_t cause)
962 tm_reclaim_thread(¤t->thread, cause);
965 static inline void tm_reclaim_task(struct task_struct *tsk)
967 /* We have to work out if we're switching from/to a task that's in the
968 * middle of a transaction.
970 * In switching we need to maintain a 2nd register state as
971 * oldtask->thread.ckpt_regs. We tm_reclaim(oldproc); this saves the
972 * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
975 * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
977 struct thread_struct *thr = &tsk->thread;
982 if (!MSR_TM_ACTIVE(thr->regs->msr))
983 goto out_and_saveregs;
985 WARN_ON(tm_suspend_disabled);
987 TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
988 "ccr=%lx, msr=%lx, trap=%lx)\n",
989 tsk->pid, thr->regs->nip,
990 thr->regs->ccr, thr->regs->msr,
993 tm_reclaim_thread(thr, TM_CAUSE_RESCHED);
995 TM_DEBUG("--- tm_reclaim on pid %d complete\n",
999 /* Always save the regs here, even if a transaction's not active.
1000 * This context-switches a thread's TM info SPRs. We do it here to
1001 * be consistent with the restore path (in recheckpoint) which
1002 * cannot happen later in _switch().
1007 extern void __tm_recheckpoint(struct thread_struct *thread);
1009 void tm_recheckpoint(struct thread_struct *thread)
1011 unsigned long flags;
1013 if (!(thread->regs->msr & MSR_TM))
1016 /* We really can't be interrupted here as the TEXASR registers can't
1017 * change and later in the trecheckpoint code, we have a userspace R1.
1018 * So let's hard disable over this region.
1020 local_irq_save(flags);
1023 /* The TM SPRs are restored here, so that TEXASR.FS can be set
1024 * before the trecheckpoint and no explosion occurs.
1026 tm_restore_sprs(thread);
1028 __tm_recheckpoint(thread);
1030 local_irq_restore(flags);
1033 static inline void tm_recheckpoint_new_task(struct task_struct *new)
1035 if (!cpu_has_feature(CPU_FTR_TM))
1038 /* Recheckpoint the registers of the thread we're about to switch to.
1040 * If the task was using FP, we non-lazily reload both the original and
1041 * the speculative FP register states. This is because the kernel
1042 * doesn't see if/when a TM rollback occurs, so if we take an FP
1043 * unavailable later, we are unable to determine which set of FP regs
1044 * need to be restored.
1046 if (!tm_enabled(new))
1049 if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
1050 tm_restore_sprs(&new->thread);
1053 /* Recheckpoint to restore original checkpointed register state. */
1054 TM_DEBUG("*** tm_recheckpoint of pid %d (new->msr 0x%lx)\n",
1055 new->pid, new->thread.regs->msr);
1057 tm_recheckpoint(&new->thread);
1060 * The checkpointed state has been restored but the live state has
1061 * not, ensure all the math functionality is turned off to trigger
1062 * restore_math() to reload.
1064 new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
1066 TM_DEBUG("*** tm_recheckpoint of pid %d complete "
1067 "(kernel msr 0x%lx)\n",
1071 static inline void __switch_to_tm(struct task_struct *prev,
1072 struct task_struct *new)
1074 if (cpu_has_feature(CPU_FTR_TM)) {
1075 if (tm_enabled(prev) || tm_enabled(new))
1078 if (tm_enabled(prev)) {
1079 prev->thread.load_tm++;
1080 tm_reclaim_task(prev);
1081 if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
1082 prev->thread.regs->msr &= ~MSR_TM;
1085 tm_recheckpoint_new_task(new);
1090 * This is called if we are on the way out to userspace and the
1091 * TIF_RESTORE_TM flag is set. It checks if we need to reload
1092 * FP and/or vector state and does so if necessary.
1093 * If userspace is inside a transaction (whether active or
1094 * suspended) and FP/VMX/VSX instructions have ever been enabled
1095 * inside that transaction, then we have to keep them enabled
1096 * and keep the FP/VMX/VSX state loaded while ever the transaction
1097 * continues. The reason is that if we didn't, and subsequently
1098 * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1099 * we don't know whether it's the same transaction, and thus we
1100 * don't know which of the checkpointed state and the transactional
1103 void restore_tm_state(struct pt_regs *regs)
1105 unsigned long msr_diff;
1108 * This is the only moment we should clear TIF_RESTORE_TM as
1109 * it is here that ckpt_regs.msr and pt_regs.msr become the same
1110 * again, anything else could lead to an incorrect ckpt_msr being
1111 * saved and therefore incorrect signal contexts.
1113 clear_thread_flag(TIF_RESTORE_TM);
1114 if (!MSR_TM_ACTIVE(regs->msr))
1117 msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1118 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1120 /* Ensure that restore_math() will restore */
1121 if (msr_diff & MSR_FP)
1122 current->thread.load_fp = 1;
1123 #ifdef CONFIG_ALTIVEC
1124 if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1125 current->thread.load_vec = 1;
1129 regs->msr |= msr_diff;
1133 #define tm_recheckpoint_new_task(new)
1134 #define __switch_to_tm(prev, new)
1135 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1137 static inline void save_sprs(struct thread_struct *t)
1139 #ifdef CONFIG_ALTIVEC
1140 if (cpu_has_feature(CPU_FTR_ALTIVEC))
1141 t->vrsave = mfspr(SPRN_VRSAVE);
1143 #ifdef CONFIG_PPC_BOOK3S_64
1144 if (cpu_has_feature(CPU_FTR_DSCR))
1145 t->dscr = mfspr(SPRN_DSCR);
1147 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1148 t->bescr = mfspr(SPRN_BESCR);
1149 t->ebbhr = mfspr(SPRN_EBBHR);
1150 t->ebbrr = mfspr(SPRN_EBBRR);
1152 t->fscr = mfspr(SPRN_FSCR);
1155 * Note that the TAR is not available for use in the kernel.
1156 * (To provide this, the TAR should be backed up/restored on
1157 * exception entry/exit instead, and be in pt_regs. FIXME,
1158 * this should be in pt_regs anyway (for debug).)
1160 t->tar = mfspr(SPRN_TAR);
1164 thread_pkey_regs_save(t);
1167 static inline void restore_sprs(struct thread_struct *old_thread,
1168 struct thread_struct *new_thread)
1170 #ifdef CONFIG_ALTIVEC
1171 if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1172 old_thread->vrsave != new_thread->vrsave)
1173 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1175 #ifdef CONFIG_PPC_BOOK3S_64
1176 if (cpu_has_feature(CPU_FTR_DSCR)) {
1177 u64 dscr = get_paca()->dscr_default;
1178 if (new_thread->dscr_inherit)
1179 dscr = new_thread->dscr;
1181 if (old_thread->dscr != dscr)
1182 mtspr(SPRN_DSCR, dscr);
1185 if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1186 if (old_thread->bescr != new_thread->bescr)
1187 mtspr(SPRN_BESCR, new_thread->bescr);
1188 if (old_thread->ebbhr != new_thread->ebbhr)
1189 mtspr(SPRN_EBBHR, new_thread->ebbhr);
1190 if (old_thread->ebbrr != new_thread->ebbrr)
1191 mtspr(SPRN_EBBRR, new_thread->ebbrr);
1193 if (old_thread->fscr != new_thread->fscr)
1194 mtspr(SPRN_FSCR, new_thread->fscr);
1196 if (old_thread->tar != new_thread->tar)
1197 mtspr(SPRN_TAR, new_thread->tar);
1200 if (cpu_has_feature(CPU_FTR_P9_TIDR) &&
1201 old_thread->tidr != new_thread->tidr)
1202 mtspr(SPRN_TIDR, new_thread->tidr);
1205 thread_pkey_regs_restore(new_thread, old_thread);
1208 struct task_struct *__switch_to(struct task_struct *prev,
1209 struct task_struct *new)
1211 struct thread_struct *new_thread, *old_thread;
1212 struct task_struct *last;
1213 #ifdef CONFIG_PPC_BOOK3S_64
1214 struct ppc64_tlb_batch *batch;
1217 new_thread = &new->thread;
1218 old_thread = ¤t->thread;
1220 WARN_ON(!irqs_disabled());
1222 #ifdef CONFIG_PPC_BOOK3S_64
1223 batch = this_cpu_ptr(&ppc64_tlb_batch);
1224 if (batch->active) {
1225 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1227 __flush_tlb_pending(batch);
1232 * On POWER9 the copy-paste buffer can only paste into
1233 * foreign real addresses, so unprivileged processes can not
1234 * see the data or use it in any way unless they have
1235 * foreign real mappings. If the new process has the foreign
1236 * real address mappings, we must issue a cp_abort to clear
1237 * any state and prevent snooping, corruption or a covert
1238 * channel. ISA v3.1 supports paste into local memory.
1240 if (new->mm && (cpu_has_feature(CPU_FTR_ARCH_31) ||
1241 atomic_read(&new->mm->context.vas_windows)))
1242 asm volatile(PPC_CP_ABORT);
1243 #endif /* CONFIG_PPC_BOOK3S_64 */
1245 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1246 switch_booke_debug_regs(&new->thread.debug);
1249 * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1252 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1253 switch_hw_breakpoint(new);
1254 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1258 * We need to save SPRs before treclaim/trecheckpoint as these will
1259 * change a number of them.
1261 save_sprs(&prev->thread);
1263 /* Save FPU, Altivec, VSX and SPE state */
1266 __switch_to_tm(prev, new);
1268 if (!radix_enabled()) {
1270 * We can't take a PMU exception inside _switch() since there
1271 * is a window where the kernel stack SLB and the kernel stack
1272 * are out of sync. Hard disable here.
1278 * Call restore_sprs() before calling _switch(). If we move it after
1279 * _switch() then we miss out on calling it for new tasks. The reason
1280 * for this is we manually create a stack frame for new tasks that
1281 * directly returns through ret_from_fork() or
1282 * ret_from_kernel_thread(). See copy_thread() for details.
1284 restore_sprs(old_thread, new_thread);
1286 last = _switch(old_thread, new_thread);
1289 * Nothing after _switch will be run for newly created tasks,
1290 * because they switch directly to ret_from_fork/ret_from_kernel_thread
1291 * etc. Code added here should have a comment explaining why that is
1295 #ifdef CONFIG_PPC_BOOK3S_64
1297 * This applies to a process that was context switched while inside
1298 * arch_enter_lazy_mmu_mode(), to re-activate the batch that was
1299 * deactivated above, before _switch(). This will never be the case
1302 if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1303 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1304 batch = this_cpu_ptr(&ppc64_tlb_batch);
1309 * Math facilities are masked out of the child MSR in copy_thread.
1310 * A new task does not need to restore_math because it will
1311 * demand fault them.
1313 if (current->thread.regs)
1314 restore_math(current->thread.regs);
1315 #endif /* CONFIG_PPC_BOOK3S_64 */
1320 #define NR_INSN_TO_PRINT 16
1322 static void show_instructions(struct pt_regs *regs)
1325 unsigned long nip = regs->nip;
1326 unsigned long pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1328 printk("Instruction dump:");
1331 * If we were executing with the MMU off for instructions, adjust pc
1332 * rather than printing XXXXXXXX.
1334 if (!IS_ENABLED(CONFIG_BOOKE) && !(regs->msr & MSR_IR)) {
1335 pc = (unsigned long)phys_to_virt(pc);
1336 nip = (unsigned long)phys_to_virt(regs->nip);
1339 for (i = 0; i < NR_INSN_TO_PRINT; i++) {
1345 if (!__kernel_text_address(pc) ||
1346 get_kernel_nofault(instr, (const void *)pc)) {
1347 pr_cont("XXXXXXXX ");
1350 pr_cont("<%08x> ", instr);
1352 pr_cont("%08x ", instr);
1361 void show_user_instructions(struct pt_regs *regs)
1364 int n = NR_INSN_TO_PRINT;
1366 char buf[96]; /* enough for 8 times 9 + 2 chars */
1368 pc = regs->nip - (NR_INSN_TO_PRINT * 3 / 4 * sizeof(int));
1370 seq_buf_init(&s, buf, sizeof(buf));
1377 for (i = 0; i < 8 && n; i++, n--, pc += sizeof(int)) {
1380 if (copy_from_user_nofault(&instr, (void __user *)pc,
1382 seq_buf_printf(&s, "XXXXXXXX ");
1385 seq_buf_printf(&s, regs->nip == pc ? "<%08x> " : "%08x ", instr);
1388 if (!seq_buf_has_overflowed(&s))
1389 pr_info("%s[%d]: code: %s\n", current->comm,
1390 current->pid, s.buffer);
1399 static struct regbit msr_bits[] = {
1400 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1422 #ifndef CONFIG_BOOKE
1429 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1433 for (; bits->bit; ++bits)
1434 if (val & bits->bit) {
1435 pr_cont("%s%s", s, bits->name);
1440 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1441 static struct regbit msr_tm_bits[] = {
1448 static void print_tm_bits(unsigned long val)
1451 * This only prints something if at least one of the TM bit is set.
1452 * Inside the TM[], the output means:
1453 * E: Enabled (bit 32)
1454 * S: Suspended (bit 33)
1455 * T: Transactional (bit 34)
1457 if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1459 print_bits(val, msr_tm_bits, "");
1464 static void print_tm_bits(unsigned long val) {}
1467 static void print_msr_bits(unsigned long val)
1470 print_bits(val, msr_bits, ",");
1476 #define REG "%016lx"
1477 #define REGS_PER_LINE 4
1478 #define LAST_VOLATILE 13
1481 #define REGS_PER_LINE 8
1482 #define LAST_VOLATILE 12
1485 void show_regs(struct pt_regs * regs)
1489 show_regs_print_info(KERN_DEFAULT);
1491 printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1492 regs->nip, regs->link, regs->ctr);
1493 printk("REGS: %px TRAP: %04lx %s (%s)\n",
1494 regs, regs->trap, print_tainted(), init_utsname()->release);
1495 printk("MSR: "REG" ", regs->msr);
1496 print_msr_bits(regs->msr);
1497 pr_cont(" CR: %08lx XER: %08lx\n", regs->ccr, regs->xer);
1499 if (!trap_is_syscall(regs) && cpu_has_feature(CPU_FTR_CFAR))
1500 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1501 if (trap == 0x200 || trap == 0x300 || trap == 0x600) {
1502 if (IS_ENABLED(CONFIG_4xx) || IS_ENABLED(CONFIG_BOOKE))
1503 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1505 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1509 pr_cont("IRQMASK: %lx ", regs->softe);
1511 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1512 if (MSR_TM_ACTIVE(regs->msr))
1513 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1516 for (i = 0; i < 32; i++) {
1517 if ((i % REGS_PER_LINE) == 0)
1518 pr_cont("\nGPR%02d: ", i);
1519 pr_cont(REG " ", regs->gpr[i]);
1520 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1525 * Lookup NIP late so we have the best change of getting the
1526 * above info out without failing
1528 if (IS_ENABLED(CONFIG_KALLSYMS)) {
1529 printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1530 printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1532 show_stack(current, (unsigned long *) regs->gpr[1], KERN_DEFAULT);
1533 if (!user_mode(regs))
1534 show_instructions(regs);
1537 void flush_thread(void)
1539 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1540 flush_ptrace_hw_breakpoint(current);
1541 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1542 set_debug_reg_defaults(¤t->thread);
1543 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1546 #ifdef CONFIG_PPC_BOOK3S_64
1547 void arch_setup_new_exec(void)
1549 if (radix_enabled())
1551 hash__setup_new_exec();
1557 * Assign a TIDR (thread ID) for task @t and set it in the thread
1558 * structure. For now, we only support setting TIDR for 'current' task.
1560 * Since the TID value is a truncated form of it PID, it is possible
1561 * (but unlikely) for 2 threads to have the same TID. In the unlikely event
1562 * that 2 threads share the same TID and are waiting, one of the following
1563 * cases will happen:
1565 * 1. The correct thread is running, the wrong thread is not
1566 * In this situation, the correct thread is woken and proceeds to pass it's
1569 * 2. Neither threads are running
1570 * In this situation, neither thread will be woken. When scheduled, the waiting
1571 * threads will execute either a wait, which will return immediately, followed
1572 * by a condition check, which will pass for the correct thread and fail
1573 * for the wrong thread, or they will execute the condition check immediately.
1575 * 3. The wrong thread is running, the correct thread is not
1576 * The wrong thread will be woken, but will fail it's condition check and
1577 * re-execute wait. The correct thread, when scheduled, will execute either
1578 * it's condition check (which will pass), or wait, which returns immediately
1579 * when called the first time after the thread is scheduled, followed by it's
1580 * condition check (which will pass).
1582 * 4. Both threads are running
1583 * Both threads will be woken. The wrong thread will fail it's condition check
1584 * and execute another wait, while the correct thread will pass it's condition
1587 * @t: the task to set the thread ID for
1589 int set_thread_tidr(struct task_struct *t)
1591 if (!cpu_has_feature(CPU_FTR_P9_TIDR))
1600 t->thread.tidr = (u16)task_pid_nr(t);
1601 mtspr(SPRN_TIDR, t->thread.tidr);
1605 EXPORT_SYMBOL_GPL(set_thread_tidr);
1607 #endif /* CONFIG_PPC64 */
1610 release_thread(struct task_struct *t)
1615 * this gets called so that we can store coprocessor state into memory and
1616 * copy the current task into the new thread.
1618 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1620 flush_all_to_thread(src);
1622 * Flush TM state out so we can copy it. __switch_to_tm() does this
1623 * flush but it removes the checkpointed state from the current CPU and
1624 * transitions the CPU out of TM mode. Hence we need to call
1625 * tm_recheckpoint_new_task() (on the same task) to restore the
1626 * checkpointed state back and the TM mode.
1628 * Can't pass dst because it isn't ready. Doesn't matter, passing
1629 * dst is only important for __switch_to()
1631 __switch_to_tm(src, src);
1635 clear_task_ebb(dst);
1640 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1642 #ifdef CONFIG_PPC_BOOK3S_64
1643 unsigned long sp_vsid;
1644 unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1646 if (radix_enabled())
1649 if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1650 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1651 << SLB_VSID_SHIFT_1T;
1653 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1655 sp_vsid |= SLB_VSID_KERNEL | llp;
1656 p->thread.ksp_vsid = sp_vsid;
1665 * Copy architecture-specific thread state
1667 int copy_thread(unsigned long clone_flags, unsigned long usp,
1668 unsigned long kthread_arg, struct task_struct *p,
1671 struct pt_regs *childregs, *kregs;
1672 extern void ret_from_fork(void);
1673 extern void ret_from_fork_scv(void);
1674 extern void ret_from_kernel_thread(void);
1676 unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1677 struct thread_info *ti = task_thread_info(p);
1678 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1682 klp_init_thread_info(p);
1684 /* Copy registers */
1685 sp -= sizeof(struct pt_regs);
1686 childregs = (struct pt_regs *) sp;
1687 if (unlikely(p->flags & (PF_KTHREAD | PF_IO_WORKER))) {
1689 memset(childregs, 0, sizeof(struct pt_regs));
1690 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1693 childregs->gpr[14] = ppc_function_entry((void *)usp);
1695 clear_tsk_thread_flag(p, TIF_32BIT);
1696 childregs->softe = IRQS_ENABLED;
1698 childregs->gpr[15] = kthread_arg;
1699 p->thread.regs = NULL; /* no user register state */
1700 ti->flags |= _TIF_RESTOREALL;
1701 f = ret_from_kernel_thread;
1704 struct pt_regs *regs = current_pt_regs();
1705 CHECK_FULL_REGS(regs);
1708 childregs->gpr[1] = usp;
1709 p->thread.regs = childregs;
1710 /* 64s sets this in ret_from_fork */
1711 if (!IS_ENABLED(CONFIG_PPC_BOOK3S_64))
1712 childregs->gpr[3] = 0; /* Result from fork() */
1713 if (clone_flags & CLONE_SETTLS) {
1714 if (!is_32bit_task())
1715 childregs->gpr[13] = tls;
1717 childregs->gpr[2] = tls;
1720 if (trap_is_scv(regs))
1721 f = ret_from_fork_scv;
1725 childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1726 sp -= STACK_FRAME_OVERHEAD;
1729 * The way this works is that at some point in the future
1730 * some task will call _switch to switch to the new task.
1731 * That will pop off the stack frame created below and start
1732 * the new task running at ret_from_fork. The new task will
1733 * do some house keeping and then return from the fork or clone
1734 * system call, using the stack frame created above.
1736 ((unsigned long *)sp)[0] = 0;
1737 sp -= sizeof(struct pt_regs);
1738 kregs = (struct pt_regs *) sp;
1739 sp -= STACK_FRAME_OVERHEAD;
1742 p->thread.ksp_limit = (unsigned long)end_of_stack(p);
1744 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1745 for (i = 0; i < nr_wp_slots(); i++)
1746 p->thread.ptrace_bps[i] = NULL;
1749 p->thread.fp_save_area = NULL;
1750 #ifdef CONFIG_ALTIVEC
1751 p->thread.vr_save_area = NULL;
1754 setup_ksp_vsid(p, sp);
1757 if (cpu_has_feature(CPU_FTR_DSCR)) {
1758 p->thread.dscr_inherit = current->thread.dscr_inherit;
1759 p->thread.dscr = mfspr(SPRN_DSCR);
1761 if (cpu_has_feature(CPU_FTR_HAS_PPR))
1762 childregs->ppr = DEFAULT_PPR;
1766 kregs->nip = ppc_function_entry(f);
1770 void preload_new_slb_context(unsigned long start, unsigned long sp);
1773 * Set up a thread for executing a new program
1775 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1778 unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1780 if (IS_ENABLED(CONFIG_PPC_BOOK3S_64) && !radix_enabled())
1781 preload_new_slb_context(start, sp);
1785 * If we exec out of a kernel thread then thread.regs will not be
1788 if (!current->thread.regs) {
1789 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1790 current->thread.regs = regs - 1;
1793 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1795 * Clear any transactional state, we're exec()ing. The cause is
1796 * not important as there will never be a recheckpoint so it's not
1799 if (MSR_TM_SUSPENDED(mfmsr()))
1800 tm_reclaim_current(0);
1803 memset(®s->gpr[1], 0, sizeof(regs->gpr) - sizeof(regs->gpr[0]));
1811 * We have just cleared all the nonvolatile GPRs, so make
1812 * FULL_REGS(regs) return true. This is necessary to allow
1813 * ptrace to examine the thread immediately after exec.
1815 SET_FULL_REGS(regs);
1820 regs->msr = MSR_USER;
1822 if (!is_32bit_task()) {
1823 unsigned long entry;
1825 if (is_elf2_task()) {
1826 /* Look ma, no function descriptors! */
1831 * The latest iteration of the ABI requires that when
1832 * calling a function (at its global entry point),
1833 * the caller must ensure r12 holds the entry point
1834 * address (so that the function can quickly
1835 * establish addressability).
1837 regs->gpr[12] = start;
1838 /* Make sure that's restored on entry to userspace. */
1839 set_thread_flag(TIF_RESTOREALL);
1843 /* start is a relocated pointer to the function
1844 * descriptor for the elf _start routine. The first
1845 * entry in the function descriptor is the entry
1846 * address of _start and the second entry is the TOC
1847 * value we need to use.
1849 __get_user(entry, (unsigned long __user *)start);
1850 __get_user(toc, (unsigned long __user *)start+1);
1852 /* Check whether the e_entry function descriptor entries
1853 * need to be relocated before we can use them.
1855 if (load_addr != 0) {
1862 regs->msr = MSR_USER64;
1866 regs->msr = MSR_USER32;
1870 current->thread.used_vsr = 0;
1872 current->thread.load_slb = 0;
1873 current->thread.load_fp = 0;
1874 memset(¤t->thread.fp_state, 0, sizeof(current->thread.fp_state));
1875 current->thread.fp_save_area = NULL;
1876 #ifdef CONFIG_ALTIVEC
1877 memset(¤t->thread.vr_state, 0, sizeof(current->thread.vr_state));
1878 current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1879 current->thread.vr_save_area = NULL;
1880 current->thread.vrsave = 0;
1881 current->thread.used_vr = 0;
1882 current->thread.load_vec = 0;
1883 #endif /* CONFIG_ALTIVEC */
1885 memset(current->thread.evr, 0, sizeof(current->thread.evr));
1886 current->thread.acc = 0;
1887 current->thread.spefscr = 0;
1888 current->thread.used_spe = 0;
1889 #endif /* CONFIG_SPE */
1890 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1891 current->thread.tm_tfhar = 0;
1892 current->thread.tm_texasr = 0;
1893 current->thread.tm_tfiar = 0;
1894 current->thread.load_tm = 0;
1895 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1897 thread_pkey_regs_init(¤t->thread);
1899 EXPORT_SYMBOL(start_thread);
1901 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1902 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1904 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1906 struct pt_regs *regs = tsk->thread.regs;
1908 /* This is a bit hairy. If we are an SPE enabled processor
1909 * (have embedded fp) we store the IEEE exception enable flags in
1910 * fpexc_mode. fpexc_mode is also used for setting FP exception
1911 * mode (asyn, precise, disabled) for 'Classic' FP. */
1912 if (val & PR_FP_EXC_SW_ENABLE) {
1913 if (cpu_has_feature(CPU_FTR_SPE)) {
1915 * When the sticky exception bits are set
1916 * directly by userspace, it must call prctl
1917 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1918 * in the existing prctl settings) or
1919 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1920 * the bits being set). <fenv.h> functions
1921 * saving and restoring the whole
1922 * floating-point environment need to do so
1923 * anyway to restore the prctl settings from
1924 * the saved environment.
1927 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1928 tsk->thread.fpexc_mode = val &
1929 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1937 /* on a CONFIG_SPE this does not hurt us. The bits that
1938 * __pack_fe01 use do not overlap with bits used for
1939 * PR_FP_EXC_SW_ENABLE. Additionally, the MSR[FE0,FE1] bits
1940 * on CONFIG_SPE implementations are reserved so writing to
1941 * them does not change anything */
1942 if (val > PR_FP_EXC_PRECISE)
1944 tsk->thread.fpexc_mode = __pack_fe01(val);
1945 if (regs != NULL && (regs->msr & MSR_FP) != 0)
1946 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1947 | tsk->thread.fpexc_mode;
1951 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1953 unsigned int val = 0;
1955 if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE) {
1956 if (cpu_has_feature(CPU_FTR_SPE)) {
1958 * When the sticky exception bits are set
1959 * directly by userspace, it must call prctl
1960 * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1961 * in the existing prctl settings) or
1962 * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1963 * the bits being set). <fenv.h> functions
1964 * saving and restoring the whole
1965 * floating-point environment need to do so
1966 * anyway to restore the prctl settings from
1967 * the saved environment.
1970 tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1971 val = tsk->thread.fpexc_mode;
1976 val = __unpack_fe01(tsk->thread.fpexc_mode);
1978 return put_user(val, (unsigned int __user *) adr);
1981 int set_endian(struct task_struct *tsk, unsigned int val)
1983 struct pt_regs *regs = tsk->thread.regs;
1985 if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1986 (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1992 if (val == PR_ENDIAN_BIG)
1993 regs->msr &= ~MSR_LE;
1994 else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1995 regs->msr |= MSR_LE;
2002 int get_endian(struct task_struct *tsk, unsigned long adr)
2004 struct pt_regs *regs = tsk->thread.regs;
2007 if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
2008 !cpu_has_feature(CPU_FTR_REAL_LE))
2014 if (regs->msr & MSR_LE) {
2015 if (cpu_has_feature(CPU_FTR_REAL_LE))
2016 val = PR_ENDIAN_LITTLE;
2018 val = PR_ENDIAN_PPC_LITTLE;
2020 val = PR_ENDIAN_BIG;
2022 return put_user(val, (unsigned int __user *)adr);
2025 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
2027 tsk->thread.align_ctl = val;
2031 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
2033 return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
2036 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
2037 unsigned long nbytes)
2039 unsigned long stack_page;
2040 unsigned long cpu = task_cpu(p);
2042 stack_page = (unsigned long)hardirq_ctx[cpu];
2043 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2046 stack_page = (unsigned long)softirq_ctx[cpu];
2047 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2053 static inline int valid_emergency_stack(unsigned long sp, struct task_struct *p,
2054 unsigned long nbytes)
2057 unsigned long stack_page;
2058 unsigned long cpu = task_cpu(p);
2060 stack_page = (unsigned long)paca_ptrs[cpu]->emergency_sp - THREAD_SIZE;
2061 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2064 # ifdef CONFIG_PPC_BOOK3S_64
2065 stack_page = (unsigned long)paca_ptrs[cpu]->nmi_emergency_sp - THREAD_SIZE;
2066 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2069 stack_page = (unsigned long)paca_ptrs[cpu]->mc_emergency_sp - THREAD_SIZE;
2070 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2079 int validate_sp(unsigned long sp, struct task_struct *p,
2080 unsigned long nbytes)
2082 unsigned long stack_page = (unsigned long)task_stack_page(p);
2084 if (sp < THREAD_SIZE)
2087 if (sp >= stack_page && sp <= stack_page + THREAD_SIZE - nbytes)
2090 if (valid_irq_stack(sp, p, nbytes))
2093 return valid_emergency_stack(sp, p, nbytes);
2096 EXPORT_SYMBOL(validate_sp);
2098 static unsigned long __get_wchan(struct task_struct *p)
2100 unsigned long ip, sp;
2103 if (!p || p == current || p->state == TASK_RUNNING)
2107 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
2111 sp = READ_ONCE_NOCHECK(*(unsigned long *)sp);
2112 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD) ||
2113 p->state == TASK_RUNNING)
2116 ip = READ_ONCE_NOCHECK(((unsigned long *)sp)[STACK_FRAME_LR_SAVE]);
2117 if (!in_sched_functions(ip))
2120 } while (count++ < 16);
2124 unsigned long get_wchan(struct task_struct *p)
2128 if (!try_get_task_stack(p))
2131 ret = __get_wchan(p);
2138 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
2140 void show_stack(struct task_struct *tsk, unsigned long *stack,
2143 unsigned long sp, ip, lr, newsp;
2146 unsigned long ret_addr;
2152 if (!try_get_task_stack(tsk))
2155 sp = (unsigned long) stack;
2158 sp = current_stack_frame();
2160 sp = tsk->thread.ksp;
2164 printk("%sCall Trace:\n", loglvl);
2166 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
2169 stack = (unsigned long *) sp;
2171 ip = stack[STACK_FRAME_LR_SAVE];
2172 if (!firstframe || ip != lr) {
2173 printk("%s["REG"] ["REG"] %pS",
2174 loglvl, sp, ip, (void *)ip);
2175 ret_addr = ftrace_graph_ret_addr(current,
2176 &ftrace_idx, ip, stack);
2178 pr_cont(" (%pS)", (void *)ret_addr);
2180 pr_cont(" (unreliable)");
2186 * See if this is an exception frame.
2187 * We look for the "regshere" marker in the current frame.
2189 if (validate_sp(sp, tsk, STACK_FRAME_WITH_PT_REGS)
2190 && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
2191 struct pt_regs *regs = (struct pt_regs *)
2192 (sp + STACK_FRAME_OVERHEAD);
2194 printk("%s--- interrupt: %lx at %pS\n LR = %pS\n",
2196 (void *)regs->nip, (void *)lr);
2201 } while (count++ < kstack_depth_to_print);
2203 put_task_stack(tsk);
2207 /* Called with hard IRQs off */
2208 void notrace __ppc64_runlatch_on(void)
2210 struct thread_info *ti = current_thread_info();
2212 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2214 * Least significant bit (RUN) is the only writable bit of
2215 * the CTRL register, so we can avoid mfspr. 2.06 is not the
2216 * earliest ISA where this is the case, but it's convenient.
2218 mtspr(SPRN_CTRLT, CTRL_RUNLATCH);
2223 * Some architectures (e.g., Cell) have writable fields other
2224 * than RUN, so do the read-modify-write.
2226 ctrl = mfspr(SPRN_CTRLF);
2227 ctrl |= CTRL_RUNLATCH;
2228 mtspr(SPRN_CTRLT, ctrl);
2231 ti->local_flags |= _TLF_RUNLATCH;
2234 /* Called with hard IRQs off */
2235 void notrace __ppc64_runlatch_off(void)
2237 struct thread_info *ti = current_thread_info();
2239 ti->local_flags &= ~_TLF_RUNLATCH;
2241 if (cpu_has_feature(CPU_FTR_ARCH_206)) {
2242 mtspr(SPRN_CTRLT, 0);
2246 ctrl = mfspr(SPRN_CTRLF);
2247 ctrl &= ~CTRL_RUNLATCH;
2248 mtspr(SPRN_CTRLT, ctrl);
2251 #endif /* CONFIG_PPC64 */
2253 unsigned long arch_align_stack(unsigned long sp)
2255 if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
2256 sp -= get_random_int() & ~PAGE_MASK;
2260 static inline unsigned long brk_rnd(void)
2262 unsigned long rnd = 0;
2264 /* 8MB for 32bit, 1GB for 64bit */
2265 if (is_32bit_task())
2266 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
2268 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
2270 return rnd << PAGE_SHIFT;
2273 unsigned long arch_randomize_brk(struct mm_struct *mm)
2275 unsigned long base = mm->brk;
2278 #ifdef CONFIG_PPC_BOOK3S_64
2280 * If we are using 1TB segments and we are allowed to randomise
2281 * the heap, we can put it above 1TB so it is backed by a 1TB
2282 * segment. Otherwise the heap will be in the bottom 1TB
2283 * which always uses 256MB segments and this may result in a
2284 * performance penalty. We don't need to worry about radix. For
2285 * radix, mmu_highuser_ssize remains unchanged from 256MB.
2287 if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2288 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2291 ret = PAGE_ALIGN(base + brk_rnd());