GNU Linux-libre 4.4.297-gnu1
[releases.git] / arch / powerpc / kernel / process.c
1 /*
2  *  Derived from "arch/i386/kernel/process.c"
3  *    Copyright (C) 1995  Linus Torvalds
4  *
5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
6  *  Paul Mackerras (paulus@cs.anu.edu.au)
7  *
8  *  PowerPC version
9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
10  *
11  *  This program is free software; you can redistribute it and/or
12  *  modify it under the terms of the GNU General Public License
13  *  as published by the Free Software Foundation; either version
14  *  2 of the License, or (at your option) any later version.
15  */
16
17 #include <linux/errno.h>
18 #include <linux/sched.h>
19 #include <linux/kernel.h>
20 #include <linux/mm.h>
21 #include <linux/smp.h>
22 #include <linux/stddef.h>
23 #include <linux/unistd.h>
24 #include <linux/ptrace.h>
25 #include <linux/slab.h>
26 #include <linux/user.h>
27 #include <linux/elf.h>
28 #include <linux/prctl.h>
29 #include <linux/init_task.h>
30 #include <linux/export.h>
31 #include <linux/kallsyms.h>
32 #include <linux/mqueue.h>
33 #include <linux/hardirq.h>
34 #include <linux/utsname.h>
35 #include <linux/ftrace.h>
36 #include <linux/kernel_stat.h>
37 #include <linux/personality.h>
38 #include <linux/random.h>
39 #include <linux/hw_breakpoint.h>
40 #include <linux/uaccess.h>
41
42 #include <asm/pgtable.h>
43 #include <asm/io.h>
44 #include <asm/processor.h>
45 #include <asm/mmu.h>
46 #include <asm/prom.h>
47 #include <asm/machdep.h>
48 #include <asm/time.h>
49 #include <asm/runlatch.h>
50 #include <asm/syscalls.h>
51 #include <asm/switch_to.h>
52 #include <asm/tm.h>
53 #include <asm/debug.h>
54 #ifdef CONFIG_PPC64
55 #include <asm/firmware.h>
56 #endif
57 #include <asm/code-patching.h>
58 #include <linux/kprobes.h>
59 #include <linux/kdebug.h>
60
61 /* Transactional Memory debug */
62 #ifdef TM_DEBUG_SW
63 #define TM_DEBUG(x...) printk(KERN_INFO x)
64 #else
65 #define TM_DEBUG(x...) do { } while(0)
66 #endif
67
68 extern unsigned long _get_SP(void);
69
70 #ifndef CONFIG_SMP
71 struct task_struct *last_task_used_math = NULL;
72 struct task_struct *last_task_used_altivec = NULL;
73 struct task_struct *last_task_used_vsx = NULL;
74 struct task_struct *last_task_used_spe = NULL;
75 #endif
76
77 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
78 void giveup_fpu_maybe_transactional(struct task_struct *tsk)
79 {
80         /*
81          * If we are saving the current thread's registers, and the
82          * thread is in a transactional state, set the TIF_RESTORE_TM
83          * bit so that we know to restore the registers before
84          * returning to userspace.
85          */
86         if (tsk == current && tsk->thread.regs &&
87             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
88             !test_thread_flag(TIF_RESTORE_TM)) {
89                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
90                 set_thread_flag(TIF_RESTORE_TM);
91         }
92
93         giveup_fpu(tsk);
94 }
95
96 void giveup_altivec_maybe_transactional(struct task_struct *tsk)
97 {
98         /*
99          * If we are saving the current thread's registers, and the
100          * thread is in a transactional state, set the TIF_RESTORE_TM
101          * bit so that we know to restore the registers before
102          * returning to userspace.
103          */
104         if (tsk == current && tsk->thread.regs &&
105             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
106             !test_thread_flag(TIF_RESTORE_TM)) {
107                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
108                 set_thread_flag(TIF_RESTORE_TM);
109         }
110
111         giveup_altivec(tsk);
112 }
113
114 #else
115 #define giveup_fpu_maybe_transactional(tsk)     giveup_fpu(tsk)
116 #define giveup_altivec_maybe_transactional(tsk) giveup_altivec(tsk)
117 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
118
119 #ifdef CONFIG_PPC_FPU
120 /*
121  * Make sure the floating-point register state in the
122  * the thread_struct is up to date for task tsk.
123  */
124 void flush_fp_to_thread(struct task_struct *tsk)
125 {
126         if (tsk->thread.regs) {
127                 /*
128                  * We need to disable preemption here because if we didn't,
129                  * another process could get scheduled after the regs->msr
130                  * test but before we have finished saving the FP registers
131                  * to the thread_struct.  That process could take over the
132                  * FPU, and then when we get scheduled again we would store
133                  * bogus values for the remaining FP registers.
134                  */
135                 preempt_disable();
136                 if (tsk->thread.regs->msr & MSR_FP) {
137 #ifdef CONFIG_SMP
138                         /*
139                          * This should only ever be called for current or
140                          * for a stopped child process.  Since we save away
141                          * the FP register state on context switch on SMP,
142                          * there is something wrong if a stopped child appears
143                          * to still have its FP state in the CPU registers.
144                          */
145                         BUG_ON(tsk != current);
146 #endif
147                         giveup_fpu_maybe_transactional(tsk);
148                 }
149                 preempt_enable();
150         }
151 }
152 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
153 #endif /* CONFIG_PPC_FPU */
154
155 void enable_kernel_fp(void)
156 {
157         WARN_ON(preemptible());
158
159 #ifdef CONFIG_SMP
160         if (current->thread.regs && (current->thread.regs->msr & MSR_FP))
161                 giveup_fpu_maybe_transactional(current);
162         else
163                 giveup_fpu(NULL);       /* just enables FP for kernel */
164 #else
165         giveup_fpu_maybe_transactional(last_task_used_math);
166 #endif /* CONFIG_SMP */
167 }
168 EXPORT_SYMBOL(enable_kernel_fp);
169
170 #ifdef CONFIG_ALTIVEC
171 void enable_kernel_altivec(void)
172 {
173         WARN_ON(preemptible());
174
175 #ifdef CONFIG_SMP
176         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC))
177                 giveup_altivec_maybe_transactional(current);
178         else
179                 giveup_altivec_notask();
180 #else
181         giveup_altivec_maybe_transactional(last_task_used_altivec);
182 #endif /* CONFIG_SMP */
183 }
184 EXPORT_SYMBOL(enable_kernel_altivec);
185
186 /*
187  * Make sure the VMX/Altivec register state in the
188  * the thread_struct is up to date for task tsk.
189  */
190 void flush_altivec_to_thread(struct task_struct *tsk)
191 {
192         if (tsk->thread.regs) {
193                 preempt_disable();
194                 if (tsk->thread.regs->msr & MSR_VEC) {
195 #ifdef CONFIG_SMP
196                         BUG_ON(tsk != current);
197 #endif
198                         giveup_altivec_maybe_transactional(tsk);
199                 }
200                 preempt_enable();
201         }
202 }
203 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
204 #endif /* CONFIG_ALTIVEC */
205
206 #ifdef CONFIG_VSX
207 void enable_kernel_vsx(void)
208 {
209         WARN_ON(preemptible());
210
211 #ifdef CONFIG_SMP
212         if (current->thread.regs &&
213             (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)))
214                 giveup_vsx(current);
215         else
216                 giveup_vsx(NULL);       /* just enable vsx for kernel - force */
217 #else
218         giveup_vsx(last_task_used_vsx);
219 #endif /* CONFIG_SMP */
220 }
221 EXPORT_SYMBOL(enable_kernel_vsx);
222
223 void giveup_vsx(struct task_struct *tsk)
224 {
225         giveup_fpu_maybe_transactional(tsk);
226         giveup_altivec_maybe_transactional(tsk);
227         __giveup_vsx(tsk);
228 }
229 EXPORT_SYMBOL(giveup_vsx);
230
231 void flush_vsx_to_thread(struct task_struct *tsk)
232 {
233         if (tsk->thread.regs) {
234                 preempt_disable();
235                 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
236 #ifdef CONFIG_SMP
237                         BUG_ON(tsk != current);
238 #endif
239                         giveup_vsx(tsk);
240                 }
241                 preempt_enable();
242         }
243 }
244 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
245 #endif /* CONFIG_VSX */
246
247 #ifdef CONFIG_SPE
248
249 void enable_kernel_spe(void)
250 {
251         WARN_ON(preemptible());
252
253 #ifdef CONFIG_SMP
254         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE))
255                 giveup_spe(current);
256         else
257                 giveup_spe(NULL);       /* just enable SPE for kernel - force */
258 #else
259         giveup_spe(last_task_used_spe);
260 #endif /* __SMP __ */
261 }
262 EXPORT_SYMBOL(enable_kernel_spe);
263
264 void flush_spe_to_thread(struct task_struct *tsk)
265 {
266         if (tsk->thread.regs) {
267                 preempt_disable();
268                 if (tsk->thread.regs->msr & MSR_SPE) {
269 #ifdef CONFIG_SMP
270                         BUG_ON(tsk != current);
271 #endif
272                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
273                         giveup_spe(tsk);
274                 }
275                 preempt_enable();
276         }
277 }
278 #endif /* CONFIG_SPE */
279
280 #ifndef CONFIG_SMP
281 /*
282  * If we are doing lazy switching of CPU state (FP, altivec or SPE),
283  * and the current task has some state, discard it.
284  */
285 void discard_lazy_cpu_state(void)
286 {
287         preempt_disable();
288         if (last_task_used_math == current)
289                 last_task_used_math = NULL;
290 #ifdef CONFIG_ALTIVEC
291         if (last_task_used_altivec == current)
292                 last_task_used_altivec = NULL;
293 #endif /* CONFIG_ALTIVEC */
294 #ifdef CONFIG_VSX
295         if (last_task_used_vsx == current)
296                 last_task_used_vsx = NULL;
297 #endif /* CONFIG_VSX */
298 #ifdef CONFIG_SPE
299         if (last_task_used_spe == current)
300                 last_task_used_spe = NULL;
301 #endif
302         preempt_enable();
303 }
304 #endif /* CONFIG_SMP */
305
306 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
307 void do_send_trap(struct pt_regs *regs, unsigned long address,
308                   unsigned long error_code, int signal_code, int breakpt)
309 {
310         siginfo_t info;
311
312         current->thread.trap_nr = signal_code;
313         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
314                         11, SIGSEGV) == NOTIFY_STOP)
315                 return;
316
317         /* Deliver the signal to userspace */
318         info.si_signo = SIGTRAP;
319         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
320         info.si_code = signal_code;
321         info.si_addr = (void __user *)address;
322         force_sig_info(SIGTRAP, &info, current);
323 }
324 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
325 void do_break (struct pt_regs *regs, unsigned long address,
326                     unsigned long error_code)
327 {
328         siginfo_t info;
329
330         current->thread.trap_nr = TRAP_HWBKPT;
331         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
332                         11, SIGSEGV) == NOTIFY_STOP)
333                 return;
334
335         if (debugger_break_match(regs))
336                 return;
337
338         /* Clear the breakpoint */
339         hw_breakpoint_disable();
340
341         /* Deliver the signal to userspace */
342         info.si_signo = SIGTRAP;
343         info.si_errno = 0;
344         info.si_code = TRAP_HWBKPT;
345         info.si_addr = (void __user *)address;
346         force_sig_info(SIGTRAP, &info, current);
347 }
348 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
349
350 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
351
352 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
353 /*
354  * Set the debug registers back to their default "safe" values.
355  */
356 static void set_debug_reg_defaults(struct thread_struct *thread)
357 {
358         thread->debug.iac1 = thread->debug.iac2 = 0;
359 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
360         thread->debug.iac3 = thread->debug.iac4 = 0;
361 #endif
362         thread->debug.dac1 = thread->debug.dac2 = 0;
363 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
364         thread->debug.dvc1 = thread->debug.dvc2 = 0;
365 #endif
366         thread->debug.dbcr0 = 0;
367 #ifdef CONFIG_BOOKE
368         /*
369          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
370          */
371         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
372                         DBCR1_IAC3US | DBCR1_IAC4US;
373         /*
374          * Force Data Address Compare User/Supervisor bits to be User-only
375          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
376          */
377         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
378 #else
379         thread->debug.dbcr1 = 0;
380 #endif
381 }
382
383 static void prime_debug_regs(struct debug_reg *debug)
384 {
385         /*
386          * We could have inherited MSR_DE from userspace, since
387          * it doesn't get cleared on exception entry.  Make sure
388          * MSR_DE is clear before we enable any debug events.
389          */
390         mtmsr(mfmsr() & ~MSR_DE);
391
392         mtspr(SPRN_IAC1, debug->iac1);
393         mtspr(SPRN_IAC2, debug->iac2);
394 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
395         mtspr(SPRN_IAC3, debug->iac3);
396         mtspr(SPRN_IAC4, debug->iac4);
397 #endif
398         mtspr(SPRN_DAC1, debug->dac1);
399         mtspr(SPRN_DAC2, debug->dac2);
400 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
401         mtspr(SPRN_DVC1, debug->dvc1);
402         mtspr(SPRN_DVC2, debug->dvc2);
403 #endif
404         mtspr(SPRN_DBCR0, debug->dbcr0);
405         mtspr(SPRN_DBCR1, debug->dbcr1);
406 #ifdef CONFIG_BOOKE
407         mtspr(SPRN_DBCR2, debug->dbcr2);
408 #endif
409 }
410 /*
411  * Unless neither the old or new thread are making use of the
412  * debug registers, set the debug registers from the values
413  * stored in the new thread.
414  */
415 void switch_booke_debug_regs(struct debug_reg *new_debug)
416 {
417         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
418                 || (new_debug->dbcr0 & DBCR0_IDM))
419                         prime_debug_regs(new_debug);
420 }
421 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
422 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
423 #ifndef CONFIG_HAVE_HW_BREAKPOINT
424 static void set_debug_reg_defaults(struct thread_struct *thread)
425 {
426         thread->hw_brk.address = 0;
427         thread->hw_brk.type = 0;
428         set_breakpoint(&thread->hw_brk);
429 }
430 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
431 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
432
433 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
434 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
435 {
436         mtspr(SPRN_DAC1, dabr);
437 #ifdef CONFIG_PPC_47x
438         isync();
439 #endif
440         return 0;
441 }
442 #elif defined(CONFIG_PPC_BOOK3S)
443 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
444 {
445         mtspr(SPRN_DABR, dabr);
446         if (cpu_has_feature(CPU_FTR_DABRX))
447                 mtspr(SPRN_DABRX, dabrx);
448         return 0;
449 }
450 #else
451 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
452 {
453         return -EINVAL;
454 }
455 #endif
456
457 static inline int set_dabr(struct arch_hw_breakpoint *brk)
458 {
459         unsigned long dabr, dabrx;
460
461         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
462         dabrx = ((brk->type >> 3) & 0x7);
463
464         if (ppc_md.set_dabr)
465                 return ppc_md.set_dabr(dabr, dabrx);
466
467         return __set_dabr(dabr, dabrx);
468 }
469
470 static inline int set_dawr(struct arch_hw_breakpoint *brk)
471 {
472         unsigned long dawr, dawrx, mrd;
473
474         dawr = brk->address;
475
476         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
477                                    << (63 - 58); //* read/write bits */
478         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
479                                    << (63 - 59); //* translate */
480         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
481                                    >> 3; //* PRIM bits */
482         /* dawr length is stored in field MDR bits 48:53.  Matches range in
483            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
484            0b111111=64DW.
485            brk->len is in bytes.
486            This aligns up to double word size, shifts and does the bias.
487         */
488         mrd = ((brk->len + 7) >> 3) - 1;
489         dawrx |= (mrd & 0x3f) << (63 - 53);
490
491         if (ppc_md.set_dawr)
492                 return ppc_md.set_dawr(dawr, dawrx);
493         mtspr(SPRN_DAWR, dawr);
494         mtspr(SPRN_DAWRX, dawrx);
495         return 0;
496 }
497
498 void __set_breakpoint(struct arch_hw_breakpoint *brk)
499 {
500         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
501
502         if (cpu_has_feature(CPU_FTR_DAWR))
503                 set_dawr(brk);
504         else
505                 set_dabr(brk);
506 }
507
508 void set_breakpoint(struct arch_hw_breakpoint *brk)
509 {
510         preempt_disable();
511         __set_breakpoint(brk);
512         preempt_enable();
513 }
514
515 #ifdef CONFIG_PPC64
516 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
517 #endif
518
519 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
520                               struct arch_hw_breakpoint *b)
521 {
522         if (a->address != b->address)
523                 return false;
524         if (a->type != b->type)
525                 return false;
526         if (a->len != b->len)
527                 return false;
528         return true;
529 }
530
531 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
532 static void tm_reclaim_thread(struct thread_struct *thr,
533                               struct thread_info *ti, uint8_t cause)
534 {
535         unsigned long msr_diff = 0;
536
537         /*
538          * If FP/VSX registers have been already saved to the
539          * thread_struct, move them to the transact_fp array.
540          * We clear the TIF_RESTORE_TM bit since after the reclaim
541          * the thread will no longer be transactional.
542          */
543         if (test_ti_thread_flag(ti, TIF_RESTORE_TM)) {
544                 msr_diff = thr->ckpt_regs.msr & ~thr->regs->msr;
545                 if (msr_diff & MSR_FP)
546                         memcpy(&thr->transact_fp, &thr->fp_state,
547                                sizeof(struct thread_fp_state));
548                 if (msr_diff & MSR_VEC)
549                         memcpy(&thr->transact_vr, &thr->vr_state,
550                                sizeof(struct thread_vr_state));
551                 clear_ti_thread_flag(ti, TIF_RESTORE_TM);
552                 msr_diff &= MSR_FP | MSR_VEC | MSR_VSX | MSR_FE0 | MSR_FE1;
553         }
554
555         /*
556          * Use the current MSR TM suspended bit to track if we have
557          * checkpointed state outstanding.
558          * On signal delivery, we'd normally reclaim the checkpointed
559          * state to obtain stack pointer (see:get_tm_stackpointer()).
560          * This will then directly return to userspace without going
561          * through __switch_to(). However, if the stack frame is bad,
562          * we need to exit this thread which calls __switch_to() which
563          * will again attempt to reclaim the already saved tm state.
564          * Hence we need to check that we've not already reclaimed
565          * this state.
566          * We do this using the current MSR, rather tracking it in
567          * some specific thread_struct bit, as it has the additional
568          * benifit of checking for a potential TM bad thing exception.
569          */
570         if (!MSR_TM_SUSPENDED(mfmsr()))
571                 return;
572
573         tm_reclaim(thr, thr->regs->msr, cause);
574
575         /* Having done the reclaim, we now have the checkpointed
576          * FP/VSX values in the registers.  These might be valid
577          * even if we have previously called enable_kernel_fp() or
578          * flush_fp_to_thread(), so update thr->regs->msr to
579          * indicate their current validity.
580          */
581         thr->regs->msr |= msr_diff;
582 }
583
584 void tm_reclaim_current(uint8_t cause)
585 {
586         tm_enable();
587         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
588 }
589
590 static inline void tm_reclaim_task(struct task_struct *tsk)
591 {
592         /* We have to work out if we're switching from/to a task that's in the
593          * middle of a transaction.
594          *
595          * In switching we need to maintain a 2nd register state as
596          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
597          * checkpointed (tbegin) state in ckpt_regs and saves the transactional
598          * (current) FPRs into oldtask->thread.transact_fpr[].
599          *
600          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
601          */
602         struct thread_struct *thr = &tsk->thread;
603
604         if (!thr->regs)
605                 return;
606
607         if (!MSR_TM_ACTIVE(thr->regs->msr))
608                 goto out_and_saveregs;
609
610         /* Stash the original thread MSR, as giveup_fpu et al will
611          * modify it.  We hold onto it to see whether the task used
612          * FP & vector regs.  If the TIF_RESTORE_TM flag is set,
613          * ckpt_regs.msr is already set.
614          */
615         if (!test_ti_thread_flag(task_thread_info(tsk), TIF_RESTORE_TM))
616                 thr->ckpt_regs.msr = thr->regs->msr;
617
618         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
619                  "ccr=%lx, msr=%lx, trap=%lx)\n",
620                  tsk->pid, thr->regs->nip,
621                  thr->regs->ccr, thr->regs->msr,
622                  thr->regs->trap);
623
624         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
625
626         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
627                  tsk->pid);
628
629 out_and_saveregs:
630         /* Always save the regs here, even if a transaction's not active.
631          * This context-switches a thread's TM info SPRs.  We do it here to
632          * be consistent with the restore path (in recheckpoint) which
633          * cannot happen later in _switch().
634          */
635         tm_save_sprs(thr);
636 }
637
638 extern void __tm_recheckpoint(struct thread_struct *thread,
639                               unsigned long orig_msr);
640
641 void tm_recheckpoint(struct thread_struct *thread,
642                      unsigned long orig_msr)
643 {
644         unsigned long flags;
645
646         /* We really can't be interrupted here as the TEXASR registers can't
647          * change and later in the trecheckpoint code, we have a userspace R1.
648          * So let's hard disable over this region.
649          */
650         local_irq_save(flags);
651         hard_irq_disable();
652
653         /* The TM SPRs are restored here, so that TEXASR.FS can be set
654          * before the trecheckpoint and no explosion occurs.
655          */
656         tm_restore_sprs(thread);
657
658         __tm_recheckpoint(thread, orig_msr);
659
660         local_irq_restore(flags);
661 }
662
663 static inline void tm_recheckpoint_new_task(struct task_struct *new)
664 {
665         unsigned long msr;
666
667         if (!cpu_has_feature(CPU_FTR_TM))
668                 return;
669
670         /* Recheckpoint the registers of the thread we're about to switch to.
671          *
672          * If the task was using FP, we non-lazily reload both the original and
673          * the speculative FP register states.  This is because the kernel
674          * doesn't see if/when a TM rollback occurs, so if we take an FP
675          * unavoidable later, we are unable to determine which set of FP regs
676          * need to be restored.
677          */
678         if (!new->thread.regs)
679                 return;
680
681         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
682                 tm_restore_sprs(&new->thread);
683                 return;
684         }
685         msr = new->thread.ckpt_regs.msr;
686         /* Recheckpoint to restore original checkpointed register state. */
687         TM_DEBUG("*** tm_recheckpoint of pid %d "
688                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
689                  new->pid, new->thread.regs->msr, msr);
690
691         /* This loads the checkpointed FP/VEC state, if used */
692         tm_recheckpoint(&new->thread, msr);
693
694         /* This loads the speculative FP/VEC state, if used */
695         if (msr & MSR_FP) {
696                 do_load_up_transact_fpu(&new->thread);
697                 new->thread.regs->msr |=
698                         (MSR_FP | new->thread.fpexc_mode);
699         }
700 #ifdef CONFIG_ALTIVEC
701         if (msr & MSR_VEC) {
702                 do_load_up_transact_altivec(&new->thread);
703                 new->thread.regs->msr |= MSR_VEC;
704         }
705 #endif
706         /* We may as well turn on VSX too since all the state is restored now */
707         if (msr & MSR_VSX)
708                 new->thread.regs->msr |= MSR_VSX;
709
710         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
711                  "(kernel msr 0x%lx)\n",
712                  new->pid, mfmsr());
713 }
714
715 static inline void __switch_to_tm(struct task_struct *prev)
716 {
717         if (cpu_has_feature(CPU_FTR_TM)) {
718                 tm_enable();
719                 tm_reclaim_task(prev);
720         }
721 }
722
723 /*
724  * This is called if we are on the way out to userspace and the
725  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
726  * FP and/or vector state and does so if necessary.
727  * If userspace is inside a transaction (whether active or
728  * suspended) and FP/VMX/VSX instructions have ever been enabled
729  * inside that transaction, then we have to keep them enabled
730  * and keep the FP/VMX/VSX state loaded while ever the transaction
731  * continues.  The reason is that if we didn't, and subsequently
732  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
733  * we don't know whether it's the same transaction, and thus we
734  * don't know which of the checkpointed state and the transactional
735  * state to use.
736  */
737 void restore_tm_state(struct pt_regs *regs)
738 {
739         unsigned long msr_diff;
740
741         clear_thread_flag(TIF_RESTORE_TM);
742         if (!MSR_TM_ACTIVE(regs->msr))
743                 return;
744
745         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
746         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
747         if (msr_diff & MSR_FP) {
748                 fp_enable();
749                 load_fp_state(&current->thread.fp_state);
750                 regs->msr |= current->thread.fpexc_mode;
751         }
752         if (msr_diff & MSR_VEC) {
753                 vec_enable();
754                 load_vr_state(&current->thread.vr_state);
755         }
756         regs->msr |= msr_diff;
757 }
758
759 #else
760 #define tm_recheckpoint_new_task(new)
761 #define __switch_to_tm(prev)
762 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
763
764 struct task_struct *__switch_to(struct task_struct *prev,
765         struct task_struct *new)
766 {
767         struct thread_struct *new_thread, *old_thread;
768         struct task_struct *last;
769 #ifdef CONFIG_PPC_BOOK3S_64
770         struct ppc64_tlb_batch *batch;
771 #endif
772
773         WARN_ON(!irqs_disabled());
774
775         /* Back up the TAR and DSCR across context switches.
776          * Note that the TAR is not available for use in the kernel.  (To
777          * provide this, the TAR should be backed up/restored on exception
778          * entry/exit instead, and be in pt_regs.  FIXME, this should be in
779          * pt_regs anyway (for debug).)
780          * Save the TAR and DSCR here before we do treclaim/trecheckpoint as
781          * these will change them.
782          */
783         save_early_sprs(&prev->thread);
784
785         __switch_to_tm(prev);
786
787 #ifdef CONFIG_SMP
788         /* avoid complexity of lazy save/restore of fpu
789          * by just saving it every time we switch out if
790          * this task used the fpu during the last quantum.
791          *
792          * If it tries to use the fpu again, it'll trap and
793          * reload its fp regs.  So we don't have to do a restore
794          * every switch, just a save.
795          *  -- Cort
796          */
797         if (prev->thread.regs && (prev->thread.regs->msr & MSR_FP))
798                 giveup_fpu(prev);
799 #ifdef CONFIG_ALTIVEC
800         /*
801          * If the previous thread used altivec in the last quantum
802          * (thus changing altivec regs) then save them.
803          * We used to check the VRSAVE register but not all apps
804          * set it, so we don't rely on it now (and in fact we need
805          * to save & restore VSCR even if VRSAVE == 0).  -- paulus
806          *
807          * On SMP we always save/restore altivec regs just to avoid the
808          * complexity of changing processors.
809          *  -- Cort
810          */
811         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VEC))
812                 giveup_altivec(prev);
813 #endif /* CONFIG_ALTIVEC */
814 #ifdef CONFIG_VSX
815         if (prev->thread.regs && (prev->thread.regs->msr & MSR_VSX))
816                 /* VMX and FPU registers are already save here */
817                 __giveup_vsx(prev);
818 #endif /* CONFIG_VSX */
819 #ifdef CONFIG_SPE
820         /*
821          * If the previous thread used spe in the last quantum
822          * (thus changing spe regs) then save them.
823          *
824          * On SMP we always save/restore spe regs just to avoid the
825          * complexity of changing processors.
826          */
827         if ((prev->thread.regs && (prev->thread.regs->msr & MSR_SPE)))
828                 giveup_spe(prev);
829 #endif /* CONFIG_SPE */
830
831 #else  /* CONFIG_SMP */
832 #ifdef CONFIG_ALTIVEC
833         /* Avoid the trap.  On smp this this never happens since
834          * we don't set last_task_used_altivec -- Cort
835          */
836         if (new->thread.regs && last_task_used_altivec == new)
837                 new->thread.regs->msr |= MSR_VEC;
838 #endif /* CONFIG_ALTIVEC */
839 #ifdef CONFIG_VSX
840         if (new->thread.regs && last_task_used_vsx == new)
841                 new->thread.regs->msr |= MSR_VSX;
842 #endif /* CONFIG_VSX */
843 #ifdef CONFIG_SPE
844         /* Avoid the trap.  On smp this this never happens since
845          * we don't set last_task_used_spe
846          */
847         if (new->thread.regs && last_task_used_spe == new)
848                 new->thread.regs->msr |= MSR_SPE;
849 #endif /* CONFIG_SPE */
850
851 #endif /* CONFIG_SMP */
852
853 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
854         switch_booke_debug_regs(&new->thread.debug);
855 #else
856 /*
857  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
858  * schedule DABR
859  */
860 #ifndef CONFIG_HAVE_HW_BREAKPOINT
861         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
862                 __set_breakpoint(&new->thread.hw_brk);
863 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
864 #endif
865
866
867         new_thread = &new->thread;
868         old_thread = &current->thread;
869
870 #ifdef CONFIG_PPC64
871         /*
872          * Collect processor utilization data per process
873          */
874         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
875                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
876                 long unsigned start_tb, current_tb;
877                 start_tb = old_thread->start_tb;
878                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
879                 old_thread->accum_tb += (current_tb - start_tb);
880                 new_thread->start_tb = current_tb;
881         }
882 #endif /* CONFIG_PPC64 */
883
884 #ifdef CONFIG_PPC_BOOK3S_64
885         batch = this_cpu_ptr(&ppc64_tlb_batch);
886         if (batch->active) {
887                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
888                 if (batch->index)
889                         __flush_tlb_pending(batch);
890                 batch->active = 0;
891         }
892 #endif /* CONFIG_PPC_BOOK3S_64 */
893
894         /*
895          * We can't take a PMU exception inside _switch() since there is a
896          * window where the kernel stack SLB and the kernel stack are out
897          * of sync. Hard disable here.
898          */
899         hard_irq_disable();
900
901         tm_recheckpoint_new_task(new);
902
903         last = _switch(old_thread, new_thread);
904
905 #ifdef CONFIG_PPC_BOOK3S_64
906         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
907                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
908                 batch = this_cpu_ptr(&ppc64_tlb_batch);
909                 batch->active = 1;
910         }
911 #endif /* CONFIG_PPC_BOOK3S_64 */
912
913         return last;
914 }
915
916 static int instructions_to_print = 16;
917
918 static void show_instructions(struct pt_regs *regs)
919 {
920         int i;
921         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
922                         sizeof(int));
923
924         printk("Instruction dump:");
925
926         for (i = 0; i < instructions_to_print; i++) {
927                 int instr;
928
929                 if (!(i % 8))
930                         printk("\n");
931
932 #if !defined(CONFIG_BOOKE)
933                 /* If executing with the IMMU off, adjust pc rather
934                  * than print XXXXXXXX.
935                  */
936                 if (!(regs->msr & MSR_IR))
937                         pc = (unsigned long)phys_to_virt(pc);
938 #endif
939
940                 if (!__kernel_text_address(pc) ||
941                      probe_kernel_address((unsigned int __user *)pc, instr)) {
942                         printk(KERN_CONT "XXXXXXXX ");
943                 } else {
944                         if (regs->nip == pc)
945                                 printk(KERN_CONT "<%08x> ", instr);
946                         else
947                                 printk(KERN_CONT "%08x ", instr);
948                 }
949
950                 pc += sizeof(int);
951         }
952
953         printk("\n");
954 }
955
956 static struct regbit {
957         unsigned long bit;
958         const char *name;
959 } msr_bits[] = {
960 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
961         {MSR_SF,        "SF"},
962         {MSR_HV,        "HV"},
963 #endif
964         {MSR_VEC,       "VEC"},
965         {MSR_VSX,       "VSX"},
966 #ifdef CONFIG_BOOKE
967         {MSR_CE,        "CE"},
968 #endif
969         {MSR_EE,        "EE"},
970         {MSR_PR,        "PR"},
971         {MSR_FP,        "FP"},
972         {MSR_ME,        "ME"},
973 #ifdef CONFIG_BOOKE
974         {MSR_DE,        "DE"},
975 #else
976         {MSR_SE,        "SE"},
977         {MSR_BE,        "BE"},
978 #endif
979         {MSR_IR,        "IR"},
980         {MSR_DR,        "DR"},
981         {MSR_PMM,       "PMM"},
982 #ifndef CONFIG_BOOKE
983         {MSR_RI,        "RI"},
984         {MSR_LE,        "LE"},
985 #endif
986         {0,             NULL}
987 };
988
989 static void printbits(unsigned long val, struct regbit *bits)
990 {
991         const char *sep = "";
992
993         printk("<");
994         for (; bits->bit; ++bits)
995                 if (val & bits->bit) {
996                         printk("%s%s", sep, bits->name);
997                         sep = ",";
998                 }
999         printk(">");
1000 }
1001
1002 #ifdef CONFIG_PPC64
1003 #define REG             "%016lx"
1004 #define REGS_PER_LINE   4
1005 #define LAST_VOLATILE   13
1006 #else
1007 #define REG             "%08lx"
1008 #define REGS_PER_LINE   8
1009 #define LAST_VOLATILE   12
1010 #endif
1011
1012 void show_regs(struct pt_regs * regs)
1013 {
1014         int i, trap;
1015
1016         show_regs_print_info(KERN_DEFAULT);
1017
1018         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1019                regs->nip, regs->link, regs->ctr);
1020         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1021                regs, regs->trap, print_tainted(), init_utsname()->release);
1022         printk("MSR: "REG" ", regs->msr);
1023         printbits(regs->msr, msr_bits);
1024         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1025         trap = TRAP(regs);
1026         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1027                 printk("CFAR: "REG" ", regs->orig_gpr3);
1028         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1029 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1030                 printk("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1031 #else
1032                 printk("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1033 #endif
1034 #ifdef CONFIG_PPC64
1035         printk("SOFTE: %ld ", regs->softe);
1036 #endif
1037 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1038         if (MSR_TM_ACTIVE(regs->msr))
1039                 printk("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1040 #endif
1041
1042         for (i = 0;  i < 32;  i++) {
1043                 if ((i % REGS_PER_LINE) == 0)
1044                         printk("\nGPR%02d: ", i);
1045                 printk(REG " ", regs->gpr[i]);
1046                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1047                         break;
1048         }
1049         printk("\n");
1050 #ifdef CONFIG_KALLSYMS
1051         /*
1052          * Lookup NIP late so we have the best change of getting the
1053          * above info out without failing
1054          */
1055         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1056         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1057 #endif
1058         show_stack(current, (unsigned long *) regs->gpr[1]);
1059         if (!user_mode(regs))
1060                 show_instructions(regs);
1061 }
1062
1063 void exit_thread(void)
1064 {
1065         discard_lazy_cpu_state();
1066 }
1067
1068 void flush_thread(void)
1069 {
1070         discard_lazy_cpu_state();
1071
1072 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1073         flush_ptrace_hw_breakpoint(current);
1074 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1075         set_debug_reg_defaults(&current->thread);
1076 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1077 }
1078
1079 void
1080 release_thread(struct task_struct *t)
1081 {
1082 }
1083
1084 /*
1085  * this gets called so that we can store coprocessor state into memory and
1086  * copy the current task into the new thread.
1087  */
1088 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1089 {
1090         flush_fp_to_thread(src);
1091         flush_altivec_to_thread(src);
1092         flush_vsx_to_thread(src);
1093         flush_spe_to_thread(src);
1094         /*
1095          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1096          * flush but it removes the checkpointed state from the current CPU and
1097          * transitions the CPU out of TM mode.  Hence we need to call
1098          * tm_recheckpoint_new_task() (on the same task) to restore the
1099          * checkpointed state back and the TM mode.
1100          */
1101         __switch_to_tm(src);
1102         tm_recheckpoint_new_task(src);
1103
1104         *dst = *src;
1105
1106         clear_task_ebb(dst);
1107
1108         return 0;
1109 }
1110
1111 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1112 {
1113 #ifdef CONFIG_PPC_STD_MMU_64
1114         unsigned long sp_vsid;
1115         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1116
1117         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1118                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1119                         << SLB_VSID_SHIFT_1T;
1120         else
1121                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1122                         << SLB_VSID_SHIFT;
1123         sp_vsid |= SLB_VSID_KERNEL | llp;
1124         p->thread.ksp_vsid = sp_vsid;
1125 #endif
1126 }
1127
1128 /*
1129  * Copy a thread..
1130  */
1131
1132 /*
1133  * Copy architecture-specific thread state
1134  */
1135 int copy_thread(unsigned long clone_flags, unsigned long usp,
1136                 unsigned long kthread_arg, struct task_struct *p)
1137 {
1138         struct pt_regs *childregs, *kregs;
1139         extern void ret_from_fork(void);
1140         extern void ret_from_kernel_thread(void);
1141         void (*f)(void);
1142         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1143
1144         /* Copy registers */
1145         sp -= sizeof(struct pt_regs);
1146         childregs = (struct pt_regs *) sp;
1147         if (unlikely(p->flags & PF_KTHREAD)) {
1148                 /* kernel thread */
1149                 struct thread_info *ti = (void *)task_stack_page(p);
1150                 memset(childregs, 0, sizeof(struct pt_regs));
1151                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1152                 /* function */
1153                 if (usp)
1154                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1155 #ifdef CONFIG_PPC64
1156                 clear_tsk_thread_flag(p, TIF_32BIT);
1157                 childregs->softe = 1;
1158 #endif
1159                 childregs->gpr[15] = kthread_arg;
1160                 p->thread.regs = NULL;  /* no user register state */
1161                 ti->flags |= _TIF_RESTOREALL;
1162                 f = ret_from_kernel_thread;
1163         } else {
1164                 /* user thread */
1165                 struct pt_regs *regs = current_pt_regs();
1166                 CHECK_FULL_REGS(regs);
1167                 *childregs = *regs;
1168                 if (usp)
1169                         childregs->gpr[1] = usp;
1170                 p->thread.regs = childregs;
1171                 childregs->gpr[3] = 0;  /* Result from fork() */
1172                 if (clone_flags & CLONE_SETTLS) {
1173 #ifdef CONFIG_PPC64
1174                         if (!is_32bit_task())
1175                                 childregs->gpr[13] = childregs->gpr[6];
1176                         else
1177 #endif
1178                                 childregs->gpr[2] = childregs->gpr[6];
1179                 }
1180
1181                 f = ret_from_fork;
1182         }
1183         sp -= STACK_FRAME_OVERHEAD;
1184
1185         /*
1186          * The way this works is that at some point in the future
1187          * some task will call _switch to switch to the new task.
1188          * That will pop off the stack frame created below and start
1189          * the new task running at ret_from_fork.  The new task will
1190          * do some house keeping and then return from the fork or clone
1191          * system call, using the stack frame created above.
1192          */
1193         ((unsigned long *)sp)[0] = 0;
1194         sp -= sizeof(struct pt_regs);
1195         kregs = (struct pt_regs *) sp;
1196         sp -= STACK_FRAME_OVERHEAD;
1197         p->thread.ksp = sp;
1198 #ifdef CONFIG_PPC32
1199         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1200                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1201 #endif
1202 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1203         p->thread.ptrace_bps[0] = NULL;
1204 #endif
1205
1206         p->thread.fp_save_area = NULL;
1207 #ifdef CONFIG_ALTIVEC
1208         p->thread.vr_save_area = NULL;
1209 #endif
1210
1211         setup_ksp_vsid(p, sp);
1212
1213 #ifdef CONFIG_PPC64 
1214         if (cpu_has_feature(CPU_FTR_DSCR)) {
1215                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1216                 p->thread.dscr = current->thread.dscr;
1217         }
1218         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1219                 p->thread.ppr = INIT_PPR;
1220 #endif
1221         kregs->nip = ppc_function_entry(f);
1222         return 0;
1223 }
1224
1225 /*
1226  * Set up a thread for executing a new program
1227  */
1228 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1229 {
1230 #ifdef CONFIG_PPC64
1231         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1232 #endif
1233
1234         /*
1235          * If we exec out of a kernel thread then thread.regs will not be
1236          * set.  Do it now.
1237          */
1238         if (!current->thread.regs) {
1239                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1240                 current->thread.regs = regs - 1;
1241         }
1242
1243 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1244         /*
1245          * Clear any transactional state, we're exec()ing. The cause is
1246          * not important as there will never be a recheckpoint so it's not
1247          * user visible.
1248          */
1249         if (MSR_TM_SUSPENDED(mfmsr()))
1250                 tm_reclaim_current(0);
1251 #endif
1252
1253         memset(regs->gpr, 0, sizeof(regs->gpr));
1254         regs->ctr = 0;
1255         regs->link = 0;
1256         regs->xer = 0;
1257         regs->ccr = 0;
1258         regs->gpr[1] = sp;
1259
1260         /*
1261          * We have just cleared all the nonvolatile GPRs, so make
1262          * FULL_REGS(regs) return true.  This is necessary to allow
1263          * ptrace to examine the thread immediately after exec.
1264          */
1265         regs->trap &= ~1UL;
1266
1267 #ifdef CONFIG_PPC32
1268         regs->mq = 0;
1269         regs->nip = start;
1270         regs->msr = MSR_USER;
1271 #else
1272         if (!is_32bit_task()) {
1273                 unsigned long entry;
1274
1275                 if (is_elf2_task()) {
1276                         /* Look ma, no function descriptors! */
1277                         entry = start;
1278
1279                         /*
1280                          * Ulrich says:
1281                          *   The latest iteration of the ABI requires that when
1282                          *   calling a function (at its global entry point),
1283                          *   the caller must ensure r12 holds the entry point
1284                          *   address (so that the function can quickly
1285                          *   establish addressability).
1286                          */
1287                         regs->gpr[12] = start;
1288                         /* Make sure that's restored on entry to userspace. */
1289                         set_thread_flag(TIF_RESTOREALL);
1290                 } else {
1291                         unsigned long toc;
1292
1293                         /* start is a relocated pointer to the function
1294                          * descriptor for the elf _start routine.  The first
1295                          * entry in the function descriptor is the entry
1296                          * address of _start and the second entry is the TOC
1297                          * value we need to use.
1298                          */
1299                         __get_user(entry, (unsigned long __user *)start);
1300                         __get_user(toc, (unsigned long __user *)start+1);
1301
1302                         /* Check whether the e_entry function descriptor entries
1303                          * need to be relocated before we can use them.
1304                          */
1305                         if (load_addr != 0) {
1306                                 entry += load_addr;
1307                                 toc   += load_addr;
1308                         }
1309                         regs->gpr[2] = toc;
1310                 }
1311                 regs->nip = entry;
1312                 regs->msr = MSR_USER64;
1313         } else {
1314                 regs->nip = start;
1315                 regs->gpr[2] = 0;
1316                 regs->msr = MSR_USER32;
1317         }
1318 #endif
1319         discard_lazy_cpu_state();
1320 #ifdef CONFIG_VSX
1321         current->thread.used_vsr = 0;
1322 #endif
1323         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1324         current->thread.fp_save_area = NULL;
1325 #ifdef CONFIG_ALTIVEC
1326         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1327         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1328         current->thread.vr_save_area = NULL;
1329         current->thread.vrsave = 0;
1330         current->thread.used_vr = 0;
1331 #endif /* CONFIG_ALTIVEC */
1332 #ifdef CONFIG_SPE
1333         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1334         current->thread.acc = 0;
1335         current->thread.spefscr = 0;
1336         current->thread.used_spe = 0;
1337 #endif /* CONFIG_SPE */
1338 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1339         if (cpu_has_feature(CPU_FTR_TM))
1340                 regs->msr |= MSR_TM;
1341         current->thread.tm_tfhar = 0;
1342         current->thread.tm_texasr = 0;
1343         current->thread.tm_tfiar = 0;
1344 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1345 }
1346 EXPORT_SYMBOL(start_thread);
1347
1348 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1349                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1350
1351 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1352 {
1353         struct pt_regs *regs = tsk->thread.regs;
1354
1355         /* This is a bit hairy.  If we are an SPE enabled  processor
1356          * (have embedded fp) we store the IEEE exception enable flags in
1357          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1358          * mode (asyn, precise, disabled) for 'Classic' FP. */
1359         if (val & PR_FP_EXC_SW_ENABLE) {
1360 #ifdef CONFIG_SPE
1361                 if (cpu_has_feature(CPU_FTR_SPE)) {
1362                         /*
1363                          * When the sticky exception bits are set
1364                          * directly by userspace, it must call prctl
1365                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1366                          * in the existing prctl settings) or
1367                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1368                          * the bits being set).  <fenv.h> functions
1369                          * saving and restoring the whole
1370                          * floating-point environment need to do so
1371                          * anyway to restore the prctl settings from
1372                          * the saved environment.
1373                          */
1374                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1375                         tsk->thread.fpexc_mode = val &
1376                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1377                         return 0;
1378                 } else {
1379                         return -EINVAL;
1380                 }
1381 #else
1382                 return -EINVAL;
1383 #endif
1384         }
1385
1386         /* on a CONFIG_SPE this does not hurt us.  The bits that
1387          * __pack_fe01 use do not overlap with bits used for
1388          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1389          * on CONFIG_SPE implementations are reserved so writing to
1390          * them does not change anything */
1391         if (val > PR_FP_EXC_PRECISE)
1392                 return -EINVAL;
1393         tsk->thread.fpexc_mode = __pack_fe01(val);
1394         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1395                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1396                         | tsk->thread.fpexc_mode;
1397         return 0;
1398 }
1399
1400 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1401 {
1402         unsigned int val;
1403
1404         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1405 #ifdef CONFIG_SPE
1406                 if (cpu_has_feature(CPU_FTR_SPE)) {
1407                         /*
1408                          * When the sticky exception bits are set
1409                          * directly by userspace, it must call prctl
1410                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1411                          * in the existing prctl settings) or
1412                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1413                          * the bits being set).  <fenv.h> functions
1414                          * saving and restoring the whole
1415                          * floating-point environment need to do so
1416                          * anyway to restore the prctl settings from
1417                          * the saved environment.
1418                          */
1419                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1420                         val = tsk->thread.fpexc_mode;
1421                 } else
1422                         return -EINVAL;
1423 #else
1424                 return -EINVAL;
1425 #endif
1426         else
1427                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1428         return put_user(val, (unsigned int __user *) adr);
1429 }
1430
1431 int set_endian(struct task_struct *tsk, unsigned int val)
1432 {
1433         struct pt_regs *regs = tsk->thread.regs;
1434
1435         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1436             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1437                 return -EINVAL;
1438
1439         if (regs == NULL)
1440                 return -EINVAL;
1441
1442         if (val == PR_ENDIAN_BIG)
1443                 regs->msr &= ~MSR_LE;
1444         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1445                 regs->msr |= MSR_LE;
1446         else
1447                 return -EINVAL;
1448
1449         return 0;
1450 }
1451
1452 int get_endian(struct task_struct *tsk, unsigned long adr)
1453 {
1454         struct pt_regs *regs = tsk->thread.regs;
1455         unsigned int val;
1456
1457         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1458             !cpu_has_feature(CPU_FTR_REAL_LE))
1459                 return -EINVAL;
1460
1461         if (regs == NULL)
1462                 return -EINVAL;
1463
1464         if (regs->msr & MSR_LE) {
1465                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1466                         val = PR_ENDIAN_LITTLE;
1467                 else
1468                         val = PR_ENDIAN_PPC_LITTLE;
1469         } else
1470                 val = PR_ENDIAN_BIG;
1471
1472         return put_user(val, (unsigned int __user *)adr);
1473 }
1474
1475 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1476 {
1477         tsk->thread.align_ctl = val;
1478         return 0;
1479 }
1480
1481 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1482 {
1483         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1484 }
1485
1486 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1487                                   unsigned long nbytes)
1488 {
1489         unsigned long stack_page;
1490         unsigned long cpu = task_cpu(p);
1491
1492         /*
1493          * Avoid crashing if the stack has overflowed and corrupted
1494          * task_cpu(p), which is in the thread_info struct.
1495          */
1496         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1497                 stack_page = (unsigned long) hardirq_ctx[cpu];
1498                 if (sp >= stack_page + sizeof(struct thread_struct)
1499                     && sp <= stack_page + THREAD_SIZE - nbytes)
1500                         return 1;
1501
1502                 stack_page = (unsigned long) softirq_ctx[cpu];
1503                 if (sp >= stack_page + sizeof(struct thread_struct)
1504                     && sp <= stack_page + THREAD_SIZE - nbytes)
1505                         return 1;
1506         }
1507         return 0;
1508 }
1509
1510 int validate_sp(unsigned long sp, struct task_struct *p,
1511                        unsigned long nbytes)
1512 {
1513         unsigned long stack_page = (unsigned long)task_stack_page(p);
1514
1515         if (sp >= stack_page + sizeof(struct thread_struct)
1516             && sp <= stack_page + THREAD_SIZE - nbytes)
1517                 return 1;
1518
1519         return valid_irq_stack(sp, p, nbytes);
1520 }
1521
1522 EXPORT_SYMBOL(validate_sp);
1523
1524 unsigned long get_wchan(struct task_struct *p)
1525 {
1526         unsigned long ip, sp;
1527         int count = 0;
1528
1529         if (!p || p == current || p->state == TASK_RUNNING)
1530                 return 0;
1531
1532         sp = p->thread.ksp;
1533         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1534                 return 0;
1535
1536         do {
1537                 sp = *(unsigned long *)sp;
1538                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1539                         return 0;
1540                 if (count > 0) {
1541                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1542                         if (!in_sched_functions(ip))
1543                                 return ip;
1544                 }
1545         } while (count++ < 16);
1546         return 0;
1547 }
1548
1549 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1550
1551 void show_stack(struct task_struct *tsk, unsigned long *stack)
1552 {
1553         unsigned long sp, ip, lr, newsp;
1554         int count = 0;
1555         int firstframe = 1;
1556 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1557         int curr_frame = current->curr_ret_stack;
1558         extern void return_to_handler(void);
1559         unsigned long rth = (unsigned long)return_to_handler;
1560 #endif
1561
1562         sp = (unsigned long) stack;
1563         if (tsk == NULL)
1564                 tsk = current;
1565         if (sp == 0) {
1566                 if (tsk == current)
1567                         sp = current_stack_pointer();
1568                 else
1569                         sp = tsk->thread.ksp;
1570         }
1571
1572         lr = 0;
1573         printk("Call Trace:\n");
1574         do {
1575                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1576                         return;
1577
1578                 stack = (unsigned long *) sp;
1579                 newsp = stack[0];
1580                 ip = stack[STACK_FRAME_LR_SAVE];
1581                 if (!firstframe || ip != lr) {
1582                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1583 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1584                         if ((ip == rth) && curr_frame >= 0) {
1585                                 printk(" (%pS)",
1586                                        (void *)current->ret_stack[curr_frame].ret);
1587                                 curr_frame--;
1588                         }
1589 #endif
1590                         if (firstframe)
1591                                 printk(" (unreliable)");
1592                         printk("\n");
1593                 }
1594                 firstframe = 0;
1595
1596                 /*
1597                  * See if this is an exception frame.
1598                  * We look for the "regshere" marker in the current frame.
1599                  */
1600                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1601                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1602                         struct pt_regs *regs = (struct pt_regs *)
1603                                 (sp + STACK_FRAME_OVERHEAD);
1604                         lr = regs->link;
1605                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1606                                regs->trap, (void *)regs->nip, (void *)lr);
1607                         firstframe = 1;
1608                 }
1609
1610                 sp = newsp;
1611         } while (count++ < kstack_depth_to_print);
1612 }
1613
1614 #ifdef CONFIG_PPC64
1615 /* Called with hard IRQs off */
1616 void notrace __ppc64_runlatch_on(void)
1617 {
1618         struct thread_info *ti = current_thread_info();
1619         unsigned long ctrl;
1620
1621         ctrl = mfspr(SPRN_CTRLF);
1622         ctrl |= CTRL_RUNLATCH;
1623         mtspr(SPRN_CTRLT, ctrl);
1624
1625         ti->local_flags |= _TLF_RUNLATCH;
1626 }
1627
1628 /* Called with hard IRQs off */
1629 void notrace __ppc64_runlatch_off(void)
1630 {
1631         struct thread_info *ti = current_thread_info();
1632         unsigned long ctrl;
1633
1634         ti->local_flags &= ~_TLF_RUNLATCH;
1635
1636         ctrl = mfspr(SPRN_CTRLF);
1637         ctrl &= ~CTRL_RUNLATCH;
1638         mtspr(SPRN_CTRLT, ctrl);
1639 }
1640 #endif /* CONFIG_PPC64 */
1641
1642 unsigned long arch_align_stack(unsigned long sp)
1643 {
1644         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1645                 sp -= get_random_int() & ~PAGE_MASK;
1646         return sp & ~0xf;
1647 }
1648
1649 static inline unsigned long brk_rnd(void)
1650 {
1651         unsigned long rnd = 0;
1652
1653         /* 8MB for 32bit, 1GB for 64bit */
1654         if (is_32bit_task())
1655                 rnd = (long)(get_random_int() % (1<<(23-PAGE_SHIFT)));
1656         else
1657                 rnd = (long)(get_random_int() % (1<<(30-PAGE_SHIFT)));
1658
1659         return rnd << PAGE_SHIFT;
1660 }
1661
1662 unsigned long arch_randomize_brk(struct mm_struct *mm)
1663 {
1664         unsigned long base = mm->brk;
1665         unsigned long ret;
1666
1667 #ifdef CONFIG_PPC_STD_MMU_64
1668         /*
1669          * If we are using 1TB segments and we are allowed to randomise
1670          * the heap, we can put it above 1TB so it is backed by a 1TB
1671          * segment. Otherwise the heap will be in the bottom 1TB
1672          * which always uses 256MB segments and this may result in a
1673          * performance penalty.
1674          */
1675         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
1676                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
1677 #endif
1678
1679         ret = PAGE_ALIGN(base + brk_rnd());
1680
1681         if (ret < mm->brk)
1682                 return mm->brk;
1683
1684         return ret;
1685 }
1686