arch/powerpc/kernel/process.c

   1 /*
   2  *  Derived from "arch/i386/kernel/process.c"
   3  *    Copyright (C) 1995  Linus Torvalds
   4  *
   5  *  Updated and modified by Cort Dougan (cort@cs.nmt.edu) and
   6  *  Paul Mackerras (paulus@cs.anu.edu.au)
   7  *
   8  *  PowerPC version
   9  *    Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
  10  *
  11  *  This program is free software; you can redistribute it and/or
  12  *  modify it under the terms of the GNU General Public License
  13  *  as published by the Free Software Foundation; either version
  14  *  2 of the License, or (at your option) any later version.
  15  */
  16
  17 #include <linux/errno.h>
  18 #include <linux/sched.h>
  19 #include <linux/kernel.h>
  20 #include <linux/mm.h>
  21 #include <linux/smp.h>
  22 #include <linux/stddef.h>
  23 #include <linux/unistd.h>
  24 #include <linux/ptrace.h>
  25 #include <linux/slab.h>
  26 #include <linux/user.h>
  27 #include <linux/elf.h>
  28 #include <linux/prctl.h>
  29 #include <linux/init_task.h>
  30 #include <linux/export.h>
  31 #include <linux/kallsyms.h>
  32 #include <linux/mqueue.h>
  33 #include <linux/hardirq.h>
  34 #include <linux/utsname.h>
  35 #include <linux/ftrace.h>
  36 #include <linux/kernel_stat.h>
  37 #include <linux/personality.h>
  38 #include <linux/random.h>
  39 #include <linux/hw_breakpoint.h>
  40 #include <linux/uaccess.h>
  41 #include <linux/elf-randomize.h>
  42
  43 #include <asm/pgtable.h>
  44 #include <asm/io.h>
  45 #include <asm/processor.h>
  46 #include <asm/mmu.h>
  47 #include <asm/prom.h>
  48 #include <asm/machdep.h>
  49 #include <asm/time.h>
  50 #include <asm/runlatch.h>
  51 #include <asm/syscalls.h>
  52 #include <asm/switch_to.h>
  53 #include <asm/tm.h>
  54 #include <asm/debug.h>
  55 #ifdef CONFIG_PPC64
  56 #include <asm/firmware.h>
  57 #endif
  58 #include <asm/code-patching.h>
  59 #include <asm/exec.h>
  60 #include <asm/livepatch.h>
  61 #include <asm/cpu_has_feature.h>
  62 #include <asm/asm-prototypes.h>
  63
  64 #include <linux/kprobes.h>
  65 #include <linux/kdebug.h>
  66
  67 /* Transactional Memory debug */
  68 #ifdef TM_DEBUG_SW
  69 #define TM_DEBUG(x...) printk(KERN_INFO x)
  70 #else
  71 #define TM_DEBUG(x...) do { } while(0)
  72 #endif
  73
  74 extern unsigned long _get_SP(void);
  75
  76 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
  77 static void check_if_tm_restore_required(struct task_struct *tsk)
  78 {
  79         /*
  80          * If we are saving the current thread's registers, and the
  81          * thread is in a transactional state, set the TIF_RESTORE_TM
  82          * bit so that we know to restore the registers before
  83          * returning to userspace.
  84          */
  85         if (tsk == current && tsk->thread.regs &&
  86             MSR_TM_ACTIVE(tsk->thread.regs->msr) &&
  87             !test_thread_flag(TIF_RESTORE_TM)) {
  88                 tsk->thread.ckpt_regs.msr = tsk->thread.regs->msr;
  89                 set_thread_flag(TIF_RESTORE_TM);
  90         }
  91 }
  92
  93 static inline bool msr_tm_active(unsigned long msr)
  94 {
  95         return MSR_TM_ACTIVE(msr);
  96 }
  97 #else
  98 static inline bool msr_tm_active(unsigned long msr) { return false; }
  99 static inline void check_if_tm_restore_required(struct task_struct *tsk) { }
 100 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
 101
 102 bool strict_msr_control;
 103 EXPORT_SYMBOL(strict_msr_control);
 104
 105 static int __init enable_strict_msr_control(char *str)
 106 {
 107         strict_msr_control = true;
 108         pr_info("Enabling strict facility control\n");
 109
 110         return 0;
 111 }
 112 early_param("ppc_strict_facility_enable", enable_strict_msr_control);
 113
 114 unsigned long msr_check_and_set(unsigned long bits)
 115 {
 116         unsigned long oldmsr = mfmsr();
 117         unsigned long newmsr;
 118
 119         newmsr = oldmsr | bits;
 120
 121 #ifdef CONFIG_VSX
 122         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 123                 newmsr |= MSR_VSX;
 124 #endif
 125
 126         if (oldmsr != newmsr)
 127                 mtmsr_isync(newmsr);
 128
 129         return newmsr;
 130 }
 131
 132 void __msr_check_and_clear(unsigned long bits)
 133 {
 134         unsigned long oldmsr = mfmsr();
 135         unsigned long newmsr;
 136
 137         newmsr = oldmsr & ~bits;
 138
 139 #ifdef CONFIG_VSX
 140         if (cpu_has_feature(CPU_FTR_VSX) && (bits & MSR_FP))
 141                 newmsr &= ~MSR_VSX;
 142 #endif
 143
 144         if (oldmsr != newmsr)
 145                 mtmsr_isync(newmsr);
 146 }
 147 EXPORT_SYMBOL(__msr_check_and_clear);
 148
 149 #ifdef CONFIG_PPC_FPU
 150 void __giveup_fpu(struct task_struct *tsk)
 151 {
 152         unsigned long msr;
 153
 154         save_fpu(tsk);
 155         msr = tsk->thread.regs->msr;
 156         msr &= ~(MSR_FP|MSR_FE0|MSR_FE1);
 157 #ifdef CONFIG_VSX
 158         if (cpu_has_feature(CPU_FTR_VSX))
 159                 msr &= ~MSR_VSX;
 160 #endif
 161         tsk->thread.regs->msr = msr;
 162 }
 163
 164 void giveup_fpu(struct task_struct *tsk)
 165 {
 166         check_if_tm_restore_required(tsk);
 167
 168         msr_check_and_set(MSR_FP);
 169         __giveup_fpu(tsk);
 170         msr_check_and_clear(MSR_FP);
 171 }
 172 EXPORT_SYMBOL(giveup_fpu);
 173
 174 /*
 175  * Make sure the floating-point register state in the
 176  * the thread_struct is up to date for task tsk.
 177  */
 178 void flush_fp_to_thread(struct task_struct *tsk)
 179 {
 180         if (tsk->thread.regs) {
 181                 /*
 182                  * We need to disable preemption here because if we didn't,
 183                  * another process could get scheduled after the regs->msr
 184                  * test but before we have finished saving the FP registers
 185                  * to the thread_struct.  That process could take over the
 186                  * FPU, and then when we get scheduled again we would store
 187                  * bogus values for the remaining FP registers.
 188                  */
 189                 preempt_disable();
 190                 if (tsk->thread.regs->msr & MSR_FP) {
 191                         /*
 192                          * This should only ever be called for current or
 193                          * for a stopped child process.  Since we save away
 194                          * the FP register state on context switch,
 195                          * there is something wrong if a stopped child appears
 196                          * to still have its FP state in the CPU registers.
 197                          */
 198                         BUG_ON(tsk != current);
 199                         giveup_fpu(tsk);
 200                 }
 201                 preempt_enable();
 202         }
 203 }
 204 EXPORT_SYMBOL_GPL(flush_fp_to_thread);
 205
 206 void enable_kernel_fp(void)
 207 {
 208         unsigned long cpumsr;
 209
 210         WARN_ON(preemptible());
 211
 212         cpumsr = msr_check_and_set(MSR_FP);
 213
 214         if (current->thread.regs && (current->thread.regs->msr & MSR_FP)) {
 215                 check_if_tm_restore_required(current);
 216                 /*
 217                  * If a thread has already been reclaimed then the
 218                  * checkpointed registers are on the CPU but have definitely
 219                  * been saved by the reclaim code. Don't need to and *cannot*
 220                  * giveup as this would save  to the 'live' structure not the
 221                  * checkpointed structure.
 222                  */
 223                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 224                         return;
 225                 __giveup_fpu(current);
 226         }
 227 }
 228 EXPORT_SYMBOL(enable_kernel_fp);
 229
 230 static int restore_fp(struct task_struct *tsk) {
 231         if (tsk->thread.load_fp || msr_tm_active(tsk->thread.regs->msr)) {
 232                 load_fp_state(&current->thread.fp_state);
 233                 current->thread.load_fp++;
 234                 return 1;
 235         }
 236         return 0;
 237 }
 238 #else
 239 static int restore_fp(struct task_struct *tsk) { return 0; }
 240 #endif /* CONFIG_PPC_FPU */
 241
 242 #ifdef CONFIG_ALTIVEC
 243 #define loadvec(thr) ((thr).load_vec)
 244
 245 static void __giveup_altivec(struct task_struct *tsk)
 246 {
 247         unsigned long msr;
 248
 249         save_altivec(tsk);
 250         msr = tsk->thread.regs->msr;
 251         msr &= ~MSR_VEC;
 252 #ifdef CONFIG_VSX
 253         if (cpu_has_feature(CPU_FTR_VSX))
 254                 msr &= ~MSR_VSX;
 255 #endif
 256         tsk->thread.regs->msr = msr;
 257 }
 258
 259 void giveup_altivec(struct task_struct *tsk)
 260 {
 261         check_if_tm_restore_required(tsk);
 262
 263         msr_check_and_set(MSR_VEC);
 264         __giveup_altivec(tsk);
 265         msr_check_and_clear(MSR_VEC);
 266 }
 267 EXPORT_SYMBOL(giveup_altivec);
 268
 269 void enable_kernel_altivec(void)
 270 {
 271         unsigned long cpumsr;
 272
 273         WARN_ON(preemptible());
 274
 275         cpumsr = msr_check_and_set(MSR_VEC);
 276
 277         if (current->thread.regs && (current->thread.regs->msr & MSR_VEC)) {
 278                 check_if_tm_restore_required(current);
 279                 /*
 280                  * If a thread has already been reclaimed then the
 281                  * checkpointed registers are on the CPU but have definitely
 282                  * been saved by the reclaim code. Don't need to and *cannot*
 283                  * giveup as this would save  to the 'live' structure not the
 284                  * checkpointed structure.
 285                  */
 286                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 287                         return;
 288                 __giveup_altivec(current);
 289         }
 290 }
 291 EXPORT_SYMBOL(enable_kernel_altivec);
 292
 293 /*
 294  * Make sure the VMX/Altivec register state in the
 295  * the thread_struct is up to date for task tsk.
 296  */
 297 void flush_altivec_to_thread(struct task_struct *tsk)
 298 {
 299         if (tsk->thread.regs) {
 300                 preempt_disable();
 301                 if (tsk->thread.regs->msr & MSR_VEC) {
 302                         BUG_ON(tsk != current);
 303                         giveup_altivec(tsk);
 304                 }
 305                 preempt_enable();
 306         }
 307 }
 308 EXPORT_SYMBOL_GPL(flush_altivec_to_thread);
 309
 310 static int restore_altivec(struct task_struct *tsk)
 311 {
 312         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
 313                 (tsk->thread.load_vec || msr_tm_active(tsk->thread.regs->msr))) {
 314                 load_vr_state(&tsk->thread.vr_state);
 315                 tsk->thread.used_vr = 1;
 316                 tsk->thread.load_vec++;
 317
 318                 return 1;
 319         }
 320         return 0;
 321 }
 322 #else
 323 #define loadvec(thr) 0
 324 static inline int restore_altivec(struct task_struct *tsk) { return 0; }
 325 #endif /* CONFIG_ALTIVEC */
 326
 327 #ifdef CONFIG_VSX
 328 static void __giveup_vsx(struct task_struct *tsk)
 329 {
 330         if (tsk->thread.regs->msr & MSR_FP)
 331                 __giveup_fpu(tsk);
 332         if (tsk->thread.regs->msr & MSR_VEC)
 333                 __giveup_altivec(tsk);
 334         tsk->thread.regs->msr &= ~MSR_VSX;
 335 }
 336
 337 static void giveup_vsx(struct task_struct *tsk)
 338 {
 339         check_if_tm_restore_required(tsk);
 340
 341         msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 342         __giveup_vsx(tsk);
 343         msr_check_and_clear(MSR_FP|MSR_VEC|MSR_VSX);
 344 }
 345
 346 static void save_vsx(struct task_struct *tsk)
 347 {
 348         if (tsk->thread.regs->msr & MSR_FP)
 349                 save_fpu(tsk);
 350         if (tsk->thread.regs->msr & MSR_VEC)
 351                 save_altivec(tsk);
 352 }
 353
 354 void enable_kernel_vsx(void)
 355 {
 356         unsigned long cpumsr;
 357
 358         WARN_ON(preemptible());
 359
 360         cpumsr = msr_check_and_set(MSR_FP|MSR_VEC|MSR_VSX);
 361
 362         if (current->thread.regs &&
 363             (current->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP))) {
 364                 check_if_tm_restore_required(current);
 365                 /*
 366                  * If a thread has already been reclaimed then the
 367                  * checkpointed registers are on the CPU but have definitely
 368                  * been saved by the reclaim code. Don't need to and *cannot*
 369                  * giveup as this would save  to the 'live' structure not the
 370                  * checkpointed structure.
 371                  */
 372                 if(!msr_tm_active(cpumsr) && msr_tm_active(current->thread.regs->msr))
 373                         return;
 374                 if (current->thread.regs->msr & MSR_FP)
 375                         __giveup_fpu(current);
 376                 if (current->thread.regs->msr & MSR_VEC)
 377                         __giveup_altivec(current);
 378                 __giveup_vsx(current);
 379         }
 380 }
 381 EXPORT_SYMBOL(enable_kernel_vsx);
 382
 383 void flush_vsx_to_thread(struct task_struct *tsk)
 384 {
 385         if (tsk->thread.regs) {
 386                 preempt_disable();
 387                 if (tsk->thread.regs->msr & (MSR_VSX|MSR_VEC|MSR_FP)) {
 388                         BUG_ON(tsk != current);
 389                         giveup_vsx(tsk);
 390                 }
 391                 preempt_enable();
 392         }
 393 }
 394 EXPORT_SYMBOL_GPL(flush_vsx_to_thread);
 395
 396 static int restore_vsx(struct task_struct *tsk)
 397 {
 398         if (cpu_has_feature(CPU_FTR_VSX)) {
 399                 tsk->thread.used_vsr = 1;
 400                 return 1;
 401         }
 402
 403         return 0;
 404 }
 405 #else
 406 static inline int restore_vsx(struct task_struct *tsk) { return 0; }
 407 static inline void save_vsx(struct task_struct *tsk) { }
 408 #endif /* CONFIG_VSX */
 409
 410 #ifdef CONFIG_SPE
 411 void giveup_spe(struct task_struct *tsk)
 412 {
 413         check_if_tm_restore_required(tsk);
 414
 415         msr_check_and_set(MSR_SPE);
 416         __giveup_spe(tsk);
 417         msr_check_and_clear(MSR_SPE);
 418 }
 419 EXPORT_SYMBOL(giveup_spe);
 420
 421 void enable_kernel_spe(void)
 422 {
 423         WARN_ON(preemptible());
 424
 425         msr_check_and_set(MSR_SPE);
 426
 427         if (current->thread.regs && (current->thread.regs->msr & MSR_SPE)) {
 428                 check_if_tm_restore_required(current);
 429                 __giveup_spe(current);
 430         }
 431 }
 432 EXPORT_SYMBOL(enable_kernel_spe);
 433
 434 void flush_spe_to_thread(struct task_struct *tsk)
 435 {
 436         if (tsk->thread.regs) {
 437                 preempt_disable();
 438                 if (tsk->thread.regs->msr & MSR_SPE) {
 439                         BUG_ON(tsk != current);
 440                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 441                         giveup_spe(tsk);
 442                 }
 443                 preempt_enable();
 444         }
 445 }
 446 #endif /* CONFIG_SPE */
 447
 448 static unsigned long msr_all_available;
 449
 450 static int __init init_msr_all_available(void)
 451 {
 452 #ifdef CONFIG_PPC_FPU
 453         msr_all_available |= MSR_FP;
 454 #endif
 455 #ifdef CONFIG_ALTIVEC
 456         if (cpu_has_feature(CPU_FTR_ALTIVEC))
 457                 msr_all_available |= MSR_VEC;
 458 #endif
 459 #ifdef CONFIG_VSX
 460         if (cpu_has_feature(CPU_FTR_VSX))
 461                 msr_all_available |= MSR_VSX;
 462 #endif
 463 #ifdef CONFIG_SPE
 464         if (cpu_has_feature(CPU_FTR_SPE))
 465                 msr_all_available |= MSR_SPE;
 466 #endif
 467
 468         return 0;
 469 }
 470 early_initcall(init_msr_all_available);
 471
 472 void giveup_all(struct task_struct *tsk)
 473 {
 474         unsigned long usermsr;
 475
 476         if (!tsk->thread.regs)
 477                 return;
 478
 479         check_if_tm_restore_required(tsk);
 480
 481         usermsr = tsk->thread.regs->msr;
 482
 483         if ((usermsr & msr_all_available) == 0)
 484                 return;
 485
 486         msr_check_and_set(msr_all_available);
 487
 488 #ifdef CONFIG_PPC_FPU
 489         if (usermsr & MSR_FP)
 490                 __giveup_fpu(tsk);
 491 #endif
 492 #ifdef CONFIG_ALTIVEC
 493         if (usermsr & MSR_VEC)
 494                 __giveup_altivec(tsk);
 495 #endif
 496 #ifdef CONFIG_VSX
 497         if (usermsr & MSR_VSX)
 498                 __giveup_vsx(tsk);
 499 #endif
 500 #ifdef CONFIG_SPE
 501         if (usermsr & MSR_SPE)
 502                 __giveup_spe(tsk);
 503 #endif
 504
 505         msr_check_and_clear(msr_all_available);
 506 }
 507 EXPORT_SYMBOL(giveup_all);
 508
 509 void restore_math(struct pt_regs *regs)
 510 {
 511         unsigned long msr;
 512
 513         if (!msr_tm_active(regs->msr) &&
 514                 !current->thread.load_fp && !loadvec(current->thread))
 515                 return;
 516
 517         msr = regs->msr;
 518         msr_check_and_set(msr_all_available);
 519
 520         /*
 521          * Only reload if the bit is not set in the user MSR, the bit BEING set
 522          * indicates that the registers are hot
 523          */
 524         if ((!(msr & MSR_FP)) && restore_fp(current))
 525                 msr |= MSR_FP | current->thread.fpexc_mode;
 526
 527         if ((!(msr & MSR_VEC)) && restore_altivec(current))
 528                 msr |= MSR_VEC;
 529
 530         if ((msr & (MSR_FP | MSR_VEC)) == (MSR_FP | MSR_VEC) &&
 531                         restore_vsx(current)) {
 532                 msr |= MSR_VSX;
 533         }
 534
 535         msr_check_and_clear(msr_all_available);
 536
 537         regs->msr = msr;
 538 }
 539
 540 void save_all(struct task_struct *tsk)
 541 {
 542         unsigned long usermsr;
 543
 544         if (!tsk->thread.regs)
 545                 return;
 546
 547         usermsr = tsk->thread.regs->msr;
 548
 549         if ((usermsr & msr_all_available) == 0)
 550                 return;
 551
 552         msr_check_and_set(msr_all_available);
 553
 554         /*
 555          * Saving the way the register space is in hardware, save_vsx boils
 556          * down to a save_fpu() and save_altivec()
 557          */
 558         if (usermsr & MSR_VSX) {
 559                 save_vsx(tsk);
 560         } else {
 561                 if (usermsr & MSR_FP)
 562                         save_fpu(tsk);
 563
 564                 if (usermsr & MSR_VEC)
 565                         save_altivec(tsk);
 566         }
 567
 568         if (usermsr & MSR_SPE)
 569                 __giveup_spe(tsk);
 570
 571         msr_check_and_clear(msr_all_available);
 572 }
 573
 574 void flush_all_to_thread(struct task_struct *tsk)
 575 {
 576         if (tsk->thread.regs) {
 577                 preempt_disable();
 578                 BUG_ON(tsk != current);
 579 #ifdef CONFIG_SPE
 580                 if (tsk->thread.regs->msr & MSR_SPE)
 581                         tsk->thread.spefscr = mfspr(SPRN_SPEFSCR);
 582 #endif
 583                 save_all(tsk);
 584
 585                 preempt_enable();
 586         }
 587 }
 588 EXPORT_SYMBOL(flush_all_to_thread);
 589
 590 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 591 void do_send_trap(struct pt_regs *regs, unsigned long address,
 592                   unsigned long error_code, int signal_code, int breakpt)
 593 {
 594         siginfo_t info;
 595
 596         current->thread.trap_nr = signal_code;
 597         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 598                         11, SIGSEGV) == NOTIFY_STOP)
 599                 return;
 600
 601         /* Deliver the signal to userspace */
 602         info.si_signo = SIGTRAP;
 603         info.si_errno = breakpt;        /* breakpoint or watchpoint id */
 604         info.si_code = signal_code;
 605         info.si_addr = (void __user *)address;
 606         force_sig_info(SIGTRAP, &info, current);
 607 }
 608 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 609 void do_break (struct pt_regs *regs, unsigned long address,
 610                     unsigned long error_code)
 611 {
 612         siginfo_t info;
 613
 614         current->thread.trap_nr = TRAP_HWBKPT;
 615         if (notify_die(DIE_DABR_MATCH, "dabr_match", regs, error_code,
 616                         11, SIGSEGV) == NOTIFY_STOP)
 617                 return;
 618
 619         if (debugger_break_match(regs))
 620                 return;
 621
 622         /* Clear the breakpoint */
 623         hw_breakpoint_disable();
 624
 625         /* Deliver the signal to userspace */
 626         info.si_signo = SIGTRAP;
 627         info.si_errno = 0;
 628         info.si_code = TRAP_HWBKPT;
 629         info.si_addr = (void __user *)address;
 630         force_sig_info(SIGTRAP, &info, current);
 631 }
 632 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 633
 634 static DEFINE_PER_CPU(struct arch_hw_breakpoint, current_brk);
 635
 636 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 637 /*
 638  * Set the debug registers back to their default "safe" values.
 639  */
 640 static void set_debug_reg_defaults(struct thread_struct *thread)
 641 {
 642         thread->debug.iac1 = thread->debug.iac2 = 0;
 643 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 644         thread->debug.iac3 = thread->debug.iac4 = 0;
 645 #endif
 646         thread->debug.dac1 = thread->debug.dac2 = 0;
 647 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 648         thread->debug.dvc1 = thread->debug.dvc2 = 0;
 649 #endif
 650         thread->debug.dbcr0 = 0;
 651 #ifdef CONFIG_BOOKE
 652         /*
 653          * Force User/Supervisor bits to b11 (user-only MSR[PR]=1)
 654          */
 655         thread->debug.dbcr1 = DBCR1_IAC1US | DBCR1_IAC2US |
 656                         DBCR1_IAC3US | DBCR1_IAC4US;
 657         /*
 658          * Force Data Address Compare User/Supervisor bits to be User-only
 659          * (0b11 MSR[PR]=1) and set all other bits in DBCR2 register to be 0.
 660          */
 661         thread->debug.dbcr2 = DBCR2_DAC1US | DBCR2_DAC2US;
 662 #else
 663         thread->debug.dbcr1 = 0;
 664 #endif
 665 }
 666
 667 static void prime_debug_regs(struct debug_reg *debug)
 668 {
 669         /*
 670          * We could have inherited MSR_DE from userspace, since
 671          * it doesn't get cleared on exception entry.  Make sure
 672          * MSR_DE is clear before we enable any debug events.
 673          */
 674         mtmsr(mfmsr() & ~MSR_DE);
 675
 676         mtspr(SPRN_IAC1, debug->iac1);
 677         mtspr(SPRN_IAC2, debug->iac2);
 678 #if CONFIG_PPC_ADV_DEBUG_IACS > 2
 679         mtspr(SPRN_IAC3, debug->iac3);
 680         mtspr(SPRN_IAC4, debug->iac4);
 681 #endif
 682         mtspr(SPRN_DAC1, debug->dac1);
 683         mtspr(SPRN_DAC2, debug->dac2);
 684 #if CONFIG_PPC_ADV_DEBUG_DVCS > 0
 685         mtspr(SPRN_DVC1, debug->dvc1);
 686         mtspr(SPRN_DVC2, debug->dvc2);
 687 #endif
 688         mtspr(SPRN_DBCR0, debug->dbcr0);
 689         mtspr(SPRN_DBCR1, debug->dbcr1);
 690 #ifdef CONFIG_BOOKE
 691         mtspr(SPRN_DBCR2, debug->dbcr2);
 692 #endif
 693 }
 694 /*
 695  * Unless neither the old or new thread are making use of the
 696  * debug registers, set the debug registers from the values
 697  * stored in the new thread.
 698  */
 699 void switch_booke_debug_regs(struct debug_reg *new_debug)
 700 {
 701         if ((current->thread.debug.dbcr0 & DBCR0_IDM)
 702                 || (new_debug->dbcr0 & DBCR0_IDM))
 703                         prime_debug_regs(new_debug);
 704 }
 705 EXPORT_SYMBOL_GPL(switch_booke_debug_regs);
 706 #else   /* !CONFIG_PPC_ADV_DEBUG_REGS */
 707 #ifndef CONFIG_HAVE_HW_BREAKPOINT
 708 static void set_debug_reg_defaults(struct thread_struct *thread)
 709 {
 710         thread->hw_brk.address = 0;
 711         thread->hw_brk.type = 0;
 712         set_breakpoint(&thread->hw_brk);
 713 }
 714 #endif /* !CONFIG_HAVE_HW_BREAKPOINT */
 715 #endif  /* CONFIG_PPC_ADV_DEBUG_REGS */
 716
 717 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
 718 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 719 {
 720         mtspr(SPRN_DAC1, dabr);
 721 #ifdef CONFIG_PPC_47x
 722         isync();
 723 #endif
 724         return 0;
 725 }
 726 #elif defined(CONFIG_PPC_BOOK3S)
 727 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 728 {
 729         mtspr(SPRN_DABR, dabr);
 730         if (cpu_has_feature(CPU_FTR_DABRX))
 731                 mtspr(SPRN_DABRX, dabrx);
 732         return 0;
 733 }
 734 #else
 735 static inline int __set_dabr(unsigned long dabr, unsigned long dabrx)
 736 {
 737         return -EINVAL;
 738 }
 739 #endif
 740
 741 static inline int set_dabr(struct arch_hw_breakpoint *brk)
 742 {
 743         unsigned long dabr, dabrx;
 744
 745         dabr = brk->address | (brk->type & HW_BRK_TYPE_DABR);
 746         dabrx = ((brk->type >> 3) & 0x7);
 747
 748         if (ppc_md.set_dabr)
 749                 return ppc_md.set_dabr(dabr, dabrx);
 750
 751         return __set_dabr(dabr, dabrx);
 752 }
 753
 754 static inline int set_dawr(struct arch_hw_breakpoint *brk)
 755 {
 756         unsigned long dawr, dawrx, mrd;
 757
 758         dawr = brk->address;
 759
 760         dawrx  = (brk->type & (HW_BRK_TYPE_READ | HW_BRK_TYPE_WRITE)) \
 761                                    << (63 - 58); //* read/write bits */
 762         dawrx |= ((brk->type & (HW_BRK_TYPE_TRANSLATE)) >> 2) \
 763                                    << (63 - 59); //* translate */
 764         dawrx |= (brk->type & (HW_BRK_TYPE_PRIV_ALL)) \
 765                                    >> 3; //* PRIM bits */
 766         /* dawr length is stored in field MDR bits 48:53.  Matches range in
 767            doublewords (64 bits) baised by -1 eg. 0b000000=1DW and
 768            0b111111=64DW.
 769            brk->len is in bytes.
 770            This aligns up to double word size, shifts and does the bias.
 771         */
 772         mrd = ((brk->len + 7) >> 3) - 1;
 773         dawrx |= (mrd & 0x3f) << (63 - 53);
 774
 775         if (ppc_md.set_dawr)
 776                 return ppc_md.set_dawr(dawr, dawrx);
 777         mtspr(SPRN_DAWR, dawr);
 778         mtspr(SPRN_DAWRX, dawrx);
 779         return 0;
 780 }
 781
 782 void __set_breakpoint(struct arch_hw_breakpoint *brk)
 783 {
 784         memcpy(this_cpu_ptr(&current_brk), brk, sizeof(*brk));
 785
 786         if (cpu_has_feature(CPU_FTR_DAWR))
 787                 set_dawr(brk);
 788         else
 789                 set_dabr(brk);
 790 }
 791
 792 void set_breakpoint(struct arch_hw_breakpoint *brk)
 793 {
 794         preempt_disable();
 795         __set_breakpoint(brk);
 796         preempt_enable();
 797 }
 798
 799 #ifdef CONFIG_PPC64
 800 DEFINE_PER_CPU(struct cpu_usage, cpu_usage_array);
 801 #endif
 802
 803 static inline bool hw_brk_match(struct arch_hw_breakpoint *a,
 804                               struct arch_hw_breakpoint *b)
 805 {
 806         if (a->address != b->address)
 807                 return false;
 808         if (a->type != b->type)
 809                 return false;
 810         if (a->len != b->len)
 811                 return false;
 812         return true;
 813 }
 814
 815 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
 816
 817 static inline bool tm_enabled(struct task_struct *tsk)
 818 {
 819         return tsk && tsk->thread.regs && (tsk->thread.regs->msr & MSR_TM);
 820 }
 821
 822 static void tm_reclaim_thread(struct thread_struct *thr,
 823                               struct thread_info *ti, uint8_t cause)
 824 {
 825         /*
 826          * Use the current MSR TM suspended bit to track if we have
 827          * checkpointed state outstanding.
 828          * On signal delivery, we'd normally reclaim the checkpointed
 829          * state to obtain stack pointer (see:get_tm_stackpointer()).
 830          * This will then directly return to userspace without going
 831          * through __switch_to(). However, if the stack frame is bad,
 832          * we need to exit this thread which calls __switch_to() which
 833          * will again attempt to reclaim the already saved tm state.
 834          * Hence we need to check that we've not already reclaimed
 835          * this state.
 836          * We do this using the current MSR, rather tracking it in
 837          * some specific thread_struct bit, as it has the additional
 838          * benefit of checking for a potential TM bad thing exception.
 839          */
 840         if (!MSR_TM_SUSPENDED(mfmsr()))
 841                 return;
 842
 843         /*
 844          * If we are in a transaction and FP is off then we can't have
 845          * used FP inside that transaction. Hence the checkpointed
 846          * state is the same as the live state. We need to copy the
 847          * live state to the checkpointed state so that when the
 848          * transaction is restored, the checkpointed state is correct
 849          * and the aborted transaction sees the correct state. We use
 850          * ckpt_regs.msr here as that's what tm_reclaim will use to
 851          * determine if it's going to write the checkpointed state or
 852          * not. So either this will write the checkpointed registers,
 853          * or reclaim will. Similarly for VMX.
 854          */
 855         if ((thr->ckpt_regs.msr & MSR_FP) == 0)
 856                 memcpy(&thr->ckfp_state, &thr->fp_state,
 857                        sizeof(struct thread_fp_state));
 858         if ((thr->ckpt_regs.msr & MSR_VEC) == 0)
 859                 memcpy(&thr->ckvr_state, &thr->vr_state,
 860                        sizeof(struct thread_vr_state));
 861
 862         giveup_all(container_of(thr, struct task_struct, thread));
 863
 864         tm_reclaim(thr, thr->ckpt_regs.msr, cause);
 865 }
 866
 867 void tm_reclaim_current(uint8_t cause)
 868 {
 869         tm_enable();
 870         tm_reclaim_thread(&current->thread, current_thread_info(), cause);
 871 }
 872
 873 static inline void tm_reclaim_task(struct task_struct *tsk)
 874 {
 875         /* We have to work out if we're switching from/to a task that's in the
 876          * middle of a transaction.
 877          *
 878          * In switching we need to maintain a 2nd register state as
 879          * oldtask->thread.ckpt_regs.  We tm_reclaim(oldproc); this saves the
 880          * checkpointed (tbegin) state in ckpt_regs, ckfp_state and
 881          * ckvr_state
 882          *
 883          * We also context switch (save) TFHAR/TEXASR/TFIAR in here.
 884          */
 885         struct thread_struct *thr = &tsk->thread;
 886
 887         if (!thr->regs)
 888                 return;
 889
 890         if (!MSR_TM_ACTIVE(thr->regs->msr))
 891                 goto out_and_saveregs;
 892
 893         TM_DEBUG("--- tm_reclaim on pid %d (NIP=%lx, "
 894                  "ccr=%lx, msr=%lx, trap=%lx)\n",
 895                  tsk->pid, thr->regs->nip,
 896                  thr->regs->ccr, thr->regs->msr,
 897                  thr->regs->trap);
 898
 899         tm_reclaim_thread(thr, task_thread_info(tsk), TM_CAUSE_RESCHED);
 900
 901         TM_DEBUG("--- tm_reclaim on pid %d complete\n",
 902                  tsk->pid);
 903
 904 out_and_saveregs:
 905         /* Always save the regs here, even if a transaction's not active.
 906          * This context-switches a thread's TM info SPRs.  We do it here to
 907          * be consistent with the restore path (in recheckpoint) which
 908          * cannot happen later in _switch().
 909          */
 910         tm_save_sprs(thr);
 911 }
 912
 913 extern void __tm_recheckpoint(struct thread_struct *thread,
 914                               unsigned long orig_msr);
 915
 916 void tm_recheckpoint(struct thread_struct *thread,
 917                      unsigned long orig_msr)
 918 {
 919         unsigned long flags;
 920
 921         if (!(thread->regs->msr & MSR_TM))
 922                 return;
 923
 924         /* We really can't be interrupted here as the TEXASR registers can't
 925          * change and later in the trecheckpoint code, we have a userspace R1.
 926          * So let's hard disable over this region.
 927          */
 928         local_irq_save(flags);
 929         hard_irq_disable();
 930
 931         /* The TM SPRs are restored here, so that TEXASR.FS can be set
 932          * before the trecheckpoint and no explosion occurs.
 933          */
 934         tm_restore_sprs(thread);
 935
 936         __tm_recheckpoint(thread, orig_msr);
 937
 938         local_irq_restore(flags);
 939 }
 940
 941 static inline void tm_recheckpoint_new_task(struct task_struct *new)
 942 {
 943         unsigned long msr;
 944
 945         if (!cpu_has_feature(CPU_FTR_TM))
 946                 return;
 947
 948         /* Recheckpoint the registers of the thread we're about to switch to.
 949          *
 950          * If the task was using FP, we non-lazily reload both the original and
 951          * the speculative FP register states.  This is because the kernel
 952          * doesn't see if/when a TM rollback occurs, so if we take an FP
 953          * unavailable later, we are unable to determine which set of FP regs
 954          * need to be restored.
 955          */
 956         if (!tm_enabled(new))
 957                 return;
 958
 959         if (!MSR_TM_ACTIVE(new->thread.regs->msr)){
 960                 tm_restore_sprs(&new->thread);
 961                 return;
 962         }
 963         msr = new->thread.ckpt_regs.msr;
 964         /* Recheckpoint to restore original checkpointed register state. */
 965         TM_DEBUG("*** tm_recheckpoint of pid %d "
 966                  "(new->msr 0x%lx, new->origmsr 0x%lx)\n",
 967                  new->pid, new->thread.regs->msr, msr);
 968
 969         tm_recheckpoint(&new->thread, msr);
 970
 971         /*
 972          * The checkpointed state has been restored but the live state has
 973          * not, ensure all the math functionality is turned off to trigger
 974          * restore_math() to reload.
 975          */
 976         new->thread.regs->msr &= ~(MSR_FP | MSR_VEC | MSR_VSX);
 977
 978         TM_DEBUG("*** tm_recheckpoint of pid %d complete "
 979                  "(kernel msr 0x%lx)\n",
 980                  new->pid, mfmsr());
 981 }
 982
 983 static inline void __switch_to_tm(struct task_struct *prev,
 984                 struct task_struct *new)
 985 {
 986         if (cpu_has_feature(CPU_FTR_TM)) {
 987                 if (tm_enabled(prev) || tm_enabled(new))
 988                         tm_enable();
 989
 990                 if (tm_enabled(prev)) {
 991                         prev->thread.load_tm++;
 992                         tm_reclaim_task(prev);
 993                         if (!MSR_TM_ACTIVE(prev->thread.regs->msr) && prev->thread.load_tm == 0)
 994                                 prev->thread.regs->msr &= ~MSR_TM;
 995                 }
 996
 997                 tm_recheckpoint_new_task(new);
 998         }
 999 }
1000
1001 /*
1002  * This is called if we are on the way out to userspace and the
1003  * TIF_RESTORE_TM flag is set.  It checks if we need to reload
1004  * FP and/or vector state and does so if necessary.
1005  * If userspace is inside a transaction (whether active or
1006  * suspended) and FP/VMX/VSX instructions have ever been enabled
1007  * inside that transaction, then we have to keep them enabled
1008  * and keep the FP/VMX/VSX state loaded while ever the transaction
1009  * continues.  The reason is that if we didn't, and subsequently
1010  * got a FP/VMX/VSX unavailable interrupt inside a transaction,
1011  * we don't know whether it's the same transaction, and thus we
1012  * don't know which of the checkpointed state and the transactional
1013  * state to use.
1014  */
1015 void restore_tm_state(struct pt_regs *regs)
1016 {
1017         unsigned long msr_diff;
1018
1019         /*
1020          * This is the only moment we should clear TIF_RESTORE_TM as
1021          * it is here that ckpt_regs.msr and pt_regs.msr become the same
1022          * again, anything else could lead to an incorrect ckpt_msr being
1023          * saved and therefore incorrect signal contexts.
1024          */
1025         clear_thread_flag(TIF_RESTORE_TM);
1026         if (!MSR_TM_ACTIVE(regs->msr))
1027                 return;
1028
1029         msr_diff = current->thread.ckpt_regs.msr & ~regs->msr;
1030         msr_diff &= MSR_FP | MSR_VEC | MSR_VSX;
1031
1032         /* Ensure that restore_math() will restore */
1033         if (msr_diff & MSR_FP)
1034                 current->thread.load_fp = 1;
1035 #ifdef CONFIG_ALTIVEC
1036         if (cpu_has_feature(CPU_FTR_ALTIVEC) && msr_diff & MSR_VEC)
1037                 current->thread.load_vec = 1;
1038 #endif
1039         restore_math(regs);
1040
1041         regs->msr |= msr_diff;
1042 }
1043
1044 #else
1045 #define tm_recheckpoint_new_task(new)
1046 #define __switch_to_tm(prev, new)
1047 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1048
1049 static inline void save_sprs(struct thread_struct *t)
1050 {
1051 #ifdef CONFIG_ALTIVEC
1052         if (cpu_has_feature(CPU_FTR_ALTIVEC))
1053                 t->vrsave = mfspr(SPRN_VRSAVE);
1054 #endif
1055 #ifdef CONFIG_PPC_BOOK3S_64
1056         if (cpu_has_feature(CPU_FTR_DSCR))
1057                 t->dscr = mfspr(SPRN_DSCR);
1058
1059         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1060                 t->bescr = mfspr(SPRN_BESCR);
1061                 t->ebbhr = mfspr(SPRN_EBBHR);
1062                 t->ebbrr = mfspr(SPRN_EBBRR);
1063
1064                 t->fscr = mfspr(SPRN_FSCR);
1065
1066                 /*
1067                  * Note that the TAR is not available for use in the kernel.
1068                  * (To provide this, the TAR should be backed up/restored on
1069                  * exception entry/exit instead, and be in pt_regs.  FIXME,
1070                  * this should be in pt_regs anyway (for debug).)
1071                  */
1072                 t->tar = mfspr(SPRN_TAR);
1073         }
1074
1075         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1076                 /* Conditionally save Load Monitor registers, if enabled */
1077                 if (t->fscr & FSCR_LM) {
1078                         t->lmrr = mfspr(SPRN_LMRR);
1079                         t->lmser = mfspr(SPRN_LMSER);
1080                 }
1081         }
1082 #endif
1083 }
1084
1085 static inline void restore_sprs(struct thread_struct *old_thread,
1086                                 struct thread_struct *new_thread)
1087 {
1088 #ifdef CONFIG_ALTIVEC
1089         if (cpu_has_feature(CPU_FTR_ALTIVEC) &&
1090             old_thread->vrsave != new_thread->vrsave)
1091                 mtspr(SPRN_VRSAVE, new_thread->vrsave);
1092 #endif
1093 #ifdef CONFIG_PPC_BOOK3S_64
1094         if (cpu_has_feature(CPU_FTR_DSCR)) {
1095                 u64 dscr = get_paca()->dscr_default;
1096                 if (new_thread->dscr_inherit)
1097                         dscr = new_thread->dscr;
1098
1099                 if (old_thread->dscr != dscr)
1100                         mtspr(SPRN_DSCR, dscr);
1101         }
1102
1103         if (cpu_has_feature(CPU_FTR_ARCH_207S)) {
1104                 if (old_thread->bescr != new_thread->bescr)
1105                         mtspr(SPRN_BESCR, new_thread->bescr);
1106                 if (old_thread->ebbhr != new_thread->ebbhr)
1107                         mtspr(SPRN_EBBHR, new_thread->ebbhr);
1108                 if (old_thread->ebbrr != new_thread->ebbrr)
1109                         mtspr(SPRN_EBBRR, new_thread->ebbrr);
1110
1111                 if (old_thread->fscr != new_thread->fscr)
1112                         mtspr(SPRN_FSCR, new_thread->fscr);
1113
1114                 if (old_thread->tar != new_thread->tar)
1115                         mtspr(SPRN_TAR, new_thread->tar);
1116         }
1117
1118         if (cpu_has_feature(CPU_FTR_ARCH_300)) {
1119                 /* Conditionally restore Load Monitor registers, if enabled */
1120                 if (new_thread->fscr & FSCR_LM) {
1121                         if (old_thread->lmrr != new_thread->lmrr)
1122                                 mtspr(SPRN_LMRR, new_thread->lmrr);
1123                         if (old_thread->lmser != new_thread->lmser)
1124                                 mtspr(SPRN_LMSER, new_thread->lmser);
1125                 }
1126         }
1127 #endif
1128 }
1129
1130 struct task_struct *__switch_to(struct task_struct *prev,
1131         struct task_struct *new)
1132 {
1133         struct thread_struct *new_thread, *old_thread;
1134         struct task_struct *last;
1135 #ifdef CONFIG_PPC_BOOK3S_64
1136         struct ppc64_tlb_batch *batch;
1137 #endif
1138
1139         new_thread = &new->thread;
1140         old_thread = &current->thread;
1141
1142         WARN_ON(!irqs_disabled());
1143
1144 #ifdef CONFIG_PPC64
1145         /*
1146          * Collect processor utilization data per process
1147          */
1148         if (firmware_has_feature(FW_FEATURE_SPLPAR)) {
1149                 struct cpu_usage *cu = this_cpu_ptr(&cpu_usage_array);
1150                 long unsigned start_tb, current_tb;
1151                 start_tb = old_thread->start_tb;
1152                 cu->current_tb = current_tb = mfspr(SPRN_PURR);
1153                 old_thread->accum_tb += (current_tb - start_tb);
1154                 new_thread->start_tb = current_tb;
1155         }
1156 #endif /* CONFIG_PPC64 */
1157
1158 #ifdef CONFIG_PPC_STD_MMU_64
1159         batch = this_cpu_ptr(&ppc64_tlb_batch);
1160         if (batch->active) {
1161                 current_thread_info()->local_flags |= _TLF_LAZY_MMU;
1162                 if (batch->index)
1163                         __flush_tlb_pending(batch);
1164                 batch->active = 0;
1165         }
1166 #endif /* CONFIG_PPC_STD_MMU_64 */
1167
1168 #ifdef CONFIG_PPC_ADV_DEBUG_REGS
1169         switch_booke_debug_regs(&new->thread.debug);
1170 #else
1171 /*
1172  * For PPC_BOOK3S_64, we use the hw-breakpoint interfaces that would
1173  * schedule DABR
1174  */
1175 #ifndef CONFIG_HAVE_HW_BREAKPOINT
1176         if (unlikely(!hw_brk_match(this_cpu_ptr(&current_brk), &new->thread.hw_brk)))
1177                 __set_breakpoint(&new->thread.hw_brk);
1178 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1179 #endif
1180
1181         /*
1182          * We need to save SPRs before treclaim/trecheckpoint as these will
1183          * change a number of them.
1184          */
1185         save_sprs(&prev->thread);
1186
1187         /* Save FPU, Altivec, VSX and SPE state */
1188         giveup_all(prev);
1189
1190         __switch_to_tm(prev, new);
1191
1192         /*
1193          * We can't take a PMU exception inside _switch() since there is a
1194          * window where the kernel stack SLB and the kernel stack are out
1195          * of sync. Hard disable here.
1196          */
1197         hard_irq_disable();
1198
1199         /*
1200          * Call restore_sprs() before calling _switch(). If we move it after
1201          * _switch() then we miss out on calling it for new tasks. The reason
1202          * for this is we manually create a stack frame for new tasks that
1203          * directly returns through ret_from_fork() or
1204          * ret_from_kernel_thread(). See copy_thread() for details.
1205          */
1206         restore_sprs(old_thread, new_thread);
1207
1208         last = _switch(old_thread, new_thread);
1209
1210 #ifdef CONFIG_PPC_STD_MMU_64
1211         if (current_thread_info()->local_flags & _TLF_LAZY_MMU) {
1212                 current_thread_info()->local_flags &= ~_TLF_LAZY_MMU;
1213                 batch = this_cpu_ptr(&ppc64_tlb_batch);
1214                 batch->active = 1;
1215         }
1216
1217         if (current_thread_info()->task->thread.regs)
1218                 restore_math(current_thread_info()->task->thread.regs);
1219 #endif /* CONFIG_PPC_STD_MMU_64 */
1220
1221         return last;
1222 }
1223
1224 static int instructions_to_print = 16;
1225
1226 static void show_instructions(struct pt_regs *regs)
1227 {
1228         int i;
1229         unsigned long pc = regs->nip - (instructions_to_print * 3 / 4 *
1230                         sizeof(int));
1231
1232         printk("Instruction dump:");
1233
1234         for (i = 0; i < instructions_to_print; i++) {
1235                 int instr;
1236
1237                 if (!(i % 8))
1238                         pr_cont("\n");
1239
1240 #if !defined(CONFIG_BOOKE)
1241                 /* If executing with the IMMU off, adjust pc rather
1242                  * than print XXXXXXXX.
1243                  */
1244                 if (!(regs->msr & MSR_IR))
1245                         pc = (unsigned long)phys_to_virt(pc);
1246 #endif
1247
1248                 if (!__kernel_text_address(pc) ||
1249                      probe_kernel_address((unsigned int __user *)pc, instr)) {
1250                         pr_cont("XXXXXXXX ");
1251                 } else {
1252                         if (regs->nip == pc)
1253                                 pr_cont("<%08x> ", instr);
1254                         else
1255                                 pr_cont("%08x ", instr);
1256                 }
1257
1258                 pc += sizeof(int);
1259         }
1260
1261         pr_cont("\n");
1262 }
1263
1264 struct regbit {
1265         unsigned long bit;
1266         const char *name;
1267 };
1268
1269 static struct regbit msr_bits[] = {
1270 #if defined(CONFIG_PPC64) && !defined(CONFIG_BOOKE)
1271         {MSR_SF,        "SF"},
1272         {MSR_HV,        "HV"},
1273 #endif
1274         {MSR_VEC,       "VEC"},
1275         {MSR_VSX,       "VSX"},
1276 #ifdef CONFIG_BOOKE
1277         {MSR_CE,        "CE"},
1278 #endif
1279         {MSR_EE,        "EE"},
1280         {MSR_PR,        "PR"},
1281         {MSR_FP,        "FP"},
1282         {MSR_ME,        "ME"},
1283 #ifdef CONFIG_BOOKE
1284         {MSR_DE,        "DE"},
1285 #else
1286         {MSR_SE,        "SE"},
1287         {MSR_BE,        "BE"},
1288 #endif
1289         {MSR_IR,        "IR"},
1290         {MSR_DR,        "DR"},
1291         {MSR_PMM,       "PMM"},
1292 #ifndef CONFIG_BOOKE
1293         {MSR_RI,        "RI"},
1294         {MSR_LE,        "LE"},
1295 #endif
1296         {0,             NULL}
1297 };
1298
1299 static void print_bits(unsigned long val, struct regbit *bits, const char *sep)
1300 {
1301         const char *s = "";
1302
1303         for (; bits->bit; ++bits)
1304                 if (val & bits->bit) {
1305                         pr_cont("%s%s", s, bits->name);
1306                         s = sep;
1307                 }
1308 }
1309
1310 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1311 static struct regbit msr_tm_bits[] = {
1312         {MSR_TS_T,      "T"},
1313         {MSR_TS_S,      "S"},
1314         {MSR_TM,        "E"},
1315         {0,             NULL}
1316 };
1317
1318 static void print_tm_bits(unsigned long val)
1319 {
1320 /*
1321  * This only prints something if at least one of the TM bit is set.
1322  * Inside the TM[], the output means:
1323  *   E: Enabled         (bit 32)
1324  *   S: Suspended       (bit 33)
1325  *   T: Transactional   (bit 34)
1326  */
1327         if (val & (MSR_TM | MSR_TS_S | MSR_TS_T)) {
1328                 pr_cont(",TM[");
1329                 print_bits(val, msr_tm_bits, "");
1330                 pr_cont("]");
1331         }
1332 }
1333 #else
1334 static void print_tm_bits(unsigned long val) {}
1335 #endif
1336
1337 static void print_msr_bits(unsigned long val)
1338 {
1339         pr_cont("<");
1340         print_bits(val, msr_bits, ",");
1341         print_tm_bits(val);
1342         pr_cont(">");
1343 }
1344
1345 #ifdef CONFIG_PPC64
1346 #define REG             "%016lx"
1347 #define REGS_PER_LINE   4
1348 #define LAST_VOLATILE   13
1349 #else
1350 #define REG             "%08lx"
1351 #define REGS_PER_LINE   8
1352 #define LAST_VOLATILE   12
1353 #endif
1354
1355 void show_regs(struct pt_regs * regs)
1356 {
1357         int i, trap;
1358
1359         show_regs_print_info(KERN_DEFAULT);
1360
1361         printk("NIP: "REG" LR: "REG" CTR: "REG"\n",
1362                regs->nip, regs->link, regs->ctr);
1363         printk("REGS: %p TRAP: %04lx   %s  (%s)\n",
1364                regs, regs->trap, print_tainted(), init_utsname()->release);
1365         printk("MSR: "REG" ", regs->msr);
1366         print_msr_bits(regs->msr);
1367         printk("  CR: %08lx  XER: %08lx\n", regs->ccr, regs->xer);
1368         trap = TRAP(regs);
1369         if ((regs->trap != 0xc00) && cpu_has_feature(CPU_FTR_CFAR))
1370                 pr_cont("CFAR: "REG" ", regs->orig_gpr3);
1371         if (trap == 0x200 || trap == 0x300 || trap == 0x600)
1372 #if defined(CONFIG_4xx) || defined(CONFIG_BOOKE)
1373                 pr_cont("DEAR: "REG" ESR: "REG" ", regs->dar, regs->dsisr);
1374 #else
1375                 pr_cont("DAR: "REG" DSISR: %08lx ", regs->dar, regs->dsisr);
1376 #endif
1377 #ifdef CONFIG_PPC64
1378         pr_cont("SOFTE: %ld ", regs->softe);
1379 #endif
1380 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1381         if (MSR_TM_ACTIVE(regs->msr))
1382                 pr_cont("\nPACATMSCRATCH: %016llx ", get_paca()->tm_scratch);
1383 #endif
1384
1385         for (i = 0;  i < 32;  i++) {
1386                 if ((i % REGS_PER_LINE) == 0)
1387                         pr_cont("\nGPR%02d: ", i);
1388                 pr_cont(REG " ", regs->gpr[i]);
1389                 if (i == LAST_VOLATILE && !FULL_REGS(regs))
1390                         break;
1391         }
1392         pr_cont("\n");
1393 #ifdef CONFIG_KALLSYMS
1394         /*
1395          * Lookup NIP late so we have the best change of getting the
1396          * above info out without failing
1397          */
1398         printk("NIP ["REG"] %pS\n", regs->nip, (void *)regs->nip);
1399         printk("LR ["REG"] %pS\n", regs->link, (void *)regs->link);
1400 #endif
1401         show_stack(current, (unsigned long *) regs->gpr[1]);
1402         if (!user_mode(regs))
1403                 show_instructions(regs);
1404 }
1405
1406 void flush_thread(void)
1407 {
1408 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1409         flush_ptrace_hw_breakpoint(current);
1410 #else /* CONFIG_HAVE_HW_BREAKPOINT */
1411         set_debug_reg_defaults(&current->thread);
1412 #endif /* CONFIG_HAVE_HW_BREAKPOINT */
1413 }
1414
1415 void
1416 release_thread(struct task_struct *t)
1417 {
1418 }
1419
1420 /*
1421  * this gets called so that we can store coprocessor state into memory and
1422  * copy the current task into the new thread.
1423  */
1424 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
1425 {
1426         flush_all_to_thread(src);
1427         /*
1428          * Flush TM state out so we can copy it.  __switch_to_tm() does this
1429          * flush but it removes the checkpointed state from the current CPU and
1430          * transitions the CPU out of TM mode.  Hence we need to call
1431          * tm_recheckpoint_new_task() (on the same task) to restore the
1432          * checkpointed state back and the TM mode.
1433          *
1434          * Can't pass dst because it isn't ready. Doesn't matter, passing
1435          * dst is only important for __switch_to()
1436          */
1437         __switch_to_tm(src, src);
1438
1439         *dst = *src;
1440
1441         clear_task_ebb(dst);
1442
1443         return 0;
1444 }
1445
1446 static void setup_ksp_vsid(struct task_struct *p, unsigned long sp)
1447 {
1448 #ifdef CONFIG_PPC_STD_MMU_64
1449         unsigned long sp_vsid;
1450         unsigned long llp = mmu_psize_defs[mmu_linear_psize].sllp;
1451
1452         if (radix_enabled())
1453                 return;
1454
1455         if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
1456                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_1T)
1457                         << SLB_VSID_SHIFT_1T;
1458         else
1459                 sp_vsid = get_kernel_vsid(sp, MMU_SEGSIZE_256M)
1460                         << SLB_VSID_SHIFT;
1461         sp_vsid |= SLB_VSID_KERNEL | llp;
1462         p->thread.ksp_vsid = sp_vsid;
1463 #endif
1464 }
1465
1466 /*
1467  * Copy a thread..
1468  */
1469
1470 /*
1471  * Copy architecture-specific thread state
1472  */
1473 int copy_thread(unsigned long clone_flags, unsigned long usp,
1474                 unsigned long kthread_arg, struct task_struct *p)
1475 {
1476         struct pt_regs *childregs, *kregs;
1477         extern void ret_from_fork(void);
1478         extern void ret_from_kernel_thread(void);
1479         void (*f)(void);
1480         unsigned long sp = (unsigned long)task_stack_page(p) + THREAD_SIZE;
1481         struct thread_info *ti = task_thread_info(p);
1482
1483         klp_init_thread_info(ti);
1484
1485         /* Copy registers */
1486         sp -= sizeof(struct pt_regs);
1487         childregs = (struct pt_regs *) sp;
1488         if (unlikely(p->flags & PF_KTHREAD)) {
1489                 /* kernel thread */
1490                 memset(childregs, 0, sizeof(struct pt_regs));
1491                 childregs->gpr[1] = sp + sizeof(struct pt_regs);
1492                 /* function */
1493                 if (usp)
1494                         childregs->gpr[14] = ppc_function_entry((void *)usp);
1495 #ifdef CONFIG_PPC64
1496                 clear_tsk_thread_flag(p, TIF_32BIT);
1497                 childregs->softe = 1;
1498 #endif
1499                 childregs->gpr[15] = kthread_arg;
1500                 p->thread.regs = NULL;  /* no user register state */
1501                 ti->flags |= _TIF_RESTOREALL;
1502                 f = ret_from_kernel_thread;
1503         } else {
1504                 /* user thread */
1505                 struct pt_regs *regs = current_pt_regs();
1506                 CHECK_FULL_REGS(regs);
1507                 *childregs = *regs;
1508                 if (usp)
1509                         childregs->gpr[1] = usp;
1510                 p->thread.regs = childregs;
1511                 childregs->gpr[3] = 0;  /* Result from fork() */
1512                 if (clone_flags & CLONE_SETTLS) {
1513 #ifdef CONFIG_PPC64
1514                         if (!is_32bit_task())
1515                                 childregs->gpr[13] = childregs->gpr[6];
1516                         else
1517 #endif
1518                                 childregs->gpr[2] = childregs->gpr[6];
1519                 }
1520
1521                 f = ret_from_fork;
1522         }
1523         childregs->msr &= ~(MSR_FP|MSR_VEC|MSR_VSX);
1524         sp -= STACK_FRAME_OVERHEAD;
1525
1526         /*
1527          * The way this works is that at some point in the future
1528          * some task will call _switch to switch to the new task.
1529          * That will pop off the stack frame created below and start
1530          * the new task running at ret_from_fork.  The new task will
1531          * do some house keeping and then return from the fork or clone
1532          * system call, using the stack frame created above.
1533          */
1534         ((unsigned long *)sp)[0] = 0;
1535         sp -= sizeof(struct pt_regs);
1536         kregs = (struct pt_regs *) sp;
1537         sp -= STACK_FRAME_OVERHEAD;
1538         p->thread.ksp = sp;
1539 #ifdef CONFIG_PPC32
1540         p->thread.ksp_limit = (unsigned long)task_stack_page(p) +
1541                                 _ALIGN_UP(sizeof(struct thread_info), 16);
1542 #endif
1543 #ifdef CONFIG_HAVE_HW_BREAKPOINT
1544         p->thread.ptrace_bps[0] = NULL;
1545 #endif
1546
1547         p->thread.fp_save_area = NULL;
1548 #ifdef CONFIG_ALTIVEC
1549         p->thread.vr_save_area = NULL;
1550 #endif
1551
1552         setup_ksp_vsid(p, sp);
1553
1554 #ifdef CONFIG_PPC64
1555         if (cpu_has_feature(CPU_FTR_DSCR)) {
1556                 p->thread.dscr_inherit = current->thread.dscr_inherit;
1557                 p->thread.dscr = mfspr(SPRN_DSCR);
1558         }
1559         if (cpu_has_feature(CPU_FTR_HAS_PPR))
1560                 p->thread.ppr = INIT_PPR;
1561 #endif
1562         kregs->nip = ppc_function_entry(f);
1563         return 0;
1564 }
1565
1566 /*
1567  * Set up a thread for executing a new program
1568  */
1569 void start_thread(struct pt_regs *regs, unsigned long start, unsigned long sp)
1570 {
1571 #ifdef CONFIG_PPC64
1572         unsigned long load_addr = regs->gpr[2]; /* saved by ELF_PLAT_INIT */
1573 #endif
1574
1575         /*
1576          * If we exec out of a kernel thread then thread.regs will not be
1577          * set.  Do it now.
1578          */
1579         if (!current->thread.regs) {
1580                 struct pt_regs *regs = task_stack_page(current) + THREAD_SIZE;
1581                 current->thread.regs = regs - 1;
1582         }
1583
1584 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1585         /*
1586          * Clear any transactional state, we're exec()ing. The cause is
1587          * not important as there will never be a recheckpoint so it's not
1588          * user visible.
1589          */
1590         if (MSR_TM_SUSPENDED(mfmsr()))
1591                 tm_reclaim_current(0);
1592 #endif
1593
1594         memset(regs->gpr, 0, sizeof(regs->gpr));
1595         regs->ctr = 0;
1596         regs->link = 0;
1597         regs->xer = 0;
1598         regs->ccr = 0;
1599         regs->gpr[1] = sp;
1600
1601         /*
1602          * We have just cleared all the nonvolatile GPRs, so make
1603          * FULL_REGS(regs) return true.  This is necessary to allow
1604          * ptrace to examine the thread immediately after exec.
1605          */
1606         regs->trap &= ~1UL;
1607
1608 #ifdef CONFIG_PPC32
1609         regs->mq = 0;
1610         regs->nip = start;
1611         regs->msr = MSR_USER;
1612 #else
1613         if (!is_32bit_task()) {
1614                 unsigned long entry;
1615
1616                 if (is_elf2_task()) {
1617                         /* Look ma, no function descriptors! */
1618                         entry = start;
1619
1620                         /*
1621                          * Ulrich says:
1622                          *   The latest iteration of the ABI requires that when
1623                          *   calling a function (at its global entry point),
1624                          *   the caller must ensure r12 holds the entry point
1625                          *   address (so that the function can quickly
1626                          *   establish addressability).
1627                          */
1628                         regs->gpr[12] = start;
1629                         /* Make sure that's restored on entry to userspace. */
1630                         set_thread_flag(TIF_RESTOREALL);
1631                 } else {
1632                         unsigned long toc;
1633
1634                         /* start is a relocated pointer to the function
1635                          * descriptor for the elf _start routine.  The first
1636                          * entry in the function descriptor is the entry
1637                          * address of _start and the second entry is the TOC
1638                          * value we need to use.
1639                          */
1640                         __get_user(entry, (unsigned long __user *)start);
1641                         __get_user(toc, (unsigned long __user *)start+1);
1642
1643                         /* Check whether the e_entry function descriptor entries
1644                          * need to be relocated before we can use them.
1645                          */
1646                         if (load_addr != 0) {
1647                                 entry += load_addr;
1648                                 toc   += load_addr;
1649                         }
1650                         regs->gpr[2] = toc;
1651                 }
1652                 regs->nip = entry;
1653                 regs->msr = MSR_USER64;
1654         } else {
1655                 regs->nip = start;
1656                 regs->gpr[2] = 0;
1657                 regs->msr = MSR_USER32;
1658         }
1659 #endif
1660 #ifdef CONFIG_VSX
1661         current->thread.used_vsr = 0;
1662 #endif
1663         current->thread.load_fp = 0;
1664         memset(&current->thread.fp_state, 0, sizeof(current->thread.fp_state));
1665         current->thread.fp_save_area = NULL;
1666 #ifdef CONFIG_ALTIVEC
1667         memset(&current->thread.vr_state, 0, sizeof(current->thread.vr_state));
1668         current->thread.vr_state.vscr.u[3] = 0x00010000; /* Java mode disabled */
1669         current->thread.vr_save_area = NULL;
1670         current->thread.vrsave = 0;
1671         current->thread.used_vr = 0;
1672         current->thread.load_vec = 0;
1673 #endif /* CONFIG_ALTIVEC */
1674 #ifdef CONFIG_SPE
1675         memset(current->thread.evr, 0, sizeof(current->thread.evr));
1676         current->thread.acc = 0;
1677         current->thread.spefscr = 0;
1678         current->thread.used_spe = 0;
1679 #endif /* CONFIG_SPE */
1680 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
1681         current->thread.tm_tfhar = 0;
1682         current->thread.tm_texasr = 0;
1683         current->thread.tm_tfiar = 0;
1684         current->thread.load_tm = 0;
1685 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
1686 }
1687 EXPORT_SYMBOL(start_thread);
1688
1689 #define PR_FP_ALL_EXCEPT (PR_FP_EXC_DIV | PR_FP_EXC_OVF | PR_FP_EXC_UND \
1690                 | PR_FP_EXC_RES | PR_FP_EXC_INV)
1691
1692 int set_fpexc_mode(struct task_struct *tsk, unsigned int val)
1693 {
1694         struct pt_regs *regs = tsk->thread.regs;
1695
1696         /* This is a bit hairy.  If we are an SPE enabled  processor
1697          * (have embedded fp) we store the IEEE exception enable flags in
1698          * fpexc_mode.  fpexc_mode is also used for setting FP exception
1699          * mode (asyn, precise, disabled) for 'Classic' FP. */
1700         if (val & PR_FP_EXC_SW_ENABLE) {
1701 #ifdef CONFIG_SPE
1702                 if (cpu_has_feature(CPU_FTR_SPE)) {
1703                         /*
1704                          * When the sticky exception bits are set
1705                          * directly by userspace, it must call prctl
1706                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1707                          * in the existing prctl settings) or
1708                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1709                          * the bits being set).  <fenv.h> functions
1710                          * saving and restoring the whole
1711                          * floating-point environment need to do so
1712                          * anyway to restore the prctl settings from
1713                          * the saved environment.
1714                          */
1715                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1716                         tsk->thread.fpexc_mode = val &
1717                                 (PR_FP_EXC_SW_ENABLE | PR_FP_ALL_EXCEPT);
1718                         return 0;
1719                 } else {
1720                         return -EINVAL;
1721                 }
1722 #else
1723                 return -EINVAL;
1724 #endif
1725         }
1726
1727         /* on a CONFIG_SPE this does not hurt us.  The bits that
1728          * __pack_fe01 use do not overlap with bits used for
1729          * PR_FP_EXC_SW_ENABLE.  Additionally, the MSR[FE0,FE1] bits
1730          * on CONFIG_SPE implementations are reserved so writing to
1731          * them does not change anything */
1732         if (val > PR_FP_EXC_PRECISE)
1733                 return -EINVAL;
1734         tsk->thread.fpexc_mode = __pack_fe01(val);
1735         if (regs != NULL && (regs->msr & MSR_FP) != 0)
1736                 regs->msr = (regs->msr & ~(MSR_FE0|MSR_FE1))
1737                         | tsk->thread.fpexc_mode;
1738         return 0;
1739 }
1740
1741 int get_fpexc_mode(struct task_struct *tsk, unsigned long adr)
1742 {
1743         unsigned int val;
1744
1745         if (tsk->thread.fpexc_mode & PR_FP_EXC_SW_ENABLE)
1746 #ifdef CONFIG_SPE
1747                 if (cpu_has_feature(CPU_FTR_SPE)) {
1748                         /*
1749                          * When the sticky exception bits are set
1750                          * directly by userspace, it must call prctl
1751                          * with PR_GET_FPEXC (with PR_FP_EXC_SW_ENABLE
1752                          * in the existing prctl settings) or
1753                          * PR_SET_FPEXC (with PR_FP_EXC_SW_ENABLE in
1754                          * the bits being set).  <fenv.h> functions
1755                          * saving and restoring the whole
1756                          * floating-point environment need to do so
1757                          * anyway to restore the prctl settings from
1758                          * the saved environment.
1759                          */
1760                         tsk->thread.spefscr_last = mfspr(SPRN_SPEFSCR);
1761                         val = tsk->thread.fpexc_mode;
1762                 } else
1763                         return -EINVAL;
1764 #else
1765                 return -EINVAL;
1766 #endif
1767         else
1768                 val = __unpack_fe01(tsk->thread.fpexc_mode);
1769         return put_user(val, (unsigned int __user *) adr);
1770 }
1771
1772 int set_endian(struct task_struct *tsk, unsigned int val)
1773 {
1774         struct pt_regs *regs = tsk->thread.regs;
1775
1776         if ((val == PR_ENDIAN_LITTLE && !cpu_has_feature(CPU_FTR_REAL_LE)) ||
1777             (val == PR_ENDIAN_PPC_LITTLE && !cpu_has_feature(CPU_FTR_PPC_LE)))
1778                 return -EINVAL;
1779
1780         if (regs == NULL)
1781                 return -EINVAL;
1782
1783         if (val == PR_ENDIAN_BIG)
1784                 regs->msr &= ~MSR_LE;
1785         else if (val == PR_ENDIAN_LITTLE || val == PR_ENDIAN_PPC_LITTLE)
1786                 regs->msr |= MSR_LE;
1787         else
1788                 return -EINVAL;
1789
1790         return 0;
1791 }
1792
1793 int get_endian(struct task_struct *tsk, unsigned long adr)
1794 {
1795         struct pt_regs *regs = tsk->thread.regs;
1796         unsigned int val;
1797
1798         if (!cpu_has_feature(CPU_FTR_PPC_LE) &&
1799             !cpu_has_feature(CPU_FTR_REAL_LE))
1800                 return -EINVAL;
1801
1802         if (regs == NULL)
1803                 return -EINVAL;
1804
1805         if (regs->msr & MSR_LE) {
1806                 if (cpu_has_feature(CPU_FTR_REAL_LE))
1807                         val = PR_ENDIAN_LITTLE;
1808                 else
1809                         val = PR_ENDIAN_PPC_LITTLE;
1810         } else
1811                 val = PR_ENDIAN_BIG;
1812
1813         return put_user(val, (unsigned int __user *)adr);
1814 }
1815
1816 int set_unalign_ctl(struct task_struct *tsk, unsigned int val)
1817 {
1818         tsk->thread.align_ctl = val;
1819         return 0;
1820 }
1821
1822 int get_unalign_ctl(struct task_struct *tsk, unsigned long adr)
1823 {
1824         return put_user(tsk->thread.align_ctl, (unsigned int __user *)adr);
1825 }
1826
1827 static inline int valid_irq_stack(unsigned long sp, struct task_struct *p,
1828                                   unsigned long nbytes)
1829 {
1830         unsigned long stack_page;
1831         unsigned long cpu = task_cpu(p);
1832
1833         /*
1834          * Avoid crashing if the stack has overflowed and corrupted
1835          * task_cpu(p), which is in the thread_info struct.
1836          */
1837         if (cpu < NR_CPUS && cpu_possible(cpu)) {
1838                 stack_page = (unsigned long) hardirq_ctx[cpu];
1839                 if (sp >= stack_page + sizeof(struct thread_struct)
1840                     && sp <= stack_page + THREAD_SIZE - nbytes)
1841                         return 1;
1842
1843                 stack_page = (unsigned long) softirq_ctx[cpu];
1844                 if (sp >= stack_page + sizeof(struct thread_struct)
1845                     && sp <= stack_page + THREAD_SIZE - nbytes)
1846                         return 1;
1847         }
1848         return 0;
1849 }
1850
1851 int validate_sp(unsigned long sp, struct task_struct *p,
1852                        unsigned long nbytes)
1853 {
1854         unsigned long stack_page = (unsigned long)task_stack_page(p);
1855
1856         if (sp >= stack_page + sizeof(struct thread_struct)
1857             && sp <= stack_page + THREAD_SIZE - nbytes)
1858                 return 1;
1859
1860         return valid_irq_stack(sp, p, nbytes);
1861 }
1862
1863 EXPORT_SYMBOL(validate_sp);
1864
1865 unsigned long get_wchan(struct task_struct *p)
1866 {
1867         unsigned long ip, sp;
1868         int count = 0;
1869
1870         if (!p || p == current || p->state == TASK_RUNNING)
1871                 return 0;
1872
1873         sp = p->thread.ksp;
1874         if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1875                 return 0;
1876
1877         do {
1878                 sp = *(unsigned long *)sp;
1879                 if (!validate_sp(sp, p, STACK_FRAME_OVERHEAD))
1880                         return 0;
1881                 if (count > 0) {
1882                         ip = ((unsigned long *)sp)[STACK_FRAME_LR_SAVE];
1883                         if (!in_sched_functions(ip))
1884                                 return ip;
1885                 }
1886         } while (count++ < 16);
1887         return 0;
1888 }
1889
1890 static int kstack_depth_to_print = CONFIG_PRINT_STACK_DEPTH;
1891
1892 void show_stack(struct task_struct *tsk, unsigned long *stack)
1893 {
1894         unsigned long sp, ip, lr, newsp;
1895         int count = 0;
1896         int firstframe = 1;
1897 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1898         int curr_frame = current->curr_ret_stack;
1899         extern void return_to_handler(void);
1900         unsigned long rth = (unsigned long)return_to_handler;
1901 #endif
1902
1903         sp = (unsigned long) stack;
1904         if (tsk == NULL)
1905                 tsk = current;
1906         if (sp == 0) {
1907                 if (tsk == current)
1908                         sp = current_stack_pointer();
1909                 else
1910                         sp = tsk->thread.ksp;
1911         }
1912
1913         lr = 0;
1914         printk("Call Trace:\n");
1915         do {
1916                 if (!validate_sp(sp, tsk, STACK_FRAME_OVERHEAD))
1917                         return;
1918
1919                 stack = (unsigned long *) sp;
1920                 newsp = stack[0];
1921                 ip = stack[STACK_FRAME_LR_SAVE];
1922                 if (!firstframe || ip != lr) {
1923                         printk("["REG"] ["REG"] %pS", sp, ip, (void *)ip);
1924 #ifdef CONFIG_FUNCTION_GRAPH_TRACER
1925                         if ((ip == rth) && curr_frame >= 0) {
1926                                 pr_cont(" (%pS)",
1927                                        (void *)current->ret_stack[curr_frame].ret);
1928                                 curr_frame--;
1929                         }
1930 #endif
1931                         if (firstframe)
1932                                 pr_cont(" (unreliable)");
1933                         pr_cont("\n");
1934                 }
1935                 firstframe = 0;
1936
1937                 /*
1938                  * See if this is an exception frame.
1939                  * We look for the "regshere" marker in the current frame.
1940                  */
1941                 if (validate_sp(sp, tsk, STACK_INT_FRAME_SIZE)
1942                     && stack[STACK_FRAME_MARKER] == STACK_FRAME_REGS_MARKER) {
1943                         struct pt_regs *regs = (struct pt_regs *)
1944                                 (sp + STACK_FRAME_OVERHEAD);
1945                         lr = regs->link;
1946                         printk("--- interrupt: %lx at %pS\n    LR = %pS\n",
1947                                regs->trap, (void *)regs->nip, (void *)lr);
1948                         firstframe = 1;
1949                 }
1950
1951                 sp = newsp;
1952         } while (count++ < kstack_depth_to_print);
1953 }
1954
1955 #ifdef CONFIG_PPC64
1956 /* Called with hard IRQs off */
1957 void notrace __ppc64_runlatch_on(void)
1958 {
1959         struct thread_info *ti = current_thread_info();
1960         unsigned long ctrl;
1961
1962         ctrl = mfspr(SPRN_CTRLF);
1963         ctrl |= CTRL_RUNLATCH;
1964         mtspr(SPRN_CTRLT, ctrl);
1965
1966         ti->local_flags |= _TLF_RUNLATCH;
1967 }
1968
1969 /* Called with hard IRQs off */
1970 void notrace __ppc64_runlatch_off(void)
1971 {
1972         struct thread_info *ti = current_thread_info();
1973         unsigned long ctrl;
1974
1975         ti->local_flags &= ~_TLF_RUNLATCH;
1976
1977         ctrl = mfspr(SPRN_CTRLF);
1978         ctrl &= ~CTRL_RUNLATCH;
1979         mtspr(SPRN_CTRLT, ctrl);
1980 }
1981 #endif /* CONFIG_PPC64 */
1982
1983 unsigned long arch_align_stack(unsigned long sp)
1984 {
1985         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
1986                 sp -= get_random_int() & ~PAGE_MASK;
1987         return sp & ~0xf;
1988 }
1989
1990 static inline unsigned long brk_rnd(void)
1991 {
1992         unsigned long rnd = 0;
1993
1994         /* 8MB for 32bit, 1GB for 64bit */
1995         if (is_32bit_task())
1996                 rnd = (get_random_long() % (1UL<<(23-PAGE_SHIFT)));
1997         else
1998                 rnd = (get_random_long() % (1UL<<(30-PAGE_SHIFT)));
1999
2000         return rnd << PAGE_SHIFT;
2001 }
2002
2003 unsigned long arch_randomize_brk(struct mm_struct *mm)
2004 {
2005         unsigned long base = mm->brk;
2006         unsigned long ret;
2007
2008 #ifdef CONFIG_PPC_STD_MMU_64
2009         /*
2010          * If we are using 1TB segments and we are allowed to randomise
2011          * the heap, we can put it above 1TB so it is backed by a 1TB
2012          * segment. Otherwise the heap will be in the bottom 1TB
2013          * which always uses 256MB segments and this may result in a
2014          * performance penalty. We don't need to worry about radix. For
2015          * radix, mmu_highuser_ssize remains unchanged from 256MB.
2016          */
2017         if (!is_32bit_task() && (mmu_highuser_ssize == MMU_SEGSIZE_1T))
2018                 base = max_t(unsigned long, mm->brk, 1UL << SID_SHIFT_1T);
2019 #endif
2020
2021         ret = PAGE_ALIGN(base + brk_rnd());
2022
2023         if (ret < mm->brk)
2024                 return mm->brk;
2025
2026         return ret;
2027 }
2028