1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Contains common pci routines for ALL ppc platform
4 * (based on pci_32.c and pci_64.c)
6 * Port for PPC64 David Engebretsen, IBM Corp.
7 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
9 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
10 * Rework, based on alpha PCI code.
12 * Common pmac/prep/chrp pci routines. -- Cort
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/export.h>
21 #include <linux/of_address.h>
22 #include <linux/of_pci.h>
24 #include <linux/shmem_fs.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
30 #include <linux/vgaarb.h>
31 #include <linux/numa.h>
33 #include <asm/processor.h>
36 #include <asm/pci-bridge.h>
37 #include <asm/byteorder.h>
38 #include <asm/machdep.h>
39 #include <asm/ppc-pci.h>
42 #include "../../../drivers/pci/pci.h"
44 /* hose_spinlock protects accesses to the the phb_bitmap. */
45 static DEFINE_SPINLOCK(hose_spinlock);
48 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
49 #define MAX_PHBS 0x10000
52 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
53 * Accesses to this bitmap should be protected by hose_spinlock.
55 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
57 /* ISA Memory physical address */
58 resource_size_t isa_mem_base;
59 EXPORT_SYMBOL(isa_mem_base);
62 static const struct dma_map_ops *pci_dma_ops;
64 void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
66 pci_dma_ops = dma_ops;
69 static int get_phb_number(struct device_node *dn)
75 * Try fixed PHB numbering first, by checking archs and reading
76 * the respective device-tree properties. Firstly, try reading
77 * standard "linux,pci-domain", then try reading "ibm,opal-phbid"
78 * (only present in powernv OPAL environment), then try device-tree
79 * alias and as the last try to use lower bits of "reg" property.
81 ret = of_get_pci_domain_nr(dn);
87 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
90 ret = of_alias_get_id(dn, "pci");
98 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
103 phb_id = (int)(prop & (MAX_PHBS - 1));
105 spin_lock(&hose_spinlock);
107 /* We need to be sure to not use the same PHB number twice. */
108 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
111 /* If everything fails then fallback to dynamic PHB numbering. */
112 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
113 BUG_ON(phb_id >= MAX_PHBS);
114 set_bit(phb_id, phb_bitmap);
117 spin_unlock(&hose_spinlock);
122 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
124 struct pci_controller *phb;
126 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
130 phb->global_number = get_phb_number(dev);
132 spin_lock(&hose_spinlock);
133 list_add_tail(&phb->list_node, &hose_list);
134 spin_unlock(&hose_spinlock);
137 phb->is_dynamic = slab_is_available();
140 int nid = of_node_to_nid(dev);
142 if (nid < 0 || !node_online(nid))
145 PHB_SET_NODE(phb, nid);
150 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
152 void pcibios_free_controller(struct pci_controller *phb)
154 spin_lock(&hose_spinlock);
156 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
157 if (phb->global_number < MAX_PHBS)
158 clear_bit(phb->global_number, phb_bitmap);
160 list_del(&phb->list_node);
161 spin_unlock(&hose_spinlock);
166 EXPORT_SYMBOL_GPL(pcibios_free_controller);
169 * This function is used to call pcibios_free_controller()
170 * in a deferred manner: a callback from the PCI subsystem.
172 * _*DO NOT*_ call pcibios_free_controller() explicitly if
173 * this is used (or it may access an invalid *phb pointer).
175 * The callback occurs when all references to the root bus
176 * are dropped (e.g., child buses/devices and their users).
178 * It's called as .release_fn() of 'struct pci_host_bridge'
179 * which is associated with the 'struct pci_controller.bus'
180 * (root bus) - it expects .release_data to hold a pointer
181 * to 'struct pci_controller'.
183 * In order to use it, register .release_fn()/release_data
186 * pci_set_host_bridge_release(bridge,
187 * pcibios_free_controller_deferred
190 * e.g. in the pcibios_root_bridge_prepare() callback from
191 * pci_create_root_bus().
193 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
195 struct pci_controller *phb = (struct pci_controller *)
196 bridge->release_data;
198 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
200 pcibios_free_controller(phb);
202 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
205 * The function is used to return the minimal alignment
206 * for memory or I/O windows of the associated P2P bridge.
207 * By default, 4KiB alignment for I/O windows and 1MiB for
210 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
213 struct pci_controller *phb = pci_bus_to_host(bus);
215 if (phb->controller_ops.window_alignment)
216 return phb->controller_ops.window_alignment(bus, type);
219 * PCI core will figure out the default
220 * alignment: 4KiB for I/O and 1MiB for
226 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
228 struct pci_controller *hose = pci_bus_to_host(bus);
230 if (hose->controller_ops.setup_bridge)
231 hose->controller_ops.setup_bridge(bus, type);
234 void pcibios_reset_secondary_bus(struct pci_dev *dev)
236 struct pci_controller *phb = pci_bus_to_host(dev->bus);
238 if (phb->controller_ops.reset_secondary_bus) {
239 phb->controller_ops.reset_secondary_bus(dev);
243 pci_reset_secondary_bus(dev);
246 resource_size_t pcibios_default_alignment(void)
248 if (ppc_md.pcibios_default_alignment)
249 return ppc_md.pcibios_default_alignment();
254 #ifdef CONFIG_PCI_IOV
255 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
257 if (ppc_md.pcibios_iov_resource_alignment)
258 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
260 return pci_iov_resource_size(pdev, resno);
263 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
265 if (ppc_md.pcibios_sriov_enable)
266 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
271 int pcibios_sriov_disable(struct pci_dev *pdev)
273 if (ppc_md.pcibios_sriov_disable)
274 return ppc_md.pcibios_sriov_disable(pdev);
279 #endif /* CONFIG_PCI_IOV */
281 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
284 return hose->pci_io_size;
286 return resource_size(&hose->io_resource);
290 int pcibios_vaddr_is_ioport(void __iomem *address)
293 struct pci_controller *hose;
294 resource_size_t size;
296 spin_lock(&hose_spinlock);
297 list_for_each_entry(hose, &hose_list, list_node) {
298 size = pcibios_io_size(hose);
299 if (address >= hose->io_base_virt &&
300 address < (hose->io_base_virt + size)) {
305 spin_unlock(&hose_spinlock);
309 unsigned long pci_address_to_pio(phys_addr_t address)
311 struct pci_controller *hose;
312 resource_size_t size;
313 unsigned long ret = ~0;
315 spin_lock(&hose_spinlock);
316 list_for_each_entry(hose, &hose_list, list_node) {
317 size = pcibios_io_size(hose);
318 if (address >= hose->io_base_phys &&
319 address < (hose->io_base_phys + size)) {
321 (unsigned long)hose->io_base_virt - _IO_BASE;
322 ret = base + (address - hose->io_base_phys);
326 spin_unlock(&hose_spinlock);
330 EXPORT_SYMBOL_GPL(pci_address_to_pio);
333 * Return the domain number for this bus.
335 int pci_domain_nr(struct pci_bus *bus)
337 struct pci_controller *hose = pci_bus_to_host(bus);
339 return hose->global_number;
341 EXPORT_SYMBOL(pci_domain_nr);
343 /* This routine is meant to be used early during boot, when the
344 * PCI bus numbers have not yet been assigned, and you need to
345 * issue PCI config cycles to an OF device.
346 * It could also be used to "fix" RTAS config cycles if you want
347 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
350 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
353 struct pci_controller *hose, *tmp;
354 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
355 if (hose->dn == node)
362 struct pci_controller *pci_find_controller_for_domain(int domain_nr)
364 struct pci_controller *hose;
366 list_for_each_entry(hose, &hose_list, list_node)
367 if (hose->global_number == domain_nr)
374 * Reads the interrupt pin to determine if interrupt is use by card.
375 * If the interrupt is used, then gets the interrupt line from the
376 * openfirmware and sets it in the pci_dev and pci_config line.
378 static int pci_read_irq_line(struct pci_dev *pci_dev)
382 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
384 /* Try to get a mapping from the device-tree */
385 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
389 /* If that fails, lets fallback to what is in the config
390 * space and map that through the default controller. We
391 * also set the type to level low since that's what PCI
392 * interrupts are. If your platform does differently, then
393 * either provide a proper interrupt tree or don't use this
396 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
400 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
401 line == 0xff || line == 0) {
404 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
407 virq = irq_create_mapping(NULL, line);
409 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
413 pr_debug(" Failed to map !\n");
417 pr_debug(" Mapped to linux irq %d\n", virq);
425 * Platform support for /proc/bus/pci/X/Y mmap()s.
428 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
430 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
431 resource_size_t ioaddr = pci_resource_start(pdev, bar);
436 /* Convert to an offset within this PCI controller */
437 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
439 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
444 * This one is used by /dev/mem and fbdev who have no clue about the
445 * PCI device, it tries to find the PCI device first and calls the
448 pgprot_t pci_phys_mem_access_prot(struct file *file,
453 struct pci_dev *pdev = NULL;
454 struct resource *found = NULL;
455 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
458 if (page_is_ram(pfn))
461 prot = pgprot_noncached(prot);
462 for_each_pci_dev(pdev) {
463 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
464 struct resource *rp = &pdev->resource[i];
465 int flags = rp->flags;
467 /* Active and same type? */
468 if ((flags & IORESOURCE_MEM) == 0)
470 /* In the range of this resource? */
471 if (offset < (rp->start & PAGE_MASK) ||
481 if (found->flags & IORESOURCE_PREFETCH)
482 prot = pgprot_noncached_wc(prot);
486 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
487 (unsigned long long)offset, pgprot_val(prot));
492 /* This provides legacy IO read access on a bus */
493 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
495 unsigned long offset;
496 struct pci_controller *hose = pci_bus_to_host(bus);
497 struct resource *rp = &hose->io_resource;
500 /* Check if port can be supported by that bus. We only check
501 * the ranges of the PHB though, not the bus itself as the rules
502 * for forwarding legacy cycles down bridges are not our problem
503 * here. So if the host bridge supports it, we do it.
505 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
508 if (!(rp->flags & IORESOURCE_IO))
510 if (offset < rp->start || (offset + size) > rp->end)
512 addr = hose->io_base_virt + port;
516 *((u8 *)val) = in_8(addr);
521 *((u16 *)val) = in_le16(addr);
526 *((u32 *)val) = in_le32(addr);
532 /* This provides legacy IO write access on a bus */
533 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
535 unsigned long offset;
536 struct pci_controller *hose = pci_bus_to_host(bus);
537 struct resource *rp = &hose->io_resource;
540 /* Check if port can be supported by that bus. We only check
541 * the ranges of the PHB though, not the bus itself as the rules
542 * for forwarding legacy cycles down bridges are not our problem
543 * here. So if the host bridge supports it, we do it.
545 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
548 if (!(rp->flags & IORESOURCE_IO))
550 if (offset < rp->start || (offset + size) > rp->end)
552 addr = hose->io_base_virt + port;
554 /* WARNING: The generic code is idiotic. It gets passed a pointer
555 * to what can be a 1, 2 or 4 byte quantity and always reads that
556 * as a u32, which means that we have to correct the location of
557 * the data read within those 32 bits for size 1 and 2
561 out_8(addr, val >> 24);
566 out_le16(addr, val >> 16);
577 /* This provides legacy IO or memory mmap access on a bus */
578 int pci_mmap_legacy_page_range(struct pci_bus *bus,
579 struct vm_area_struct *vma,
580 enum pci_mmap_state mmap_state)
582 struct pci_controller *hose = pci_bus_to_host(bus);
583 resource_size_t offset =
584 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
585 resource_size_t size = vma->vm_end - vma->vm_start;
588 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
589 pci_domain_nr(bus), bus->number,
590 mmap_state == pci_mmap_mem ? "MEM" : "IO",
591 (unsigned long long)offset,
592 (unsigned long long)(offset + size - 1));
594 if (mmap_state == pci_mmap_mem) {
597 * Because X is lame and can fail starting if it gets an error trying
598 * to mmap legacy_mem (instead of just moving on without legacy memory
599 * access) we fake it here by giving it anonymous memory, effectively
600 * behaving just like /dev/zero
602 if ((offset + size) > hose->isa_mem_size) {
604 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
605 current->comm, current->pid, pci_domain_nr(bus), bus->number);
606 if (vma->vm_flags & VM_SHARED)
607 return shmem_zero_setup(vma);
610 offset += hose->isa_mem_phys;
612 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
613 unsigned long roffset = offset + io_offset;
614 rp = &hose->io_resource;
615 if (!(rp->flags & IORESOURCE_IO))
617 if (roffset < rp->start || (roffset + size) > rp->end)
619 offset += hose->io_base_phys;
621 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
623 vma->vm_pgoff = offset >> PAGE_SHIFT;
624 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
625 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
626 vma->vm_end - vma->vm_start,
630 void pci_resource_to_user(const struct pci_dev *dev, int bar,
631 const struct resource *rsrc,
632 resource_size_t *start, resource_size_t *end)
634 struct pci_bus_region region;
636 if (rsrc->flags & IORESOURCE_IO) {
637 pcibios_resource_to_bus(dev->bus, ®ion,
638 (struct resource *) rsrc);
639 *start = region.start;
644 /* We pass a CPU physical address to userland for MMIO instead of a
645 * BAR value because X is lame and expects to be able to use that
646 * to pass to /dev/mem!
648 * That means we may have 64-bit values where some apps only expect
649 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
651 *start = rsrc->start;
656 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
657 * @hose: newly allocated pci_controller to be setup
658 * @dev: device node of the host bridge
659 * @primary: set if primary bus (32 bits only, soon to be deprecated)
661 * This function will parse the "ranges" property of a PCI host bridge device
662 * node and setup the resource mapping of a pci controller based on its
665 * Life would be boring if it wasn't for a few issues that we have to deal
668 * - We can only cope with one IO space range and up to 3 Memory space
669 * ranges. However, some machines (thanks Apple !) tend to split their
670 * space into lots of small contiguous ranges. So we have to coalesce.
672 * - Some busses have IO space not starting at 0, which causes trouble with
673 * the way we do our IO resource renumbering. The code somewhat deals with
674 * it for 64 bits but I would expect problems on 32 bits.
676 * - Some 32 bits platforms such as 4xx can have physical space larger than
677 * 32 bits so we need to use 64 bits values for the parsing
679 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
680 struct device_node *dev, int primary)
683 struct resource *res;
684 struct of_pci_range range;
685 struct of_pci_range_parser parser;
687 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
688 dev, primary ? "(primary)" : "");
690 /* Check for ranges property */
691 if (of_pci_range_parser_init(&parser, dev))
695 for_each_of_pci_range(&parser, &range) {
696 /* If we failed translation or got a zero-sized region
697 * (some FW try to feed us with non sensical zero sized regions
698 * such as power3 which look like some kind of attempt at exposing
699 * the VGA memory hole)
701 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
704 /* Act based on address space type */
706 switch (range.flags & IORESOURCE_TYPE_BITS) {
709 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
710 range.cpu_addr, range.cpu_addr + range.size - 1,
713 /* We support only one IO range */
714 if (hose->pci_io_size) {
716 " \\--> Skipped (too many) !\n");
720 /* On 32 bits, limit I/O space to 16MB */
721 if (range.size > 0x01000000)
722 range.size = 0x01000000;
724 /* 32 bits needs to map IOs here */
725 hose->io_base_virt = ioremap(range.cpu_addr,
728 /* Expect trouble if pci_addr is not 0 */
731 (unsigned long)hose->io_base_virt;
732 #endif /* CONFIG_PPC32 */
733 /* pci_io_size and io_base_phys always represent IO
734 * space starting at 0 so we factor in pci_addr
736 hose->pci_io_size = range.pci_addr + range.size;
737 hose->io_base_phys = range.cpu_addr - range.pci_addr;
740 res = &hose->io_resource;
741 range.cpu_addr = range.pci_addr;
745 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
746 range.cpu_addr, range.cpu_addr + range.size - 1,
748 (range.flags & IORESOURCE_PREFETCH) ?
751 /* We support only 3 memory ranges */
754 " \\--> Skipped (too many) !\n");
757 /* Handles ISA memory hole space here */
758 if (range.pci_addr == 0) {
759 if (primary || isa_mem_base == 0)
760 isa_mem_base = range.cpu_addr;
761 hose->isa_mem_phys = range.cpu_addr;
762 hose->isa_mem_size = range.size;
766 hose->mem_offset[memno] = range.cpu_addr -
768 res = &hose->mem_resources[memno++];
772 res->name = dev->full_name;
773 res->flags = range.flags;
774 res->start = range.cpu_addr;
775 res->end = range.cpu_addr + range.size - 1;
776 res->parent = res->child = res->sibling = NULL;
781 /* Decide whether to display the domain number in /proc */
782 int pci_proc_domain(struct pci_bus *bus)
784 struct pci_controller *hose = pci_bus_to_host(bus);
786 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
788 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
789 return hose->global_number != 0;
793 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
795 if (ppc_md.pcibios_root_bridge_prepare)
796 return ppc_md.pcibios_root_bridge_prepare(bridge);
801 /* This header fixup will do the resource fixup for all devices as they are
802 * probed, but not for bridge ranges
804 static void pcibios_fixup_resources(struct pci_dev *dev)
806 struct pci_controller *hose = pci_bus_to_host(dev->bus);
810 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
818 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
819 struct resource *res = dev->resource + i;
820 struct pci_bus_region reg;
824 /* If we're going to re-assign everything, we mark all resources
825 * as unset (and 0-base them). In addition, we mark BARs starting
826 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
827 * since in that case, we don't want to re-assign anything
829 pcibios_resource_to_bus(dev->bus, ®, res);
830 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
831 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
832 /* Only print message if not re-assigning */
833 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
834 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
835 pci_name(dev), i, res);
836 res->end -= res->start;
838 res->flags |= IORESOURCE_UNSET;
842 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
845 /* Call machine specific resource fixup */
846 if (ppc_md.pcibios_fixup_resources)
847 ppc_md.pcibios_fixup_resources(dev);
849 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
851 /* This function tries to figure out if a bridge resource has been initialized
852 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
853 * things go more smoothly when it gets it right. It should covers cases such
854 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
856 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
857 struct resource *res)
859 struct pci_controller *hose = pci_bus_to_host(bus);
860 struct pci_dev *dev = bus->self;
861 resource_size_t offset;
862 struct pci_bus_region region;
866 /* We don't do anything if PCI_PROBE_ONLY is set */
867 if (pci_has_flag(PCI_PROBE_ONLY))
870 /* Job is a bit different between memory and IO */
871 if (res->flags & IORESOURCE_MEM) {
872 pcibios_resource_to_bus(dev->bus, ®ion, res);
874 /* If the BAR is non-0 then it's probably been initialized */
875 if (region.start != 0)
878 /* The BAR is 0, let's check if memory decoding is enabled on
879 * the bridge. If not, we consider it unassigned
881 pci_read_config_word(dev, PCI_COMMAND, &command);
882 if ((command & PCI_COMMAND_MEMORY) == 0)
885 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
886 * resources covers that starting address (0 then it's good enough for
887 * us for memory space)
889 for (i = 0; i < 3; i++) {
890 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
891 hose->mem_resources[i].start == hose->mem_offset[i])
895 /* Well, it starts at 0 and we know it will collide so we may as
896 * well consider it as unassigned. That covers the Apple case.
900 /* If the BAR is non-0, then we consider it assigned */
901 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
902 if (((res->start - offset) & 0xfffffffful) != 0)
905 /* Here, we are a bit different than memory as typically IO space
906 * starting at low addresses -is- valid. What we do instead if that
907 * we consider as unassigned anything that doesn't have IO enabled
908 * in the PCI command register, and that's it.
910 pci_read_config_word(dev, PCI_COMMAND, &command);
911 if (command & PCI_COMMAND_IO)
914 /* It's starting at 0 and IO is disabled in the bridge, consider
921 /* Fixup resources of a PCI<->PCI bridge */
922 static void pcibios_fixup_bridge(struct pci_bus *bus)
924 struct resource *res;
927 struct pci_dev *dev = bus->self;
929 pci_bus_for_each_resource(bus, res, i) {
930 if (!res || !res->flags)
932 if (i >= 3 && bus->self->transparent)
935 /* If we're going to reassign everything, we can
936 * shrink the P2P resource to have size as being
937 * of 0 in order to save space.
939 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
940 res->flags |= IORESOURCE_UNSET;
946 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
948 /* Try to detect uninitialized P2P bridge resources,
949 * and clear them out so they get re-assigned later
951 if (pcibios_uninitialized_bridge_resource(bus, res)) {
953 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
958 void pcibios_setup_bus_self(struct pci_bus *bus)
960 struct pci_controller *phb;
962 /* Fix up the bus resources for P2P bridges */
963 if (bus->self != NULL)
964 pcibios_fixup_bridge(bus);
966 /* Platform specific bus fixups. This is currently only used
967 * by fsl_pci and I'm hoping to get rid of it at some point
969 if (ppc_md.pcibios_fixup_bus)
970 ppc_md.pcibios_fixup_bus(bus);
972 /* Setup bus DMA mappings */
973 phb = pci_bus_to_host(bus);
974 if (phb->controller_ops.dma_bus_setup)
975 phb->controller_ops.dma_bus_setup(bus);
978 void pcibios_bus_add_device(struct pci_dev *dev)
980 struct pci_controller *phb;
981 /* Fixup NUMA node as it may not be setup yet by the generic
982 * code and is needed by the DMA init
984 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
986 /* Hook up default DMA ops */
987 set_dma_ops(&dev->dev, pci_dma_ops);
988 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET;
990 /* Additional platform DMA/iommu setup */
991 phb = pci_bus_to_host(dev->bus);
992 if (phb->controller_ops.dma_dev_setup)
993 phb->controller_ops.dma_dev_setup(dev);
995 /* Read default IRQs and fixup if necessary */
996 pci_read_irq_line(dev);
997 if (ppc_md.pci_irq_fixup)
998 ppc_md.pci_irq_fixup(dev);
1000 if (ppc_md.pcibios_bus_add_device)
1001 ppc_md.pcibios_bus_add_device(dev);
1004 int pcibios_add_device(struct pci_dev *dev)
1006 #ifdef CONFIG_PCI_IOV
1007 if (ppc_md.pcibios_fixup_sriov)
1008 ppc_md.pcibios_fixup_sriov(dev);
1009 #endif /* CONFIG_PCI_IOV */
1014 void pcibios_set_master(struct pci_dev *dev)
1016 /* No special bus mastering setup handling */
1019 void pcibios_fixup_bus(struct pci_bus *bus)
1021 /* When called from the generic PCI probe, read PCI<->PCI bridge
1022 * bases. This is -not- called when generating the PCI tree from
1023 * the OF device-tree.
1025 pci_read_bridge_bases(bus);
1027 /* Now fixup the bus bus */
1028 pcibios_setup_bus_self(bus);
1030 EXPORT_SYMBOL(pcibios_fixup_bus);
1032 static int skip_isa_ioresource_align(struct pci_dev *dev)
1034 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1035 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1041 * We need to avoid collisions with `mirrored' VGA ports
1042 * and other strange ISA hardware, so we always want the
1043 * addresses to be allocated in the 0x000-0x0ff region
1046 * Why? Because some silly external IO cards only decode
1047 * the low 10 bits of the IO address. The 0x00-0xff region
1048 * is reserved for motherboard devices that decode all 16
1049 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1050 * but we want to try to avoid allocating at 0x2900-0x2bff
1051 * which might have be mirrored at 0x0100-0x03ff..
1053 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1054 resource_size_t size, resource_size_t align)
1056 struct pci_dev *dev = data;
1057 resource_size_t start = res->start;
1059 if (res->flags & IORESOURCE_IO) {
1060 if (skip_isa_ioresource_align(dev))
1063 start = (start + 0x3ff) & ~0x3ff;
1068 EXPORT_SYMBOL(pcibios_align_resource);
1071 * Reparent resource children of pr that conflict with res
1072 * under res, and make res replace those children.
1074 static int reparent_resources(struct resource *parent,
1075 struct resource *res)
1077 struct resource *p, **pp;
1078 struct resource **firstpp = NULL;
1080 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1081 if (p->end < res->start)
1083 if (res->end < p->start)
1085 if (p->start < res->start || p->end > res->end)
1086 return -1; /* not completely contained */
1087 if (firstpp == NULL)
1090 if (firstpp == NULL)
1091 return -1; /* didn't find any conflicting entries? */
1092 res->parent = parent;
1093 res->child = *firstpp;
1097 for (p = res->child; p != NULL; p = p->sibling) {
1099 pr_debug("PCI: Reparented %s %pR under %s\n",
1100 p->name, p, res->name);
1106 * Handle resources of PCI devices. If the world were perfect, we could
1107 * just allocate all the resource regions and do nothing more. It isn't.
1108 * On the other hand, we cannot just re-allocate all devices, as it would
1109 * require us to know lots of host bridge internals. So we attempt to
1110 * keep as much of the original configuration as possible, but tweak it
1111 * when it's found to be wrong.
1113 * Known BIOS problems we have to work around:
1114 * - I/O or memory regions not configured
1115 * - regions configured, but not enabled in the command register
1116 * - bogus I/O addresses above 64K used
1117 * - expansion ROMs left enabled (this may sound harmless, but given
1118 * the fact the PCI specs explicitly allow address decoders to be
1119 * shared between expansion ROMs and other resource regions, it's
1120 * at least dangerous)
1123 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1124 * This gives us fixed barriers on where we can allocate.
1125 * (2) Allocate resources for all enabled devices. If there is
1126 * a collision, just mark the resource as unallocated. Also
1127 * disable expansion ROMs during this step.
1128 * (3) Try to allocate resources for disabled devices. If the
1129 * resources were assigned correctly, everything goes well,
1130 * if they weren't, they won't disturb allocation of other
1132 * (4) Assign new addresses to resources which were either
1133 * not configured at all or misconfigured. If explicitly
1134 * requested by the user, configure expansion ROM address
1138 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1142 struct resource *res, *pr;
1144 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1145 pci_domain_nr(bus), bus->number);
1147 pci_bus_for_each_resource(bus, res, i) {
1148 if (!res || !res->flags || res->start > res->end || res->parent)
1151 /* If the resource was left unset at this point, we clear it */
1152 if (res->flags & IORESOURCE_UNSET)
1153 goto clear_resource;
1155 if (bus->parent == NULL)
1156 pr = (res->flags & IORESOURCE_IO) ?
1157 &ioport_resource : &iomem_resource;
1159 pr = pci_find_parent_resource(bus->self, res);
1161 /* this happens when the generic PCI
1162 * code (wrongly) decides that this
1163 * bridge is transparent -- paulus
1169 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1170 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1171 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1173 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1174 struct pci_dev *dev = bus->self;
1176 if (request_resource(pr, res) == 0)
1179 * Must be a conflict with an existing entry.
1180 * Move that entry (or entries) under the
1181 * bridge resource and try again.
1183 if (reparent_resources(pr, res) == 0)
1186 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1187 pci_claim_bridge_resource(dev,
1188 i + PCI_BRIDGE_RESOURCES) == 0)
1191 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1194 /* The resource might be figured out when doing
1195 * reassignment based on the resources required
1196 * by the downstream PCI devices. Here we set
1197 * the size of the resource to be 0 in order to
1205 list_for_each_entry(b, &bus->children, node)
1206 pcibios_allocate_bus_resources(b);
1209 static inline void alloc_resource(struct pci_dev *dev, int idx)
1211 struct resource *pr, *r = &dev->resource[idx];
1213 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1214 pci_name(dev), idx, r);
1216 pr = pci_find_parent_resource(dev, r);
1217 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1218 request_resource(pr, r) < 0) {
1219 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1220 " of device %s, will remap\n", idx, pci_name(dev));
1222 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1223 /* We'll assign a new address later */
1224 r->flags |= IORESOURCE_UNSET;
1230 static void __init pcibios_allocate_resources(int pass)
1232 struct pci_dev *dev = NULL;
1237 for_each_pci_dev(dev) {
1238 pci_read_config_word(dev, PCI_COMMAND, &command);
1239 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1240 r = &dev->resource[idx];
1241 if (r->parent) /* Already allocated */
1243 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1244 continue; /* Not assigned at all */
1245 /* We only allocate ROMs on pass 1 just in case they
1246 * have been screwed up by firmware
1248 if (idx == PCI_ROM_RESOURCE )
1250 if (r->flags & IORESOURCE_IO)
1251 disabled = !(command & PCI_COMMAND_IO);
1253 disabled = !(command & PCI_COMMAND_MEMORY);
1254 if (pass == disabled)
1255 alloc_resource(dev, idx);
1259 r = &dev->resource[PCI_ROM_RESOURCE];
1261 /* Turn the ROM off, leave the resource region,
1262 * but keep it unregistered.
1265 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1266 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1267 pr_debug("PCI: Switching off ROM of %s\n",
1269 r->flags &= ~IORESOURCE_ROM_ENABLE;
1270 pci_write_config_dword(dev, dev->rom_base_reg,
1271 reg & ~PCI_ROM_ADDRESS_ENABLE);
1277 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1279 struct pci_controller *hose = pci_bus_to_host(bus);
1280 resource_size_t offset;
1281 struct resource *res, *pres;
1284 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1287 if (!(hose->io_resource.flags & IORESOURCE_IO))
1289 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1290 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1291 BUG_ON(res == NULL);
1292 res->name = "Legacy IO";
1293 res->flags = IORESOURCE_IO;
1294 res->start = offset;
1295 res->end = (offset + 0xfff) & 0xfffffffful;
1296 pr_debug("Candidate legacy IO: %pR\n", res);
1297 if (request_resource(&hose->io_resource, res)) {
1299 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1300 pci_domain_nr(bus), bus->number, res);
1305 /* Check for memory */
1306 for (i = 0; i < 3; i++) {
1307 pres = &hose->mem_resources[i];
1308 offset = hose->mem_offset[i];
1309 if (!(pres->flags & IORESOURCE_MEM))
1311 pr_debug("hose mem res: %pR\n", pres);
1312 if ((pres->start - offset) <= 0xa0000 &&
1313 (pres->end - offset) >= 0xbffff)
1318 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1319 BUG_ON(res == NULL);
1320 res->name = "Legacy VGA memory";
1321 res->flags = IORESOURCE_MEM;
1322 res->start = 0xa0000 + offset;
1323 res->end = 0xbffff + offset;
1324 pr_debug("Candidate VGA memory: %pR\n", res);
1325 if (request_resource(pres, res)) {
1327 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1328 pci_domain_nr(bus), bus->number, res);
1333 void __init pcibios_resource_survey(void)
1337 /* Allocate and assign resources */
1338 list_for_each_entry(b, &pci_root_buses, node)
1339 pcibios_allocate_bus_resources(b);
1340 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1341 pcibios_allocate_resources(0);
1342 pcibios_allocate_resources(1);
1345 /* Before we start assigning unassigned resource, we try to reserve
1346 * the low IO area and the VGA memory area if they intersect the
1347 * bus available resources to avoid allocating things on top of them
1349 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1350 list_for_each_entry(b, &pci_root_buses, node)
1351 pcibios_reserve_legacy_regions(b);
1354 /* Now, if the platform didn't decide to blindly trust the firmware,
1355 * we proceed to assigning things that were left unassigned
1357 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1358 pr_debug("PCI: Assigning unassigned resources...\n");
1359 pci_assign_unassigned_resources();
1363 /* This is used by the PCI hotplug driver to allocate resource
1364 * of newly plugged busses. We can try to consolidate with the
1365 * rest of the code later, for now, keep it as-is as our main
1366 * resource allocation function doesn't deal with sub-trees yet.
1368 void pcibios_claim_one_bus(struct pci_bus *bus)
1370 struct pci_dev *dev;
1371 struct pci_bus *child_bus;
1373 list_for_each_entry(dev, &bus->devices, bus_list) {
1376 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1377 struct resource *r = &dev->resource[i];
1379 if (r->parent || !r->start || !r->flags)
1382 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1383 pci_name(dev), i, r);
1385 if (pci_claim_resource(dev, i) == 0)
1388 pci_claim_bridge_resource(dev, i);
1392 list_for_each_entry(child_bus, &bus->children, node)
1393 pcibios_claim_one_bus(child_bus);
1395 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1398 /* pcibios_finish_adding_to_bus
1400 * This is to be called by the hotplug code after devices have been
1401 * added to a bus, this include calling it for a PHB that is just
1404 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1406 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1407 pci_domain_nr(bus), bus->number);
1409 /* Allocate bus and devices resources */
1410 pcibios_allocate_bus_resources(bus);
1411 pcibios_claim_one_bus(bus);
1412 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1414 pci_assign_unassigned_bridge_resources(bus->self);
1416 pci_assign_unassigned_bus_resources(bus);
1419 /* Add new devices to global lists. Register in proc, sysfs. */
1420 pci_bus_add_devices(bus);
1422 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1424 int pcibios_enable_device(struct pci_dev *dev, int mask)
1426 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1428 if (phb->controller_ops.enable_device_hook)
1429 if (!phb->controller_ops.enable_device_hook(dev))
1432 return pci_enable_resources(dev, mask);
1435 void pcibios_disable_device(struct pci_dev *dev)
1437 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1439 if (phb->controller_ops.disable_device)
1440 phb->controller_ops.disable_device(dev);
1443 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1445 return (unsigned long) hose->io_base_virt - _IO_BASE;
1448 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1449 struct list_head *resources)
1451 struct resource *res;
1452 resource_size_t offset;
1455 /* Hookup PHB IO resource */
1456 res = &hose->io_resource;
1459 pr_debug("PCI: I/O resource not set for host"
1460 " bridge %pOF (domain %d)\n",
1461 hose->dn, hose->global_number);
1463 offset = pcibios_io_space_offset(hose);
1465 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1466 res, (unsigned long long)offset);
1467 pci_add_resource_offset(resources, res, offset);
1470 /* Hookup PHB Memory resources */
1471 for (i = 0; i < 3; ++i) {
1472 res = &hose->mem_resources[i];
1476 offset = hose->mem_offset[i];
1477 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1478 res, (unsigned long long)offset);
1480 pci_add_resource_offset(resources, res, offset);
1485 * Null PCI config access functions, for the case when we can't
1488 #define NULL_PCI_OP(rw, size, type) \
1490 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1492 return PCIBIOS_DEVICE_NOT_FOUND; \
1496 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1499 return PCIBIOS_DEVICE_NOT_FOUND;
1503 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1506 return PCIBIOS_DEVICE_NOT_FOUND;
1509 static struct pci_ops null_pci_ops =
1511 .read = null_read_config,
1512 .write = null_write_config,
1516 * These functions are used early on before PCI scanning is done
1517 * and all of the pci_dev and pci_bus structures have been created.
1519 static struct pci_bus *
1520 fake_pci_bus(struct pci_controller *hose, int busnr)
1522 static struct pci_bus bus;
1525 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1529 bus.ops = hose? hose->ops: &null_pci_ops;
1533 #define EARLY_PCI_OP(rw, size, type) \
1534 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1535 int devfn, int offset, type value) \
1537 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1538 devfn, offset, value); \
1541 EARLY_PCI_OP(read, byte, u8 *)
1542 EARLY_PCI_OP(read, word, u16 *)
1543 EARLY_PCI_OP(read, dword, u32 *)
1544 EARLY_PCI_OP(write, byte, u8)
1545 EARLY_PCI_OP(write, word, u16)
1546 EARLY_PCI_OP(write, dword, u32)
1548 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1551 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1554 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1556 struct pci_controller *hose = bus->sysdata;
1558 return of_node_get(hose->dn);
1562 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1563 * @hose: Pointer to the PCI host controller instance structure
1565 void pcibios_scan_phb(struct pci_controller *hose)
1567 LIST_HEAD(resources);
1568 struct pci_bus *bus;
1569 struct device_node *node = hose->dn;
1572 pr_debug("PCI: Scanning PHB %pOF\n", node);
1574 /* Get some IO space for the new PHB */
1575 pcibios_setup_phb_io_space(hose);
1577 /* Wire up PHB bus resources */
1578 pcibios_setup_phb_resources(hose, &resources);
1580 hose->busn.start = hose->first_busno;
1581 hose->busn.end = hose->last_busno;
1582 hose->busn.flags = IORESOURCE_BUS;
1583 pci_add_resource(&resources, &hose->busn);
1585 /* Create an empty bus for the toplevel */
1586 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1587 hose->ops, hose, &resources);
1589 pr_err("Failed to create bus for PCI domain %04x\n",
1590 hose->global_number);
1591 pci_free_resource_list(&resources);
1596 /* Get probe mode and perform scan */
1597 mode = PCI_PROBE_NORMAL;
1598 if (node && hose->controller_ops.probe_mode)
1599 mode = hose->controller_ops.probe_mode(bus);
1600 pr_debug(" probe mode: %d\n", mode);
1601 if (mode == PCI_PROBE_DEVTREE)
1602 of_scan_bus(node, bus);
1604 if (mode == PCI_PROBE_NORMAL) {
1605 pci_bus_update_busn_res_end(bus, 255);
1606 hose->last_busno = pci_scan_child_bus(bus);
1607 pci_bus_update_busn_res_end(bus, hose->last_busno);
1610 /* Platform gets a chance to do some global fixups before
1611 * we proceed to resource allocation
1613 if (ppc_md.pcibios_fixup_phb)
1614 ppc_md.pcibios_fixup_phb(hose);
1616 /* Configure PCI Express settings */
1617 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1618 struct pci_bus *child;
1619 list_for_each_entry(child, &bus->children, node)
1620 pcie_bus_configure_settings(child);
1623 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1625 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1627 int i, class = dev->class >> 8;
1628 /* When configured as agent, programing interface = 1 */
1629 int prog_if = dev->class & 0xf;
1631 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1632 class == PCI_CLASS_BRIDGE_OTHER) &&
1633 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1635 (dev->bus->parent == NULL)) {
1636 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1637 dev->resource[i].start = 0;
1638 dev->resource[i].end = 0;
1639 dev->resource[i].flags = 0;
1643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1647 static int __init discover_phbs(void)
1649 if (ppc_md.discover_phbs)
1650 ppc_md.discover_phbs();
1654 core_initcall(discover_phbs);