1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Contains common pci routines for ALL ppc platform
4 * (based on pci_32.c and pci_64.c)
6 * Port for PPC64 David Engebretsen, IBM Corp.
7 * Contains common pci routines for ppc64 platform, pSeries and iSeries brands.
9 * Copyright (C) 2003 Anton Blanchard <anton@au.ibm.com>, IBM
10 * Rework, based on alpha PCI code.
12 * Common pmac/prep/chrp pci routines. -- Cort
15 #include <linux/kernel.h>
16 #include <linux/pci.h>
17 #include <linux/string.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/export.h>
21 #include <linux/of_address.h>
22 #include <linux/of_pci.h>
24 #include <linux/shmem_fs.h>
25 #include <linux/list.h>
26 #include <linux/syscalls.h>
27 #include <linux/irq.h>
28 #include <linux/vmalloc.h>
29 #include <linux/slab.h>
30 #include <linux/vgaarb.h>
31 #include <linux/numa.h>
33 #include <asm/processor.h>
36 #include <asm/pci-bridge.h>
37 #include <asm/byteorder.h>
38 #include <asm/machdep.h>
39 #include <asm/ppc-pci.h>
42 #include "../../../drivers/pci/pci.h"
44 /* hose_spinlock protects accesses to the the phb_bitmap. */
45 static DEFINE_SPINLOCK(hose_spinlock);
48 /* For dynamic PHB numbering on get_phb_number(): max number of PHBs. */
49 #define MAX_PHBS 0x10000
52 * For dynamic PHB numbering: used/free PHBs tracking bitmap.
53 * Accesses to this bitmap should be protected by hose_spinlock.
55 static DECLARE_BITMAP(phb_bitmap, MAX_PHBS);
57 /* ISA Memory physical address */
58 resource_size_t isa_mem_base;
59 EXPORT_SYMBOL(isa_mem_base);
62 static const struct dma_map_ops *pci_dma_ops;
64 void set_pci_dma_ops(const struct dma_map_ops *dma_ops)
66 pci_dma_ops = dma_ops;
69 static int get_phb_number(struct device_node *dn)
75 * Try fixed PHB numbering first, by checking archs and reading
76 * the respective device-tree properties. Firstly, try reading
77 * standard "linux,pci-domain", then try reading "ibm,opal-phbid"
78 * (only present in powernv OPAL environment), then try device-tree
79 * alias and as the last try to use lower bits of "reg" property.
81 ret = of_get_pci_domain_nr(dn);
87 ret = of_property_read_u64(dn, "ibm,opal-phbid", &prop);
90 ret = of_alias_get_id(dn, "pci");
98 ret = of_property_read_u32_index(dn, "reg", 1, &prop_32);
103 phb_id = (int)(prop & (MAX_PHBS - 1));
105 spin_lock(&hose_spinlock);
107 /* We need to be sure to not use the same PHB number twice. */
108 if ((phb_id >= 0) && !test_and_set_bit(phb_id, phb_bitmap))
111 /* If everything fails then fallback to dynamic PHB numbering. */
112 phb_id = find_first_zero_bit(phb_bitmap, MAX_PHBS);
113 BUG_ON(phb_id >= MAX_PHBS);
114 set_bit(phb_id, phb_bitmap);
117 spin_unlock(&hose_spinlock);
122 struct pci_controller *pcibios_alloc_controller(struct device_node *dev)
124 struct pci_controller *phb;
126 phb = zalloc_maybe_bootmem(sizeof(struct pci_controller), GFP_KERNEL);
130 phb->global_number = get_phb_number(dev);
132 spin_lock(&hose_spinlock);
133 list_add_tail(&phb->list_node, &hose_list);
134 spin_unlock(&hose_spinlock);
137 phb->is_dynamic = slab_is_available();
140 int nid = of_node_to_nid(dev);
142 if (nid < 0 || !node_online(nid))
145 PHB_SET_NODE(phb, nid);
150 EXPORT_SYMBOL_GPL(pcibios_alloc_controller);
152 void pcibios_free_controller(struct pci_controller *phb)
154 spin_lock(&hose_spinlock);
156 /* Clear bit of phb_bitmap to allow reuse of this PHB number. */
157 if (phb->global_number < MAX_PHBS)
158 clear_bit(phb->global_number, phb_bitmap);
160 list_del(&phb->list_node);
161 spin_unlock(&hose_spinlock);
166 EXPORT_SYMBOL_GPL(pcibios_free_controller);
169 * This function is used to call pcibios_free_controller()
170 * in a deferred manner: a callback from the PCI subsystem.
172 * _*DO NOT*_ call pcibios_free_controller() explicitly if
173 * this is used (or it may access an invalid *phb pointer).
175 * The callback occurs when all references to the root bus
176 * are dropped (e.g., child buses/devices and their users).
178 * It's called as .release_fn() of 'struct pci_host_bridge'
179 * which is associated with the 'struct pci_controller.bus'
180 * (root bus) - it expects .release_data to hold a pointer
181 * to 'struct pci_controller'.
183 * In order to use it, register .release_fn()/release_data
186 * pci_set_host_bridge_release(bridge,
187 * pcibios_free_controller_deferred
190 * e.g. in the pcibios_root_bridge_prepare() callback from
191 * pci_create_root_bus().
193 void pcibios_free_controller_deferred(struct pci_host_bridge *bridge)
195 struct pci_controller *phb = (struct pci_controller *)
196 bridge->release_data;
198 pr_debug("domain %d, dynamic %d\n", phb->global_number, phb->is_dynamic);
200 pcibios_free_controller(phb);
202 EXPORT_SYMBOL_GPL(pcibios_free_controller_deferred);
205 * The function is used to return the minimal alignment
206 * for memory or I/O windows of the associated P2P bridge.
207 * By default, 4KiB alignment for I/O windows and 1MiB for
210 resource_size_t pcibios_window_alignment(struct pci_bus *bus,
213 struct pci_controller *phb = pci_bus_to_host(bus);
215 if (phb->controller_ops.window_alignment)
216 return phb->controller_ops.window_alignment(bus, type);
219 * PCI core will figure out the default
220 * alignment: 4KiB for I/O and 1MiB for
226 void pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
228 struct pci_controller *hose = pci_bus_to_host(bus);
230 if (hose->controller_ops.setup_bridge)
231 hose->controller_ops.setup_bridge(bus, type);
234 void pcibios_reset_secondary_bus(struct pci_dev *dev)
236 struct pci_controller *phb = pci_bus_to_host(dev->bus);
238 if (phb->controller_ops.reset_secondary_bus) {
239 phb->controller_ops.reset_secondary_bus(dev);
243 pci_reset_secondary_bus(dev);
246 resource_size_t pcibios_default_alignment(void)
248 if (ppc_md.pcibios_default_alignment)
249 return ppc_md.pcibios_default_alignment();
254 #ifdef CONFIG_PCI_IOV
255 resource_size_t pcibios_iov_resource_alignment(struct pci_dev *pdev, int resno)
257 if (ppc_md.pcibios_iov_resource_alignment)
258 return ppc_md.pcibios_iov_resource_alignment(pdev, resno);
260 return pci_iov_resource_size(pdev, resno);
263 int pcibios_sriov_enable(struct pci_dev *pdev, u16 num_vfs)
265 if (ppc_md.pcibios_sriov_enable)
266 return ppc_md.pcibios_sriov_enable(pdev, num_vfs);
271 int pcibios_sriov_disable(struct pci_dev *pdev)
273 if (ppc_md.pcibios_sriov_disable)
274 return ppc_md.pcibios_sriov_disable(pdev);
279 #endif /* CONFIG_PCI_IOV */
281 void pcibios_bus_add_device(struct pci_dev *pdev)
283 if (ppc_md.pcibios_bus_add_device)
284 ppc_md.pcibios_bus_add_device(pdev);
287 static resource_size_t pcibios_io_size(const struct pci_controller *hose)
290 return hose->pci_io_size;
292 return resource_size(&hose->io_resource);
296 int pcibios_vaddr_is_ioport(void __iomem *address)
299 struct pci_controller *hose;
300 resource_size_t size;
302 spin_lock(&hose_spinlock);
303 list_for_each_entry(hose, &hose_list, list_node) {
304 size = pcibios_io_size(hose);
305 if (address >= hose->io_base_virt &&
306 address < (hose->io_base_virt + size)) {
311 spin_unlock(&hose_spinlock);
315 unsigned long pci_address_to_pio(phys_addr_t address)
317 struct pci_controller *hose;
318 resource_size_t size;
319 unsigned long ret = ~0;
321 spin_lock(&hose_spinlock);
322 list_for_each_entry(hose, &hose_list, list_node) {
323 size = pcibios_io_size(hose);
324 if (address >= hose->io_base_phys &&
325 address < (hose->io_base_phys + size)) {
327 (unsigned long)hose->io_base_virt - _IO_BASE;
328 ret = base + (address - hose->io_base_phys);
332 spin_unlock(&hose_spinlock);
336 EXPORT_SYMBOL_GPL(pci_address_to_pio);
339 * Return the domain number for this bus.
341 int pci_domain_nr(struct pci_bus *bus)
343 struct pci_controller *hose = pci_bus_to_host(bus);
345 return hose->global_number;
347 EXPORT_SYMBOL(pci_domain_nr);
349 /* This routine is meant to be used early during boot, when the
350 * PCI bus numbers have not yet been assigned, and you need to
351 * issue PCI config cycles to an OF device.
352 * It could also be used to "fix" RTAS config cycles if you want
353 * to set pci_assign_all_buses to 1 and still use RTAS for PCI
356 struct pci_controller* pci_find_hose_for_OF_device(struct device_node* node)
359 struct pci_controller *hose, *tmp;
360 list_for_each_entry_safe(hose, tmp, &hose_list, list_node)
361 if (hose->dn == node)
368 struct pci_controller *pci_find_controller_for_domain(int domain_nr)
370 struct pci_controller *hose;
372 list_for_each_entry(hose, &hose_list, list_node)
373 if (hose->global_number == domain_nr)
380 * Reads the interrupt pin to determine if interrupt is use by card.
381 * If the interrupt is used, then gets the interrupt line from the
382 * openfirmware and sets it in the pci_dev and pci_config line.
384 static int pci_read_irq_line(struct pci_dev *pci_dev)
388 pr_debug("PCI: Try to map irq for %s...\n", pci_name(pci_dev));
390 /* Try to get a mapping from the device-tree */
391 virq = of_irq_parse_and_map_pci(pci_dev, 0, 0);
395 /* If that fails, lets fallback to what is in the config
396 * space and map that through the default controller. We
397 * also set the type to level low since that's what PCI
398 * interrupts are. If your platform does differently, then
399 * either provide a proper interrupt tree or don't use this
402 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_PIN, &pin))
406 if (pci_read_config_byte(pci_dev, PCI_INTERRUPT_LINE, &line) ||
407 line == 0xff || line == 0) {
410 pr_debug(" No map ! Using line %d (pin %d) from PCI config\n",
413 virq = irq_create_mapping(NULL, line);
415 irq_set_irq_type(virq, IRQ_TYPE_LEVEL_LOW);
419 pr_debug(" Failed to map !\n");
423 pr_debug(" Mapped to linux irq %d\n", virq);
431 * Platform support for /proc/bus/pci/X/Y mmap()s.
434 int pci_iobar_pfn(struct pci_dev *pdev, int bar, struct vm_area_struct *vma)
436 struct pci_controller *hose = pci_bus_to_host(pdev->bus);
437 resource_size_t ioaddr = pci_resource_start(pdev, bar);
442 /* Convert to an offset within this PCI controller */
443 ioaddr -= (unsigned long)hose->io_base_virt - _IO_BASE;
445 vma->vm_pgoff += (ioaddr + hose->io_base_phys) >> PAGE_SHIFT;
450 * This one is used by /dev/mem and fbdev who have no clue about the
451 * PCI device, it tries to find the PCI device first and calls the
454 pgprot_t pci_phys_mem_access_prot(struct file *file,
459 struct pci_dev *pdev = NULL;
460 struct resource *found = NULL;
461 resource_size_t offset = ((resource_size_t)pfn) << PAGE_SHIFT;
464 if (page_is_ram(pfn))
467 prot = pgprot_noncached(prot);
468 for_each_pci_dev(pdev) {
469 for (i = 0; i <= PCI_ROM_RESOURCE; i++) {
470 struct resource *rp = &pdev->resource[i];
471 int flags = rp->flags;
473 /* Active and same type? */
474 if ((flags & IORESOURCE_MEM) == 0)
476 /* In the range of this resource? */
477 if (offset < (rp->start & PAGE_MASK) ||
487 if (found->flags & IORESOURCE_PREFETCH)
488 prot = pgprot_noncached_wc(prot);
492 pr_debug("PCI: Non-PCI map for %llx, prot: %lx\n",
493 (unsigned long long)offset, pgprot_val(prot));
498 /* This provides legacy IO read access on a bus */
499 int pci_legacy_read(struct pci_bus *bus, loff_t port, u32 *val, size_t size)
501 unsigned long offset;
502 struct pci_controller *hose = pci_bus_to_host(bus);
503 struct resource *rp = &hose->io_resource;
506 /* Check if port can be supported by that bus. We only check
507 * the ranges of the PHB though, not the bus itself as the rules
508 * for forwarding legacy cycles down bridges are not our problem
509 * here. So if the host bridge supports it, we do it.
511 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
514 if (!(rp->flags & IORESOURCE_IO))
516 if (offset < rp->start || (offset + size) > rp->end)
518 addr = hose->io_base_virt + port;
522 *((u8 *)val) = in_8(addr);
527 *((u16 *)val) = in_le16(addr);
532 *((u32 *)val) = in_le32(addr);
538 /* This provides legacy IO write access on a bus */
539 int pci_legacy_write(struct pci_bus *bus, loff_t port, u32 val, size_t size)
541 unsigned long offset;
542 struct pci_controller *hose = pci_bus_to_host(bus);
543 struct resource *rp = &hose->io_resource;
546 /* Check if port can be supported by that bus. We only check
547 * the ranges of the PHB though, not the bus itself as the rules
548 * for forwarding legacy cycles down bridges are not our problem
549 * here. So if the host bridge supports it, we do it.
551 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
554 if (!(rp->flags & IORESOURCE_IO))
556 if (offset < rp->start || (offset + size) > rp->end)
558 addr = hose->io_base_virt + port;
560 /* WARNING: The generic code is idiotic. It gets passed a pointer
561 * to what can be a 1, 2 or 4 byte quantity and always reads that
562 * as a u32, which means that we have to correct the location of
563 * the data read within those 32 bits for size 1 and 2
567 out_8(addr, val >> 24);
572 out_le16(addr, val >> 16);
583 /* This provides legacy IO or memory mmap access on a bus */
584 int pci_mmap_legacy_page_range(struct pci_bus *bus,
585 struct vm_area_struct *vma,
586 enum pci_mmap_state mmap_state)
588 struct pci_controller *hose = pci_bus_to_host(bus);
589 resource_size_t offset =
590 ((resource_size_t)vma->vm_pgoff) << PAGE_SHIFT;
591 resource_size_t size = vma->vm_end - vma->vm_start;
594 pr_debug("pci_mmap_legacy_page_range(%04x:%02x, %s @%llx..%llx)\n",
595 pci_domain_nr(bus), bus->number,
596 mmap_state == pci_mmap_mem ? "MEM" : "IO",
597 (unsigned long long)offset,
598 (unsigned long long)(offset + size - 1));
600 if (mmap_state == pci_mmap_mem) {
603 * Because X is lame and can fail starting if it gets an error trying
604 * to mmap legacy_mem (instead of just moving on without legacy memory
605 * access) we fake it here by giving it anonymous memory, effectively
606 * behaving just like /dev/zero
608 if ((offset + size) > hose->isa_mem_size) {
610 "Process %s (pid:%d) mapped non-existing PCI legacy memory for 0%04x:%02x\n",
611 current->comm, current->pid, pci_domain_nr(bus), bus->number);
612 if (vma->vm_flags & VM_SHARED)
613 return shmem_zero_setup(vma);
616 offset += hose->isa_mem_phys;
618 unsigned long io_offset = (unsigned long)hose->io_base_virt - _IO_BASE;
619 unsigned long roffset = offset + io_offset;
620 rp = &hose->io_resource;
621 if (!(rp->flags & IORESOURCE_IO))
623 if (roffset < rp->start || (roffset + size) > rp->end)
625 offset += hose->io_base_phys;
627 pr_debug(" -> mapping phys %llx\n", (unsigned long long)offset);
629 vma->vm_pgoff = offset >> PAGE_SHIFT;
630 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
631 return remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
632 vma->vm_end - vma->vm_start,
636 void pci_resource_to_user(const struct pci_dev *dev, int bar,
637 const struct resource *rsrc,
638 resource_size_t *start, resource_size_t *end)
640 struct pci_bus_region region;
642 if (rsrc->flags & IORESOURCE_IO) {
643 pcibios_resource_to_bus(dev->bus, ®ion,
644 (struct resource *) rsrc);
645 *start = region.start;
650 /* We pass a CPU physical address to userland for MMIO instead of a
651 * BAR value because X is lame and expects to be able to use that
652 * to pass to /dev/mem!
654 * That means we may have 64-bit values where some apps only expect
655 * 32 (like X itself since it thinks only Sparc has 64-bit MMIO).
657 *start = rsrc->start;
662 * pci_process_bridge_OF_ranges - Parse PCI bridge resources from device tree
663 * @hose: newly allocated pci_controller to be setup
664 * @dev: device node of the host bridge
665 * @primary: set if primary bus (32 bits only, soon to be deprecated)
667 * This function will parse the "ranges" property of a PCI host bridge device
668 * node and setup the resource mapping of a pci controller based on its
671 * Life would be boring if it wasn't for a few issues that we have to deal
674 * - We can only cope with one IO space range and up to 3 Memory space
675 * ranges. However, some machines (thanks Apple !) tend to split their
676 * space into lots of small contiguous ranges. So we have to coalesce.
678 * - Some busses have IO space not starting at 0, which causes trouble with
679 * the way we do our IO resource renumbering. The code somewhat deals with
680 * it for 64 bits but I would expect problems on 32 bits.
682 * - Some 32 bits platforms such as 4xx can have physical space larger than
683 * 32 bits so we need to use 64 bits values for the parsing
685 void pci_process_bridge_OF_ranges(struct pci_controller *hose,
686 struct device_node *dev, int primary)
689 struct resource *res;
690 struct of_pci_range range;
691 struct of_pci_range_parser parser;
693 printk(KERN_INFO "PCI host bridge %pOF %s ranges:\n",
694 dev, primary ? "(primary)" : "");
696 /* Check for ranges property */
697 if (of_pci_range_parser_init(&parser, dev))
701 for_each_of_pci_range(&parser, &range) {
702 /* If we failed translation or got a zero-sized region
703 * (some FW try to feed us with non sensical zero sized regions
704 * such as power3 which look like some kind of attempt at exposing
705 * the VGA memory hole)
707 if (range.cpu_addr == OF_BAD_ADDR || range.size == 0)
710 /* Act based on address space type */
712 switch (range.flags & IORESOURCE_TYPE_BITS) {
715 " IO 0x%016llx..0x%016llx -> 0x%016llx\n",
716 range.cpu_addr, range.cpu_addr + range.size - 1,
719 /* We support only one IO range */
720 if (hose->pci_io_size) {
722 " \\--> Skipped (too many) !\n");
726 /* On 32 bits, limit I/O space to 16MB */
727 if (range.size > 0x01000000)
728 range.size = 0x01000000;
730 /* 32 bits needs to map IOs here */
731 hose->io_base_virt = ioremap(range.cpu_addr,
734 /* Expect trouble if pci_addr is not 0 */
737 (unsigned long)hose->io_base_virt;
738 #endif /* CONFIG_PPC32 */
739 /* pci_io_size and io_base_phys always represent IO
740 * space starting at 0 so we factor in pci_addr
742 hose->pci_io_size = range.pci_addr + range.size;
743 hose->io_base_phys = range.cpu_addr - range.pci_addr;
746 res = &hose->io_resource;
747 range.cpu_addr = range.pci_addr;
751 " MEM 0x%016llx..0x%016llx -> 0x%016llx %s\n",
752 range.cpu_addr, range.cpu_addr + range.size - 1,
754 (range.pci_space & 0x40000000) ?
757 /* We support only 3 memory ranges */
760 " \\--> Skipped (too many) !\n");
763 /* Handles ISA memory hole space here */
764 if (range.pci_addr == 0) {
765 if (primary || isa_mem_base == 0)
766 isa_mem_base = range.cpu_addr;
767 hose->isa_mem_phys = range.cpu_addr;
768 hose->isa_mem_size = range.size;
772 hose->mem_offset[memno] = range.cpu_addr -
774 res = &hose->mem_resources[memno++];
778 res->name = dev->full_name;
779 res->flags = range.flags;
780 res->start = range.cpu_addr;
781 res->end = range.cpu_addr + range.size - 1;
782 res->parent = res->child = res->sibling = NULL;
787 /* Decide whether to display the domain number in /proc */
788 int pci_proc_domain(struct pci_bus *bus)
790 struct pci_controller *hose = pci_bus_to_host(bus);
792 if (!pci_has_flag(PCI_ENABLE_PROC_DOMAINS))
794 if (pci_has_flag(PCI_COMPAT_DOMAIN_0))
795 return hose->global_number != 0;
799 int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
801 if (ppc_md.pcibios_root_bridge_prepare)
802 return ppc_md.pcibios_root_bridge_prepare(bridge);
807 /* This header fixup will do the resource fixup for all devices as they are
808 * probed, but not for bridge ranges
810 static void pcibios_fixup_resources(struct pci_dev *dev)
812 struct pci_controller *hose = pci_bus_to_host(dev->bus);
816 printk(KERN_ERR "No host bridge for PCI dev %s !\n",
824 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
825 struct resource *res = dev->resource + i;
826 struct pci_bus_region reg;
830 /* If we're going to re-assign everything, we mark all resources
831 * as unset (and 0-base them). In addition, we mark BARs starting
832 * at 0 as unset as well, except if PCI_PROBE_ONLY is also set
833 * since in that case, we don't want to re-assign anything
835 pcibios_resource_to_bus(dev->bus, ®, res);
836 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC) ||
837 (reg.start == 0 && !pci_has_flag(PCI_PROBE_ONLY))) {
838 /* Only print message if not re-assigning */
839 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC))
840 pr_debug("PCI:%s Resource %d %pR is unassigned\n",
841 pci_name(dev), i, res);
842 res->end -= res->start;
844 res->flags |= IORESOURCE_UNSET;
848 pr_debug("PCI:%s Resource %d %pR\n", pci_name(dev), i, res);
851 /* Call machine specific resource fixup */
852 if (ppc_md.pcibios_fixup_resources)
853 ppc_md.pcibios_fixup_resources(dev);
855 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI_ANY_ID, pcibios_fixup_resources);
857 /* This function tries to figure out if a bridge resource has been initialized
858 * by the firmware or not. It doesn't have to be absolutely bullet proof, but
859 * things go more smoothly when it gets it right. It should covers cases such
860 * as Apple "closed" bridge resources and bare-metal pSeries unassigned bridges
862 static int pcibios_uninitialized_bridge_resource(struct pci_bus *bus,
863 struct resource *res)
865 struct pci_controller *hose = pci_bus_to_host(bus);
866 struct pci_dev *dev = bus->self;
867 resource_size_t offset;
868 struct pci_bus_region region;
872 /* We don't do anything if PCI_PROBE_ONLY is set */
873 if (pci_has_flag(PCI_PROBE_ONLY))
876 /* Job is a bit different between memory and IO */
877 if (res->flags & IORESOURCE_MEM) {
878 pcibios_resource_to_bus(dev->bus, ®ion, res);
880 /* If the BAR is non-0 then it's probably been initialized */
881 if (region.start != 0)
884 /* The BAR is 0, let's check if memory decoding is enabled on
885 * the bridge. If not, we consider it unassigned
887 pci_read_config_word(dev, PCI_COMMAND, &command);
888 if ((command & PCI_COMMAND_MEMORY) == 0)
891 /* Memory decoding is enabled and the BAR is 0. If any of the bridge
892 * resources covers that starting address (0 then it's good enough for
893 * us for memory space)
895 for (i = 0; i < 3; i++) {
896 if ((hose->mem_resources[i].flags & IORESOURCE_MEM) &&
897 hose->mem_resources[i].start == hose->mem_offset[i])
901 /* Well, it starts at 0 and we know it will collide so we may as
902 * well consider it as unassigned. That covers the Apple case.
906 /* If the BAR is non-0, then we consider it assigned */
907 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
908 if (((res->start - offset) & 0xfffffffful) != 0)
911 /* Here, we are a bit different than memory as typically IO space
912 * starting at low addresses -is- valid. What we do instead if that
913 * we consider as unassigned anything that doesn't have IO enabled
914 * in the PCI command register, and that's it.
916 pci_read_config_word(dev, PCI_COMMAND, &command);
917 if (command & PCI_COMMAND_IO)
920 /* It's starting at 0 and IO is disabled in the bridge, consider
927 /* Fixup resources of a PCI<->PCI bridge */
928 static void pcibios_fixup_bridge(struct pci_bus *bus)
930 struct resource *res;
933 struct pci_dev *dev = bus->self;
935 pci_bus_for_each_resource(bus, res, i) {
936 if (!res || !res->flags)
938 if (i >= 3 && bus->self->transparent)
941 /* If we're going to reassign everything, we can
942 * shrink the P2P resource to have size as being
943 * of 0 in order to save space.
945 if (pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
946 res->flags |= IORESOURCE_UNSET;
952 pr_debug("PCI:%s Bus rsrc %d %pR\n", pci_name(dev), i, res);
954 /* Try to detect uninitialized P2P bridge resources,
955 * and clear them out so they get re-assigned later
957 if (pcibios_uninitialized_bridge_resource(bus, res)) {
959 pr_debug("PCI:%s (unassigned)\n", pci_name(dev));
964 void pcibios_setup_bus_self(struct pci_bus *bus)
966 struct pci_controller *phb;
968 /* Fix up the bus resources for P2P bridges */
969 if (bus->self != NULL)
970 pcibios_fixup_bridge(bus);
972 /* Platform specific bus fixups. This is currently only used
973 * by fsl_pci and I'm hoping to get rid of it at some point
975 if (ppc_md.pcibios_fixup_bus)
976 ppc_md.pcibios_fixup_bus(bus);
978 /* Setup bus DMA mappings */
979 phb = pci_bus_to_host(bus);
980 if (phb->controller_ops.dma_bus_setup)
981 phb->controller_ops.dma_bus_setup(bus);
984 static void pcibios_setup_device(struct pci_dev *dev)
986 struct pci_controller *phb;
987 /* Fixup NUMA node as it may not be setup yet by the generic
988 * code and is needed by the DMA init
990 set_dev_node(&dev->dev, pcibus_to_node(dev->bus));
992 /* Hook up default DMA ops */
993 set_dma_ops(&dev->dev, pci_dma_ops);
994 dev->dev.archdata.dma_offset = PCI_DRAM_OFFSET;
996 /* Additional platform DMA/iommu setup */
997 phb = pci_bus_to_host(dev->bus);
998 if (phb->controller_ops.dma_dev_setup)
999 phb->controller_ops.dma_dev_setup(dev);
1001 /* Read default IRQs and fixup if necessary */
1002 pci_read_irq_line(dev);
1003 if (ppc_md.pci_irq_fixup)
1004 ppc_md.pci_irq_fixup(dev);
1007 int pcibios_add_device(struct pci_dev *dev)
1010 * We can only call pcibios_setup_device() after bus setup is complete,
1011 * since some of the platform specific DMA setup code depends on it.
1013 if (dev->bus->is_added)
1014 pcibios_setup_device(dev);
1016 #ifdef CONFIG_PCI_IOV
1017 if (ppc_md.pcibios_fixup_sriov)
1018 ppc_md.pcibios_fixup_sriov(dev);
1019 #endif /* CONFIG_PCI_IOV */
1024 void pcibios_setup_bus_devices(struct pci_bus *bus)
1026 struct pci_dev *dev;
1028 pr_debug("PCI: Fixup bus devices %d (%s)\n",
1029 bus->number, bus->self ? pci_name(bus->self) : "PHB");
1031 list_for_each_entry(dev, &bus->devices, bus_list) {
1032 /* Cardbus can call us to add new devices to a bus, so ignore
1033 * those who are already fully discovered
1035 if (pci_dev_is_added(dev))
1038 pcibios_setup_device(dev);
1042 void pcibios_set_master(struct pci_dev *dev)
1044 /* No special bus mastering setup handling */
1047 void pcibios_fixup_bus(struct pci_bus *bus)
1049 /* When called from the generic PCI probe, read PCI<->PCI bridge
1050 * bases. This is -not- called when generating the PCI tree from
1051 * the OF device-tree.
1053 pci_read_bridge_bases(bus);
1055 /* Now fixup the bus bus */
1056 pcibios_setup_bus_self(bus);
1058 /* Now fixup devices on that bus */
1059 pcibios_setup_bus_devices(bus);
1061 EXPORT_SYMBOL(pcibios_fixup_bus);
1063 void pci_fixup_cardbus(struct pci_bus *bus)
1065 /* Now fixup devices on that bus */
1066 pcibios_setup_bus_devices(bus);
1070 static int skip_isa_ioresource_align(struct pci_dev *dev)
1072 if (pci_has_flag(PCI_CAN_SKIP_ISA_ALIGN) &&
1073 !(dev->bus->bridge_ctl & PCI_BRIDGE_CTL_ISA))
1079 * We need to avoid collisions with `mirrored' VGA ports
1080 * and other strange ISA hardware, so we always want the
1081 * addresses to be allocated in the 0x000-0x0ff region
1084 * Why? Because some silly external IO cards only decode
1085 * the low 10 bits of the IO address. The 0x00-0xff region
1086 * is reserved for motherboard devices that decode all 16
1087 * bits, so it's ok to allocate at, say, 0x2800-0x28ff,
1088 * but we want to try to avoid allocating at 0x2900-0x2bff
1089 * which might have be mirrored at 0x0100-0x03ff..
1091 resource_size_t pcibios_align_resource(void *data, const struct resource *res,
1092 resource_size_t size, resource_size_t align)
1094 struct pci_dev *dev = data;
1095 resource_size_t start = res->start;
1097 if (res->flags & IORESOURCE_IO) {
1098 if (skip_isa_ioresource_align(dev))
1101 start = (start + 0x3ff) & ~0x3ff;
1106 EXPORT_SYMBOL(pcibios_align_resource);
1109 * Reparent resource children of pr that conflict with res
1110 * under res, and make res replace those children.
1112 static int reparent_resources(struct resource *parent,
1113 struct resource *res)
1115 struct resource *p, **pp;
1116 struct resource **firstpp = NULL;
1118 for (pp = &parent->child; (p = *pp) != NULL; pp = &p->sibling) {
1119 if (p->end < res->start)
1121 if (res->end < p->start)
1123 if (p->start < res->start || p->end > res->end)
1124 return -1; /* not completely contained */
1125 if (firstpp == NULL)
1128 if (firstpp == NULL)
1129 return -1; /* didn't find any conflicting entries? */
1130 res->parent = parent;
1131 res->child = *firstpp;
1135 for (p = res->child; p != NULL; p = p->sibling) {
1137 pr_debug("PCI: Reparented %s %pR under %s\n",
1138 p->name, p, res->name);
1144 * Handle resources of PCI devices. If the world were perfect, we could
1145 * just allocate all the resource regions and do nothing more. It isn't.
1146 * On the other hand, we cannot just re-allocate all devices, as it would
1147 * require us to know lots of host bridge internals. So we attempt to
1148 * keep as much of the original configuration as possible, but tweak it
1149 * when it's found to be wrong.
1151 * Known BIOS problems we have to work around:
1152 * - I/O or memory regions not configured
1153 * - regions configured, but not enabled in the command register
1154 * - bogus I/O addresses above 64K used
1155 * - expansion ROMs left enabled (this may sound harmless, but given
1156 * the fact the PCI specs explicitly allow address decoders to be
1157 * shared between expansion ROMs and other resource regions, it's
1158 * at least dangerous)
1161 * (1) Allocate resources for all buses behind PCI-to-PCI bridges.
1162 * This gives us fixed barriers on where we can allocate.
1163 * (2) Allocate resources for all enabled devices. If there is
1164 * a collision, just mark the resource as unallocated. Also
1165 * disable expansion ROMs during this step.
1166 * (3) Try to allocate resources for disabled devices. If the
1167 * resources were assigned correctly, everything goes well,
1168 * if they weren't, they won't disturb allocation of other
1170 * (4) Assign new addresses to resources which were either
1171 * not configured at all or misconfigured. If explicitly
1172 * requested by the user, configure expansion ROM address
1176 static void pcibios_allocate_bus_resources(struct pci_bus *bus)
1180 struct resource *res, *pr;
1182 pr_debug("PCI: Allocating bus resources for %04x:%02x...\n",
1183 pci_domain_nr(bus), bus->number);
1185 pci_bus_for_each_resource(bus, res, i) {
1186 if (!res || !res->flags || res->start > res->end || res->parent)
1189 /* If the resource was left unset at this point, we clear it */
1190 if (res->flags & IORESOURCE_UNSET)
1191 goto clear_resource;
1193 if (bus->parent == NULL)
1194 pr = (res->flags & IORESOURCE_IO) ?
1195 &ioport_resource : &iomem_resource;
1197 pr = pci_find_parent_resource(bus->self, res);
1199 /* this happens when the generic PCI
1200 * code (wrongly) decides that this
1201 * bridge is transparent -- paulus
1207 pr_debug("PCI: %s (bus %d) bridge rsrc %d: %pR, parent %p (%s)\n",
1208 bus->self ? pci_name(bus->self) : "PHB", bus->number,
1209 i, res, pr, (pr && pr->name) ? pr->name : "nil");
1211 if (pr && !(pr->flags & IORESOURCE_UNSET)) {
1212 struct pci_dev *dev = bus->self;
1214 if (request_resource(pr, res) == 0)
1217 * Must be a conflict with an existing entry.
1218 * Move that entry (or entries) under the
1219 * bridge resource and try again.
1221 if (reparent_resources(pr, res) == 0)
1224 if (dev && i < PCI_BRIDGE_RESOURCE_NUM &&
1225 pci_claim_bridge_resource(dev,
1226 i + PCI_BRIDGE_RESOURCES) == 0)
1229 pr_warn("PCI: Cannot allocate resource region %d of PCI bridge %d, will remap\n",
1232 /* The resource might be figured out when doing
1233 * reassignment based on the resources required
1234 * by the downstream PCI devices. Here we set
1235 * the size of the resource to be 0 in order to
1243 list_for_each_entry(b, &bus->children, node)
1244 pcibios_allocate_bus_resources(b);
1247 static inline void alloc_resource(struct pci_dev *dev, int idx)
1249 struct resource *pr, *r = &dev->resource[idx];
1251 pr_debug("PCI: Allocating %s: Resource %d: %pR\n",
1252 pci_name(dev), idx, r);
1254 pr = pci_find_parent_resource(dev, r);
1255 if (!pr || (pr->flags & IORESOURCE_UNSET) ||
1256 request_resource(pr, r) < 0) {
1257 printk(KERN_WARNING "PCI: Cannot allocate resource region %d"
1258 " of device %s, will remap\n", idx, pci_name(dev));
1260 pr_debug("PCI: parent is %p: %pR\n", pr, pr);
1261 /* We'll assign a new address later */
1262 r->flags |= IORESOURCE_UNSET;
1268 static void __init pcibios_allocate_resources(int pass)
1270 struct pci_dev *dev = NULL;
1275 for_each_pci_dev(dev) {
1276 pci_read_config_word(dev, PCI_COMMAND, &command);
1277 for (idx = 0; idx <= PCI_ROM_RESOURCE; idx++) {
1278 r = &dev->resource[idx];
1279 if (r->parent) /* Already allocated */
1281 if (!r->flags || (r->flags & IORESOURCE_UNSET))
1282 continue; /* Not assigned at all */
1283 /* We only allocate ROMs on pass 1 just in case they
1284 * have been screwed up by firmware
1286 if (idx == PCI_ROM_RESOURCE )
1288 if (r->flags & IORESOURCE_IO)
1289 disabled = !(command & PCI_COMMAND_IO);
1291 disabled = !(command & PCI_COMMAND_MEMORY);
1292 if (pass == disabled)
1293 alloc_resource(dev, idx);
1297 r = &dev->resource[PCI_ROM_RESOURCE];
1299 /* Turn the ROM off, leave the resource region,
1300 * but keep it unregistered.
1303 pci_read_config_dword(dev, dev->rom_base_reg, ®);
1304 if (reg & PCI_ROM_ADDRESS_ENABLE) {
1305 pr_debug("PCI: Switching off ROM of %s\n",
1307 r->flags &= ~IORESOURCE_ROM_ENABLE;
1308 pci_write_config_dword(dev, dev->rom_base_reg,
1309 reg & ~PCI_ROM_ADDRESS_ENABLE);
1315 static void __init pcibios_reserve_legacy_regions(struct pci_bus *bus)
1317 struct pci_controller *hose = pci_bus_to_host(bus);
1318 resource_size_t offset;
1319 struct resource *res, *pres;
1322 pr_debug("Reserving legacy ranges for domain %04x\n", pci_domain_nr(bus));
1325 if (!(hose->io_resource.flags & IORESOURCE_IO))
1327 offset = (unsigned long)hose->io_base_virt - _IO_BASE;
1328 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1329 BUG_ON(res == NULL);
1330 res->name = "Legacy IO";
1331 res->flags = IORESOURCE_IO;
1332 res->start = offset;
1333 res->end = (offset + 0xfff) & 0xfffffffful;
1334 pr_debug("Candidate legacy IO: %pR\n", res);
1335 if (request_resource(&hose->io_resource, res)) {
1337 "PCI %04x:%02x Cannot reserve Legacy IO %pR\n",
1338 pci_domain_nr(bus), bus->number, res);
1343 /* Check for memory */
1344 for (i = 0; i < 3; i++) {
1345 pres = &hose->mem_resources[i];
1346 offset = hose->mem_offset[i];
1347 if (!(pres->flags & IORESOURCE_MEM))
1349 pr_debug("hose mem res: %pR\n", pres);
1350 if ((pres->start - offset) <= 0xa0000 &&
1351 (pres->end - offset) >= 0xbffff)
1356 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
1357 BUG_ON(res == NULL);
1358 res->name = "Legacy VGA memory";
1359 res->flags = IORESOURCE_MEM;
1360 res->start = 0xa0000 + offset;
1361 res->end = 0xbffff + offset;
1362 pr_debug("Candidate VGA memory: %pR\n", res);
1363 if (request_resource(pres, res)) {
1365 "PCI %04x:%02x Cannot reserve VGA memory %pR\n",
1366 pci_domain_nr(bus), bus->number, res);
1371 void __init pcibios_resource_survey(void)
1375 /* Allocate and assign resources */
1376 list_for_each_entry(b, &pci_root_buses, node)
1377 pcibios_allocate_bus_resources(b);
1378 if (!pci_has_flag(PCI_REASSIGN_ALL_RSRC)) {
1379 pcibios_allocate_resources(0);
1380 pcibios_allocate_resources(1);
1383 /* Before we start assigning unassigned resource, we try to reserve
1384 * the low IO area and the VGA memory area if they intersect the
1385 * bus available resources to avoid allocating things on top of them
1387 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1388 list_for_each_entry(b, &pci_root_buses, node)
1389 pcibios_reserve_legacy_regions(b);
1392 /* Now, if the platform didn't decide to blindly trust the firmware,
1393 * we proceed to assigning things that were left unassigned
1395 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1396 pr_debug("PCI: Assigning unassigned resources...\n");
1397 pci_assign_unassigned_resources();
1401 /* This is used by the PCI hotplug driver to allocate resource
1402 * of newly plugged busses. We can try to consolidate with the
1403 * rest of the code later, for now, keep it as-is as our main
1404 * resource allocation function doesn't deal with sub-trees yet.
1406 void pcibios_claim_one_bus(struct pci_bus *bus)
1408 struct pci_dev *dev;
1409 struct pci_bus *child_bus;
1411 list_for_each_entry(dev, &bus->devices, bus_list) {
1414 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1415 struct resource *r = &dev->resource[i];
1417 if (r->parent || !r->start || !r->flags)
1420 pr_debug("PCI: Claiming %s: Resource %d: %pR\n",
1421 pci_name(dev), i, r);
1423 if (pci_claim_resource(dev, i) == 0)
1426 pci_claim_bridge_resource(dev, i);
1430 list_for_each_entry(child_bus, &bus->children, node)
1431 pcibios_claim_one_bus(child_bus);
1433 EXPORT_SYMBOL_GPL(pcibios_claim_one_bus);
1436 /* pcibios_finish_adding_to_bus
1438 * This is to be called by the hotplug code after devices have been
1439 * added to a bus, this include calling it for a PHB that is just
1442 void pcibios_finish_adding_to_bus(struct pci_bus *bus)
1444 pr_debug("PCI: Finishing adding to hotplug bus %04x:%02x\n",
1445 pci_domain_nr(bus), bus->number);
1447 /* Allocate bus and devices resources */
1448 pcibios_allocate_bus_resources(bus);
1449 pcibios_claim_one_bus(bus);
1450 if (!pci_has_flag(PCI_PROBE_ONLY)) {
1452 pci_assign_unassigned_bridge_resources(bus->self);
1454 pci_assign_unassigned_bus_resources(bus);
1458 eeh_add_device_tree_late(bus);
1460 /* Add new devices to global lists. Register in proc, sysfs. */
1461 pci_bus_add_devices(bus);
1463 /* sysfs files should only be added after devices are added */
1464 eeh_add_sysfs_files(bus);
1466 EXPORT_SYMBOL_GPL(pcibios_finish_adding_to_bus);
1468 int pcibios_enable_device(struct pci_dev *dev, int mask)
1470 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1472 if (phb->controller_ops.enable_device_hook)
1473 if (!phb->controller_ops.enable_device_hook(dev))
1476 return pci_enable_resources(dev, mask);
1479 void pcibios_disable_device(struct pci_dev *dev)
1481 struct pci_controller *phb = pci_bus_to_host(dev->bus);
1483 if (phb->controller_ops.disable_device)
1484 phb->controller_ops.disable_device(dev);
1487 resource_size_t pcibios_io_space_offset(struct pci_controller *hose)
1489 return (unsigned long) hose->io_base_virt - _IO_BASE;
1492 static void pcibios_setup_phb_resources(struct pci_controller *hose,
1493 struct list_head *resources)
1495 struct resource *res;
1496 resource_size_t offset;
1499 /* Hookup PHB IO resource */
1500 res = &hose->io_resource;
1503 pr_debug("PCI: I/O resource not set for host"
1504 " bridge %pOF (domain %d)\n",
1505 hose->dn, hose->global_number);
1507 offset = pcibios_io_space_offset(hose);
1509 pr_debug("PCI: PHB IO resource = %pR off 0x%08llx\n",
1510 res, (unsigned long long)offset);
1511 pci_add_resource_offset(resources, res, offset);
1514 /* Hookup PHB Memory resources */
1515 for (i = 0; i < 3; ++i) {
1516 res = &hose->mem_resources[i];
1520 offset = hose->mem_offset[i];
1521 pr_debug("PCI: PHB MEM resource %d = %pR off 0x%08llx\n", i,
1522 res, (unsigned long long)offset);
1524 pci_add_resource_offset(resources, res, offset);
1529 * Null PCI config access functions, for the case when we can't
1532 #define NULL_PCI_OP(rw, size, type) \
1534 null_##rw##_config_##size(struct pci_dev *dev, int offset, type val) \
1536 return PCIBIOS_DEVICE_NOT_FOUND; \
1540 null_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
1543 return PCIBIOS_DEVICE_NOT_FOUND;
1547 null_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
1550 return PCIBIOS_DEVICE_NOT_FOUND;
1553 static struct pci_ops null_pci_ops =
1555 .read = null_read_config,
1556 .write = null_write_config,
1560 * These functions are used early on before PCI scanning is done
1561 * and all of the pci_dev and pci_bus structures have been created.
1563 static struct pci_bus *
1564 fake_pci_bus(struct pci_controller *hose, int busnr)
1566 static struct pci_bus bus;
1569 printk(KERN_ERR "Can't find hose for PCI bus %d!\n", busnr);
1573 bus.ops = hose? hose->ops: &null_pci_ops;
1577 #define EARLY_PCI_OP(rw, size, type) \
1578 int early_##rw##_config_##size(struct pci_controller *hose, int bus, \
1579 int devfn, int offset, type value) \
1581 return pci_bus_##rw##_config_##size(fake_pci_bus(hose, bus), \
1582 devfn, offset, value); \
1585 EARLY_PCI_OP(read, byte, u8 *)
1586 EARLY_PCI_OP(read, word, u16 *)
1587 EARLY_PCI_OP(read, dword, u32 *)
1588 EARLY_PCI_OP(write, byte, u8)
1589 EARLY_PCI_OP(write, word, u16)
1590 EARLY_PCI_OP(write, dword, u32)
1592 int early_find_capability(struct pci_controller *hose, int bus, int devfn,
1595 return pci_bus_find_capability(fake_pci_bus(hose, bus), devfn, cap);
1598 struct device_node *pcibios_get_phb_of_node(struct pci_bus *bus)
1600 struct pci_controller *hose = bus->sysdata;
1602 return of_node_get(hose->dn);
1606 * pci_scan_phb - Given a pci_controller, setup and scan the PCI bus
1607 * @hose: Pointer to the PCI host controller instance structure
1609 void pcibios_scan_phb(struct pci_controller *hose)
1611 LIST_HEAD(resources);
1612 struct pci_bus *bus;
1613 struct device_node *node = hose->dn;
1616 pr_debug("PCI: Scanning PHB %pOF\n", node);
1618 /* Get some IO space for the new PHB */
1619 pcibios_setup_phb_io_space(hose);
1621 /* Wire up PHB bus resources */
1622 pcibios_setup_phb_resources(hose, &resources);
1624 hose->busn.start = hose->first_busno;
1625 hose->busn.end = hose->last_busno;
1626 hose->busn.flags = IORESOURCE_BUS;
1627 pci_add_resource(&resources, &hose->busn);
1629 /* Create an empty bus for the toplevel */
1630 bus = pci_create_root_bus(hose->parent, hose->first_busno,
1631 hose->ops, hose, &resources);
1633 pr_err("Failed to create bus for PCI domain %04x\n",
1634 hose->global_number);
1635 pci_free_resource_list(&resources);
1640 /* Get probe mode and perform scan */
1641 mode = PCI_PROBE_NORMAL;
1642 if (node && hose->controller_ops.probe_mode)
1643 mode = hose->controller_ops.probe_mode(bus);
1644 pr_debug(" probe mode: %d\n", mode);
1645 if (mode == PCI_PROBE_DEVTREE)
1646 of_scan_bus(node, bus);
1648 if (mode == PCI_PROBE_NORMAL) {
1649 pci_bus_update_busn_res_end(bus, 255);
1650 hose->last_busno = pci_scan_child_bus(bus);
1651 pci_bus_update_busn_res_end(bus, hose->last_busno);
1654 /* Platform gets a chance to do some global fixups before
1655 * we proceed to resource allocation
1657 if (ppc_md.pcibios_fixup_phb)
1658 ppc_md.pcibios_fixup_phb(hose);
1660 /* Configure PCI Express settings */
1661 if (bus && !pci_has_flag(PCI_PROBE_ONLY)) {
1662 struct pci_bus *child;
1663 list_for_each_entry(child, &bus->children, node)
1664 pcie_bus_configure_settings(child);
1667 EXPORT_SYMBOL_GPL(pcibios_scan_phb);
1669 static void fixup_hide_host_resource_fsl(struct pci_dev *dev)
1671 int i, class = dev->class >> 8;
1672 /* When configured as agent, programing interface = 1 */
1673 int prog_if = dev->class & 0xf;
1675 if ((class == PCI_CLASS_PROCESSOR_POWERPC ||
1676 class == PCI_CLASS_BRIDGE_OTHER) &&
1677 (dev->hdr_type == PCI_HEADER_TYPE_NORMAL) &&
1679 (dev->bus->parent == NULL)) {
1680 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1681 dev->resource[i].start = 0;
1682 dev->resource[i].end = 0;
1683 dev->resource[i].flags = 0;
1687 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MOTOROLA, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1688 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, fixup_hide_host_resource_fsl);
1691 static int __init discover_phbs(void)
1693 if (ppc_md.discover_phbs)
1694 ppc_md.discover_phbs();
1698 core_initcall(discover_phbs);