1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * This file contains miscellaneous low-level functions.
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
6 * Largely rewritten by Cort Dougan (cort@cs.nmt.edu)
10 * Copyright (C) 2002-2003 Eric Biederman <ebiederm@xmission.com>
11 * GameCube/ppc32 port Copyright (C) 2004 Albert Herranz
12 * PPC44x port. Copyright (C) 2011, IBM Corporation
13 * Author: Suzuki Poulose <suzuki@in.ibm.com>
16 #include <linux/sys.h>
17 #include <asm/unistd.h>
18 #include <asm/errno.h>
21 #include <asm/cache.h>
22 #include <asm/cputable.h>
24 #include <asm/ppc_asm.h>
25 #include <asm/thread_info.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/processor.h>
28 #include <asm/kexec.h>
30 #include <asm/ptrace.h>
31 #include <asm/export.h>
32 #include <asm/feature-fixups.h>
37 * We store the saved ksp_limit in the unused part
38 * of the STACK_FRAME_OVERHEAD
40 _GLOBAL(call_do_softirq)
43 lwz r10,THREAD+KSP_LIMIT(r2)
44 stw r3, THREAD+KSP_LIMIT(r2)
45 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r3)
52 stw r10,THREAD+KSP_LIMIT(r2)
57 * void call_do_irq(struct pt_regs *regs, void *sp);
62 lwz r10,THREAD+KSP_LIMIT(r2)
63 stw r4, THREAD+KSP_LIMIT(r2)
64 stwu r1,THREAD_SIZE-STACK_FRAME_OVERHEAD(r4)
71 stw r10,THREAD+KSP_LIMIT(r2)
76 * This returns the high 64 bits of the product of two 64-bit numbers.
88 1: beqlr cr1 /* all done if high part of A is 0 */
102 * reloc_got2 runs through the .got2 section adding an offset
107 lis r7,__got2_start@ha
108 addi r7,r7,__got2_start@l
110 addi r8,r8,__got2_end@l
130 * call_setup_cpu - call the setup_cpu function for this cpu
131 * r3 = data offset, r24 = cpu number
133 * Setup function is called with:
135 * r4 = ptr to CPU spec (relocated)
137 _GLOBAL(call_setup_cpu)
138 addis r4,r3,cur_cpu_spec@ha
139 addi r4,r4,cur_cpu_spec@l
142 lwz r5,CPU_SPEC_SETUP(r4)
149 #if defined(CONFIG_CPU_FREQ_PMAC) && defined(CONFIG_PPC_BOOK3S_32)
151 /* This gets called by via-pmu.c to switch the PLL selection
152 * on 750fx CPU. This function should really be moved to some
153 * other place (as most of the cpufreq code in via-pmu
155 _GLOBAL(low_choose_750fx_pll)
161 /* If switching to PLL1, disable HID0:BTIC */
172 /* Calc new HID1 value */
173 mfspr r4,SPRN_HID1 /* Build a HID1:PS bit from parameter */
174 rlwinm r5,r3,16,15,15 /* Clear out HID1:PS from value read */
175 rlwinm r4,r4,0,16,14 /* Could have I used rlwimi here ? */
180 /* Store new HID1 image */
186 addis r6,r6,nap_save_hid1@ha
187 stw r4,nap_save_hid1@l(r6)
189 /* If switching to PLL0, enable HID0:BTIC */
204 _GLOBAL(low_choose_7447a_dfs)
210 /* Calc new HID1 value */
212 insrwi r4,r3,1,9 /* insert parameter into bit 9 */
222 #endif /* CONFIG_CPU_FREQ_PMAC && CONFIG_PPC_BOOK3S_32 */
225 * complement mask on the msr then "or" some values on.
226 * _nmask_and_or_msr(nmask, value_to_or)
228 _GLOBAL(_nmask_and_or_msr)
229 mfmsr r0 /* Get current msr */
230 andc r0,r0,r3 /* And off the bits set in r3 (first parm) */
231 or r0,r0,r4 /* Or on the bits in r4 (second parm) */
232 SYNC /* Some chip revs have problems here... */
233 mtmsr r0 /* Update machine state */
240 * Do an IO access in real mode
244 rlwinm r0,r7,0,~MSR_DR
257 * Do an IO access in real mode
261 rlwinm r0,r7,0,~MSR_DR
273 #endif /* CONFIG_40x */
277 * Flush instruction cache.
278 * This is a no-op on the 601.
280 #ifndef CONFIG_PPC_8xx
281 _GLOBAL(flush_instruction_cache)
282 #if defined(CONFIG_4xx)
294 #elif defined(CONFIG_FSL_BOOKE)
297 ori r3,r3,L1CSR0_CFI|L1CSR0_CLFC
298 /* msync; isync recommended here */
304 ori r3,r3,L1CSR1_ICFI|L1CSR1_ICLFR
306 #elif defined(CONFIG_PPC_BOOK3S_601)
307 blr /* for 601, do nothing */
309 /* 603/604 processor - use invalidate-all bit in HID0 */
313 #endif /* CONFIG_4xx */
316 EXPORT_SYMBOL(flush_instruction_cache)
317 #endif /* CONFIG_PPC_8xx */
320 * Copy a whole page. We use the dcbz instruction on the destination
321 * to reduce memory traffic (it eliminates the unnecessary reads of
322 * the destination into cache). This requires that the destination
325 #define COPY_16_BYTES \
336 rlwinm r5, r3, 0, L1_CACHE_BYTES - 1
339 0: twnei r5, 0 /* WARN if r3 is not cache aligned */
340 EMIT_BUG_ENTRY 0b,__FILE__,__LINE__, BUGFLAG_WARNING
346 #if MAX_COPY_PREFETCH > 1
347 li r0,MAX_COPY_PREFETCH
351 addi r11,r11,L1_CACHE_BYTES
353 #else /* MAX_COPY_PREFETCH == 1 */
355 li r11,L1_CACHE_BYTES+4
356 #endif /* MAX_COPY_PREFETCH */
357 li r0,PAGE_SIZE/L1_CACHE_BYTES - MAX_COPY_PREFETCH
365 #if L1_CACHE_BYTES >= 32
367 #if L1_CACHE_BYTES >= 64
370 #if L1_CACHE_BYTES >= 128
380 crnot 4*cr0+eq,4*cr0+eq
381 li r0,MAX_COPY_PREFETCH
384 EXPORT_SYMBOL(copy_page)
387 * Extended precision shifts.
389 * Updated to be valid for shift counts from 0 to 63 inclusive.
392 * R3/R4 has 64 bit value
396 * ashrdi3: arithmetic right shift (sign propagation)
397 * lshrdi3: logical right shift
398 * ashldi3: left shift
402 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
403 addi r7,r5,32 # could be xori, or addi with -32
404 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
405 rlwinm r8,r7,0,32 # t3 = (count < 32) ? 32 : 0
406 sraw r7,r3,r7 # t2 = MSW >> (count-32)
407 or r4,r4,r6 # LSW |= t1
408 slw r7,r7,r8 # t2 = (count < 32) ? 0 : t2
409 sraw r3,r3,r5 # MSW = MSW >> count
410 or r4,r4,r7 # LSW |= t2
412 EXPORT_SYMBOL(__ashrdi3)
416 slw r3,r3,r5 # MSW = count > 31 ? 0 : MSW << count
417 addi r7,r5,32 # could be xori, or addi with -32
418 srw r6,r4,r6 # t1 = count > 31 ? 0 : LSW >> (32-count)
419 slw r7,r4,r7 # t2 = count < 32 ? 0 : LSW << (count-32)
420 or r3,r3,r6 # MSW |= t1
421 slw r4,r4,r5 # LSW = LSW << count
422 or r3,r3,r7 # MSW |= t2
424 EXPORT_SYMBOL(__ashldi3)
428 srw r4,r4,r5 # LSW = count > 31 ? 0 : LSW >> count
429 addi r7,r5,32 # could be xori, or addi with -32
430 slw r6,r3,r6 # t1 = count > 31 ? 0 : MSW << (32-count)
431 srw r7,r3,r7 # t2 = count < 32 ? 0 : MSW >> (count-32)
432 or r4,r4,r6 # LSW |= t1
433 srw r3,r3,r5 # MSW = MSW >> count
434 or r4,r4,r7 # LSW |= t2
436 EXPORT_SYMBOL(__lshrdi3)
439 * 64-bit comparison: __cmpdi2(s64 a, s64 b)
440 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
452 EXPORT_SYMBOL(__cmpdi2)
454 * 64-bit comparison: __ucmpdi2(u64 a, u64 b)
455 * Returns 0 if a < b, 1 if a == b, 2 if a > b.
467 EXPORT_SYMBOL(__ucmpdi2)
474 rlwimi r9,r4,24,16,23
475 rlwimi r10,r3,24,16,23
479 EXPORT_SYMBOL(__bswapdi2)
482 _GLOBAL(start_secondary_resume)
484 rlwinm r1, r1, 0, 0, 31 - THREAD_SHIFT
485 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
487 stw r3,0(r1) /* Zero the stack frame pointer */
490 #endif /* CONFIG_SMP */
493 * This routine is just here to keep GCC happy - sigh...
498 #ifdef CONFIG_KEXEC_CORE
500 * Must be relocatable PIC code callable as a C function.
502 .globl relocate_new_kernel
505 /* r4 = reboot_code_buffer */
506 /* r5 = start_address */
508 #ifdef CONFIG_FSL_BOOKE
514 #define ENTRY_MAPPING_KEXEC_SETUP
515 #include "fsl_booke_entry_mapping.S"
516 #undef ENTRY_MAPPING_KEXEC_SETUP
523 #elif defined(CONFIG_44x)
525 /* Save our parameters */
530 #ifdef CONFIG_PPC_47x
531 /* Check for 47x cores */
534 cmplwi cr0,r3,PVR_476FPE@h
536 cmplwi cr0,r3,PVR_476@h
538 cmplwi cr0,r3,PVR_476_ISS@h
540 #endif /* CONFIG_PPC_47x */
543 * Code for setting up 1:1 mapping for PPC440x for KEXEC
545 * We cannot switch off the MMU on PPC44x.
547 * 1) Invalidate all the mappings except the one we are running from.
548 * 2) Create a tmp mapping for our code in the other address space(TS) and
549 * jump to it. Invalidate the entry we started in.
550 * 3) Create a 1:1 mapping for 0-2GiB in chunks of 256M in original TS.
551 * 4) Jump to the 1:1 mapping in original TS.
552 * 5) Invalidate the tmp mapping.
554 * - Based on the kexec support code for FSL BookE
559 * Load the PID with kernel PID (0).
560 * Also load our MSR_IS and TID to MMUCR for TLB search.
567 oris r3,r3,PPC44x_MMUCR_STS@h
573 * Invalidate all the TLB entries except the current entry
574 * where we are running from
576 bl 0f /* Find our address */
577 0: mflr r5 /* Make it accessible */
578 tlbsx r23,0,r5 /* Find entry we are in */
579 li r4,0 /* Start at TLB entry 0 */
580 li r3,0 /* Set PAGEID inval value */
581 1: cmpw r23,r4 /* Is this our entry? */
582 beq skip /* If so, skip the inval */
583 tlbwe r3,r4,PPC44x_TLB_PAGEID /* If not, inval the entry */
585 addi r4,r4,1 /* Increment */
586 cmpwi r4,64 /* Are we done? */
587 bne 1b /* If not, repeat */
590 /* Create a temp mapping and jump to it */
591 andi. r6, r23, 1 /* Find the index to use */
592 addi r24, r6, 1 /* r24 will contain 1 or 2 */
594 mfmsr r9 /* get the MSR */
595 rlwinm r5, r9, 27, 31, 31 /* Extract the MSR[IS] */
596 xori r7, r5, 1 /* Use the other address space */
598 /* Read the current mapping entries */
599 tlbre r3, r23, PPC44x_TLB_PAGEID
600 tlbre r4, r23, PPC44x_TLB_XLAT
601 tlbre r5, r23, PPC44x_TLB_ATTRIB
603 /* Save our current XLAT entry */
606 /* Extract the TLB PageSize */
607 li r10, 1 /* r10 will hold PageSize */
608 rlwinm r11, r3, 0, 24, 27 /* bits 24-27 */
610 /* XXX: As of now we use 256M, 4K pages */
611 cmpwi r11, PPC44x_TLB_256M
613 rotlwi r10, r10, 28 /* r10 = 256M */
616 cmpwi r11, PPC44x_TLB_4K
618 rotlwi r10, r10, 12 /* r10 = 4K */
621 rotlwi r10, r10, 10 /* r10 = 1K */
625 * Write out the tmp 1:1 mapping for this code in other address space
626 * Fixup EPN = RPN , TS=other address space
628 insrwi r3, r7, 1, 23 /* Bit 23 is TS for PAGEID field */
630 /* Write out the tmp mapping entries */
631 tlbwe r3, r24, PPC44x_TLB_PAGEID
632 tlbwe r4, r24, PPC44x_TLB_XLAT
633 tlbwe r5, r24, PPC44x_TLB_ATTRIB
635 subi r11, r10, 1 /* PageOffset Mask = PageSize - 1 */
636 not r10, r11 /* Mask for PageNum */
638 /* Switch to other address space in MSR */
639 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
643 addi r8, r8, (2f-1b) /* Find the target offset */
645 /* Jump to the tmp mapping */
651 /* Invalidate the entry we were executing from */
653 tlbwe r3, r23, PPC44x_TLB_PAGEID
655 /* attribute fields. rwx for SUPERVISOR mode */
657 ori r5, r5, (PPC44x_TLB_SW | PPC44x_TLB_SR | PPC44x_TLB_SX | PPC44x_TLB_G)
659 /* Create 1:1 mapping in 256M pages */
660 xori r7, r7, 1 /* Revert back to Original TS */
662 li r8, 0 /* PageNumber */
663 li r6, 3 /* TLB Index, start at 3 */
666 rotlwi r3, r8, 28 /* Create EPN (bits 0-3) */
667 mr r4, r3 /* RPN = EPN */
668 ori r3, r3, (PPC44x_TLB_VALID | PPC44x_TLB_256M) /* SIZE = 256M, Valid */
669 insrwi r3, r7, 1, 23 /* Set TS from r7 */
671 tlbwe r3, r6, PPC44x_TLB_PAGEID /* PageID field : EPN, V, SIZE */
672 tlbwe r4, r6, PPC44x_TLB_XLAT /* Address translation : RPN */
673 tlbwe r5, r6, PPC44x_TLB_ATTRIB /* Attributes */
675 addi r8, r8, 1 /* Increment PN */
676 addi r6, r6, 1 /* Increment TLB Index */
677 cmpwi r8, 8 /* Are we done ? */
681 /* Jump to the new mapping 1:1 */
683 insrwi r9, r7, 1, 26 /* Set MSR[IS] = r7 */
687 and r8, r8, r11 /* Get our offset within page */
690 and r5, r25, r10 /* Get our target PageNum */
691 or r8, r8, r5 /* Target jump address */
697 /* Invalidate the tmp entry we used */
699 tlbwe r3, r24, PPC44x_TLB_PAGEID
703 #ifdef CONFIG_PPC_47x
705 /* 1:1 mapping for 47x */
710 * Load the kernel pid (0) to PID and also to MMUCR[TID].
711 * Also set the MSR IS->MMUCR STS
714 mtspr SPRN_PID, r3 /* Set PID */
715 mfmsr r4 /* Get MSR */
716 andi. r4, r4, MSR_IS@l /* TS=1? */
717 beq 1f /* If not, leave STS=0 */
718 oris r3, r3, PPC47x_MMUCR_STS@h /* Set STS=1 */
719 1: mtspr SPRN_MMUCR, r3 /* Put MMUCR */
722 /* Find the entry we are running from */
726 tlbre r24, r23, 0 /* TLB Word 0 */
727 tlbre r25, r23, 1 /* TLB Word 1 */
728 tlbre r26, r23, 2 /* TLB Word 2 */
732 * Invalidates all the tlb entries by writing to 256 RPNs(r4)
733 * of 4k page size in all 4 ways (0-3 in r3).
734 * This would invalidate the entire UTLB including the one we are
735 * running from. However the shadow TLB entries would help us
736 * to continue the execution, until we flush them (rfi/isync).
738 addis r3, 0, 0x8000 /* specify the way */
739 addi r4, 0, 0 /* TLB Word0 = (EPN=0, VALID = 0) */
743 /* Align the loop to speed things up. from head_44x.S */
751 addis r3, r3, 0x2000 /* Increment the way */
755 addis r4, r4, 0x100 /* Increment the EPN */
759 /* Create the entries in the other address space */
761 rlwinm r7, r5, 27, 31, 31 /* Get the TS (Bit 26) from MSR */
762 xori r7, r7, 1 /* r7 = !TS */
764 insrwi r24, r7, 1, 21 /* Change the TS in the saved TLB word 0 */
767 * write out the TLB entries for the tmp mapping
768 * Use way '0' so that we could easily invalidate it later.
770 lis r3, 0x8000 /* Way '0' */
776 /* Update the msr to the new TS */
788 * Now we are in the tmp address space.
789 * Create a 1:1 mapping for 0-2GiB in the original TS.
793 li r4, 0 /* TLB Word 0 */
794 li r5, 0 /* TLB Word 1 */
796 ori r6, r6, PPC47x_TLB2_S_RWX /* TLB word 2 */
798 li r8, 0 /* PageIndex */
800 xori r7, r7, 1 /* revert back to original TS */
803 rotlwi r5, r8, 28 /* RPN = PageIndex * 256M */
804 /* ERPN = 0 as we don't use memory above 2G */
806 mr r4, r5 /* EPN = RPN */
807 ori r4, r4, (PPC47x_TLB0_VALID | PPC47x_TLB0_256M)
808 insrwi r4, r7, 1, 21 /* Insert the TS to Word 0 */
810 tlbwe r4, r3, 0 /* Write out the entries */
814 cmpwi r8, 8 /* Have we completed ? */
817 /* make sure we complete the TLB write up */
821 * Prepare to jump to the 1:1 mapping.
822 * 1) Extract page size of the tmp mapping
823 * DSIZ = TLB_Word0[22:27]
824 * 2) Calculate the physical address of the address
827 rlwinm r10, r24, 0, 22, 27
829 cmpwi r10, PPC47x_TLB0_4K
831 li r10, 0x1000 /* r10 = 4k */
835 /* Defaults to 256M */
840 addi r4, r4, (2f-1b) /* virtual address of 2f */
842 subi r11, r10, 1 /* offsetmask = Pagesize - 1 */
843 not r10, r11 /* Pagemask = ~(offsetmask) */
845 and r5, r25, r10 /* Physical page */
846 and r6, r4, r11 /* offset within the current page */
848 or r5, r5, r6 /* Physical address for 2f */
850 /* Switch the TS in MSR to the original one */
859 /* Invalidate the tmp mapping */
860 lis r3, 0x8000 /* Way '0' */
862 clrrwi r24, r24, 12 /* Clear the valid bit */
867 /* Make sure we complete the TLB write and flush the shadow TLB */
875 /* Restore the parameters */
885 * Set Machine Status Register to a known status,
886 * switch the MMU off and jump to 1: in a single step.
890 ori r8, r8, MSR_RI|MSR_ME
892 addi r8, r4, 1f - relocate_new_kernel
899 /* from this point address translation is turned off */
900 /* and interrupts are disabled */
902 /* set a new stack at the bottom of our page... */
903 /* (not really needed now) */
904 addi r1, r4, KEXEC_CONTROL_PAGE_SIZE - 8 /* for LR Save+Back Chain */
908 li r6, 0 /* checksum */
912 0: /* top, read another word for the indirection page */
916 /* is it a destination page? (r8) */
917 rlwinm. r7, r0, 0, 31, 31 /* IND_DESTINATION (1<<0) */
920 rlwinm r8, r0, 0, 0, 19 /* clear kexec flags, page align */
923 2: /* is it an indirection page? (r3) */
924 rlwinm. r7, r0, 0, 30, 30 /* IND_INDIRECTION (1<<1) */
927 rlwinm r3, r0, 0, 0, 19 /* clear kexec flags, page align */
931 2: /* are we done? */
932 rlwinm. r7, r0, 0, 29, 29 /* IND_DONE (1<<2) */
936 2: /* is it a source page? (r9) */
937 rlwinm. r7, r0, 0, 28, 28 /* IND_SOURCE (1<<3) */
940 rlwinm r9, r0, 0, 0, 19 /* clear kexec flags, page align */
947 lwzu r0, 4(r9) /* do the copy */
961 /* To be certain of avoiding problems with self-modifying code
962 * execute a serializing instruction here.
967 mfspr r3, SPRN_PIR /* current core we are running on */
968 mr r4, r5 /* load physical address of chunk called */
970 /* jump to the entry point, usually the setup routine */
976 relocate_new_kernel_end:
978 .globl relocate_new_kernel_size
979 relocate_new_kernel_size:
980 .long relocate_new_kernel_end - relocate_new_kernel