1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Derived from arch/i386/kernel/irq.c
4 * Copyright (C) 1992 Linus Torvalds
5 * Adapted from arch/i386 by Gary Thomas
6 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
7 * Updated and modified by Cort Dougan <cort@fsmlabs.com>
8 * Copyright (C) 1996-2001 Cort Dougan
9 * Adapted for Power Macintosh by Paul Mackerras
10 * Copyright (C) 1996 Paul Mackerras (paulus@cs.anu.edu.au)
12 * This file contains the code used by various IRQ handling routines:
13 * asking for different IRQ's should be done through these routines
14 * instead of just grabbing them. Thus setups with different IRQ numbers
15 * shouldn't result in any weird surprises, and installing new handlers
18 * The MPC8xx has an interrupt mask in the SIU. If a bit is set, the
19 * interrupt is _enabled_. As expected, IRQ0 is bit 0 in the 32-bit
20 * mask register (of which only 16 are defined), hence the weird shifting
21 * and complement of the cached_irq_mask. I want to be able to stuff
22 * this right into the SIU SMASK register.
23 * Many of the prep/chrp functions are conditional compiled on CONFIG_PPC_8xx
24 * to reduce code space and undefined function references.
29 #include <linux/export.h>
30 #include <linux/threads.h>
31 #include <linux/kernel_stat.h>
32 #include <linux/signal.h>
33 #include <linux/sched.h>
34 #include <linux/ptrace.h>
35 #include <linux/ioport.h>
36 #include <linux/interrupt.h>
37 #include <linux/timex.h>
38 #include <linux/init.h>
39 #include <linux/slab.h>
40 #include <linux/delay.h>
41 #include <linux/irq.h>
42 #include <linux/seq_file.h>
43 #include <linux/cpumask.h>
44 #include <linux/profile.h>
45 #include <linux/bitops.h>
46 #include <linux/list.h>
47 #include <linux/radix-tree.h>
48 #include <linux/mutex.h>
49 #include <linux/pci.h>
50 #include <linux/debugfs.h>
52 #include <linux/of_irq.h>
53 #include <linux/vmalloc.h>
54 #include <linux/pgtable.h>
56 #include <linux/uaccess.h>
59 #include <asm/cache.h>
61 #include <asm/ptrace.h>
62 #include <asm/machdep.h>
65 #include <asm/livepatch.h>
66 #include <asm/asm-prototypes.h>
67 #include <asm/hw_irq.h>
71 #include <asm/firmware.h>
72 #include <asm/lv1call.h>
73 #include <asm/dbell.h>
75 #define CREATE_TRACE_POINTS
76 #include <asm/trace.h>
77 #include <asm/cpu_has_feature.h>
79 DEFINE_PER_CPU_SHARED_ALIGNED(irq_cpustat_t, irq_stat);
80 EXPORT_PER_CPU_SYMBOL(irq_stat);
83 atomic_t ppc_n_lost_interrupts;
86 extern int tau_initialized;
87 u32 tau_interrupts(unsigned long cpu);
89 #endif /* CONFIG_PPC32 */
93 int distribute_irqs = 1;
95 static inline notrace unsigned long get_irq_happened(void)
97 unsigned long happened;
99 __asm__ __volatile__("lbz %0,%1(13)"
100 : "=r" (happened) : "i" (offsetof(struct paca_struct, irq_happened)));
105 #ifdef CONFIG_PPC_BOOK3E
107 /* This is called whenever we are re-enabling interrupts
108 * and returns either 0 (nothing to do) or 500/900/280 if
109 * there's an EE, DEC or DBELL to generate.
111 * This is called in two contexts: From arch_local_irq_restore()
112 * before soft-enabling interrupts, and from the exception exit
113 * path when returning from an interrupt from a soft-disabled to
114 * a soft enabled context. In both case we have interrupts hard
117 * We take care of only clearing the bits we handled in the
118 * PACA irq_happened field since we can only re-emit one at a
119 * time and we don't want to "lose" one.
121 notrace unsigned int __check_irq_replay(void)
124 * We use local_paca rather than get_paca() to avoid all
125 * the debug_smp_processor_id() business in this low level
128 unsigned char happened = local_paca->irq_happened;
131 * We are responding to the next interrupt, so interrupt-off
132 * latencies should be reset here.
135 trace_hardirqs_off();
137 if (happened & PACA_IRQ_DEC) {
138 local_paca->irq_happened &= ~PACA_IRQ_DEC;
142 if (happened & PACA_IRQ_EE) {
143 local_paca->irq_happened &= ~PACA_IRQ_EE;
147 if (happened & PACA_IRQ_DBELL) {
148 local_paca->irq_happened &= ~PACA_IRQ_DBELL;
152 if (happened & PACA_IRQ_HARD_DIS)
153 local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
155 /* There should be nothing left ! */
156 BUG_ON(local_paca->irq_happened != 0);
162 * This is specifically called by assembly code to re-enable interrupts
163 * if they are currently disabled. This is typically called before
164 * schedule() or do_signal() when returning to userspace. We do it
165 * in C to avoid the burden of dealing with lockdep etc...
167 * NOTE: This is called with interrupts hard disabled but not marked
168 * as such in paca->irq_happened, so we need to resync this.
170 void notrace restore_interrupts(void)
172 if (irqs_disabled()) {
173 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
179 #endif /* CONFIG_PPC_BOOK3E */
181 void replay_soft_interrupts(void)
186 * Be careful here, calling these interrupt handlers can cause
187 * softirqs to be raised, which they may run when calling irq_exit,
188 * which will cause local_irq_enable() to be run, which can then
189 * recurse into this function. Don't keep any state across
190 * interrupt handler calls which may change underneath us.
192 * We use local_paca rather than get_paca() to avoid all the
193 * debug_smp_processor_id() business in this low level function.
196 ppc_save_regs(®s);
197 regs.softe = IRQS_ENABLED;
200 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
201 WARN_ON_ONCE(mfmsr() & MSR_EE);
204 * Force the delivery of pending soft-disabled interrupts on PS3.
205 * Any HV call will have this side effect.
207 if (firmware_has_feature(FW_FEATURE_PS3_LV1)) {
209 lv1_get_version_info(&tmp, &tmp2);
213 * Check if an hypervisor Maintenance interrupt happened.
214 * This is a higher priority interrupt than the others, so
217 if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (local_paca->irq_happened & PACA_IRQ_HMI)) {
218 local_paca->irq_happened &= ~PACA_IRQ_HMI;
220 handle_hmi_exception(®s);
221 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
225 if (local_paca->irq_happened & PACA_IRQ_DEC) {
226 local_paca->irq_happened &= ~PACA_IRQ_DEC;
228 timer_interrupt(®s);
229 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
233 if (local_paca->irq_happened & PACA_IRQ_EE) {
234 local_paca->irq_happened &= ~PACA_IRQ_EE;
237 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
241 if (IS_ENABLED(CONFIG_PPC_DOORBELL) && (local_paca->irq_happened & PACA_IRQ_DBELL)) {
242 local_paca->irq_happened &= ~PACA_IRQ_DBELL;
243 if (IS_ENABLED(CONFIG_PPC_BOOK3E))
247 doorbell_exception(®s);
248 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
252 /* Book3E does not support soft-masking PMI interrupts */
253 if (IS_ENABLED(CONFIG_PPC_BOOK3S) && (local_paca->irq_happened & PACA_IRQ_PMI)) {
254 local_paca->irq_happened &= ~PACA_IRQ_PMI;
256 performance_monitor_exception(®s);
257 if (!(local_paca->irq_happened & PACA_IRQ_HARD_DIS))
261 if (local_paca->irq_happened & ~PACA_IRQ_HARD_DIS) {
263 * We are responding to the next interrupt, so interrupt-off
264 * latencies should be reset here.
267 trace_hardirqs_off();
272 #if defined(CONFIG_PPC_BOOK3S_64) && defined(CONFIG_PPC_KUAP)
273 static inline void replay_soft_interrupts_irqrestore(void)
275 unsigned long kuap_state = get_kuap();
278 * Check if anything calls local_irq_enable/restore() when KUAP is
279 * disabled (user access enabled). We handle that case here by saving
280 * and re-locking AMR but we shouldn't get here in the first place,
285 if (kuap_state != AMR_KUAP_BLOCKED)
286 set_kuap(AMR_KUAP_BLOCKED);
288 replay_soft_interrupts();
290 if (kuap_state != AMR_KUAP_BLOCKED)
291 set_kuap(kuap_state);
294 #define replay_soft_interrupts_irqrestore() replay_soft_interrupts()
297 notrace void arch_local_irq_restore(unsigned long mask)
299 unsigned char irq_happened;
301 /* Write the new soft-enabled value */
302 irq_soft_mask_set(mask);
307 * From this point onward, we can take interrupts, preempt,
308 * etc... unless we got hard-disabled. We check if an event
309 * happened. If none happened, we know we can just return.
311 * We may have preempted before the check below, in which case
312 * we are checking the "new" CPU instead of the old one. This
313 * is only a problem if an event happened on the "old" CPU.
315 * External interrupt events will have caused interrupts to
316 * be hard-disabled, so there is no problem, we
317 * cannot have preempted.
319 irq_happened = get_irq_happened();
321 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
322 WARN_ON_ONCE(!(mfmsr() & MSR_EE));
326 /* We need to hard disable to replay. */
327 if (!(irq_happened & PACA_IRQ_HARD_DIS)) {
328 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG))
329 WARN_ON_ONCE(!(mfmsr() & MSR_EE));
330 __hard_irq_disable();
331 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
334 * We should already be hard disabled here. We had bugs
335 * where that wasn't the case so let's dbl check it and
336 * warn if we are wrong. Only do that when IRQ tracing
337 * is enabled as mfmsr() can be costly.
339 if (IS_ENABLED(CONFIG_PPC_IRQ_SOFT_MASK_DEBUG)) {
340 if (WARN_ON_ONCE(mfmsr() & MSR_EE))
341 __hard_irq_disable();
344 if (irq_happened == PACA_IRQ_HARD_DIS) {
345 local_paca->irq_happened = 0;
352 * Disable preempt here, so that the below preempt_enable will
353 * perform resched if required (a replayed interrupt may set
357 irq_soft_mask_set(IRQS_ALL_DISABLED);
358 trace_hardirqs_off();
360 replay_soft_interrupts_irqrestore();
361 local_paca->irq_happened = 0;
364 irq_soft_mask_set(IRQS_ENABLED);
368 EXPORT_SYMBOL(arch_local_irq_restore);
371 * This is a helper to use when about to go into idle low-power
372 * when the latter has the side effect of re-enabling interrupts
373 * (such as calling H_CEDE under pHyp).
375 * You call this function with interrupts soft-disabled (this is
376 * already the case when ppc_md.power_save is called). The function
377 * will return whether to enter power save or just return.
379 * In the former case, it will have notified lockdep of interrupts
380 * being re-enabled and generally sanitized the lazy irq state,
381 * and in the latter case it will leave with interrupts hard
382 * disabled and marked as such, so the local_irq_enable() call
383 * in arch_cpu_idle() will properly re-enable everything.
385 bool prep_irq_for_idle(void)
388 * First we need to hard disable to ensure no interrupt
389 * occurs before we effectively enter the low power state
391 __hard_irq_disable();
392 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
395 * If anything happened while we were soft-disabled,
396 * we return now and do not enter the low power state.
398 if (lazy_irq_pending())
401 /* Tell lockdep we are about to re-enable */
405 * Mark interrupts as soft-enabled and clear the
406 * PACA_IRQ_HARD_DIS from the pending mask since we
407 * are about to hard enable as well as a side effect
408 * of entering the low power state.
410 local_paca->irq_happened &= ~PACA_IRQ_HARD_DIS;
411 irq_soft_mask_set(IRQS_ENABLED);
413 /* Tell the caller to enter the low power state */
417 #ifdef CONFIG_PPC_BOOK3S
419 * This is for idle sequences that return with IRQs off, but the
420 * idle state itself wakes on interrupt. Tell the irq tracer that
421 * IRQs are enabled for the duration of idle so it does not get long
422 * off times. Must be paired with fini_irq_for_idle_irqsoff.
424 bool prep_irq_for_idle_irqsoff(void)
426 WARN_ON(!irqs_disabled());
429 * First we need to hard disable to ensure no interrupt
430 * occurs before we effectively enter the low power state
432 __hard_irq_disable();
433 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
436 * If anything happened while we were soft-disabled,
437 * we return now and do not enter the low power state.
439 if (lazy_irq_pending())
442 /* Tell lockdep we are about to re-enable */
449 * Take the SRR1 wakeup reason, index into this table to find the
450 * appropriate irq_happened bit.
452 * Sytem reset exceptions taken in idle state also come through here,
453 * but they are NMI interrupts so do not need to wait for IRQs to be
454 * restored, and should be taken as early as practical. These are marked
455 * with 0xff in the table. The Power ISA specifies 0100b as the system
456 * reset interrupt reason.
458 #define IRQ_SYSTEM_RESET 0xff
460 static const u8 srr1_to_lazyirq[0x10] = {
472 void replay_system_reset(void)
476 ppc_save_regs(®s);
478 get_paca()->in_nmi = 1;
479 system_reset_exception(®s);
480 get_paca()->in_nmi = 0;
482 EXPORT_SYMBOL_GPL(replay_system_reset);
484 void irq_set_pending_from_srr1(unsigned long srr1)
486 unsigned int idx = (srr1 & SRR1_WAKEMASK_P8) >> 18;
487 u8 reason = srr1_to_lazyirq[idx];
490 * Take the system reset now, which is immediately after registers
491 * are restored from idle. It's an NMI, so interrupts need not be
492 * re-enabled before it is taken.
494 if (unlikely(reason == IRQ_SYSTEM_RESET)) {
495 replay_system_reset();
499 if (reason == PACA_IRQ_DBELL) {
501 * When doorbell triggers a system reset wakeup, the message
502 * is not cleared, so if the doorbell interrupt is replayed
503 * and the IPI handled, the doorbell interrupt would still
504 * fire when EE is enabled.
506 * To avoid taking the superfluous doorbell interrupt,
507 * execute a msgclr here before the interrupt is replayed.
509 ppc_msgclr(PPC_DBELL_MSGTYPE);
513 * The 0 index (SRR1[42:45]=b0000) must always evaluate to 0,
514 * so this can be called unconditionally with the SRR1 wake
515 * reason as returned by the idle code, which uses 0 to mean no
518 * If a future CPU was to designate this as an interrupt reason,
519 * then a new index for no interrupt must be assigned.
521 local_paca->irq_happened |= reason;
523 #endif /* CONFIG_PPC_BOOK3S */
526 * Force a replay of the external interrupt handler on this CPU.
528 void force_external_irq_replay(void)
531 * This must only be called with interrupts soft-disabled,
532 * the replay will happen when re-enabling.
534 WARN_ON(!arch_irqs_disabled());
537 * Interrupts must always be hard disabled before irq_happened is
538 * modified (to prevent lost update in case of interrupt between
541 __hard_irq_disable();
542 local_paca->irq_happened |= PACA_IRQ_HARD_DIS;
544 /* Indicate in the PACA that we have an interrupt to replay */
545 local_paca->irq_happened |= PACA_IRQ_EE;
548 #endif /* CONFIG_PPC64 */
550 int arch_show_interrupts(struct seq_file *p, int prec)
554 #if defined(CONFIG_PPC32) && defined(CONFIG_TAU_INT)
555 if (tau_initialized) {
556 seq_printf(p, "%*s: ", prec, "TAU");
557 for_each_online_cpu(j)
558 seq_printf(p, "%10u ", tau_interrupts(j));
559 seq_puts(p, " PowerPC Thermal Assist (cpu temp)\n");
561 #endif /* CONFIG_PPC32 && CONFIG_TAU_INT */
563 seq_printf(p, "%*s: ", prec, "LOC");
564 for_each_online_cpu(j)
565 seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_event);
566 seq_printf(p, " Local timer interrupts for timer event device\n");
568 seq_printf(p, "%*s: ", prec, "BCT");
569 for_each_online_cpu(j)
570 seq_printf(p, "%10u ", per_cpu(irq_stat, j).broadcast_irqs_event);
571 seq_printf(p, " Broadcast timer interrupts for timer event device\n");
573 seq_printf(p, "%*s: ", prec, "LOC");
574 for_each_online_cpu(j)
575 seq_printf(p, "%10u ", per_cpu(irq_stat, j).timer_irqs_others);
576 seq_printf(p, " Local timer interrupts for others\n");
578 seq_printf(p, "%*s: ", prec, "SPU");
579 for_each_online_cpu(j)
580 seq_printf(p, "%10u ", per_cpu(irq_stat, j).spurious_irqs);
581 seq_printf(p, " Spurious interrupts\n");
583 seq_printf(p, "%*s: ", prec, "PMI");
584 for_each_online_cpu(j)
585 seq_printf(p, "%10u ", per_cpu(irq_stat, j).pmu_irqs);
586 seq_printf(p, " Performance monitoring interrupts\n");
588 seq_printf(p, "%*s: ", prec, "MCE");
589 for_each_online_cpu(j)
590 seq_printf(p, "%10u ", per_cpu(irq_stat, j).mce_exceptions);
591 seq_printf(p, " Machine check exceptions\n");
593 #ifdef CONFIG_PPC_BOOK3S_64
594 if (cpu_has_feature(CPU_FTR_HVMODE)) {
595 seq_printf(p, "%*s: ", prec, "HMI");
596 for_each_online_cpu(j)
597 seq_printf(p, "%10u ", paca_ptrs[j]->hmi_irqs);
598 seq_printf(p, " Hypervisor Maintenance Interrupts\n");
602 seq_printf(p, "%*s: ", prec, "NMI");
603 for_each_online_cpu(j)
604 seq_printf(p, "%10u ", per_cpu(irq_stat, j).sreset_irqs);
605 seq_printf(p, " System Reset interrupts\n");
607 #ifdef CONFIG_PPC_WATCHDOG
608 seq_printf(p, "%*s: ", prec, "WDG");
609 for_each_online_cpu(j)
610 seq_printf(p, "%10u ", per_cpu(irq_stat, j).soft_nmi_irqs);
611 seq_printf(p, " Watchdog soft-NMI interrupts\n");
614 #ifdef CONFIG_PPC_DOORBELL
615 if (cpu_has_feature(CPU_FTR_DBELL)) {
616 seq_printf(p, "%*s: ", prec, "DBL");
617 for_each_online_cpu(j)
618 seq_printf(p, "%10u ", per_cpu(irq_stat, j).doorbell_irqs);
619 seq_printf(p, " Doorbell interrupts\n");
629 u64 arch_irq_stat_cpu(unsigned int cpu)
631 u64 sum = per_cpu(irq_stat, cpu).timer_irqs_event;
633 sum += per_cpu(irq_stat, cpu).broadcast_irqs_event;
634 sum += per_cpu(irq_stat, cpu).pmu_irqs;
635 sum += per_cpu(irq_stat, cpu).mce_exceptions;
636 sum += per_cpu(irq_stat, cpu).spurious_irqs;
637 sum += per_cpu(irq_stat, cpu).timer_irqs_others;
638 #ifdef CONFIG_PPC_BOOK3S_64
639 sum += paca_ptrs[cpu]->hmi_irqs;
641 sum += per_cpu(irq_stat, cpu).sreset_irqs;
642 #ifdef CONFIG_PPC_WATCHDOG
643 sum += per_cpu(irq_stat, cpu).soft_nmi_irqs;
645 #ifdef CONFIG_PPC_DOORBELL
646 sum += per_cpu(irq_stat, cpu).doorbell_irqs;
652 static inline void check_stack_overflow(void)
656 if (!IS_ENABLED(CONFIG_DEBUG_STACKOVERFLOW))
659 sp = current_stack_pointer & (THREAD_SIZE - 1);
661 /* check for stack overflow: is there less than 2KB free? */
662 if (unlikely(sp < 2048)) {
663 pr_err("do_IRQ: stack overflow: %ld\n", sp);
668 void __do_irq(struct pt_regs *regs)
674 trace_irq_entry(regs);
677 * Query the platform PIC for the interrupt & ack it.
679 * This will typically lower the interrupt line to the CPU
681 irq = ppc_md.get_irq();
683 /* We can hard enable interrupts now to allow perf interrupts */
684 may_hard_irq_enable();
686 /* And finally process it */
688 __this_cpu_inc(irq_stat.spurious_irqs);
690 generic_handle_irq(irq);
692 trace_irq_exit(regs);
697 void do_IRQ(struct pt_regs *regs)
699 struct pt_regs *old_regs = set_irq_regs(regs);
700 void *cursp, *irqsp, *sirqsp;
702 /* Switch to the irq stack to handle this */
703 cursp = (void *)(current_stack_pointer & ~(THREAD_SIZE - 1));
704 irqsp = hardirq_ctx[raw_smp_processor_id()];
705 sirqsp = softirq_ctx[raw_smp_processor_id()];
707 check_stack_overflow();
709 /* Already there ? */
710 if (unlikely(cursp == irqsp || cursp == sirqsp)) {
712 set_irq_regs(old_regs);
715 /* Switch stack and call */
716 call_do_irq(regs, irqsp);
718 set_irq_regs(old_regs);
721 static void *__init alloc_vm_stack(void)
723 return __vmalloc_node(THREAD_SIZE, THREAD_ALIGN, THREADINFO_GFP,
724 NUMA_NO_NODE, (void *)_RET_IP_);
727 static void __init vmap_irqstack_init(void)
731 for_each_possible_cpu(i) {
732 softirq_ctx[i] = alloc_vm_stack();
733 hardirq_ctx[i] = alloc_vm_stack();
738 void __init init_IRQ(void)
740 if (IS_ENABLED(CONFIG_VMAP_STACK))
741 vmap_irqstack_init();
747 #if defined(CONFIG_BOOKE) || defined(CONFIG_40x)
748 void *critirq_ctx[NR_CPUS] __read_mostly;
749 void *dbgirq_ctx[NR_CPUS] __read_mostly;
750 void *mcheckirq_ctx[NR_CPUS] __read_mostly;
753 void *softirq_ctx[NR_CPUS] __read_mostly;
754 void *hardirq_ctx[NR_CPUS] __read_mostly;
756 void do_softirq_own_stack(void)
758 call_do_softirq(softirq_ctx[smp_processor_id()]);
761 irq_hw_number_t virq_to_hw(unsigned int virq)
763 struct irq_data *irq_data = irq_get_irq_data(virq);
764 return WARN_ON(!irq_data) ? 0 : irq_data->hwirq;
766 EXPORT_SYMBOL_GPL(virq_to_hw);
769 int irq_choose_cpu(const struct cpumask *mask)
773 if (cpumask_equal(mask, cpu_online_mask)) {
774 static int irq_rover;
775 static DEFINE_RAW_SPINLOCK(irq_rover_lock);
778 /* Round-robin distribution... */
780 raw_spin_lock_irqsave(&irq_rover_lock, flags);
782 irq_rover = cpumask_next(irq_rover, cpu_online_mask);
783 if (irq_rover >= nr_cpu_ids)
784 irq_rover = cpumask_first(cpu_online_mask);
788 raw_spin_unlock_irqrestore(&irq_rover_lock, flags);
790 cpuid = cpumask_first_and(mask, cpu_online_mask);
791 if (cpuid >= nr_cpu_ids)
795 return get_hard_smp_processor_id(cpuid);
798 int irq_choose_cpu(const struct cpumask *mask)
800 return hard_smp_processor_id();
805 static int __init setup_noirqdistrib(char *str)
811 __setup("noirqdistrib", setup_noirqdistrib);
812 #endif /* CONFIG_PPC64 */