2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/processor.h>
14 #include <asm/cputable.h>
15 #include <asm/thread_info.h>
16 #include <asm/ppc_asm.h>
17 #include <asm/asm-offsets.h>
18 #include <asm/ppc-opcode.h>
19 #include <asm/hw_irq.h>
20 #include <asm/kvm_book3s_asm.h>
22 #include <asm/cpuidle.h>
23 #include <asm/exception-64s.h>
24 #include <asm/book3s/64/mmu-hash.h>
30 * Use unused space in the interrupt stack to save and restore
31 * registers for winkle support.
46 #define PSSCR_EC_ESL_MASK_SHIFTED (PSSCR_EC | PSSCR_ESL) >> 16
51 * Used by threads before entering deep idle states. Saves SPRs
52 * in interrupt stack frame
56 * Note all register i.e per-core, per-subcore or per-thread is saved
57 * here since any thread in the core might wake up first
61 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
71 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
89 * On POWER9, there are idle states such as stop4, invoked via cpuidle,
90 * that lose hypervisor resources. In such cases, we need to save
91 * additional SPRs before entering those idle states so that they can
92 * be restored to their older values on wakeup from the idle state.
94 * On POWER8, the only such deep idle state is winkle which is used
95 * only in the context of CPU-Hotplug, where these additional SPRs are
96 * reinitiazed to a sane value. Hence there is no need to save/restore
101 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
103 power9_save_additional_sprs:
106 std r3, STOP_PID(r13)
107 std r4, STOP_LDBAR(r13)
111 std r3, STOP_FSCR(r13)
112 std r4, STOP_HFSCR(r13)
116 std r3, STOP_MMCRA(r13)
117 std r4, STOP_MMCR1(r13)
120 std r3, STOP_MMCR2(r13)
123 power9_restore_additional_sprs:
129 ld r3, STOP_LDBAR(r13)
130 ld r4, STOP_FSCR(r13)
134 ld r3, STOP_HFSCR(r13)
135 ld r4, STOP_MMCRA(r13)
138 /* We have already restored PACA_MMCR0 */
139 ld r3, STOP_MMCR1(r13)
140 ld r4, STOP_MMCR2(r13)
143 ld r4, PACA_SPRG_VDSO(r13)
148 * Used by threads when the lock bit of core_idle_state is set.
149 * Threads will spin in HMT_LOW until the lock bit is cleared.
150 * r14 - pointer to core_idle_state
151 * r15 - used to load contents of core_idle_state
152 * r9 - used as a temporary variable
158 andis. r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
162 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
163 bne- core_idle_lock_held
166 /* Reuse some unused pt_regs slots for AMR/IAMR/UAMOR/UAMOR */
167 #define PNV_POWERSAVE_AMR _TRAP
168 #define PNV_POWERSAVE_IAMR _DAR
169 #define PNV_POWERSAVE_UAMOR _DSISR
170 #define PNV_POWERSAVE_AMOR RESULT
173 * Pass requested state in r3:
174 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
175 * - Requested PSSCR value in POWER9
177 * Address of idle handler to branch to in realmode in r4
179 pnv_powersave_common:
180 /* Use r3 to pass state nap/sleep/winkle */
181 /* NAP is a state loss, we create a regs frame on the
182 * stack, fill it up with the state we care about and
183 * stick a pointer to it in PACAR1. We really only
184 * need to save PC, some CR bits and the NV GPRs,
185 * but for now an interrupt frame will do.
191 stdu r1,-INT_FRAME_SIZE(r1)
195 /* We haven't lost state ... yet */
197 stb r0,PACA_NAPSTATELOST(r13)
199 /* Continue saving state */
207 std r4, PNV_POWERSAVE_AMR(r1)
208 std r5, PNV_POWERSAVE_IAMR(r1)
209 std r6, PNV_POWERSAVE_UAMOR(r1)
210 BEGIN_FTR_SECTION_NESTED(42)
212 std r7, PNV_POWERSAVE_AMOR(r1)
213 END_FTR_SECTION_NESTED_IFSET(CPU_FTR_HVMODE, 42)
214 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
222 * POWER9 does not require real mode to stop, and presently does not
223 * set hwthread_state for KVM (threads don't share MMU context), so
224 * we can remain in virtual mode for this.
227 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
230 * Go to real mode to do the nap, as required by the architecture.
231 * Also, we need to be in real mode before setting hwthread_state,
232 * because as soon as we do that, another thread can switch
233 * the MMU context to the guest.
235 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
240 * This is the sequence required to execute idle instructions, as
241 * specified in ISA v2.07 (and earlier). MSR[IR] and MSR[DR] must be 0.
243 #define IDLE_STATE_ENTER_SEQ_NORET(IDLE_INST) \
244 /* Magic NAP/SLEEP/WINKLE mode enter sequence */ \
248 236: cmpd cr0,r0,r0; \
253 .globl pnv_enter_arch207_idle_mode
254 pnv_enter_arch207_idle_mode:
255 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
256 /* Tell KVM we're entering idle */
257 li r4,KVM_HWTHREAD_IN_IDLE
258 /******************************************************/
259 /* N O T E W E L L ! ! ! N O T E W E L L */
260 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
261 /* MUST occur in real mode, i.e. with the MMU off, */
262 /* and the MMU must stay off until we clear this flag */
263 /* and test HSTATE_HWTHREAD_REQ(r13) in */
264 /* pnv_powersave_wakeup in this file. */
265 /* The reason is that another thread can switch the */
266 /* MMU to a guest context whenever this flag is set */
267 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
268 /* that would potentially cause this thread to start */
269 /* executing instructions from guest memory in */
270 /* hypervisor mode, leading to a host crash or data */
271 /* corruption, or worse. */
272 /******************************************************/
273 stb r4,HSTATE_HWTHREAD_STATE(r13)
275 stb r3,PACA_THREAD_IDLE_STATE(r13)
276 cmpwi cr3,r3,PNV_THREAD_SLEEP
278 IDLE_STATE_ENTER_SEQ_NORET(PPC_NAP)
281 /* Sleep or winkle */
282 lbz r7,PACA_THREAD_MASK(r13)
283 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
286 lis r5,PNV_CORE_IDLE_WINKLE_COUNT@h
291 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
292 bnel- core_idle_lock_held
294 add r15,r15,r5 /* Add if winkle */
295 andc r15,r15,r7 /* Clear thread bit */
297 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
300 * If cr0 = 0, then current thread is the last thread of the core entering
301 * sleep. Last thread needs to execute the hardware bug workaround code if
302 * required by the platform.
303 * Make the workaround call unconditionally here. The below branch call is
304 * patched out when the idle states are discovered if the platform does not
307 .global pnv_fastsleep_workaround_at_entry
308 pnv_fastsleep_workaround_at_entry:
309 beq fastsleep_workaround_at_entry
315 common_enter: /* common code for all the threads entering sleep or winkle */
317 IDLE_STATE_ENTER_SEQ_NORET(PPC_SLEEP)
319 fastsleep_workaround_at_entry:
320 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
325 /* Fast sleep workaround */
328 bl opal_config_cpu_idle_state
331 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
337 bl save_sprs_to_stack
339 IDLE_STATE_ENTER_SEQ_NORET(PPC_WINKLE)
342 * r3 - PSSCR value corresponding to the requested stop state.
344 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
345 power_enter_stop_kvm_rm:
347 * This is currently unused because POWER9 KVM does not have to
348 * gather secondary threads into sibling mode, but the code is
349 * here in case that function is required.
351 * Tell KVM we're entering idle.
353 li r4,KVM_HWTHREAD_IN_IDLE
354 /* DO THIS IN REAL MODE! See comment above. */
355 stb r4,HSTATE_HWTHREAD_STATE(r13)
359 * Check if we are executing the lite variant with ESL=EC=0
361 andis. r4,r3,PSSCR_EC_ESL_MASK_SHIFTED
362 clrldi r3,r3,60 /* r3 = Bits[60:63] = Requested Level (RL) */
363 bne .Lhandle_esl_ec_set
365 li r3,0 /* Since we didn't lose state, return 0 */
368 * pnv_wakeup_noloss() expects r12 to contain the SRR1 value so
369 * it can determine if the wakeup reason is an HMI in
370 * CHECK_HMI_INTERRUPT.
372 * However, when we wakeup with ESL=0, SRR1 will not contain the wakeup
373 * reason, so there is no point setting r12 to SRR1.
375 * Further, we clear r12 here, so that we don't accidentally enter the
376 * HMI in pnv_wakeup_noloss() if the value of r12[42:45] == WAKE_HMI.
383 * POWER9 DD2 can incorrectly set PMAO when waking up after a
384 * state-loss idle. Saving and restoring MMCR0 over idle is a
391 * Check if the requested state is a deep idle state.
393 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
394 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
396 bge .Lhandle_deep_stop
397 PPC_STOP /* Does not return (system reset interrupt) */
401 * Entering deep idle state.
402 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
403 * stack and enter stop
405 lbz r7,PACA_THREAD_MASK(r13)
406 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
410 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
411 bnel- core_idle_lock_held
412 andc r15,r15,r7 /* Clear thread bit */
418 bl save_sprs_to_stack
420 PPC_STOP /* Does not return (system reset interrupt) */
423 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
424 * r3 contains desired idle state (PNV_THREAD_NAP/SLEEP/WINKLE).
426 _GLOBAL(power7_idle_insn)
427 /* Now check if user or arch enabled NAP mode */
428 LOAD_REG_ADDR(r4, pnv_enter_arch207_idle_mode)
429 b pnv_powersave_common
431 #define CHECK_HMI_INTERRUPT \
432 BEGIN_FTR_SECTION_NESTED(66); \
433 rlwinm r0,r12,45-31,0xf; /* extract wake reason field (P8) */ \
434 FTR_SECTION_ELSE_NESTED(66); \
435 rlwinm r0,r12,45-31,0xe; /* P7 wake reason field is 3 bits */ \
436 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
437 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
439 /* Invoke opal call to handle hmi */ \
440 ld r2,PACATOC(r13); \
442 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
443 li r3,0; /* NULL argument */ \
444 bl hmi_exception_realmode; \
446 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
450 * Entered with MSR[EE]=0 and no soft-masked interrupts pending.
451 * r3 contains desired PSSCR register value.
453 _GLOBAL(power9_idle_stop)
454 std r3, PACA_REQ_PSSCR(r13)
456 LOAD_REG_ADDR(r4,power_enter_stop)
457 b pnv_powersave_common
461 * On waking up from stop 0,1,2 with ESL=1 on POWER9 DD1,
462 * HSPRG0 will be set to the HSPRG0 value of one of the
463 * threads in this core. Thus the value we have in r13
464 * may not be this thread's paca pointer.
466 * Fortunately, the TIR remains invariant. Since this thread's
467 * paca pointer is recorded in all its sibling's paca, we can
468 * correctly recover this thread's paca pointer if we
469 * know the index of this thread in the core.
471 * This index can be obtained from the TIR.
473 * i.e, thread's position in the core = TIR.
474 * If this value is i, then this thread's paca is
475 * paca->thread_sibling_pacas[i].
477 power9_dd1_recover_paca:
480 * Since each entry in thread_sibling_pacas is 8 bytes
481 * we need to left-shift by 3 bits. Thus r4 = i * 8
484 /* Get &paca->thread_sibling_pacas[0] in r5 */
485 ld r5, PACA_SIBLING_PACA_PTRS(r13)
486 /* Load paca->thread_sibling_pacas[i] into r13 */
490 * Indicate that we have lost NVGPR state
491 * which needs to be restored from the stack.
494 stb r3,PACA_NAPSTATELOST(r13)
498 * Called from machine check handler for powersave wakeups.
499 * Low level machine check processing has already been done. Now just
500 * go through the wake up path to get everything in order.
502 * r3 - The original SRR1 value.
503 * Original SRR[01] have been clobbered.
506 .global pnv_powersave_wakeup_mce
507 pnv_powersave_wakeup_mce:
508 /* Set cr3 for pnv_powersave_wakeup */
509 rlwinm r11,r3,47-31,30,31
513 * Now put the original SRR1 with SRR1_WAKEMCE_RESVD as the wake
514 * reason into r12, which allows reuse of the system reset wakeup
515 * code without being mistaken for another type of wakeup.
517 oris r12,r3,SRR1_WAKEMCE_RESVD@h
519 b pnv_powersave_wakeup
521 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
522 kvm_start_guest_check:
523 li r0,KVM_HWTHREAD_IN_KERNEL
524 stb r0,HSTATE_HWTHREAD_STATE(r13)
525 /* Order setting hwthread_state vs. testing hwthread_req */
527 lbz r0,HSTATE_HWTHREAD_REQ(r13)
534 * Called from reset vector for powersave wakeups.
535 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
538 .global pnv_powersave_wakeup
539 pnv_powersave_wakeup:
543 BEGIN_FTR_SECTION_NESTED(70)
544 bl power9_dd1_recover_paca
545 END_FTR_SECTION_NESTED_IFSET(CPU_FTR_POWER9_DD1, 70)
546 bl pnv_restore_hyp_resource_arch300
548 bl pnv_restore_hyp_resource_arch207
549 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
551 li r0,PNV_THREAD_RUNNING
552 stb r0,PACA_THREAD_IDLE_STATE(r13) /* Clear thread state */
556 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
558 bl kvm_start_guest_check
559 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
562 /* Return SRR1 from power7_nap() */
563 blt cr3,pnv_wakeup_noloss
567 * Check whether we have woken up with hypervisor state loss.
568 * If yes, restore hypervisor state and return back to link.
570 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
572 pnv_restore_hyp_resource_arch300:
574 * Workaround for POWER9, if we lost resources, the ERAT
575 * might have been mixed up and needs flushing. We also need
576 * to reload MMCR0 (see comment above). We also need to set
577 * then clear bit 60 in MMCRA to ensure the PMU starts running.
583 ori r4,r4,(1 << (63-60))
585 xori r4,r4,(1 << (63-60))
591 * POWER ISA 3. Use PSSCR to determine if we
592 * are waking up from deep idle state
594 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
595 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
597 BEGIN_FTR_SECTION_NESTED(71)
599 * Assume that we are waking up from the state
600 * same as the Requested Level (RL) in the PSSCR
601 * which are Bits 60-63
603 ld r5,PACA_REQ_PSSCR(r13)
605 FTR_SECTION_ELSE_NESTED(71)
607 * 0-3 bits correspond to Power-Saving Level Status
608 * which indicates the idle state we are waking up from
612 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_POWER9_DD1, 71)
614 bge cr4,pnv_wakeup_tb_loss /* returns to caller */
616 blr /* Waking up without hypervisor state loss. */
618 /* Same calling convention as arch300 */
619 pnv_restore_hyp_resource_arch207:
621 * POWER ISA 2.07 or less.
622 * Check if we slept with sleep or winkle.
624 lbz r4,PACA_THREAD_IDLE_STATE(r13)
625 cmpwi cr2,r4,PNV_THREAD_NAP
626 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
629 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
630 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
631 * indicates we are waking with hypervisor state loss from nap.
635 blr /* Waking up without hypervisor state loss */
638 * Called if waking up from idle state which can cause either partial or
639 * complete hyp state loss.
640 * In POWER8, called if waking up from fastsleep or winkle
641 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
644 * cr3 - gt if waking up with partial/complete hypervisor state loss
647 * cr4 - gt or eq if waking up from complete hypervisor state loss.
650 * r4 - PACA_THREAD_IDLE_STATE
655 * Before entering any idle state, the NVGPRs are saved in the stack.
656 * If there was a state loss, or PACA_NAPSTATELOST was set, then the
657 * NVGPRs are restored. If we are here, it is likely that state is lost,
658 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach
659 * here are the same as the test to restore NVGPRS:
660 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
661 * and SRR1 test for restoring NVGPRs.
663 * We are about to clobber NVGPRs now, so set NAPSTATELOST to
664 * guarantee they will always be restored. This might be tightened
665 * with careful reading of specs (particularly for ISA300) but this
666 * is already a slow wakeup path and it's simpler to be safe.
669 stb r0,PACA_NAPSTATELOST(r13)
673 * Save SRR1 and LR in NVGPRs as they might be clobbered in
674 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
675 * to determine the wakeup reason if we branch to kvm_start_guest. LR
676 * is required to return back to reset vector after hypervisor state
677 * restore is complete.
684 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
686 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
687 lbz r7,PACA_THREAD_MASK(r13)
690 * Take the core lock to synchronize against other threads.
692 * Lock bit is set in one of the 2 cases-
693 * a. In the sleep/winkle enter path, the last thread is executing
694 * fastsleep workaround code.
695 * b. In the wake up path, another thread is executing fastsleep
696 * workaround undo code or resyncing timebase or restoring context
697 * In either case loop until the lock bit is cleared.
701 andis. r9,r15,PNV_CORE_IDLE_LOCK_BIT@h
702 bnel- core_idle_lock_held
703 oris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
708 andi. r9,r15,PNV_CORE_IDLE_THREAD_BITS
713 * cr2 - eq if first thread to wakeup in core
714 * cr3- gt if waking up with partial/complete hypervisor state loss
716 * cr4 - gt or eq if waking up from complete hypervisor state loss.
722 * If yes, check if all threads were in winkle, decrement our
723 * winkle count, set all thread winkle bits if all were in winkle.
724 * Check if our thread has a winkle bit set, and set cr4 accordingly
725 * (to match ISA300, above). Pseudo-code for core idle state
726 * transitions for ISA207 is as follows (everything happens atomically
727 * due to store conditional and/or lock bit):
734 * core_idle_state &= ~thread_in_core
739 * bool first_in_core, first_in_subcore;
741 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
742 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
744 * core_idle_state |= thread_in_core;
749 * core_idle_state &= ~thread_in_core;
750 * core_idle_state += 1 << WINKLE_COUNT_SHIFT;
755 * bool first_in_core, first_in_subcore, winkle_state_lost;
757 * first_in_core = (core_idle_state & IDLE_THREAD_BITS) == 0;
758 * first_in_subcore = (core_idle_state & SUBCORE_SIBLING_MASK) == 0;
760 * core_idle_state |= thread_in_core;
762 * if ((core_idle_state & WINKLE_MASK) == (8 << WINKLE_COUNT_SIHFT))
763 * core_idle_state |= THREAD_WINKLE_BITS;
764 * core_idle_state -= 1 << WINKLE_COUNT_SHIFT;
766 * winkle_state_lost = core_idle_state &
767 * (thread_in_core << WINKLE_THREAD_SHIFT);
768 * core_idle_state &= ~(thread_in_core << WINKLE_THREAD_SHIFT);
772 cmpwi r18,PNV_THREAD_WINKLE
774 andis. r9,r15,PNV_CORE_IDLE_WINKLE_COUNT_ALL_BIT@h
775 subis r15,r15,PNV_CORE_IDLE_WINKLE_COUNT@h
777 ori r15,r15,PNV_CORE_IDLE_THREAD_WINKLE_BITS /* all were winkle */
779 /* Shift thread bit to winkle mask, then test if this thread is set,
780 * and remove it from the winkle bits */
784 cmpwi cr4,r8,1 /* cr4 will be gt if our bit is set, lt if not */
786 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
788 cmpwi r4,0 /* Check if first in subcore */
790 or r15,r15,r7 /* Set thread bit */
791 beq first_thread_in_subcore
792 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
794 or r15,r15,r7 /* Set thread bit */
795 beq cr2,first_thread_in_core
797 /* Not first thread in core or subcore to wake up */
800 first_thread_in_subcore:
802 * If waking up from sleep, subcore state is not lost. Hence
803 * skip subcore state restore
805 blt cr4,subcore_state_restored
807 /* Restore per-subcore state */
816 subcore_state_restored:
818 * Check if the thread is also the first thread in the core. If not,
819 * skip to clear_lock.
823 first_thread_in_core:
826 * First thread in the core waking up from any state which can cause
827 * partial or complete hypervisor state loss. It needs to
828 * call the fastsleep workaround code if the platform requires it.
829 * Call it unconditionally here. The below branch instruction will
830 * be patched out if the platform does not have fastsleep or does not
831 * require the workaround. Patching will be performed during the
832 * discovery of idle-states.
834 .global pnv_fastsleep_workaround_at_exit
835 pnv_fastsleep_workaround_at_exit:
836 b fastsleep_workaround_at_exit
840 * Use cr3 which indicates that we are waking up with atleast partial
841 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
843 ble cr3,.Ltb_resynced
844 /* Time base re-sync */
845 bl opal_resync_timebase;
847 * If waking up from sleep (POWER8), per core state
848 * is not lost, skip to clear_lock.
854 * First thread in the core to wake up and its waking up with
855 * complete hypervisor state loss. Restore per core hypervisor
865 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
873 xoris r15,r15,PNV_CORE_IDLE_LOCK_BIT@h
879 * Common to all threads.
881 * If waking up from sleep, hypervisor state is not lost. Hence
882 * skip hypervisor state restore.
884 blt cr4,hypervisor_state_restored
886 /* Waking up from winkle */
888 BEGIN_MMU_FTR_SECTION
890 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
891 /* Restore SLB from PACA */
892 ld r8,PACA_SLBSHADOWPTR(r13)
895 li r3, SLBSHADOW_SAVEAREA
899 andis. r7,r5,SLB_ESID_V@h
906 /* Restore per thread state */
917 /* Call cur_cpu_spec->cpu_restore() */
918 LOAD_REG_ADDR(r4, cur_cpu_spec)
920 ld r12,CPU_SPEC_RESTORE(r4)
921 #ifdef PPC64_ELF_ABI_v1
928 * On POWER9, we can come here on wakeup from a cpuidle stop state.
929 * Hence restore the additional SPRs to the saved value.
931 * On POWER8, we come here only on winkle. Since winkle is used
932 * only in the case of CPU-Hotplug, we don't need to restore
933 * the additional SPRs.
936 bl power9_restore_additional_sprs
937 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
938 hypervisor_state_restored:
942 blr /* return to pnv_powersave_wakeup */
944 fastsleep_workaround_at_exit:
947 bl opal_config_cpu_idle_state
951 * R3 here contains the value that will be returned to the caller
953 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
955 .global pnv_wakeup_loss
960 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
965 /* These regs were saved in pnv_powersave_common() */
966 ld r4, PNV_POWERSAVE_AMR(r1)
967 ld r5, PNV_POWERSAVE_IAMR(r1)
968 ld r6, PNV_POWERSAVE_UAMOR(r1)
972 BEGIN_FTR_SECTION_NESTED(42)
973 ld r7, PNV_POWERSAVE_AMOR(r1)
975 END_FTR_SECTION_NESTED_IFSET(CPU_FTR_HVMODE, 42)
977 * We don't need an isync here after restoring IAMR because the upcoming
978 * mtmsrd is execution synchronizing.
980 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
985 addi r1,r1,INT_FRAME_SIZE
992 * R3 here contains the value that will be returned to the caller
994 * R12 contains SRR1 for CHECK_HMI_INTERRUPT.
997 lbz r0,PACA_NAPSTATELOST(r13)
1003 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
1007 addi r1,r1,INT_FRAME_SIZE