2 * This file contains idle entry/exit functions for POWER7,
3 * POWER8 and POWER9 CPUs.
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version
8 * 2 of the License, or (at your option) any later version.
11 #include <linux/threads.h>
12 #include <asm/exception-64s.h>
13 #include <asm/processor.h>
15 #include <asm/cputable.h>
16 #include <asm/thread_info.h>
17 #include <asm/ppc_asm.h>
18 #include <asm/asm-offsets.h>
19 #include <asm/ppc-opcode.h>
20 #include <asm/hw_irq.h>
21 #include <asm/kvm_book3s_asm.h>
23 #include <asm/cpuidle.h>
24 #include <asm/book3s/64/mmu-hash.h>
30 * Use unused space in the interrupt stack to save and restore
31 * registers for winkle support.
44 #define PSSCR_HV_TEMPLATE PSSCR_ESL | PSSCR_EC | \
45 PSSCR_PSLL_MASK | PSSCR_TR_MASK | \
51 * Used by threads before entering deep idle states. Saves SPRs
52 * in interrupt stack frame
56 * Note all register i.e per-core, per-subcore or per-thread is saved
57 * here since any thread in the core might wake up first
63 * Note - SDR1 is dropped in Power ISA v3. Hence not restoring
69 ALT_FTR_SECTION_END_IFSET(CPU_FTR_ARCH_300)
90 * Used by threads when the lock bit of core_idle_state is set.
91 * Threads will spin in HMT_LOW until the lock bit is cleared.
92 * r14 - pointer to core_idle_state
93 * r15 - used to load contents of core_idle_state
94 * r9 - used as a temporary variable
100 andi. r15,r15,PNV_CORE_IDLE_LOCK_BIT
104 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
105 bne core_idle_lock_held
109 * Pass requested state in r3:
110 * r3 - PNV_THREAD_NAP/SLEEP/WINKLE in POWER8
111 * - Requested STOP state in POWER9
113 * To check IRQ_HAPPENED in r4
117 * Address to 'rfid' to in r5
119 _GLOBAL(pnv_powersave_common)
120 /* Use r3 to pass state nap/sleep/winkle */
121 /* NAP is a state loss, we create a regs frame on the
122 * stack, fill it up with the state we care about and
123 * stick a pointer to it in PACAR1. We really only
124 * need to save PC, some CR bits and the NV GPRs,
125 * but for now an interrupt frame will do.
129 stdu r1,-INT_FRAME_SIZE(r1)
133 /* Hard disable interrupts */
137 mtmsrd r9,1 /* hard-disable interrupts */
139 /* Check if something happened while soft-disabled */
140 lbz r0,PACAIRQHAPPENED(r13)
141 andi. r0,r0,~PACA_IRQ_HARD_DIS@l
145 addi r1,r1,INT_FRAME_SIZE
147 li r3,0 /* Return 0 (no nap) */
151 1: /* We mark irqs hard disabled as this is the state we'll
152 * be in when returning and we need to tell arch_local_irq_restore()
155 li r0,PACA_IRQ_HARD_DIS
156 stb r0,PACAIRQHAPPENED(r13)
158 /* We haven't lost state ... yet */
160 stb r0,PACA_NAPSTATELOST(r13)
162 /* Continue saving state */
171 * Go to real mode to do the nap, as required by the architecture.
172 * Also, we need to be in real mode before setting hwthread_state,
173 * because as soon as we do that, another thread can switch
174 * the MMU context to the guest.
176 LOAD_REG_IMMEDIATE(r7, MSR_IDLE)
179 mtmsrd r6, 1 /* clear RI before setting SRR0/1 */
184 .globl pnv_enter_arch207_idle_mode
185 pnv_enter_arch207_idle_mode:
186 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
187 /* Tell KVM we're entering idle */
188 li r4,KVM_HWTHREAD_IN_IDLE
189 /******************************************************/
190 /* N O T E W E L L ! ! ! N O T E W E L L */
191 /* The following store to HSTATE_HWTHREAD_STATE(r13) */
192 /* MUST occur in real mode, i.e. with the MMU off, */
193 /* and the MMU must stay off until we clear this flag */
194 /* and test HSTATE_HWTHREAD_REQ(r13) in the system */
195 /* reset interrupt vector in exceptions-64s.S. */
196 /* The reason is that another thread can switch the */
197 /* MMU to a guest context whenever this flag is set */
198 /* to KVM_HWTHREAD_IN_IDLE, and if the MMU was on, */
199 /* that would potentially cause this thread to start */
200 /* executing instructions from guest memory in */
201 /* hypervisor mode, leading to a host crash or data */
202 /* corruption, or worse. */
203 /******************************************************/
204 stb r4,HSTATE_HWTHREAD_STATE(r13)
206 stb r3,PACA_THREAD_IDLE_STATE(r13)
207 cmpwi cr3,r3,PNV_THREAD_SLEEP
209 IDLE_STATE_ENTER_SEQ(PPC_NAP)
212 /* Sleep or winkle */
213 lbz r7,PACA_THREAD_MASK(r13)
214 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
218 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
219 bnel core_idle_lock_held
221 andc r15,r15,r7 /* Clear thread bit */
223 andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
226 * If cr0 = 0, then current thread is the last thread of the core entering
227 * sleep. Last thread needs to execute the hardware bug workaround code if
228 * required by the platform.
229 * Make the workaround call unconditionally here. The below branch call is
230 * patched out when the idle states are discovered if the platform does not
233 .global pnv_fastsleep_workaround_at_entry
234 pnv_fastsleep_workaround_at_entry:
235 beq fastsleep_workaround_at_entry
241 common_enter: /* common code for all the threads entering sleep or winkle */
243 IDLE_STATE_ENTER_SEQ(PPC_SLEEP)
245 fastsleep_workaround_at_entry:
246 ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
251 /* Fast sleep workaround */
254 bl opal_rm_config_cpu_idle_state
263 bl save_sprs_to_stack
265 IDLE_STATE_ENTER_SEQ(PPC_WINKLE)
268 * r3 - requested stop state
271 #ifdef CONFIG_KVM_BOOK3S_HV_POSSIBLE
272 /* Tell KVM we're entering idle */
273 li r4,KVM_HWTHREAD_IN_IDLE
274 /* DO THIS IN REAL MODE! See comment above. */
275 stb r4,HSTATE_HWTHREAD_STATE(r13)
278 * Check if the requested state is a deep idle state.
280 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
281 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
284 IDLE_STATE_ENTER_SEQ(PPC_STOP)
287 * Entering deep idle state.
288 * Clear thread bit in PACA_CORE_IDLE_STATE, save SPRs to
289 * stack and enter stop
291 lbz r7,PACA_THREAD_MASK(r13)
292 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
296 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
297 bnel core_idle_lock_held
298 andc r15,r15,r7 /* Clear thread bit */
304 bl save_sprs_to_stack
306 IDLE_STATE_ENTER_SEQ(PPC_STOP)
309 /* Now check if user or arch enabled NAP mode */
310 LOAD_REG_ADDRBASE(r3,powersave_nap)
311 lwz r4,ADDROFF(powersave_nap)(r3)
320 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
321 b pnv_powersave_common
324 _GLOBAL(power7_sleep)
325 li r3,PNV_THREAD_SLEEP
327 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
328 b pnv_powersave_common
331 _GLOBAL(power7_winkle)
332 li r3,PNV_THREAD_WINKLE
334 LOAD_REG_ADDR(r5, pnv_enter_arch207_idle_mode)
335 b pnv_powersave_common
338 #define CHECK_HMI_INTERRUPT \
339 mfspr r0,SPRN_SRR1; \
340 BEGIN_FTR_SECTION_NESTED(66); \
341 rlwinm r0,r0,45-31,0xf; /* extract wake reason field (P8) */ \
342 FTR_SECTION_ELSE_NESTED(66); \
343 rlwinm r0,r0,45-31,0xe; /* P7 wake reason field is 3 bits */ \
344 ALT_FTR_SECTION_END_NESTED_IFSET(CPU_FTR_ARCH_207S, 66); \
345 cmpwi r0,0xa; /* Hypervisor maintenance ? */ \
347 /* Invoke opal call to handle hmi */ \
348 ld r2,PACATOC(r13); \
350 std r3,ORIG_GPR3(r1); /* Save original r3 */ \
351 li r3,0; /* NULL argument */ \
352 bl hmi_exception_realmode; \
354 ld r3,ORIG_GPR3(r1); /* Restore original r3 */ \
359 * r3 - requested stop state
361 _GLOBAL(power9_idle_stop)
362 LOAD_REG_IMMEDIATE(r4, PSSCR_HV_TEMPLATE)
366 LOAD_REG_ADDR(r5,power_enter_stop)
367 b pnv_powersave_common
370 * Called from reset vector. Check whether we have woken up with
371 * hypervisor state loss. If yes, restore hypervisor state and return
372 * back to reset vector.
374 * r13 - Contents of HSPRG0
375 * cr3 - set to gt if waking up with partial/complete hypervisor state loss
377 _GLOBAL(pnv_restore_hyp_resource)
381 * POWER ISA 3. Use PSSCR to determine if we
382 * are waking up from deep idle state
384 LOAD_REG_ADDRBASE(r5,pnv_first_deep_stop_state)
385 ld r4,ADDROFF(pnv_first_deep_stop_state)(r5)
389 * 0-3 bits correspond to Power-Saving Level Status
390 * which indicates the idle state we are waking up from
394 bge cr4,pnv_wakeup_tb_loss
396 * Waking up without hypervisor state loss. Return to
401 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
404 * POWER ISA 2.07 or less.
405 * Check if last bit of HSPGR0 is set. This indicates whether we are
406 * waking up from winkle.
411 /* Now that we are sure r13 is corrected, load TOC */
414 mtspr SPRN_HSPRG0,r13
416 lbz r0,PACA_THREAD_IDLE_STATE(r13)
417 cmpwi cr2,r0,PNV_THREAD_NAP
418 bgt cr2,pnv_wakeup_tb_loss /* Either sleep or Winkle */
421 * We fall through here if PACA_THREAD_IDLE_STATE shows we are waking
422 * up from nap. At this stage CR3 shouldn't contains 'gt' since that
423 * indicates we are waking with hypervisor state loss from nap.
427 blr /* Return back to System Reset vector from where
428 pnv_restore_hyp_resource was invoked */
431 * Called if waking up from idle state which can cause either partial or
432 * complete hyp state loss.
433 * In POWER8, called if waking up from fastsleep or winkle
434 * In POWER9, called if waking up from stop state >= pnv_first_deep_stop_state
437 * cr3 - gt if waking up with partial/complete hypervisor state loss
438 * cr4 - gt or eq if waking up from complete hypervisor state loss.
440 _GLOBAL(pnv_wakeup_tb_loss)
443 * Before entering any idle state, the NVGPRs are saved in the stack.
444 * If there was a state loss, or PACA_NAPSTATELOST was set, then the
445 * NVGPRs are restored. If we are here, it is likely that state is lost,
446 * but not guaranteed -- neither ISA207 nor ISA300 tests to reach
447 * here are the same as the test to restore NVGPRS:
448 * PACA_THREAD_IDLE_STATE test for ISA207, PSSCR test for ISA300,
449 * and SRR1 test for restoring NVGPRs.
451 * We are about to clobber NVGPRs now, so set NAPSTATELOST to
452 * guarantee they will always be restored. This might be tightened
453 * with careful reading of specs (particularly for ISA300) but this
454 * is already a slow wakeup path and it's simpler to be safe.
457 stb r0,PACA_NAPSTATELOST(r13)
461 * Save SRR1 and LR in NVGPRs as they might be clobbered in
462 * opal_call() (called in CHECK_HMI_INTERRUPT). SRR1 is required
463 * to determine the wakeup reason if we branch to kvm_start_guest. LR
464 * is required to return back to reset vector after hypervisor state
465 * restore is complete.
471 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
473 lbz r7,PACA_THREAD_MASK(r13)
474 ld r14,PACA_CORE_IDLE_STATE_PTR(r13)
477 andi. r9,r15,PNV_CORE_IDLE_LOCK_BIT
479 * Lock bit is set in one of the 2 cases-
480 * a. In the sleep/winkle enter path, the last thread is executing
481 * fastsleep workaround code.
482 * b. In the wake up path, another thread is executing fastsleep
483 * workaround undo code or resyncing timebase or restoring context
484 * In either case loop until the lock bit is cleared.
486 bnel core_idle_lock_held
492 * cr2 - eq if first thread to wakeup in core
493 * cr3- gt if waking up with partial/complete hypervisor state loss
494 * cr4 - gt or eq if waking up from complete hypervisor state loss.
497 ori r15,r15,PNV_CORE_IDLE_LOCK_BIT
503 lbz r4,PACA_SUBCORE_SIBLING_MASK(r13)
505 cmpwi r4,0 /* Check if first in subcore */
507 or r15,r15,r7 /* Set thread bit */
508 beq first_thread_in_subcore
509 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_300)
511 or r15,r15,r7 /* Set thread bit */
512 beq cr2,first_thread_in_core
514 /* Not first thread in core or subcore to wake up */
517 first_thread_in_subcore:
519 * If waking up from sleep, subcore state is not lost. Hence
520 * skip subcore state restore
522 blt cr4,subcore_state_restored
524 /* Restore per-subcore state */
533 subcore_state_restored:
535 * Check if the thread is also the first thread in the core. If not,
536 * skip to clear_lock.
540 first_thread_in_core:
543 * First thread in the core waking up from any state which can cause
544 * partial or complete hypervisor state loss. It needs to
545 * call the fastsleep workaround code if the platform requires it.
546 * Call it unconditionally here. The below branch instruction will
547 * be patched out if the platform does not have fastsleep or does not
548 * require the workaround. Patching will be performed during the
549 * discovery of idle-states.
551 .global pnv_fastsleep_workaround_at_exit
552 pnv_fastsleep_workaround_at_exit:
553 b fastsleep_workaround_at_exit
557 * Use cr3 which indicates that we are waking up with atleast partial
558 * hypervisor state loss to determine if TIMEBASE RESYNC is needed.
561 /* Time base re-sync */
562 bl opal_rm_resync_timebase;
564 * If waking up from sleep, per core state is not lost, skip to
570 * First thread in the core to wake up and its waking up with
571 * complete hypervisor state loss. Restore per core hypervisor
579 END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
587 andi. r15,r15,PNV_CORE_IDLE_THREAD_BITS
593 * Common to all threads.
595 * If waking up from sleep, hypervisor state is not lost. Hence
596 * skip hypervisor state restore.
598 blt cr4,hypervisor_state_restored
600 /* Waking up from winkle */
602 BEGIN_MMU_FTR_SECTION
604 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
605 /* Restore SLB from PACA */
606 ld r8,PACA_SLBSHADOWPTR(r13)
609 li r3, SLBSHADOW_SAVEAREA
613 andis. r7,r5,SLB_ESID_V@h
620 /* Restore per thread state */
631 /* Call cur_cpu_spec->cpu_restore() */
632 LOAD_REG_ADDR(r4, cur_cpu_spec)
634 ld r12,CPU_SPEC_RESTORE(r4)
635 #ifdef PPC64_ELF_ABI_v1
641 hypervisor_state_restored:
645 blr /* Return back to System Reset vector from where
646 pnv_restore_hyp_resource was invoked */
648 fastsleep_workaround_at_exit:
651 bl opal_rm_config_cpu_idle_state
655 * R3 here contains the value that will be returned to the caller
658 _GLOBAL(pnv_wakeup_loss)
662 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
668 addi r1,r1,INT_FRAME_SIZE
675 * R3 here contains the value that will be returned to the caller
678 _GLOBAL(pnv_wakeup_noloss)
679 lbz r0,PACA_NAPSTATELOST(r13)
684 END_FTR_SECTION_IFSET(CPU_FTR_HVMODE)
689 addi r1,r1,INT_FRAME_SIZE