1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * HW_breakpoint: a unified kernel/user-space hardware breakpoint facility,
4 * using the CPU's debug registers. Derived from
5 * "arch/x86/kernel/hw_breakpoint.c"
7 * Copyright 2010 IBM Corporation
8 * Author: K.Prasad <prasad@linux.vnet.ibm.com>
11 #include <linux/hw_breakpoint.h>
12 #include <linux/notifier.h>
13 #include <linux/kprobes.h>
14 #include <linux/percpu.h>
15 #include <linux/kernel.h>
16 #include <linux/sched.h>
17 #include <linux/smp.h>
18 #include <linux/debugfs.h>
19 #include <linux/init.h>
21 #include <asm/hw_breakpoint.h>
22 #include <asm/processor.h>
23 #include <asm/sstep.h>
24 #include <asm/debug.h>
25 #include <asm/debugfs.h>
26 #include <asm/hvcall.h>
28 #include <linux/uaccess.h>
31 * Stores the breakpoints currently in use on each breakpoint address
32 * register for every cpu
34 static DEFINE_PER_CPU(struct perf_event *, bp_per_reg[HBP_NUM_MAX]);
37 * Returns total number of data or instruction breakpoints available.
39 int hw_breakpoint_slots(int type)
41 if (type == TYPE_DATA)
43 return 0; /* no instruction breakpoints available */
46 static bool single_step_pending(void)
50 for (i = 0; i < nr_wp_slots(); i++) {
51 if (current->thread.last_hit_ubp[i])
58 * Install a perf counter breakpoint.
60 * We seek a free debug address register and use it for this
63 * Atomic: we hold the counter->ctx->lock and we only handle variables
64 * and registers local to this cpu.
66 int arch_install_hw_breakpoint(struct perf_event *bp)
68 struct arch_hw_breakpoint *info = counter_arch_bp(bp);
69 struct perf_event **slot;
72 for (i = 0; i < nr_wp_slots(); i++) {
73 slot = this_cpu_ptr(&bp_per_reg[i]);
80 if (WARN_ONCE(i == nr_wp_slots(), "Can't find any breakpoint slot"))
84 * Do not install DABR values if the instruction must be single-stepped.
85 * If so, DABR will be populated in single_step_dabr_instruction().
87 if (!single_step_pending())
88 __set_breakpoint(i, info);
94 * Uninstall the breakpoint contained in the given counter.
96 * First we search the debug address register it uses and then we disable
99 * Atomic: we hold the counter->ctx->lock and we only handle variables
100 * and registers local to this cpu.
102 void arch_uninstall_hw_breakpoint(struct perf_event *bp)
104 struct arch_hw_breakpoint null_brk = {0};
105 struct perf_event **slot;
108 for (i = 0; i < nr_wp_slots(); i++) {
109 slot = this_cpu_ptr(&bp_per_reg[i]);
116 if (WARN_ONCE(i == nr_wp_slots(), "Can't find any breakpoint slot"))
119 __set_breakpoint(i, &null_brk);
122 static bool is_ptrace_bp(struct perf_event *bp)
124 return bp->overflow_handler == ptrace_triggered;
128 struct list_head list;
129 struct perf_event *bp;
133 static DEFINE_PER_CPU(struct breakpoint *, cpu_bps[HBP_NUM_MAX]);
134 static LIST_HEAD(task_bps);
136 static struct breakpoint *alloc_breakpoint(struct perf_event *bp)
138 struct breakpoint *tmp;
140 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
142 return ERR_PTR(-ENOMEM);
144 tmp->ptrace_bp = is_ptrace_bp(bp);
148 static bool bp_addr_range_overlap(struct perf_event *bp1, struct perf_event *bp2)
150 __u64 bp1_saddr, bp1_eaddr, bp2_saddr, bp2_eaddr;
152 bp1_saddr = ALIGN_DOWN(bp1->attr.bp_addr, HW_BREAKPOINT_SIZE);
153 bp1_eaddr = ALIGN(bp1->attr.bp_addr + bp1->attr.bp_len, HW_BREAKPOINT_SIZE);
154 bp2_saddr = ALIGN_DOWN(bp2->attr.bp_addr, HW_BREAKPOINT_SIZE);
155 bp2_eaddr = ALIGN(bp2->attr.bp_addr + bp2->attr.bp_len, HW_BREAKPOINT_SIZE);
157 return (bp1_saddr < bp2_eaddr && bp1_eaddr > bp2_saddr);
160 static bool alternate_infra_bp(struct breakpoint *b, struct perf_event *bp)
162 return is_ptrace_bp(bp) ? !b->ptrace_bp : b->ptrace_bp;
165 static bool can_co_exist(struct breakpoint *b, struct perf_event *bp)
167 return !(alternate_infra_bp(b, bp) && bp_addr_range_overlap(b->bp, bp));
170 static int task_bps_add(struct perf_event *bp)
172 struct breakpoint *tmp;
174 tmp = alloc_breakpoint(bp);
178 list_add(&tmp->list, &task_bps);
182 static void task_bps_remove(struct perf_event *bp)
184 struct list_head *pos, *q;
186 list_for_each_safe(pos, q, &task_bps) {
187 struct breakpoint *tmp = list_entry(pos, struct breakpoint, list);
190 list_del(&tmp->list);
198 * If any task has breakpoint from alternate infrastructure,
199 * return true. Otherwise return false.
201 static bool all_task_bps_check(struct perf_event *bp)
203 struct breakpoint *tmp;
205 list_for_each_entry(tmp, &task_bps, list) {
206 if (!can_co_exist(tmp, bp))
213 * If same task has breakpoint from alternate infrastructure,
214 * return true. Otherwise return false.
216 static bool same_task_bps_check(struct perf_event *bp)
218 struct breakpoint *tmp;
220 list_for_each_entry(tmp, &task_bps, list) {
221 if (tmp->bp->hw.target == bp->hw.target &&
222 !can_co_exist(tmp, bp))
228 static int cpu_bps_add(struct perf_event *bp)
230 struct breakpoint **cpu_bp;
231 struct breakpoint *tmp;
234 tmp = alloc_breakpoint(bp);
238 cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
239 for (i = 0; i < nr_wp_slots(); i++) {
248 static void cpu_bps_remove(struct perf_event *bp)
250 struct breakpoint **cpu_bp;
253 cpu_bp = per_cpu_ptr(cpu_bps, bp->cpu);
254 for (i = 0; i < nr_wp_slots(); i++) {
258 if (cpu_bp[i]->bp == bp) {
266 static bool cpu_bps_check(int cpu, struct perf_event *bp)
268 struct breakpoint **cpu_bp;
271 cpu_bp = per_cpu_ptr(cpu_bps, cpu);
272 for (i = 0; i < nr_wp_slots(); i++) {
273 if (cpu_bp[i] && !can_co_exist(cpu_bp[i], bp))
279 static bool all_cpu_bps_check(struct perf_event *bp)
283 for_each_online_cpu(cpu) {
284 if (cpu_bps_check(cpu, bp))
291 * We don't use any locks to serialize accesses to cpu_bps or task_bps
292 * because are already inside nr_bp_mutex.
294 int arch_reserve_bp_slot(struct perf_event *bp)
298 /* ptrace breakpoint */
299 if (is_ptrace_bp(bp)) {
300 if (all_cpu_bps_check(bp))
303 if (same_task_bps_check(bp))
306 return task_bps_add(bp);
309 /* perf breakpoint */
310 if (is_kernel_addr(bp->attr.bp_addr))
313 if (bp->hw.target && bp->cpu == -1) {
314 if (same_task_bps_check(bp))
317 return task_bps_add(bp);
318 } else if (!bp->hw.target && bp->cpu != -1) {
319 if (all_task_bps_check(bp))
322 return cpu_bps_add(bp);
325 if (same_task_bps_check(bp))
328 ret = cpu_bps_add(bp);
331 ret = task_bps_add(bp);
338 void arch_release_bp_slot(struct perf_event *bp)
340 if (!is_kernel_addr(bp->attr.bp_addr)) {
349 * Perform cleanup of arch-specific counters during unregistration
352 void arch_unregister_hw_breakpoint(struct perf_event *bp)
355 * If the breakpoint is unregistered between a hw_breakpoint_handler()
356 * and the single_step_dabr_instruction(), then cleanup the breakpoint
357 * restoration variables to prevent dangling pointers.
358 * FIXME, this should not be using bp->ctx at all! Sayeth peterz.
360 if (bp->ctx && bp->ctx->task && bp->ctx->task != ((void *)-1L)) {
363 for (i = 0; i < nr_wp_slots(); i++) {
364 if (bp->ctx->task->thread.last_hit_ubp[i] == bp)
365 bp->ctx->task->thread.last_hit_ubp[i] = NULL;
371 * Check for virtual address in kernel space.
373 int arch_check_bp_in_kernelspace(struct arch_hw_breakpoint *hw)
375 return is_kernel_addr(hw->address);
378 int arch_bp_generic_fields(int type, int *gen_bp_type)
381 if (type & HW_BRK_TYPE_READ)
382 *gen_bp_type |= HW_BREAKPOINT_R;
383 if (type & HW_BRK_TYPE_WRITE)
384 *gen_bp_type |= HW_BREAKPOINT_W;
385 if (*gen_bp_type == 0)
391 * Watchpoint match range is always doubleword(8 bytes) aligned on
392 * powerpc. If the given range is crossing doubleword boundary, we
393 * need to increase the length such that next doubleword also get
396 * address len = 6 bytes
398 * |------------v--|------v--------|
399 * | | | | | | | | | | | | | | | | |
400 * |---------------|---------------|
403 * In this case, we should configure hw as:
404 * start_addr = address & ~(HW_BREAKPOINT_SIZE - 1)
407 * @start_addr is inclusive but @end_addr is exclusive.
409 static int hw_breakpoint_validate_len(struct arch_hw_breakpoint *hw)
411 u16 max_len = DABR_MAX_LEN;
413 unsigned long start_addr, end_addr;
415 start_addr = ALIGN_DOWN(hw->address, HW_BREAKPOINT_SIZE);
416 end_addr = ALIGN(hw->address + hw->len, HW_BREAKPOINT_SIZE);
417 hw_len = end_addr - start_addr;
419 if (dawr_enabled()) {
420 max_len = DAWR_MAX_LEN;
421 /* DAWR region can't cross 512 bytes boundary on p10 predecessors */
422 if (!cpu_has_feature(CPU_FTR_ARCH_31) &&
423 (ALIGN_DOWN(start_addr, SZ_512) != ALIGN_DOWN(end_addr - 1, SZ_512)))
425 } else if (IS_ENABLED(CONFIG_PPC_8xx)) {
426 /* 8xx can setup a range without limitation */
430 if (hw_len > max_len)
438 * Validate the arch-specific HW Breakpoint register settings
440 int hw_breakpoint_arch_parse(struct perf_event *bp,
441 const struct perf_event_attr *attr,
442 struct arch_hw_breakpoint *hw)
446 if (!bp || !attr->bp_len)
449 hw->type = HW_BRK_TYPE_TRANSLATE;
450 if (attr->bp_type & HW_BREAKPOINT_R)
451 hw->type |= HW_BRK_TYPE_READ;
452 if (attr->bp_type & HW_BREAKPOINT_W)
453 hw->type |= HW_BRK_TYPE_WRITE;
454 if (hw->type == HW_BRK_TYPE_TRANSLATE)
455 /* must set alteast read or write */
457 if (!attr->exclude_user)
458 hw->type |= HW_BRK_TYPE_USER;
459 if (!attr->exclude_kernel)
460 hw->type |= HW_BRK_TYPE_KERNEL;
461 if (!attr->exclude_hv)
462 hw->type |= HW_BRK_TYPE_HYP;
463 hw->address = attr->bp_addr;
464 hw->len = attr->bp_len;
466 if (!ppc_breakpoint_available())
469 return hw_breakpoint_validate_len(hw);
473 * Restores the breakpoint on the debug registers.
474 * Invoke this function if it is known that the execution context is
475 * about to change to cause loss of MSR_SE settings.
477 void thread_change_pc(struct task_struct *tsk, struct pt_regs *regs)
479 struct arch_hw_breakpoint *info;
484 for (i = 0; i < nr_wp_slots(); i++) {
485 if (unlikely(tsk->thread.last_hit_ubp[i]))
491 regs->msr &= ~MSR_SE;
492 for (i = 0; i < nr_wp_slots(); i++) {
493 info = counter_arch_bp(__this_cpu_read(bp_per_reg[i]));
494 __set_breakpoint(i, info);
495 tsk->thread.last_hit_ubp[i] = NULL;
502 static bool is_larx_stcx_instr(int type)
504 return type == LARX || type == STCX;
507 static bool is_octword_vsx_instr(int type, int size)
509 return ((type == LOAD_VSX || type == STORE_VSX) && size == 32);
513 * We've failed in reliably handling the hw-breakpoint. Unregister
514 * it and throw a warning message to let the user know about it.
516 static void handler_error(struct perf_event *bp, struct arch_hw_breakpoint *info)
518 WARN(1, "Unable to handle hardware breakpoint. Breakpoint at 0x%lx will be disabled.",
520 perf_event_disable_inatomic(bp);
523 static void larx_stcx_err(struct perf_event *bp, struct arch_hw_breakpoint *info)
525 printk_ratelimited("Breakpoint hit on instruction that can't be emulated. Breakpoint at 0x%lx will be disabled.\n",
527 perf_event_disable_inatomic(bp);
530 static bool stepping_handler(struct pt_regs *regs, struct perf_event **bp,
531 struct arch_hw_breakpoint **info, int *hit,
532 struct ppc_inst instr)
537 /* Do not emulate user-space instructions, instead single-step them */
538 if (user_mode(regs)) {
539 for (i = 0; i < nr_wp_slots(); i++) {
542 current->thread.last_hit_ubp[i] = bp[i];
549 stepped = emulate_step(regs, instr);
551 for (i = 0; i < nr_wp_slots(); i++) {
554 handler_error(bp[i], info[i]);
562 static void handle_p10dd1_spurious_exception(struct arch_hw_breakpoint **info,
563 int *hit, unsigned long ea)
566 unsigned long hw_end_addr;
569 * Handle spurious exception only when any bp_per_reg is set.
570 * Otherwise this might be created by xmon and not actually a
571 * spurious exception.
573 for (i = 0; i < nr_wp_slots(); i++) {
577 hw_end_addr = ALIGN(info[i]->address + info[i]->len, HW_BREAKPOINT_SIZE);
580 * Ending address of DAWR range is less than starting
583 if ((hw_end_addr - 1) >= ea)
587 * Those addresses need to be in the same or in two
588 * consecutive 512B blocks;
590 if (((hw_end_addr - 1) >> 10) != (ea >> 10))
594 * 'op address + 64B' generates an address that has a
595 * carry into bit 52 (crosses 2K boundary).
597 if ((ea & 0x800) == ((ea + 64) & 0x800))
603 if (i == nr_wp_slots())
606 for (i = 0; i < nr_wp_slots(); i++) {
609 info[i]->type |= HW_BRK_TYPE_EXTRANEOUS_IRQ;
615 * Handle a DABR or DAWR exception.
617 * Called in atomic context.
619 int hw_breakpoint_handler(struct die_args *args)
622 int rc = NOTIFY_STOP;
623 struct perf_event *bp[HBP_NUM_MAX] = { NULL };
624 struct pt_regs *regs = args->regs;
625 struct arch_hw_breakpoint *info[HBP_NUM_MAX] = { NULL };
627 int hit[HBP_NUM_MAX] = {0};
629 bool ptrace_bp = false;
630 struct ppc_inst instr = ppc_inst(0);
635 /* Disable breakpoints during exception handling */
636 hw_breakpoint_disable();
639 * The counter may be concurrently released but that can only
640 * occur from a call_rcu() path. We can then safely fetch
641 * the breakpoint, use its callback, touch its counter
642 * while we are in an rcu_read_lock() path.
646 if (!IS_ENABLED(CONFIG_PPC_8xx))
647 wp_get_instr_detail(regs, &instr, &type, &size, &ea);
649 for (i = 0; i < nr_wp_slots(); i++) {
650 bp[i] = __this_cpu_read(bp_per_reg[i]);
654 info[i] = counter_arch_bp(bp[i]);
655 info[i]->type &= ~HW_BRK_TYPE_EXTRANEOUS_IRQ;
657 if (wp_check_constraints(regs, instr, ea, type, size, info[i])) {
658 if (!IS_ENABLED(CONFIG_PPC_8xx) &&
659 ppc_inst_equal(instr, ppc_inst(0))) {
660 handler_error(bp[i], info[i]);
666 if (is_ptrace_bp(bp[i]))
677 /* Workaround for Power10 DD1 */
678 if (!IS_ENABLED(CONFIG_PPC_8xx) && mfspr(SPRN_PVR) == 0x800100 &&
679 is_octword_vsx_instr(type, size)) {
680 handle_p10dd1_spurious_exception(info, hit, ea);
688 * Return early after invoking user-callback function without restoring
689 * DABR if the breakpoint is from ptrace which always operates in
690 * one-shot mode. The ptrace-ed process will receive the SIGTRAP signal
691 * generated in do_dabr().
694 for (i = 0; i < nr_wp_slots(); i++) {
697 perf_bp_event(bp[i], regs);
704 if (!IS_ENABLED(CONFIG_PPC_8xx)) {
705 if (is_larx_stcx_instr(type)) {
706 for (i = 0; i < nr_wp_slots(); i++) {
709 larx_stcx_err(bp[i], info[i]);
715 if (!stepping_handler(regs, bp, info, hit, instr))
720 * As a policy, the callback is invoked in a 'trigger-after-execute'
723 for (i = 0; i < nr_wp_slots(); i++) {
726 if (!(info[i]->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
727 perf_bp_event(bp[i], regs);
731 for (i = 0; i < nr_wp_slots(); i++) {
734 __set_breakpoint(i, info[i]);
741 NOKPROBE_SYMBOL(hw_breakpoint_handler);
744 * Handle single-step exceptions following a DABR hit.
746 * Called in atomic context.
748 static int single_step_dabr_instruction(struct die_args *args)
750 struct pt_regs *regs = args->regs;
751 struct perf_event *bp = NULL;
752 struct arch_hw_breakpoint *info;
757 * Check if we are single-stepping as a result of a
758 * previous HW Breakpoint exception
760 for (i = 0; i < nr_wp_slots(); i++) {
761 bp = current->thread.last_hit_ubp[i];
767 info = counter_arch_bp(bp);
770 * We shall invoke the user-defined callback function in the
771 * single stepping handler to confirm to 'trigger-after-execute'
774 if (!(info->type & HW_BRK_TYPE_EXTRANEOUS_IRQ))
775 perf_bp_event(bp, regs);
776 current->thread.last_hit_ubp[i] = NULL;
782 for (i = 0; i < nr_wp_slots(); i++) {
783 bp = __this_cpu_read(bp_per_reg[i]);
787 info = counter_arch_bp(bp);
788 __set_breakpoint(i, info);
792 * If the process was being single-stepped by ptrace, let the
793 * other single-step actions occur (e.g. generate SIGTRAP).
795 if (test_thread_flag(TIF_SINGLESTEP))
800 NOKPROBE_SYMBOL(single_step_dabr_instruction);
803 * Handle debug exception notifications.
805 * Called in atomic context.
807 int hw_breakpoint_exceptions_notify(
808 struct notifier_block *unused, unsigned long val, void *data)
810 int ret = NOTIFY_DONE;
814 ret = hw_breakpoint_handler(data);
817 ret = single_step_dabr_instruction(data);
823 NOKPROBE_SYMBOL(hw_breakpoint_exceptions_notify);
826 * Release the user breakpoints used by ptrace
828 void flush_ptrace_hw_breakpoint(struct task_struct *tsk)
831 struct thread_struct *t = &tsk->thread;
833 for (i = 0; i < nr_wp_slots(); i++) {
834 unregister_hw_breakpoint(t->ptrace_bps[i]);
835 t->ptrace_bps[i] = NULL;
839 void hw_breakpoint_pmu_read(struct perf_event *bp)
844 void ptrace_triggered(struct perf_event *bp,
845 struct perf_sample_data *data, struct pt_regs *regs)
847 struct perf_event_attr attr;
850 * Disable the breakpoint request here since ptrace has defined a
851 * one-shot behaviour for breakpoint exceptions in PPC64.
852 * The SIGTRAP signal is generated automatically for us in do_dabr().
853 * We don't have to do anything about that here
856 attr.disabled = true;
857 modify_user_hw_breakpoint(bp, &attr);