1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Kernel execution entry point code.
5 * Copyright (c) 1995-1996 Gary Thomas <gdt@linuxppc.org>
6 * Initial PowerPC version.
7 * Copyright (c) 1996 Cort Dougan <cort@cs.nmt.edu>
9 * Copyright (c) 1996 Paul Mackerras <paulus@cs.anu.edu.au>
10 * Low-level exception handers, MMU support, and rewrite.
11 * Copyright (c) 1997 Dan Malek <dmalek@jlc.net>
12 * PowerPC 8xx modifications.
13 * Copyright (c) 1998-1999 TiVo, Inc.
14 * PowerPC 403GCX modifications.
15 * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu>
16 * PowerPC 403GCX/405GP modifications.
17 * Copyright 2000 MontaVista Software Inc.
18 * PPC405 modifications
19 * PowerPC 403GCX/405GP modifications.
20 * Author: MontaVista Software, Inc.
21 * frank_rowand@mvista.com or source@mvista.com
22 * debbie_chu@mvista.com
23 * Copyright 2002-2004 MontaVista Software, Inc.
24 * PowerPC 44x support, Matt Porter <mporter@kernel.crashing.org>
25 * Copyright 2004 Freescale Semiconductor, Inc
26 * PowerPC e500 modifications, Kumar Gala <galak@kernel.crashing.org>
29 #include <linux/init.h>
30 #include <linux/threads.h>
31 #include <asm/processor.h>
34 #include <asm/pgtable.h>
35 #include <asm/cputable.h>
36 #include <asm/thread_info.h>
37 #include <asm/ppc_asm.h>
38 #include <asm/asm-offsets.h>
39 #include <asm/cache.h>
40 #include <asm/ptrace.h>
41 #include <asm/export.h>
42 #include <asm/feature-fixups.h>
43 #include "head_booke.h"
45 /* As with the other PowerPC ports, it is expected that when code
46 * execution begins here, the following registers contain valid, yet
47 * optional, information:
49 * r3 - Board info structure pointer (DRAM, frequency, MAC address, etc.)
50 * r4 - Starting address of the init RAM disk
51 * r5 - Ending address of the init RAM disk
52 * r6 - Start of kernel command line string (e.g. "mem=128")
53 * r7 - End of kernel command line string
60 * Reserve a word at a fixed location to store the address
65 /* Translate device tree address to physical, save in r30/r31 */
70 li r25,0 /* phys kernel start (low) */
71 li r24,0 /* CPU number */
72 li r23,0 /* phys kernel start (high) */
74 #ifdef CONFIG_RELOCATABLE
75 LOAD_REG_ADDR_PIC(r3, _stext) /* Get our current runtime base */
77 /* Translate _stext address to physical, save in r23/r25 */
84 addis r3,r8,(is_second_reloc - 0b)@ha
85 lwz r19,(is_second_reloc - 0b)@l(r3)
87 /* Check if this is the second relocation. */
92 * For the second relocation, we already get the real memstart_addr
93 * from device tree. So we will map PAGE_OFFSET to memstart_addr,
94 * then the virtual address of start kernel should be:
95 * PAGE_OFFSET + (kernstart_addr - memstart_addr)
96 * Since the offset between kernstart_addr and memstart_addr should
97 * never be beyond 1G, so we can just use the lower 32bit of them
98 * for the calculation.
102 addis r4,r8,(kernstart_addr - 0b)@ha
103 addi r4,r4,(kernstart_addr - 0b)@l
106 addis r6,r8,(memstart_addr - 0b)@ha
107 addi r6,r6,(memstart_addr - 0b)@l
116 * We have the runtime (virutal) address of our base.
117 * We calculate our shift of offset from a 64M page.
118 * We could map the 64M page we belong to at PAGE_OFFSET and
119 * get going from there.
122 ori r4,r4,KERNELBASE@l
123 rlwinm r6,r25,0,0x3ffffff /* r6 = PHYS_START % 64M */
124 rlwinm r5,r4,0,0x3ffffff /* r5 = KERNELBASE % 64M */
125 subf r3,r5,r6 /* r3 = r6 - r5 */
126 add r3,r4,r3 /* Required Virtual Address */
131 * For the second relocation, we already set the right tlb entries
132 * for the kernel space, so skip the code in fsl_booke_entry_mapping.S
138 /* We try to not make any assumptions about how the boot loader
139 * setup or used the TLBs. We invalidate all mappings from the
140 * boot loader and load a single entry in TLB1[0] to map the
141 * first 64M of kernel memory. Any boot info passed from the
142 * bootloader needs to live in this first 64M.
144 * Requirement on bootloader:
145 * - The page we're executing in needs to reside in TLB1 and
146 * have IPROT=1. If not an invalidate broadcast could
147 * evict the entry we're currently executing in.
149 * r3 = Index of TLB1 were executing in
150 * r4 = Current MSR[IS]
151 * r5 = Index of TLB1 temp mapping
153 * Later in mapin_ram we will correctly map lowmem, and resize TLB1[0]
157 _ENTRY(__early_start)
159 #define ENTRY_MAPPING_BOOT_SETUP
160 #include "fsl_booke_entry_mapping.S"
161 #undef ENTRY_MAPPING_BOOT_SETUP
164 /* Establish the interrupt vector offsets */
165 SET_IVOR(0, CriticalInput);
166 SET_IVOR(1, MachineCheck);
167 SET_IVOR(2, DataStorage);
168 SET_IVOR(3, InstructionStorage);
169 SET_IVOR(4, ExternalInput);
170 SET_IVOR(5, Alignment);
171 SET_IVOR(6, Program);
172 SET_IVOR(7, FloatingPointUnavailable);
173 SET_IVOR(8, SystemCall);
174 SET_IVOR(9, AuxillaryProcessorUnavailable);
175 SET_IVOR(10, Decrementer);
176 SET_IVOR(11, FixedIntervalTimer);
177 SET_IVOR(12, WatchdogTimer);
178 SET_IVOR(13, DataTLBError);
179 SET_IVOR(14, InstructionTLBError);
180 SET_IVOR(15, DebugCrit);
182 /* Establish the interrupt vector base */
183 lis r4,interrupt_base@h /* IVPR only uses the high 16-bits */
186 /* Setup the defaults for TLB entries */
187 li r2,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
189 oris r2,r2,MAS4_TLBSELD(1)@h
193 #if !defined(CONFIG_BDI_SWITCH)
195 * The Abatron BDI JTAG debugger does not tolerate others
196 * mucking with the debug registers.
201 /* clear any residual debug events */
207 /* Check to see if we're the second processor, and jump
208 * to the secondary_start code if so
210 LOAD_REG_ADDR_PIC(r24, boot_cpuid)
214 bne __secondary_start
218 * This is where the main kernel code starts.
223 ori r2,r2,init_task@l
225 /* ptr to current thread */
226 addi r4,r2,THREAD /* init task's THREAD */
227 mtspr SPRN_SPRG_THREAD,r4
230 lis r1,init_thread_union@h
231 ori r1,r1,init_thread_union@l
233 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
236 stw r24, TASK_CPU(r2)
244 #ifdef CONFIG_RELOCATABLE
247 #ifdef CONFIG_PHYS_64BIT
256 #ifdef CONFIG_DYNAMIC_MEMSTART
257 lis r3,kernstart_addr@ha
258 la r3,kernstart_addr@l(r3)
259 #ifdef CONFIG_PHYS_64BIT
268 * Decide what sort of machine this is and initialize the MMU.
275 /* Setup PTE pointers for the Abatron bdiGDB */
276 lis r6, swapper_pg_dir@h
277 ori r6, r6, swapper_pg_dir@l
278 lis r5, abatron_pteptrs@h
279 ori r5, r5, abatron_pteptrs@l
281 ori r4, r4, KERNELBASE@l
282 stw r5, 0(r4) /* Save abatron_pteptrs at a fixed location */
286 lis r4,start_kernel@h
287 ori r4,r4,start_kernel@l
289 ori r3,r3,MSR_KERNEL@l
292 rfi /* change context and jump to start_kernel */
294 /* Macros to hide the PTE size differences
296 * FIND_PTE -- walks the page tables given EA & pgdir pointer
298 * r11 -- PGDIR pointer
300 * label 2: is the bailout case
302 * if we find the pte (fall through):
303 * r11 is low pte word
304 * r12 is pointer to the pte
305 * r10 is the pshift from the PGD, if we're a hugepage
307 #ifdef CONFIG_PTE_64BIT
308 #ifdef CONFIG_HUGETLB_PAGE
310 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
311 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
312 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
313 blt 1000f; /* Normal non-huge page */ \
314 beq 2f; /* Bail if no table */ \
315 oris r11, r11, PD_HUGE@h; /* Put back address bit */ \
316 andi. r10, r11, HUGEPD_SHIFT_MASK@l; /* extract size field */ \
317 xor r12, r10, r11; /* drop size bits from pointer */ \
319 1000: rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
320 li r10, 0; /* clear r10 */ \
321 1001: lwz r11, 4(r12); /* Get pte entry */
324 rlwinm r12, r10, 13, 19, 29; /* Compute pgdir/pmd offset */ \
325 lwzx r11, r12, r11; /* Get pgd/pmd entry */ \
326 rlwinm. r12, r11, 0, 0, 20; /* Extract pt base address */ \
327 beq 2f; /* Bail if no table */ \
328 rlwimi r12, r10, 23, 20, 28; /* Compute pte address */ \
329 lwz r11, 4(r12); /* Get pte entry */
330 #endif /* HUGEPAGE */
331 #else /* !PTE_64BIT */
333 rlwimi r11, r10, 12, 20, 29; /* Create L1 (pgdir/pmd) address */ \
334 lwz r11, 0(r11); /* Get L1 entry */ \
335 rlwinm. r12, r11, 0, 0, 19; /* Extract L2 (pte) base address */ \
336 beq 2f; /* Bail if no table */ \
337 rlwimi r12, r10, 22, 20, 29; /* Compute PTE address */ \
338 lwz r11, 0(r12); /* Get Linux PTE */
342 * Interrupt vector entry code
344 * The Book E MMUs are always on so we don't need to handle
345 * interrupts in real mode as with previous PPC processors. In
346 * this case we handle interrupts in the kernel virtual address
349 * Interrupt vectors are dynamically placed relative to the
350 * interrupt prefix as determined by the address of interrupt_base.
351 * The interrupt vectors offsets are programmed using the labels
352 * for each interrupt vector entry.
354 * Interrupt vectors must be aligned on a 16 byte boundary.
355 * We align on a 32 byte cache line boundary for good measure.
359 /* Critical Input Interrupt */
360 CRITICAL_EXCEPTION(0x0100, CRITICAL, CriticalInput, unknown_exception)
362 /* Machine Check Interrupt */
364 /* no RFMCI, MCSRRs on E200 */
365 CRITICAL_EXCEPTION(0x0200, MACHINE_CHECK, MachineCheck, \
366 machine_check_exception)
368 MCHECK_EXCEPTION(0x0200, MachineCheck, machine_check_exception)
371 /* Data Storage Interrupt */
372 START_EXCEPTION(DataStorage)
373 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE)
374 mfspr r5,SPRN_ESR /* Grab the ESR, save it, pass arg3 */
376 mfspr r4,SPRN_DEAR /* Grab the DEAR, save it, pass arg2 */
377 andis. r10,r5,(ESR_ILK|ESR_DLK)@h
379 EXC_XFER_LITE(0x0300, handle_page_fault)
381 addi r3,r1,STACK_FRAME_OVERHEAD
382 EXC_XFER_LITE(0x0300, CacheLockingException)
384 /* Instruction Storage Interrupt */
385 INSTRUCTION_STORAGE_EXCEPTION
387 /* External Input Interrupt */
388 EXCEPTION(0x0500, EXTERNAL, ExternalInput, do_IRQ, EXC_XFER_LITE)
390 /* Alignment Interrupt */
393 /* Program Interrupt */
396 /* Floating Point Unavailable Interrupt */
397 #ifdef CONFIG_PPC_FPU
398 FP_UNAVAILABLE_EXCEPTION
401 /* E200 treats 'normal' floating point instructions as FP Unavail exception */
402 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
403 program_check_exception, EXC_XFER_STD)
405 EXCEPTION(0x0800, FP_UNAVAIL, FloatingPointUnavailable, \
406 unknown_exception, EXC_XFER_STD)
410 /* System Call Interrupt */
411 START_EXCEPTION(SystemCall)
412 SYSCALL_ENTRY 0xc00 BOOKE_INTERRUPT_SYSCALL SPRN_SRR1
414 /* Auxiliary Processor Unavailable Interrupt */
415 EXCEPTION(0x2900, AP_UNAVAIL, AuxillaryProcessorUnavailable, \
416 unknown_exception, EXC_XFER_STD)
418 /* Decrementer Interrupt */
419 DECREMENTER_EXCEPTION
421 /* Fixed Internal Timer Interrupt */
422 /* TODO: Add FIT support */
423 EXCEPTION(0x3100, FIT, FixedIntervalTimer, \
424 unknown_exception, EXC_XFER_STD)
426 /* Watchdog Timer Interrupt */
427 #ifdef CONFIG_BOOKE_WDT
428 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, WatchdogException)
430 CRITICAL_EXCEPTION(0x3200, WATCHDOG, WatchdogTimer, unknown_exception)
433 /* Data TLB Error Interrupt */
434 START_EXCEPTION(DataTLBError)
435 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
436 mfspr r10, SPRN_SPRG_THREAD
437 stw r11, THREAD_NORMSAVE(0)(r10)
438 #ifdef CONFIG_KVM_BOOKE_HV
441 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
443 stw r12, THREAD_NORMSAVE(1)(r10)
444 stw r13, THREAD_NORMSAVE(2)(r10)
446 stw r13, THREAD_NORMSAVE(3)(r10)
447 DO_KVM BOOKE_INTERRUPT_DTLB_MISS SPRN_SRR1
448 START_BTB_FLUSH_SECTION
454 END_BTB_FLUSH_SECTION
455 mfspr r10, SPRN_DEAR /* Get faulting address */
457 /* If we are faulting a kernel address, we have to use the
458 * kernel page tables.
460 lis r11, PAGE_OFFSET@h
463 lis r11, swapper_pg_dir@h
464 ori r11, r11, swapper_pg_dir@l
466 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
467 rlwinm r12,r12,0,16,1
472 /* Get the PGD for the current thread */
474 mfspr r11,SPRN_SPRG_THREAD
478 /* Mask of required permission bits. Note that while we
479 * do copy ESR:ST to _PAGE_RW position as trying to write
480 * to an RO page is pretty common, we don't do it with
481 * _PAGE_DIRTY. We could do it, but it's a fairly rare
482 * event so I'd rather take the overhead when it happens
483 * rather than adding an instruction here. We should measure
484 * whether the whole thing is worth it in the first place
485 * as we could avoid loading SPRN_ESR completely in the first
488 * TODO: Is it worth doing that mfspr & rlwimi in the first
489 * place or can we save a couple of instructions here ?
492 #ifdef CONFIG_PTE_64BIT
494 oris r13,r13,_PAGE_ACCESSED@h
496 li r13,_PAGE_PRESENT|_PAGE_ACCESSED
498 rlwimi r13,r12,11,29,29
501 andc. r13,r13,r11 /* Check permission */
503 #ifdef CONFIG_PTE_64BIT
505 subf r13,r11,r12 /* create false data dep */
506 lwzx r13,r11,r13 /* Get upper pte bits */
508 lwz r13,0(r12) /* Get upper pte bits */
512 bne 2f /* Bail if permission/valid mismach */
514 /* Jump to common tlb load */
517 /* The bailout. Restore registers to pre-exception conditions
518 * and call the heavyweights to help us out.
520 mfspr r10, SPRN_SPRG_THREAD
521 lwz r11, THREAD_NORMSAVE(3)(r10)
523 lwz r13, THREAD_NORMSAVE(2)(r10)
524 lwz r12, THREAD_NORMSAVE(1)(r10)
525 lwz r11, THREAD_NORMSAVE(0)(r10)
526 mfspr r10, SPRN_SPRG_RSCRATCH0
529 /* Instruction TLB Error Interrupt */
531 * Nearly the same as above, except we get our
532 * information from different registers and bailout
533 * to a different point.
535 START_EXCEPTION(InstructionTLBError)
536 mtspr SPRN_SPRG_WSCRATCH0, r10 /* Save some working registers */
537 mfspr r10, SPRN_SPRG_THREAD
538 stw r11, THREAD_NORMSAVE(0)(r10)
539 #ifdef CONFIG_KVM_BOOKE_HV
542 END_FTR_SECTION_IFSET(CPU_FTR_EMB_HV)
544 stw r12, THREAD_NORMSAVE(1)(r10)
545 stw r13, THREAD_NORMSAVE(2)(r10)
547 stw r13, THREAD_NORMSAVE(3)(r10)
548 DO_KVM BOOKE_INTERRUPT_ITLB_MISS SPRN_SRR1
549 START_BTB_FLUSH_SECTION
555 END_BTB_FLUSH_SECTION
557 mfspr r10, SPRN_SRR0 /* Get faulting address */
559 /* If we are faulting a kernel address, we have to use the
560 * kernel page tables.
562 lis r11, PAGE_OFFSET@h
565 lis r11, swapper_pg_dir@h
566 ori r11, r11, swapper_pg_dir@l
568 mfspr r12,SPRN_MAS1 /* Set TID to 0 */
569 rlwinm r12,r12,0,16,1
572 /* Make up the required permissions for kernel code */
573 #ifdef CONFIG_PTE_64BIT
574 li r13,_PAGE_PRESENT | _PAGE_BAP_SX
575 oris r13,r13,_PAGE_ACCESSED@h
577 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
581 /* Get the PGD for the current thread */
583 mfspr r11,SPRN_SPRG_THREAD
586 /* Make up the required permissions for user code */
587 #ifdef CONFIG_PTE_64BIT
588 li r13,_PAGE_PRESENT | _PAGE_BAP_UX
589 oris r13,r13,_PAGE_ACCESSED@h
591 li r13,_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_EXEC
596 andc. r13,r13,r11 /* Check permission */
598 #ifdef CONFIG_PTE_64BIT
600 subf r13,r11,r12 /* create false data dep */
601 lwzx r13,r11,r13 /* Get upper pte bits */
603 lwz r13,0(r12) /* Get upper pte bits */
607 bne 2f /* Bail if permission mismach */
609 /* Jump to common TLB load point */
613 /* The bailout. Restore registers to pre-exception conditions
614 * and call the heavyweights to help us out.
616 mfspr r10, SPRN_SPRG_THREAD
617 lwz r11, THREAD_NORMSAVE(3)(r10)
619 lwz r13, THREAD_NORMSAVE(2)(r10)
620 lwz r12, THREAD_NORMSAVE(1)(r10)
621 lwz r11, THREAD_NORMSAVE(0)(r10)
622 mfspr r10, SPRN_SPRG_RSCRATCH0
625 /* Define SPE handlers for e200 and e500v2 */
627 /* SPE Unavailable */
628 START_EXCEPTION(SPEUnavailable)
629 NORMAL_EXCEPTION_PROLOG(SPE_UNAVAIL)
632 b fast_exception_return
633 1: addi r3,r1,STACK_FRAME_OVERHEAD
634 EXC_XFER_LITE(0x2010, KernelSPE)
635 #elif defined(CONFIG_SPE_POSSIBLE)
636 EXCEPTION(0x2020, SPE_UNAVAIL, SPEUnavailable, \
637 unknown_exception, EXC_XFER_STD)
638 #endif /* CONFIG_SPE_POSSIBLE */
640 /* SPE Floating Point Data */
642 EXCEPTION(0x2030, SPE_FP_DATA, SPEFloatingPointData,
643 SPEFloatingPointException, EXC_XFER_STD)
645 /* SPE Floating Point Round */
646 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
647 SPEFloatingPointRoundException, EXC_XFER_STD)
648 #elif defined(CONFIG_SPE_POSSIBLE)
649 EXCEPTION(0x2040, SPE_FP_DATA, SPEFloatingPointData,
650 unknown_exception, EXC_XFER_STD)
651 EXCEPTION(0x2050, SPE_FP_ROUND, SPEFloatingPointRound, \
652 unknown_exception, EXC_XFER_STD)
653 #endif /* CONFIG_SPE_POSSIBLE */
656 /* Performance Monitor */
657 EXCEPTION(0x2060, PERFORMANCE_MONITOR, PerformanceMonitor, \
658 performance_monitor_exception, EXC_XFER_STD)
660 EXCEPTION(0x2070, DOORBELL, Doorbell, doorbell_exception, EXC_XFER_STD)
662 CRITICAL_EXCEPTION(0x2080, DOORBELL_CRITICAL, \
663 CriticalDoorbell, unknown_exception)
665 /* Debug Interrupt */
666 DEBUG_DEBUG_EXCEPTION
669 GUEST_DOORBELL_EXCEPTION
671 CRITICAL_EXCEPTION(0, GUEST_DBELL_CRIT, CriticalGuestDoorbell, \
675 EXCEPTION(0, HV_SYSCALL, Hypercall, unknown_exception, EXC_XFER_STD)
677 /* Embedded Hypervisor Privilege */
678 EXCEPTION(0, HV_PRIV, Ehvpriv, unknown_exception, EXC_XFER_STD)
687 * Both the instruction and data TLB miss get to this
688 * point to load the TLB.
689 * r10 - tsize encoding (if HUGETLB_PAGE) or available to use
690 * r11 - TLB (info from Linux PTE)
691 * r12 - available to use
692 * r13 - upper bits of PTE (if PTE_64BIT) or available to use
693 * CR5 - results of addr >= PAGE_OFFSET
694 * MAS0, MAS1 - loaded with proper value when we get here
695 * MAS2, MAS3 - will need additional info from Linux PTE
696 * Upon exit, we reload everything and RFI.
699 #ifdef CONFIG_HUGETLB_PAGE
700 cmpwi 6, r10, 0 /* check for huge page */
701 beq 6, finish_tlb_load_cont /* !huge */
703 /* Alas, we need more scratch registers for hugepages */
704 mfspr r12, SPRN_SPRG_THREAD
705 stw r14, THREAD_NORMSAVE(4)(r12)
706 stw r15, THREAD_NORMSAVE(5)(r12)
707 stw r16, THREAD_NORMSAVE(6)(r12)
708 stw r17, THREAD_NORMSAVE(7)(r12)
710 /* Get the next_tlbcam_idx percpu var */
712 lwz r15, TASK_CPU-THREAD(r12)
713 lis r14, __per_cpu_offset@h
714 ori r14, r14, __per_cpu_offset@l
715 rlwinm r15, r15, 2, 0, 29
720 lis r17, next_tlbcam_idx@h
721 ori r17, r17, next_tlbcam_idx@l
722 add r17, r17, r16 /* r17 = *next_tlbcam_idx */
723 lwz r15, 0(r17) /* r15 = next_tlbcam_idx */
725 lis r14, MAS0_TLBSEL(1)@h /* select TLB1 (TLBCAM) */
726 rlwimi r14, r15, 16, 4, 15 /* next_tlbcam_idx entry */
729 /* Extract TLB1CFG(NENTRY) */
730 mfspr r16, SPRN_TLB1CFG
731 andi. r16, r16, 0xfff
733 /* Update next_tlbcam_idx, wrapping when necessary */
737 lis r14, tlbcam_index@h
738 ori r14, r14, tlbcam_index@l
743 * Calc MAS1_TSIZE from r10 (which has pshift encoded)
744 * tlb_enc = (pshift - 10).
748 rlwimi r16, r15, 7, 20, 24
751 /* copy the pshift for use later */
756 #endif /* CONFIG_HUGETLB_PAGE */
759 * We set execute, because we don't have the granularity to
760 * properly set this at the page level (Linux problem).
761 * Many of these bits are software only. Bits we don't set
762 * here we (properly should) assume have the appropriate value.
764 finish_tlb_load_cont:
765 #ifdef CONFIG_PTE_64BIT
766 rlwinm r12, r11, 32-2, 26, 31 /* Move in perm bits */
767 andi. r10, r11, _PAGE_DIRTY
769 li r10, MAS3_SW | MAS3_UW
771 1: rlwimi r12, r13, 20, 0, 11 /* grab RPN[32:43] */
772 rlwimi r12, r11, 20, 12, 19 /* grab RPN[44:51] */
773 2: mtspr SPRN_MAS3, r12
774 BEGIN_MMU_FTR_SECTION
775 srwi r10, r13, 12 /* grab RPN[12:31] */
777 END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS)
779 li r10, (_PAGE_EXEC | _PAGE_PRESENT)
781 rlwimi r10, r11, 31, 29, 29 /* extract _PAGE_DIRTY into SW */
783 andi. r10, r11, _PAGE_USER /* Test for _PAGE_USER */
787 rlwimi r13, r12, 0, 20, 31 /* Get RPN from PTE, merge w/ perms */
792 #ifdef CONFIG_PTE_64BIT
793 rlwimi r12, r11, 32-19, 27, 31 /* extract WIMGE from pte */
795 rlwimi r12, r11, 26, 27, 31 /* extract WIMGE from pte */
797 #ifdef CONFIG_HUGETLB_PAGE
798 beq 6, 3f /* don't mask if page isn't huge */
802 rlwinm r13, r13, 0, 0, 19 /* bottom bits used for WIMGE/etc */
803 andc r12, r12, r13 /* mask off ea bits within the page */
805 3: mtspr SPRN_MAS2, r12
808 /* Round robin TLB1 entries assignment */
811 /* Extract TLB1CFG(NENTRY) */
812 mfspr r11, SPRN_TLB1CFG
813 andi. r11, r11, 0xfff
815 /* Extract MAS0(NV) */
816 andi. r13, r12, 0xfff
821 /* check if we need to wrap */
824 /* wrap back to first free tlbcam entry */
825 lis r13, tlbcam_index@ha
826 lwz r13, tlbcam_index@l(r13)
827 rlwimi r12, r13, 0, 20, 31
830 #endif /* CONFIG_E200 */
835 /* Done...restore registers and get out of here. */
836 mfspr r10, SPRN_SPRG_THREAD
837 #ifdef CONFIG_HUGETLB_PAGE
838 beq 6, 8f /* skip restore for 4k page faults */
839 lwz r14, THREAD_NORMSAVE(4)(r10)
840 lwz r15, THREAD_NORMSAVE(5)(r10)
841 lwz r16, THREAD_NORMSAVE(6)(r10)
842 lwz r17, THREAD_NORMSAVE(7)(r10)
844 8: lwz r11, THREAD_NORMSAVE(3)(r10)
846 lwz r13, THREAD_NORMSAVE(2)(r10)
847 lwz r12, THREAD_NORMSAVE(1)(r10)
848 lwz r11, THREAD_NORMSAVE(0)(r10)
849 mfspr r10, SPRN_SPRG_RSCRATCH0
850 rfi /* Force context change */
853 /* Note that the SPE support is closely modeled after the AltiVec
854 * support. Changes to one are likely to be applicable to the
858 * Disable SPE for the task which had SPE previously,
859 * and save its SPE registers in its thread_struct.
860 * Enables SPE for use in the kernel on return.
861 * On SMP we know the SPE units are free, since we give it up every
866 mtmsr r5 /* enable use of SPE now */
868 /* enable use of SPE after return */
870 mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
873 stw r4,THREAD_USED_SPE(r5)
876 REST_32EVRS(0,r10,r5,THREAD_EVR0)
880 * SPE unavailable trap from kernel - print a message, but let
881 * the task use SPE in the kernel until it returns to user mode.
886 stw r3,_MSR(r1) /* enable use of SPE after return */
890 mr r4,r2 /* current */
896 87: .string "SPE used in kernel (task=%p, pc=%x) \n"
900 #endif /* CONFIG_SPE */
903 * Translate the effec addr in r3 to phys addr. The phys addr will be put
904 * into r3(higher 32bit) and r4(lower 32bit)
909 rlwinm r9,r9,16,0x3fff0000 /* turn PID into MAS6[SPID] */
910 rlwimi r9,r8,28,0x00000001 /* turn MSR[DS] into MAS6[SAS] */
913 tlbsx 0,r3 /* must succeed */
917 rlwinm r9,r8,25,0x1f /* r9 = log2(page size) */
919 slw r10,r10,r9 /* r10 = page size */
921 and r11,r3,r10 /* r11 = page offset */
922 andc r4,r12,r10 /* r4 = page base */
923 or r4,r4,r11 /* r4 = devtree phys addr */
924 #ifdef CONFIG_PHYS_64BIT
934 /* Adjust or setup IVORs for e200 */
935 _GLOBAL(__setup_e200_ivors)
938 li r3,SPEUnavailable@l
940 li r3,SPEFloatingPointData@l
942 li r3,SPEFloatingPointRound@l
949 #ifndef CONFIG_PPC_E500MC
950 /* Adjust or setup IVORs for e500v1/v2 */
951 _GLOBAL(__setup_e500_ivors)
954 li r3,SPEUnavailable@l
956 li r3,SPEFloatingPointData@l
958 li r3,SPEFloatingPointRound@l
960 li r3,PerformanceMonitor@l
965 /* Adjust or setup IVORs for e500mc */
966 _GLOBAL(__setup_e500mc_ivors)
969 li r3,PerformanceMonitor@l
973 li r3,CriticalDoorbell@l
978 /* setup ehv ivors for */
979 _GLOBAL(__setup_ehv_ivors)
980 li r3,GuestDoorbell@l
982 li r3,CriticalGuestDoorbell@l
990 #endif /* CONFIG_PPC_E500MC */
991 #endif /* CONFIG_E500 */
995 * extern void __giveup_spe(struct task_struct *prev)
998 _GLOBAL(__giveup_spe)
999 addi r3,r3,THREAD /* want THREAD of task */
1002 SAVE_32EVRS(0, r4, r3, THREAD_EVR0)
1003 evxor evr6, evr6, evr6 /* clear out evr6 */
1004 evmwumiaa evr6, evr6, evr6 /* evr6 <- ACC = 0 * 0 + ACC */
1006 evstddx evr6, r4, r3 /* save off accumulator */
1008 lwz r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1010 andc r4,r4,r3 /* disable SPE for previous task */
1011 stw r4,_MSR-STACK_FRAME_OVERHEAD(r5)
1014 #endif /* CONFIG_SPE */
1017 * extern void abort(void)
1019 * At present, this routine just applies a system reset.
1023 mtspr SPRN_DBCR0,r13 /* disable all debug events */
1026 ori r13,r13,MSR_DE@l /* Enable Debug Events */
1029 mfspr r13,SPRN_DBCR0
1030 lis r13,(DBCR0_IDM|DBCR0_RST_CHIP)@h
1031 mtspr SPRN_DBCR0,r13
1034 _GLOBAL(set_context)
1036 #ifdef CONFIG_BDI_SWITCH
1037 /* Context switch the PTE pointer for the Abatron BDI2000.
1038 * The PGDIR is the second parameter.
1040 lis r5, abatron_pteptrs@h
1041 ori r5, r5, abatron_pteptrs@l
1045 isync /* Force context change */
1049 /* When we get here, r24 needs to hold the CPU # */
1050 .globl __secondary_start
1052 LOAD_REG_ADDR_PIC(r3, tlbcam_index)
1055 li r26,0 /* r26 safe? */
1058 mr r27,r3 /* tlb entry */
1059 /* Load each CAM entry */
1064 mr r3,r27 /* tlb entry */
1065 LOAD_REG_ADDR_PIC(r4, memstart_addr)
1067 mr r5,r25 /* phys kernel start */
1068 rlwinm r5,r5,0,~0x3ffffff /* aligned 64M */
1069 subf r4,r5,r4 /* memstart_addr - phys kernel start */
1070 li r5,0 /* no device tree */
1071 li r6,0 /* not boot cpu */
1075 lis r3,__secondary_hold_acknowledge@h
1076 ori r3,r3,__secondary_hold_acknowledge@l
1080 mr r4,r24 /* Why? */
1083 /* get current's stack and current */
1084 lis r2,secondary_current@ha
1085 lwz r2,secondary_current@l(r2)
1086 lwz r1,TASK_STACK(r2)
1089 addi r1,r1,THREAD_SIZE-STACK_FRAME_OVERHEAD
1093 /* ptr to current thread */
1094 addi r4,r2,THREAD /* address of our thread_struct */
1095 mtspr SPRN_SPRG_THREAD,r4
1097 /* Setup the defaults for TLB entries */
1098 li r4,(MAS4_TSIZED(BOOK3E_PAGESZ_4K))@l
1101 /* Jump to start_secondary */
1103 ori r4,r4,MSR_KERNEL@l
1104 lis r3,start_secondary@h
1105 ori r3,r3,start_secondary@l
1112 .globl __secondary_hold_acknowledge
1113 __secondary_hold_acknowledge:
1118 * Create a tlb entry with the same effective and physical address as
1119 * the tlb entry used by the current running code. But set the TS to 1.
1120 * Then switch to the address space 1. It will return with the r3 set to
1121 * the ESEL of the new created tlb.
1123 _GLOBAL(switch_to_as1)
1126 /* Find a entry not used */
1127 mfspr r3,SPRN_TLB1CFG
1130 rlwinm r4,r4,16,0x3fff0000 /* turn PID into MAS6[SPID] */
1132 1: lis r4,0x1000 /* Set MAS0(TLBSEL) = 1 */
1134 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1138 andis. r4,r4,MAS1_VALID@h
1141 /* Get the tlb entry used by the current running code */
1147 ori r4,r4,MAS1_TS /* Set the TS = 1 */
1151 rlwinm r4,r4,0,~MAS0_ESEL_MASK
1152 rlwimi r4,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1159 ori r4,r4,MSR_IS | MSR_DS
1166 * Restore to the address space 0 and also invalidate the tlb entry created
1168 * r3 - the tlb entry which should be invalidated
1169 * r4 - __pa(PAGE_OFFSET in AS1) - __pa(PAGE_OFFSET in AS0)
1170 * r5 - device tree virtual address. If r4 is 0, r5 is ignored.
1173 _GLOBAL(restore_to_as0)
1181 * We may map the PAGE_OFFSET in AS0 to a different physical address,
1182 * so we need calculate the right jump and device tree address based
1183 * on the offset passed by r4.
1190 li r8,(MSR_IS | MSR_DS)
1198 /* Invalidate the temporary tlb entry for AS1 */
1199 1: lis r9,0x1000 /* Set MAS0(TLBSEL) = 1 */
1200 rlwimi r9,r3,16,4,15 /* Setup MAS0 = TLBSEL | ESEL(r3) */
1204 rlwinm r9,r9,0,2,31 /* Clear MAS1 Valid and IPPROT */
1212 bne 3f /* offset != 0 && is_boot_cpu */
1217 * The PAGE_OFFSET will map to a different physical address,
1218 * jump to _start to do another relocation again.
1224 * We put a few things here that have to be page-aligned. This stuff
1225 * goes at the beginning of the data segment, which is page-aligned.
1231 .globl empty_zero_page
1234 EXPORT_SYMBOL(empty_zero_page)
1235 .globl swapper_pg_dir
1237 .space PGD_TABLE_SIZE
1240 * Room for two PTE pointers, usually the kernel and current user pointers
1241 * to their respective root page table.