1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __HEAD_BOOKE_H__
3 #define __HEAD_BOOKE_H__
5 #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
6 #include <asm/kvm_asm.h>
7 #include <asm/kvm_booke_hv_asm.h>
8 #include <asm/thread_info.h> /* for THREAD_SHIFT */
13 * Macros used for common Book-e exception handling
16 #define SET_IVOR(vector_number, vector_label) \
17 li r26,vector_label@l; \
18 mtspr SPRN_IVOR##vector_number,r26; \
21 #if (THREAD_SHIFT < 15)
22 #define ALLOC_STACK_FRAME(reg, val) \
25 #define ALLOC_STACK_FRAME(reg, val) \
26 addis reg,reg,val@ha; \
31 * Macro used to get to thread save registers.
32 * Note that entries 0-3 are used for the prolog code, and the remaining
33 * entries are available for specific exception use in the event a handler
34 * requires more than 4 scratch registers.
36 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
38 #ifdef CONFIG_PPC_E500
39 #define BOOKE_CLEAR_BTB(reg) \
40 START_BTB_FLUSH_SECTION \
44 #define BOOKE_CLEAR_BTB(reg)
48 #define NORMAL_EXCEPTION_PROLOG(trapno, intno) \
49 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
50 mfspr r10, SPRN_SPRG_THREAD; \
51 stw r11, THREAD_NORMSAVE(0)(r10); \
52 stw r13, THREAD_NORMSAVE(2)(r10); \
53 mfcr r13; /* save CR in r13 for now */\
54 mfspr r11, SPRN_SRR1; \
55 DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \
56 andi. r11, r11, MSR_PR; /* check whether user or kernel */\
57 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL); \
61 BOOKE_CLEAR_BTB(r11) \
62 /* if from user, start at top of this thread's kernel stack */ \
63 lwz r11, TASK_STACK - THREAD(r10); \
64 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \
65 1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \
66 stw r13, _CCR(r11); /* save various registers */ \
69 mfspr r13, SPRN_SPRG_RSCRATCH0; \
70 stw r13, GPR10(r11); \
71 lwz r12, THREAD_NORMSAVE(0)(r10); \
73 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
76 mfspr r12,SPRN_SRR0; \
81 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
82 COMMON_EXCEPTION_PROLOG_END trapno
84 .macro COMMON_EXCEPTION_PROLOG_END trapno
86 lis r10, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
87 addi r10, r10, STACK_FRAME_REGS_MARKER@l
88 stw r10, STACK_INT_FRAME_MARKER(r1)
97 mfspr r2,SPRN_SPRG_THREAD
103 addi r3,r1,STACK_INT_FRAME_REGS
106 .macro prepare_transfer_to_handler
107 #ifdef CONFIG_PPC_E500
110 bl prepare_transfer_to_handler
115 .macro SYSCALL_ENTRY trapno intno srr1
116 mfspr r10, SPRN_SPRG_THREAD
117 #ifdef CONFIG_KVM_BOOKE_HV
119 mtspr SPRN_SPRG_WSCRATCH0, r10
120 stw r11, THREAD_NORMSAVE(0)(r10)
121 stw r13, THREAD_NORMSAVE(2)(r10)
122 mfcr r13 /* save CR in r13 for now */
124 mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */
126 b kvmppc_handler_\intno\()_\srr1
129 lwz r13, THREAD_NORMSAVE(2)(r10)
132 ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
139 lwz r1, TASK_STACK - THREAD(r10)
140 rlwinm r12,r12,0,4,2 /* Clear SO bit in CR */
141 ALLOC_STACK_FRAME(r1, THREAD_SIZE - INT_FRAME_SIZE)
145 b transfer_to_syscall /* jump to handler */
148 /* To handle the additional exception priority levels on 40x and Book-E
149 * processors we allocate a stack per additional priority level.
151 * On 40x critical is the only additional level
152 * On 44x/e500 we have critical and machine check
154 * Additionally we reserve a SPRG for each priority level so we can free up a
155 * GPR to use as the base for indirect access to the exception stacks. This
156 * is necessary since the MMU is always on, for Book-E parts, and the stacks
157 * are offset from KERNELBASE.
159 * There is some space optimization to be had here if desired. However
160 * to allow for a common kernel with support for debug exceptions either
161 * going to critical or their own debug level we aren't currently
162 * providing configurations that micro-optimize space usage.
165 #define MC_STACK_BASE mcheckirq_ctx
166 #define CRIT_STACK_BASE critirq_ctx
169 #define DBG_STACK_BASE dbgirq_ctx
172 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
175 addis r8,r8,level##_STACK_BASE@ha; \
176 lwz r8,level##_STACK_BASE@l(r8); \
177 addi r8,r8,THREAD_SIZE - INT_FRAME_SIZE;
179 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
180 lis r8,level##_STACK_BASE@ha; \
181 lwz r8,level##_STACK_BASE@l(r8); \
182 addi r8,r8,THREAD_SIZE - INT_FRAME_SIZE;
186 * Exception prolog for critical/machine check exceptions. This is a
187 * little different from the normal exception prolog above since a
188 * critical/machine check exception can potentially occur at any point
189 * during normal exception processing. Thus we cannot use the same SPRG
190 * registers as the normal prolog above. Instead we use a portion of the
191 * critical/machine check exception stack at low physical addresses.
193 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, trapno, intno, exc_level_srr0, exc_level_srr1) \
194 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \
195 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
196 stw r9,GPR9(r8); /* save various registers */\
197 mfcr r9; /* save CR in r9 for now */\
200 stw r9,_CCR(r8); /* save CR on stack */\
201 mfspr r11,exc_level_srr1; /* check whether user or kernel */\
202 DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \
203 BOOKE_CLEAR_BTB(r10) \
204 andi. r11,r11,MSR_PR; \
205 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
207 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
208 lwz r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\
209 addi r11,r11,THREAD_SIZE - INT_FRAME_SIZE; /* allocate stack frame */\
211 /* COMING FROM USER MODE */ \
212 stw r9,_CCR(r11); /* save CR */\
213 lwz r10,GPR10(r8); /* copy regs from exception stack */\
215 stw r10,GPR10(r11); \
218 stw r10,GPR11(r11); \
220 /* COMING FROM PRIV MODE */ \
222 2: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \
223 stw r12,GPR12(r11); /* save various registers */\
225 stw r10,_LINK(r11); \
226 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
227 stw r12,_DEAR(r11); /* since they may have had stuff */\
228 mfspr r9,SPRN_ESR; /* in them at the point where the */\
229 stw r9,_ESR(r11); /* exception was taken */\
230 mfspr r12,exc_level_srr0; \
232 mfspr r9,exc_level_srr1; \
235 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
236 COMMON_EXCEPTION_PROLOG_END trapno
238 #define SAVE_xSRR(xSRR) \
239 mfspr r0,SPRN_##xSRR##0; \
240 stw r0,_##xSRR##0(r1); \
241 mfspr r0,SPRN_##xSRR##1; \
242 stw r0,_##xSRR##1(r1)
246 #ifdef CONFIG_PPC_E500
257 #ifdef CONFIG_PHYS_64BIT
260 #endif /* CONFIG_PHYS_64BIT */
261 #endif /* CONFIG_PPC_E500 */
268 #define CRITICAL_EXCEPTION_PROLOG(trapno, intno) \
269 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, trapno+2, intno, SPRN_CSRR0, SPRN_CSRR1)
270 #define DEBUG_EXCEPTION_PROLOG(trapno) \
271 EXC_LEVEL_EXCEPTION_PROLOG(DBG, trapno+8, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
272 #define MCHECK_EXCEPTION_PROLOG(trapno) \
273 EXC_LEVEL_EXCEPTION_PROLOG(MC, trapno+4, MACHINE_CHECK, \
274 SPRN_MCSRR0, SPRN_MCSRR1)
277 * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
278 * being delivered to the host. This exception can only happen
279 * inside a KVM guest -- so we just handle up to the DO_KVM rather
280 * than try to fit this into one of the existing prolog macros.
282 #define GUEST_DOORBELL_EXCEPTION \
283 START_EXCEPTION(GuestDoorbell); \
284 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
285 mfspr r10, SPRN_SPRG_THREAD; \
286 stw r11, THREAD_NORMSAVE(0)(r10); \
287 mfspr r11, SPRN_SRR1; \
288 stw r13, THREAD_NORMSAVE(2)(r10); \
289 mfcr r13; /* save CR in r13 for now */\
290 DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \
296 #define START_EXCEPTION(label) \
300 #define EXCEPTION(n, intno, label, hdlr) \
301 START_EXCEPTION(label); \
302 NORMAL_EXCEPTION_PROLOG(n, intno); \
303 prepare_transfer_to_handler; \
307 #define CRITICAL_EXCEPTION(n, intno, label, hdlr) \
308 START_EXCEPTION(label); \
309 CRITICAL_EXCEPTION_PROLOG(n, intno); \
312 prepare_transfer_to_handler; \
316 #define MCHECK_EXCEPTION(n, label, hdlr) \
317 START_EXCEPTION(label); \
318 MCHECK_EXCEPTION_PROLOG(n); \
325 prepare_transfer_to_handler; \
327 b ret_from_mcheck_exc
329 /* Check for a single step debug exception while in an exception
330 * handler before state has been saved. This is to catch the case
331 * where an instruction that we are trying to single step causes
332 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
333 * the exception handler generates a single step debug exception.
335 * If we get a debug trap on the first instruction of an exception handler,
336 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
337 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
338 * The exception handler was handling a non-critical interrupt, so it will
339 * save (and later restore) the MSR via SPRN_CSRR1, which will still have
340 * the MSR_DE bit set.
342 #define DEBUG_DEBUG_EXCEPTION \
343 START_EXCEPTION(DebugDebug); \
344 DEBUG_EXCEPTION_PROLOG(2000); \
347 * If there is a single step or branch-taken exception in an \
348 * exception entry sequence, it was probably meant to apply to \
349 * the code where the exception occurred (since exception entry \
350 * doesn't turn off DE automatically). We simulate the effect \
351 * of turning off DE on entry to an exception handler by turning \
352 * off DE in the DSRR1 value and clearing the debug status. \
354 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
355 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
358 lis r10,interrupt_base@h; /* check if exception in vectors */ \
359 ori r10,r10,interrupt_base@l; \
361 blt+ 2f; /* addr below exception vectors */ \
363 lis r10,interrupt_end@h; \
364 ori r10,r10,interrupt_end@l; \
366 bgt+ 2f; /* addr above exception vectors */ \
368 /* here it looks like we got an inappropriate debug exception. */ \
369 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
370 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
371 mtspr SPRN_DBSR,r10; \
372 /* restore state and get out */ \
377 mtspr SPRN_DSRR0,r12; \
378 mtspr SPRN_DSRR1,r9; \
380 lwz r12,GPR12(r11); \
381 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \
382 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
385 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \
390 /* continue normal handling for a debug exception... */ \
391 2: mfspr r4,SPRN_DBSR; \
392 stw r4,_ESR(r11); /* DebugException takes DBSR in _ESR */\
396 prepare_transfer_to_handler; \
400 #define DEBUG_CRIT_EXCEPTION \
401 START_EXCEPTION(DebugCrit); \
402 CRITICAL_EXCEPTION_PROLOG(2000,DEBUG); \
405 * If there is a single step or branch-taken exception in an \
406 * exception entry sequence, it was probably meant to apply to \
407 * the code where the exception occurred (since exception entry \
408 * doesn't turn off DE automatically). We simulate the effect \
409 * of turning off DE on entry to an exception handler by turning \
410 * off DE in the CSRR1 value and clearing the debug status. \
412 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
413 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
416 lis r10,interrupt_base@h; /* check if exception in vectors */ \
417 ori r10,r10,interrupt_base@l; \
419 blt+ 2f; /* addr below exception vectors */ \
421 lis r10,interrupt_end@h; \
422 ori r10,r10,interrupt_end@l; \
424 bgt+ 2f; /* addr above exception vectors */ \
426 /* here it looks like we got an inappropriate debug exception. */ \
427 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
428 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
429 mtspr SPRN_DBSR,r10; \
430 /* restore state and get out */ \
435 mtspr SPRN_CSRR0,r12; \
436 mtspr SPRN_CSRR1,r9; \
438 lwz r12,GPR12(r11); \
439 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \
440 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
443 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \
448 /* continue normal handling for a critical exception... */ \
449 2: mfspr r4,SPRN_DBSR; \
450 stw r4,_ESR(r11); /* DebugException takes DBSR in _ESR */\
453 prepare_transfer_to_handler; \
457 #define DATA_STORAGE_EXCEPTION \
458 START_EXCEPTION(DataStorage) \
459 NORMAL_EXCEPTION_PROLOG(0x300, DATA_STORAGE); \
460 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
462 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \
463 stw r4, _DEAR(r11); \
464 prepare_transfer_to_handler; \
469 * Instruction TLB Error interrupt handlers may call InstructionStorage
470 * directly without clearing ESR, so the ESR at this point may be left over
471 * from a prior interrupt.
473 * In any case, do_page_fault for BOOK3E does not use ESR and always expects
474 * dsisr to be 0. ESR_DST from a prior store in particular would confuse fault
477 #define INSTRUCTION_STORAGE_EXCEPTION \
478 START_EXCEPTION(InstructionStorage) \
479 NORMAL_EXCEPTION_PROLOG(0x400, INST_STORAGE); \
480 li r5,0; /* Store 0 in regs->esr (dsisr) */ \
482 stw r12, _DEAR(r11); /* Set regs->dear (dar) to SRR0 */ \
483 prepare_transfer_to_handler; \
487 #define ALIGNMENT_EXCEPTION \
488 START_EXCEPTION(Alignment) \
489 NORMAL_EXCEPTION_PROLOG(0x600, ALIGNMENT); \
490 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
492 prepare_transfer_to_handler; \
493 bl alignment_exception; \
497 #define PROGRAM_EXCEPTION \
498 START_EXCEPTION(Program) \
499 NORMAL_EXCEPTION_PROLOG(0x700, PROGRAM); \
500 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
502 prepare_transfer_to_handler; \
503 bl program_check_exception; \
507 #define DECREMENTER_EXCEPTION \
508 START_EXCEPTION(Decrementer) \
509 NORMAL_EXCEPTION_PROLOG(0x900, DECREMENTER); \
510 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
511 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
512 prepare_transfer_to_handler; \
513 bl timer_interrupt; \
516 #define FP_UNAVAILABLE_EXCEPTION \
517 START_EXCEPTION(FloatingPointUnavailable) \
518 NORMAL_EXCEPTION_PROLOG(0x800, FP_UNAVAIL); \
520 bl load_up_fpu; /* if from user, just load it up */ \
521 b fast_exception_return; \
522 1: prepare_transfer_to_handler; \
523 bl kernel_fp_unavailable_exception; \
526 #endif /* __ASSEMBLY__ */
527 #endif /* __HEAD_BOOKE_H__ */