arch/powerpc/kernel/head_booke.h

   1 #ifndef __HEAD_BOOKE_H__
   2 #define __HEAD_BOOKE_H__
   3
   4 #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
   5 #include <asm/kvm_asm.h>
   6 #include <asm/kvm_booke_hv_asm.h>
   7
   8 /*
   9  * Macros used for common Book-e exception handling
  10  */
  11
  12 #define SET_IVOR(vector_number, vector_label)           \
  13                 li      r26,vector_label@l;             \
  14                 mtspr   SPRN_IVOR##vector_number,r26;   \
  15                 sync
  16
  17 #if (THREAD_SHIFT < 15)
  18 #define ALLOC_STACK_FRAME(reg, val)                     \
  19         addi reg,reg,val
  20 #else
  21 #define ALLOC_STACK_FRAME(reg, val)                     \
  22         addis   reg,reg,val@ha;                         \
  23         addi    reg,reg,val@l
  24 #endif
  25
  26 /*
  27  * Macro used to get to thread save registers.
  28  * Note that entries 0-3 are used for the prolog code, and the remaining
  29  * entries are available for specific exception use in the event a handler
  30  * requires more than 4 scratch registers.
  31  */
  32 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
  33
  34 #ifdef CONFIG_PPC_FSL_BOOK3E
  35 #define BOOKE_CLEAR_BTB(reg)                                                                    \
  36 START_BTB_FLUSH_SECTION                                                         \
  37         BTB_FLUSH(reg)                                                                  \
  38 END_BTB_FLUSH_SECTION
  39 #else
  40 #define BOOKE_CLEAR_BTB(reg)
  41 #endif
  42
  43
  44 #define NORMAL_EXCEPTION_PROLOG(intno)                                               \
  45         mtspr   SPRN_SPRG_WSCRATCH0, r10;       /* save one register */      \
  46         mfspr   r10, SPRN_SPRG_THREAD;                                       \
  47         stw     r11, THREAD_NORMSAVE(0)(r10);                                \
  48         stw     r13, THREAD_NORMSAVE(2)(r10);                                \
  49         mfcr    r13;                    /* save CR in r13 for now          */\
  50         mfspr   r11, SPRN_SRR1;                                              \
  51         DO_KVM  BOOKE_INTERRUPT_##intno SPRN_SRR1;                           \
  52         andi.   r11, r11, MSR_PR;       /* check whether user or kernel    */\
  53         mr      r11, r1;                                                     \
  54         beq     1f;                                                          \
  55         BOOKE_CLEAR_BTB(r11)                                            \
  56         /* if from user, start at top of this thread's kernel stack */       \
  57         lwz     r11, THREAD_INFO-THREAD(r10);                                \
  58         ALLOC_STACK_FRAME(r11, THREAD_SIZE);                                 \
  59 1 :     subi    r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */     \
  60         stw     r13, _CCR(r11);         /* save various registers */         \
  61         stw     r12,GPR12(r11);                                              \
  62         stw     r9,GPR9(r11);                                                \
  63         mfspr   r13, SPRN_SPRG_RSCRATCH0;                                    \
  64         stw     r13, GPR10(r11);                                             \
  65         lwz     r12, THREAD_NORMSAVE(0)(r10);                                \
  66         stw     r12,GPR11(r11);                                              \
  67         lwz     r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */              \
  68         mflr    r10;                                                         \
  69         stw     r10,_LINK(r11);                                              \
  70         mfspr   r12,SPRN_SRR0;                                               \
  71         stw     r1, GPR1(r11);                                               \
  72         mfspr   r9,SPRN_SRR1;                                                \
  73         stw     r1, 0(r11);                                                  \
  74         mr      r1, r11;                                                     \
  75         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
  76         stw     r0,GPR0(r11);                                                \
  77         lis     r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
  78         addi    r10, r10, STACK_FRAME_REGS_MARKER@l;                         \
  79         stw     r10, 8(r11);                                                 \
  80         SAVE_4GPRS(3, r11);                                                  \
  81         SAVE_2GPRS(7, r11)
  82
  83 /* To handle the additional exception priority levels on 40x and Book-E
  84  * processors we allocate a stack per additional priority level.
  85  *
  86  * On 40x critical is the only additional level
  87  * On 44x/e500 we have critical and machine check
  88  * On e200 we have critical and debug (machine check occurs via critical)
  89  *
  90  * Additionally we reserve a SPRG for each priority level so we can free up a
  91  * GPR to use as the base for indirect access to the exception stacks.  This
  92  * is necessary since the MMU is always on, for Book-E parts, and the stacks
  93  * are offset from KERNELBASE.
  94  *
  95  * There is some space optimization to be had here if desired.  However
  96  * to allow for a common kernel with support for debug exceptions either
  97  * going to critical or their own debug level we aren't currently
  98  * providing configurations that micro-optimize space usage.
  99  */
 100
 101 #define MC_STACK_BASE           mcheckirq_ctx
 102 #define CRIT_STACK_BASE         critirq_ctx
 103
 104 /* only on e500mc/e200 */
 105 #define DBG_STACK_BASE          dbgirq_ctx
 106
 107 #define EXC_LVL_FRAME_OVERHEAD  (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
 108
 109 #ifdef CONFIG_SMP
 110 #define BOOKE_LOAD_EXC_LEVEL_STACK(level)               \
 111         mfspr   r8,SPRN_PIR;                            \
 112         slwi    r8,r8,2;                                \
 113         addis   r8,r8,level##_STACK_BASE@ha;            \
 114         lwz     r8,level##_STACK_BASE@l(r8);            \
 115         addi    r8,r8,EXC_LVL_FRAME_OVERHEAD;
 116 #else
 117 #define BOOKE_LOAD_EXC_LEVEL_STACK(level)               \
 118         lis     r8,level##_STACK_BASE@ha;               \
 119         lwz     r8,level##_STACK_BASE@l(r8);            \
 120         addi    r8,r8,EXC_LVL_FRAME_OVERHEAD;
 121 #endif
 122
 123 /*
 124  * Exception prolog for critical/machine check exceptions.  This is a
 125  * little different from the normal exception prolog above since a
 126  * critical/machine check exception can potentially occur at any point
 127  * during normal exception processing. Thus we cannot use the same SPRG
 128  * registers as the normal prolog above. Instead we use a portion of the
 129  * critical/machine check exception stack at low physical addresses.
 130  */
 131 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, intno, exc_level_srr0, exc_level_srr1) \
 132         mtspr   SPRN_SPRG_WSCRATCH_##exc_level,r8;                           \
 133         BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
 134         stw     r9,GPR9(r8);            /* save various registers          */\
 135         mfcr    r9;                     /* save CR in r9 for now           */\
 136         stw     r10,GPR10(r8);                                               \
 137         stw     r11,GPR11(r8);                                               \
 138         stw     r9,_CCR(r8);            /* save CR on stack                */\
 139         mfspr   r11,exc_level_srr1;     /* check whether user or kernel    */\
 140         DO_KVM  BOOKE_INTERRUPT_##intno exc_level_srr1;                      \
 141         BOOKE_CLEAR_BTB(r10)                                            \
 142         andi.   r11,r11,MSR_PR;                                              \
 143         mfspr   r11,SPRN_SPRG_THREAD;   /* if from user, start at top of   */\
 144         lwz     r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
 145         addi    r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame    */\
 146         beq     1f;                                                          \
 147         /* COMING FROM USER MODE */                                          \
 148         stw     r9,_CCR(r11);           /* save CR                         */\
 149         lwz     r10,GPR10(r8);          /* copy regs from exception stack  */\
 150         lwz     r9,GPR9(r8);                                                 \
 151         stw     r10,GPR10(r11);                                              \
 152         lwz     r10,GPR11(r8);                                               \
 153         stw     r9,GPR9(r11);                                                \
 154         stw     r10,GPR11(r11);                                              \
 155         b       2f;                                                          \
 156         /* COMING FROM PRIV MODE */                                          \
 157 1:      lwz     r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11);                     \
 158         lwz     r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11);                  \
 159         stw     r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8);                      \
 160         stw     r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8);                   \
 161         lwz     r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11);                      \
 162         stw     r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8);                       \
 163         mr      r11,r8;                                                      \
 164 2:      mfspr   r8,SPRN_SPRG_RSCRATCH_##exc_level;                           \
 165         stw     r12,GPR12(r11);         /* save various registers          */\
 166         mflr    r10;                                                         \
 167         stw     r10,_LINK(r11);                                              \
 168         mfspr   r12,SPRN_DEAR;          /* save DEAR and ESR in the frame  */\
 169         stw     r12,_DEAR(r11);         /* since they may have had stuff   */\
 170         mfspr   r9,SPRN_ESR;            /* in them at the point where the  */\
 171         stw     r9,_ESR(r11);           /* exception was taken             */\
 172         mfspr   r12,exc_level_srr0;                                          \
 173         stw     r1,GPR1(r11);                                                \
 174         mfspr   r9,exc_level_srr1;                                           \
 175         stw     r1,0(r11);                                                   \
 176         mr      r1,r11;                                                      \
 177         rlwinm  r9,r9,0,14,12;          /* clear MSR_WE (necessary?)       */\
 178         stw     r0,GPR0(r11);                                                \
 179         SAVE_4GPRS(3, r11);                                                  \
 180         SAVE_2GPRS(7, r11)
 181
 182 #define CRITICAL_EXCEPTION_PROLOG(intno) \
 183                 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1)
 184 #define DEBUG_EXCEPTION_PROLOG \
 185                 EXC_LEVEL_EXCEPTION_PROLOG(DBG, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
 186 #define MCHECK_EXCEPTION_PROLOG \
 187                 EXC_LEVEL_EXCEPTION_PROLOG(MC, MACHINE_CHECK, \
 188                         SPRN_MCSRR0, SPRN_MCSRR1)
 189
 190 /*
 191  * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
 192  * being delivered to the host.  This exception can only happen
 193  * inside a KVM guest -- so we just handle up to the DO_KVM rather
 194  * than try to fit this into one of the existing prolog macros.
 195  */
 196 #define GUEST_DOORBELL_EXCEPTION \
 197         START_EXCEPTION(GuestDoorbell);                                      \
 198         mtspr   SPRN_SPRG_WSCRATCH0, r10;       /* save one register */      \
 199         mfspr   r10, SPRN_SPRG_THREAD;                                       \
 200         stw     r11, THREAD_NORMSAVE(0)(r10);                                \
 201         mfspr   r11, SPRN_SRR1;                                              \
 202         stw     r13, THREAD_NORMSAVE(2)(r10);                                \
 203         mfcr    r13;                    /* save CR in r13 for now          */\
 204         DO_KVM  BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1;                      \
 205         trap
 206
 207 /*
 208  * Exception vectors.
 209  */
 210 #define START_EXCEPTION(label)                                               \
 211         .align 5;                                                            \
 212 label:
 213
 214 #define EXCEPTION(n, intno, label, hdlr, xfer)                  \
 215         START_EXCEPTION(label);                                 \
 216         NORMAL_EXCEPTION_PROLOG(intno);                         \
 217         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 218         xfer(n, hdlr)
 219
 220 #define CRITICAL_EXCEPTION(n, intno, label, hdlr)                       \
 221         START_EXCEPTION(label);                                         \
 222         CRITICAL_EXCEPTION_PROLOG(intno);                               \
 223         addi    r3,r1,STACK_FRAME_OVERHEAD;                             \
 224         EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 225                           NOCOPY, crit_transfer_to_handler, \
 226                           ret_from_crit_exc)
 227
 228 #define MCHECK_EXCEPTION(n, label, hdlr)                        \
 229         START_EXCEPTION(label);                                 \
 230         MCHECK_EXCEPTION_PROLOG;                                \
 231         mfspr   r5,SPRN_ESR;                                    \
 232         stw     r5,_ESR(r11);                                   \
 233         addi    r3,r1,STACK_FRAME_OVERHEAD;                     \
 234         EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
 235                           NOCOPY, mcheck_transfer_to_handler,   \
 236                           ret_from_mcheck_exc)
 237
 238 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret)   \
 239         li      r10,trap;                                       \
 240         stw     r10,_TRAP(r11);                                 \
 241         lis     r10,msr@h;                                      \
 242         ori     r10,r10,msr@l;                                  \
 243         copyee(r10, r9);                                        \
 244         bl      tfer;                                           \
 245         .long   hdlr;                                           \
 246         .long   ret
 247
 248 #define COPY_EE(d, s)           rlwimi d,s,0,16,16
 249 #define NOCOPY(d, s)
 250
 251 #define EXC_XFER_STD(n, hdlr)           \
 252         EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
 253                           ret_from_except_full)
 254
 255 #define EXC_XFER_LITE(n, hdlr)          \
 256         EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
 257                           ret_from_except)
 258
 259 #define EXC_XFER_EE(n, hdlr)            \
 260         EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
 261                           ret_from_except_full)
 262
 263 #define EXC_XFER_EE_LITE(n, hdlr)       \
 264         EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
 265                           ret_from_except)
 266
 267 /* Check for a single step debug exception while in an exception
 268  * handler before state has been saved.  This is to catch the case
 269  * where an instruction that we are trying to single step causes
 270  * an exception (eg ITLB/DTLB miss) and thus the first instruction of
 271  * the exception handler generates a single step debug exception.
 272  *
 273  * If we get a debug trap on the first instruction of an exception handler,
 274  * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
 275  * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
 276  * The exception handler was handling a non-critical interrupt, so it will
 277  * save (and later restore) the MSR via SPRN_CSRR1, which will still have
 278  * the MSR_DE bit set.
 279  */
 280 #define DEBUG_DEBUG_EXCEPTION                                                 \
 281         START_EXCEPTION(DebugDebug);                                          \
 282         DEBUG_EXCEPTION_PROLOG;                                               \
 283                                                                               \
 284         /*                                                                    \
 285          * If there is a single step or branch-taken exception in an          \
 286          * exception entry sequence, it was probably meant to apply to        \
 287          * the code where the exception occurred (since exception entry       \
 288          * doesn't turn off DE automatically).  We simulate the effect        \
 289          * of turning off DE on entry to an exception handler by turning      \
 290          * off DE in the DSRR1 value and clearing the debug status.           \
 291          */                                                                   \
 292         mfspr   r10,SPRN_DBSR;          /* check single-step/branch taken */  \
 293         andis.  r10,r10,(DBSR_IC|DBSR_BT)@h;                                  \
 294         beq+    2f;                                                           \
 295                                                                               \
 296         lis     r10,interrupt_base@h;   /* check if exception in vectors */   \
 297         ori     r10,r10,interrupt_base@l;                                     \
 298         cmplw   r12,r10;                                                      \
 299         blt+    2f;                     /* addr below exception vectors */    \
 300                                                                               \
 301         lis     r10,interrupt_end@h;                                          \
 302         ori     r10,r10,interrupt_end@l;                                      \
 303         cmplw   r12,r10;                                                      \
 304         bgt+    2f;                     /* addr above exception vectors */    \
 305                                                                               \
 306         /* here it looks like we got an inappropriate debug exception. */     \
 307 1:      rlwinm  r9,r9,0,~MSR_DE;        /* clear DE in the CDRR1 value */     \
 308         lis     r10,(DBSR_IC|DBSR_BT)@h;        /* clear the IC event */      \
 309         mtspr   SPRN_DBSR,r10;                                                \
 310         /* restore state and get out */                                       \
 311         lwz     r10,_CCR(r11);                                                \
 312         lwz     r0,GPR0(r11);                                                 \
 313         lwz     r1,GPR1(r11);                                                 \
 314         mtcrf   0x80,r10;                                                     \
 315         mtspr   SPRN_DSRR0,r12;                                               \
 316         mtspr   SPRN_DSRR1,r9;                                                \
 317         lwz     r9,GPR9(r11);                                                 \
 318         lwz     r12,GPR12(r11);                                               \
 319         mtspr   SPRN_SPRG_WSCRATCH_DBG,r8;                                    \
 320         BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
 321         lwz     r10,GPR10(r8);                                                \
 322         lwz     r11,GPR11(r8);                                                \
 323         mfspr   r8,SPRN_SPRG_RSCRATCH_DBG;                                    \
 324                                                                               \
 325         PPC_RFDI;                                                             \
 326         b       .;                                                            \
 327                                                                               \
 328         /* continue normal handling for a debug exception... */               \
 329 2:      mfspr   r4,SPRN_DBSR;                                                 \
 330         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 331         EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
 332
 333 #define DEBUG_CRIT_EXCEPTION                                                  \
 334         START_EXCEPTION(DebugCrit);                                           \
 335         CRITICAL_EXCEPTION_PROLOG(DEBUG);                                     \
 336                                                                               \
 337         /*                                                                    \
 338          * If there is a single step or branch-taken exception in an          \
 339          * exception entry sequence, it was probably meant to apply to        \
 340          * the code where the exception occurred (since exception entry       \
 341          * doesn't turn off DE automatically).  We simulate the effect        \
 342          * of turning off DE on entry to an exception handler by turning      \
 343          * off DE in the CSRR1 value and clearing the debug status.           \
 344          */                                                                   \
 345         mfspr   r10,SPRN_DBSR;          /* check single-step/branch taken */  \
 346         andis.  r10,r10,(DBSR_IC|DBSR_BT)@h;                                  \
 347         beq+    2f;                                                           \
 348                                                                               \
 349         lis     r10,interrupt_base@h;   /* check if exception in vectors */   \
 350         ori     r10,r10,interrupt_base@l;                                     \
 351         cmplw   r12,r10;                                                      \
 352         blt+    2f;                     /* addr below exception vectors */    \
 353                                                                               \
 354         lis     r10,interrupt_end@h;                                          \
 355         ori     r10,r10,interrupt_end@l;                                      \
 356         cmplw   r12,r10;                                                      \
 357         bgt+    2f;                     /* addr above exception vectors */    \
 358                                                                               \
 359         /* here it looks like we got an inappropriate debug exception. */     \
 360 1:      rlwinm  r9,r9,0,~MSR_DE;        /* clear DE in the CSRR1 value */     \
 361         lis     r10,(DBSR_IC|DBSR_BT)@h;        /* clear the IC event */      \
 362         mtspr   SPRN_DBSR,r10;                                                \
 363         /* restore state and get out */                                       \
 364         lwz     r10,_CCR(r11);                                                \
 365         lwz     r0,GPR0(r11);                                                 \
 366         lwz     r1,GPR1(r11);                                                 \
 367         mtcrf   0x80,r10;                                                     \
 368         mtspr   SPRN_CSRR0,r12;                                               \
 369         mtspr   SPRN_CSRR1,r9;                                                \
 370         lwz     r9,GPR9(r11);                                                 \
 371         lwz     r12,GPR12(r11);                                               \
 372         mtspr   SPRN_SPRG_WSCRATCH_CRIT,r8;                                   \
 373         BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */  \
 374         lwz     r10,GPR10(r8);                                                \
 375         lwz     r11,GPR11(r8);                                                \
 376         mfspr   r8,SPRN_SPRG_RSCRATCH_CRIT;                                   \
 377                                                                               \
 378         rfci;                                                                 \
 379         b       .;                                                            \
 380                                                                               \
 381         /* continue normal handling for a critical exception... */            \
 382 2:      mfspr   r4,SPRN_DBSR;                                                 \
 383         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 384         EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
 385
 386 #define DATA_STORAGE_EXCEPTION                                                \
 387         START_EXCEPTION(DataStorage)                                          \
 388         NORMAL_EXCEPTION_PROLOG(DATA_STORAGE);                \
 389         mfspr   r5,SPRN_ESR;            /* Grab the ESR and save it */        \
 390         stw     r5,_ESR(r11);                                                 \
 391         mfspr   r4,SPRN_DEAR;           /* Grab the DEAR */                   \
 392         EXC_XFER_LITE(0x0300, handle_page_fault)
 393
 394 #define INSTRUCTION_STORAGE_EXCEPTION                                         \
 395         START_EXCEPTION(InstructionStorage)                                   \
 396         NORMAL_EXCEPTION_PROLOG(INST_STORAGE);                \
 397         mfspr   r5,SPRN_ESR;            /* Grab the ESR and save it */        \
 398         stw     r5,_ESR(r11);                                                 \
 399         mr      r4,r12;                 /* Pass SRR0 as arg2 */               \
 400         li      r5,0;                   /* Pass zero as arg3 */               \
 401         EXC_XFER_LITE(0x0400, handle_page_fault)
 402
 403 #define ALIGNMENT_EXCEPTION                                                   \
 404         START_EXCEPTION(Alignment)                                            \
 405         NORMAL_EXCEPTION_PROLOG(ALIGNMENT);                   \
 406         mfspr   r4,SPRN_DEAR;           /* Grab the DEAR and save it */       \
 407         stw     r4,_DEAR(r11);                                                \
 408         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 409         EXC_XFER_EE(0x0600, alignment_exception)
 410
 411 #define PROGRAM_EXCEPTION                                                     \
 412         START_EXCEPTION(Program)                                              \
 413         NORMAL_EXCEPTION_PROLOG(PROGRAM);                     \
 414         mfspr   r4,SPRN_ESR;            /* Grab the ESR and save it */        \
 415         stw     r4,_ESR(r11);                                                 \
 416         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 417         EXC_XFER_STD(0x0700, program_check_exception)
 418
 419 #define DECREMENTER_EXCEPTION                                                 \
 420         START_EXCEPTION(Decrementer)                                          \
 421         NORMAL_EXCEPTION_PROLOG(DECREMENTER);                 \
 422         lis     r0,TSR_DIS@h;           /* Setup the DEC interrupt mask */    \
 423         mtspr   SPRN_TSR,r0;            /* Clear the DEC interrupt */         \
 424         addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 425         EXC_XFER_LITE(0x0900, timer_interrupt)
 426
 427 #define FP_UNAVAILABLE_EXCEPTION                                              \
 428         START_EXCEPTION(FloatingPointUnavailable)                             \
 429         NORMAL_EXCEPTION_PROLOG(FP_UNAVAIL);                  \
 430         beq     1f;                                                           \
 431         bl      load_up_fpu;            /* if from user, just load it up */   \
 432         b       fast_exception_return;                                        \
 433 1:      addi    r3,r1,STACK_FRAME_OVERHEAD;                                   \
 434         EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
 435
 436 #ifndef __ASSEMBLY__
 437 struct exception_regs {
 438         unsigned long mas0;
 439         unsigned long mas1;
 440         unsigned long mas2;
 441         unsigned long mas3;
 442         unsigned long mas6;
 443         unsigned long mas7;
 444         unsigned long srr0;
 445         unsigned long srr1;
 446         unsigned long csrr0;
 447         unsigned long csrr1;
 448         unsigned long dsrr0;
 449         unsigned long dsrr1;
 450         unsigned long saved_ksp_limit;
 451 };
 452
 453 /* ensure this structure is always sized to a multiple of the stack alignment */
 454 #define STACK_EXC_LVL_FRAME_SIZE        _ALIGN_UP(sizeof (struct exception_regs), 16)
 455
 456 #endif /* __ASSEMBLY__ */
 457 #endif /* __HEAD_BOOKE_H__ */