1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __HEAD_BOOKE_H__
3 #define __HEAD_BOOKE_H__
5 #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
6 #include <asm/kvm_asm.h>
7 #include <asm/kvm_booke_hv_asm.h>
10 * Macros used for common Book-e exception handling
13 #define SET_IVOR(vector_number, vector_label) \
14 li r26,vector_label@l; \
15 mtspr SPRN_IVOR##vector_number,r26; \
18 #if (THREAD_SHIFT < 15)
19 #define ALLOC_STACK_FRAME(reg, val) \
22 #define ALLOC_STACK_FRAME(reg, val) \
23 addis reg,reg,val@ha; \
28 * Macro used to get to thread save registers.
29 * Note that entries 0-3 are used for the prolog code, and the remaining
30 * entries are available for specific exception use in the event a handler
31 * requires more than 4 scratch registers.
33 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
35 #ifdef CONFIG_PPC_FSL_BOOK3E
36 #define BOOKE_CLEAR_BTB(reg) \
37 START_BTB_FLUSH_SECTION \
41 #define BOOKE_CLEAR_BTB(reg)
45 #define NORMAL_EXCEPTION_PROLOG(intno) \
46 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
47 mfspr r10, SPRN_SPRG_THREAD; \
48 stw r11, THREAD_NORMSAVE(0)(r10); \
49 stw r13, THREAD_NORMSAVE(2)(r10); \
50 mfcr r13; /* save CR in r13 for now */\
51 mfspr r11, SPRN_SRR1; \
52 DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \
53 andi. r11, r11, MSR_PR; /* check whether user or kernel */\
56 BOOKE_CLEAR_BTB(r11) \
57 /* if from user, start at top of this thread's kernel stack */ \
58 lwz r11, THREAD_INFO-THREAD(r10); \
59 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \
60 1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \
61 stw r13, _CCR(r11); /* save various registers */ \
64 mfspr r13, SPRN_SPRG_RSCRATCH0; \
65 stw r13, GPR10(r11); \
66 lwz r12, THREAD_NORMSAVE(0)(r10); \
68 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
71 mfspr r12,SPRN_SRR0; \
76 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
78 lis r10, STACK_FRAME_REGS_MARKER@ha;/* exception frame marker */ \
79 addi r10, r10, STACK_FRAME_REGS_MARKER@l; \
84 /* To handle the additional exception priority levels on 40x and Book-E
85 * processors we allocate a stack per additional priority level.
87 * On 40x critical is the only additional level
88 * On 44x/e500 we have critical and machine check
89 * On e200 we have critical and debug (machine check occurs via critical)
91 * Additionally we reserve a SPRG for each priority level so we can free up a
92 * GPR to use as the base for indirect access to the exception stacks. This
93 * is necessary since the MMU is always on, for Book-E parts, and the stacks
94 * are offset from KERNELBASE.
96 * There is some space optimization to be had here if desired. However
97 * to allow for a common kernel with support for debug exceptions either
98 * going to critical or their own debug level we aren't currently
99 * providing configurations that micro-optimize space usage.
102 #define MC_STACK_BASE mcheckirq_ctx
103 #define CRIT_STACK_BASE critirq_ctx
105 /* only on e500mc/e200 */
106 #define DBG_STACK_BASE dbgirq_ctx
108 #define EXC_LVL_FRAME_OVERHEAD (THREAD_SIZE - INT_FRAME_SIZE - EXC_LVL_SIZE)
111 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
114 addis r8,r8,level##_STACK_BASE@ha; \
115 lwz r8,level##_STACK_BASE@l(r8); \
116 addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
118 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
119 lis r8,level##_STACK_BASE@ha; \
120 lwz r8,level##_STACK_BASE@l(r8); \
121 addi r8,r8,EXC_LVL_FRAME_OVERHEAD;
125 * Exception prolog for critical/machine check exceptions. This is a
126 * little different from the normal exception prolog above since a
127 * critical/machine check exception can potentially occur at any point
128 * during normal exception processing. Thus we cannot use the same SPRG
129 * registers as the normal prolog above. Instead we use a portion of the
130 * critical/machine check exception stack at low physical addresses.
132 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, intno, exc_level_srr0, exc_level_srr1) \
133 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \
134 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
135 stw r9,GPR9(r8); /* save various registers */\
136 mfcr r9; /* save CR in r9 for now */\
139 stw r9,_CCR(r8); /* save CR on stack */\
140 mfspr r11,exc_level_srr1; /* check whether user or kernel */\
141 DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \
142 BOOKE_CLEAR_BTB(r10) \
143 andi. r11,r11,MSR_PR; \
144 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
145 lwz r11,THREAD_INFO-THREAD(r11); /* this thread's kernel stack */\
146 addi r11,r11,EXC_LVL_FRAME_OVERHEAD; /* allocate stack frame */\
148 /* COMING FROM USER MODE */ \
149 stw r9,_CCR(r11); /* save CR */\
150 lwz r10,GPR10(r8); /* copy regs from exception stack */\
152 stw r10,GPR10(r11); \
155 stw r10,GPR11(r11); \
157 /* COMING FROM PRIV MODE */ \
158 1: lwz r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r11); \
159 lwz r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r11); \
160 stw r9,TI_FLAGS-EXC_LVL_FRAME_OVERHEAD(r8); \
161 stw r10,TI_PREEMPT-EXC_LVL_FRAME_OVERHEAD(r8); \
162 lwz r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r11); \
163 stw r9,TI_TASK-EXC_LVL_FRAME_OVERHEAD(r8); \
165 2: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \
166 stw r12,GPR12(r11); /* save various registers */\
168 stw r10,_LINK(r11); \
169 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
170 stw r12,_DEAR(r11); /* since they may have had stuff */\
171 mfspr r9,SPRN_ESR; /* in them at the point where the */\
172 stw r9,_ESR(r11); /* exception was taken */\
173 mfspr r12,exc_level_srr0; \
175 mfspr r9,exc_level_srr1; \
178 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
180 SAVE_4GPRS(3, r11); \
183 #define CRITICAL_EXCEPTION_PROLOG(intno) \
184 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, intno, SPRN_CSRR0, SPRN_CSRR1)
185 #define DEBUG_EXCEPTION_PROLOG \
186 EXC_LEVEL_EXCEPTION_PROLOG(DBG, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
187 #define MCHECK_EXCEPTION_PROLOG \
188 EXC_LEVEL_EXCEPTION_PROLOG(MC, MACHINE_CHECK, \
189 SPRN_MCSRR0, SPRN_MCSRR1)
192 * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
193 * being delivered to the host. This exception can only happen
194 * inside a KVM guest -- so we just handle up to the DO_KVM rather
195 * than try to fit this into one of the existing prolog macros.
197 #define GUEST_DOORBELL_EXCEPTION \
198 START_EXCEPTION(GuestDoorbell); \
199 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
200 mfspr r10, SPRN_SPRG_THREAD; \
201 stw r11, THREAD_NORMSAVE(0)(r10); \
202 mfspr r11, SPRN_SRR1; \
203 stw r13, THREAD_NORMSAVE(2)(r10); \
204 mfcr r13; /* save CR in r13 for now */\
205 DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \
211 #define START_EXCEPTION(label) \
215 #define EXCEPTION(n, intno, label, hdlr, xfer) \
216 START_EXCEPTION(label); \
217 NORMAL_EXCEPTION_PROLOG(intno); \
218 addi r3,r1,STACK_FRAME_OVERHEAD; \
221 #define CRITICAL_EXCEPTION(n, intno, label, hdlr) \
222 START_EXCEPTION(label); \
223 CRITICAL_EXCEPTION_PROLOG(intno); \
224 addi r3,r1,STACK_FRAME_OVERHEAD; \
225 EXC_XFER_TEMPLATE(hdlr, n+2, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
226 NOCOPY, crit_transfer_to_handler, \
229 #define MCHECK_EXCEPTION(n, label, hdlr) \
230 START_EXCEPTION(label); \
231 MCHECK_EXCEPTION_PROLOG; \
234 addi r3,r1,STACK_FRAME_OVERHEAD; \
235 EXC_XFER_TEMPLATE(hdlr, n+4, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), \
236 NOCOPY, mcheck_transfer_to_handler, \
239 #define EXC_XFER_TEMPLATE(hdlr, trap, msr, copyee, tfer, ret) \
241 stw r10,_TRAP(r11); \
249 #define COPY_EE(d, s) rlwimi d,s,0,16,16
252 #define EXC_XFER_STD(n, hdlr) \
253 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, NOCOPY, transfer_to_handler_full, \
254 ret_from_except_full)
256 #define EXC_XFER_LITE(n, hdlr) \
257 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, NOCOPY, transfer_to_handler, \
260 #define EXC_XFER_EE(n, hdlr) \
261 EXC_XFER_TEMPLATE(hdlr, n, MSR_KERNEL, COPY_EE, transfer_to_handler_full, \
262 ret_from_except_full)
264 #define EXC_XFER_EE_LITE(n, hdlr) \
265 EXC_XFER_TEMPLATE(hdlr, n+1, MSR_KERNEL, COPY_EE, transfer_to_handler, \
268 /* Check for a single step debug exception while in an exception
269 * handler before state has been saved. This is to catch the case
270 * where an instruction that we are trying to single step causes
271 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
272 * the exception handler generates a single step debug exception.
274 * If we get a debug trap on the first instruction of an exception handler,
275 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
276 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
277 * The exception handler was handling a non-critical interrupt, so it will
278 * save (and later restore) the MSR via SPRN_CSRR1, which will still have
279 * the MSR_DE bit set.
281 #define DEBUG_DEBUG_EXCEPTION \
282 START_EXCEPTION(DebugDebug); \
283 DEBUG_EXCEPTION_PROLOG; \
286 * If there is a single step or branch-taken exception in an \
287 * exception entry sequence, it was probably meant to apply to \
288 * the code where the exception occurred (since exception entry \
289 * doesn't turn off DE automatically). We simulate the effect \
290 * of turning off DE on entry to an exception handler by turning \
291 * off DE in the DSRR1 value and clearing the debug status. \
293 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
294 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
297 lis r10,interrupt_base@h; /* check if exception in vectors */ \
298 ori r10,r10,interrupt_base@l; \
300 blt+ 2f; /* addr below exception vectors */ \
302 lis r10,interrupt_end@h; \
303 ori r10,r10,interrupt_end@l; \
305 bgt+ 2f; /* addr above exception vectors */ \
307 /* here it looks like we got an inappropriate debug exception. */ \
308 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
309 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
310 mtspr SPRN_DBSR,r10; \
311 /* restore state and get out */ \
316 mtspr SPRN_DSRR0,r12; \
317 mtspr SPRN_DSRR1,r9; \
319 lwz r12,GPR12(r11); \
320 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \
321 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
324 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \
329 /* continue normal handling for a debug exception... */ \
330 2: mfspr r4,SPRN_DBSR; \
331 addi r3,r1,STACK_FRAME_OVERHEAD; \
332 EXC_XFER_TEMPLATE(DebugException, 0x2008, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, debug_transfer_to_handler, ret_from_debug_exc)
334 #define DEBUG_CRIT_EXCEPTION \
335 START_EXCEPTION(DebugCrit); \
336 CRITICAL_EXCEPTION_PROLOG(DEBUG); \
339 * If there is a single step or branch-taken exception in an \
340 * exception entry sequence, it was probably meant to apply to \
341 * the code where the exception occurred (since exception entry \
342 * doesn't turn off DE automatically). We simulate the effect \
343 * of turning off DE on entry to an exception handler by turning \
344 * off DE in the CSRR1 value and clearing the debug status. \
346 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
347 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
350 lis r10,interrupt_base@h; /* check if exception in vectors */ \
351 ori r10,r10,interrupt_base@l; \
353 blt+ 2f; /* addr below exception vectors */ \
355 lis r10,interrupt_end@h; \
356 ori r10,r10,interrupt_end@l; \
358 bgt+ 2f; /* addr above exception vectors */ \
360 /* here it looks like we got an inappropriate debug exception. */ \
361 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
362 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
363 mtspr SPRN_DBSR,r10; \
364 /* restore state and get out */ \
369 mtspr SPRN_CSRR0,r12; \
370 mtspr SPRN_CSRR1,r9; \
372 lwz r12,GPR12(r11); \
373 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \
374 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
377 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \
382 /* continue normal handling for a critical exception... */ \
383 2: mfspr r4,SPRN_DBSR; \
384 addi r3,r1,STACK_FRAME_OVERHEAD; \
385 EXC_XFER_TEMPLATE(DebugException, 0x2002, (MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)), NOCOPY, crit_transfer_to_handler, ret_from_crit_exc)
387 #define DATA_STORAGE_EXCEPTION \
388 START_EXCEPTION(DataStorage) \
389 NORMAL_EXCEPTION_PROLOG(DATA_STORAGE); \
390 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
392 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \
393 EXC_XFER_LITE(0x0300, handle_page_fault)
395 #define INSTRUCTION_STORAGE_EXCEPTION \
396 START_EXCEPTION(InstructionStorage) \
397 NORMAL_EXCEPTION_PROLOG(INST_STORAGE); \
398 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
400 mr r4,r12; /* Pass SRR0 as arg2 */ \
401 li r5,0; /* Pass zero as arg3 */ \
402 EXC_XFER_LITE(0x0400, handle_page_fault)
404 #define ALIGNMENT_EXCEPTION \
405 START_EXCEPTION(Alignment) \
406 NORMAL_EXCEPTION_PROLOG(ALIGNMENT); \
407 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
409 addi r3,r1,STACK_FRAME_OVERHEAD; \
410 EXC_XFER_EE(0x0600, alignment_exception)
412 #define PROGRAM_EXCEPTION \
413 START_EXCEPTION(Program) \
414 NORMAL_EXCEPTION_PROLOG(PROGRAM); \
415 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
417 addi r3,r1,STACK_FRAME_OVERHEAD; \
418 EXC_XFER_STD(0x0700, program_check_exception)
420 #define DECREMENTER_EXCEPTION \
421 START_EXCEPTION(Decrementer) \
422 NORMAL_EXCEPTION_PROLOG(DECREMENTER); \
423 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
424 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
425 addi r3,r1,STACK_FRAME_OVERHEAD; \
426 EXC_XFER_LITE(0x0900, timer_interrupt)
428 #define FP_UNAVAILABLE_EXCEPTION \
429 START_EXCEPTION(FloatingPointUnavailable) \
430 NORMAL_EXCEPTION_PROLOG(FP_UNAVAIL); \
432 bl load_up_fpu; /* if from user, just load it up */ \
433 b fast_exception_return; \
434 1: addi r3,r1,STACK_FRAME_OVERHEAD; \
435 EXC_XFER_EE_LITE(0x800, kernel_fp_unavailable_exception)
438 struct exception_regs {
451 unsigned long saved_ksp_limit;
454 /* ensure this structure is always sized to a multiple of the stack alignment */
455 #define STACK_EXC_LVL_FRAME_SIZE _ALIGN_UP(sizeof (struct exception_regs), 16)
457 #endif /* __ASSEMBLY__ */
458 #endif /* __HEAD_BOOKE_H__ */