1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __HEAD_BOOKE_H__
3 #define __HEAD_BOOKE_H__
5 #include <asm/ptrace.h> /* for STACK_FRAME_REGS_MARKER */
6 #include <asm/kvm_asm.h>
7 #include <asm/kvm_booke_hv_asm.h>
12 * Macros used for common Book-e exception handling
15 #define SET_IVOR(vector_number, vector_label) \
16 li r26,vector_label@l; \
17 mtspr SPRN_IVOR##vector_number,r26; \
20 #if (THREAD_SHIFT < 15)
21 #define ALLOC_STACK_FRAME(reg, val) \
24 #define ALLOC_STACK_FRAME(reg, val) \
25 addis reg,reg,val@ha; \
30 * Macro used to get to thread save registers.
31 * Note that entries 0-3 are used for the prolog code, and the remaining
32 * entries are available for specific exception use in the event a handler
33 * requires more than 4 scratch registers.
35 #define THREAD_NORMSAVE(offset) (THREAD_NORMSAVES + (offset * 4))
37 #ifdef CONFIG_PPC_E500
38 #define BOOKE_CLEAR_BTB(reg) \
39 START_BTB_FLUSH_SECTION \
43 #define BOOKE_CLEAR_BTB(reg)
47 #define NORMAL_EXCEPTION_PROLOG(trapno, intno) \
48 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
49 mfspr r10, SPRN_SPRG_THREAD; \
50 stw r11, THREAD_NORMSAVE(0)(r10); \
51 stw r13, THREAD_NORMSAVE(2)(r10); \
52 mfcr r13; /* save CR in r13 for now */\
53 mfspr r11, SPRN_SRR1; \
54 DO_KVM BOOKE_INTERRUPT_##intno SPRN_SRR1; \
55 andi. r11, r11, MSR_PR; /* check whether user or kernel */\
56 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL); \
60 BOOKE_CLEAR_BTB(r11) \
61 /* if from user, start at top of this thread's kernel stack */ \
62 lwz r11, TASK_STACK - THREAD(r10); \
63 ALLOC_STACK_FRAME(r11, THREAD_SIZE); \
64 1 : subi r11, r11, INT_FRAME_SIZE; /* Allocate exception frame */ \
65 stw r13, _CCR(r11); /* save various registers */ \
68 mfspr r13, SPRN_SPRG_RSCRATCH0; \
69 stw r13, GPR10(r11); \
70 lwz r12, THREAD_NORMSAVE(0)(r10); \
72 lwz r13, THREAD_NORMSAVE(2)(r10); /* restore r13 */ \
75 mfspr r12,SPRN_SRR0; \
80 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
81 COMMON_EXCEPTION_PROLOG_END trapno
83 .macro COMMON_EXCEPTION_PROLOG_END trapno
85 lis r10, STACK_FRAME_REGS_MARKER@ha /* exception frame marker */
86 addi r10, r10, STACK_FRAME_REGS_MARKER@l
96 mfspr r2,SPRN_SPRG_THREAD
102 addi r3,r1,STACK_FRAME_OVERHEAD
105 .macro prepare_transfer_to_handler
106 #ifdef CONFIG_PPC_E500
109 bl prepare_transfer_to_handler
114 .macro SYSCALL_ENTRY trapno intno srr1
115 mfspr r10, SPRN_SPRG_THREAD
116 #ifdef CONFIG_KVM_BOOKE_HV
118 mtspr SPRN_SPRG_WSCRATCH0, r10
119 stw r11, THREAD_NORMSAVE(0)(r10)
120 stw r13, THREAD_NORMSAVE(2)(r10)
121 mfcr r13 /* save CR in r13 for now */
123 mtocrf 0x80, r11 /* check MSR[GS] without clobbering reg */
125 b kvmppc_handler_\intno\()_\srr1
128 lwz r13, THREAD_NORMSAVE(2)(r10)
131 ALT_FTR_SECTION_END_IFSET(CPU_FTR_EMB_HV)
138 lwz r1, TASK_STACK - THREAD(r10)
139 rlwinm r12,r12,0,4,2 /* Clear SO bit in CR */
140 ALLOC_STACK_FRAME(r1, THREAD_SIZE - INT_FRAME_SIZE)
144 b transfer_to_syscall /* jump to handler */
147 /* To handle the additional exception priority levels on 40x and Book-E
148 * processors we allocate a stack per additional priority level.
150 * On 40x critical is the only additional level
151 * On 44x/e500 we have critical and machine check
153 * Additionally we reserve a SPRG for each priority level so we can free up a
154 * GPR to use as the base for indirect access to the exception stacks. This
155 * is necessary since the MMU is always on, for Book-E parts, and the stacks
156 * are offset from KERNELBASE.
158 * There is some space optimization to be had here if desired. However
159 * to allow for a common kernel with support for debug exceptions either
160 * going to critical or their own debug level we aren't currently
161 * providing configurations that micro-optimize space usage.
164 #define MC_STACK_BASE mcheckirq_ctx
165 #define CRIT_STACK_BASE critirq_ctx
168 #define DBG_STACK_BASE dbgirq_ctx
171 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
174 addis r8,r8,level##_STACK_BASE@ha; \
175 lwz r8,level##_STACK_BASE@l(r8); \
176 addi r8,r8,THREAD_SIZE - INT_FRAME_SIZE;
178 #define BOOKE_LOAD_EXC_LEVEL_STACK(level) \
179 lis r8,level##_STACK_BASE@ha; \
180 lwz r8,level##_STACK_BASE@l(r8); \
181 addi r8,r8,THREAD_SIZE - INT_FRAME_SIZE;
185 * Exception prolog for critical/machine check exceptions. This is a
186 * little different from the normal exception prolog above since a
187 * critical/machine check exception can potentially occur at any point
188 * during normal exception processing. Thus we cannot use the same SPRG
189 * registers as the normal prolog above. Instead we use a portion of the
190 * critical/machine check exception stack at low physical addresses.
192 #define EXC_LEVEL_EXCEPTION_PROLOG(exc_level, trapno, intno, exc_level_srr0, exc_level_srr1) \
193 mtspr SPRN_SPRG_WSCRATCH_##exc_level,r8; \
194 BOOKE_LOAD_EXC_LEVEL_STACK(exc_level);/* r8 points to the exc_level stack*/ \
195 stw r9,GPR9(r8); /* save various registers */\
196 mfcr r9; /* save CR in r9 for now */\
199 stw r9,_CCR(r8); /* save CR on stack */\
200 mfspr r11,exc_level_srr1; /* check whether user or kernel */\
201 DO_KVM BOOKE_INTERRUPT_##intno exc_level_srr1; \
202 BOOKE_CLEAR_BTB(r10) \
203 andi. r11,r11,MSR_PR; \
204 LOAD_REG_IMMEDIATE(r11, MSR_KERNEL & ~(MSR_ME|MSR_DE|MSR_CE)); \
206 mfspr r11,SPRN_SPRG_THREAD; /* if from user, start at top of */\
207 lwz r11, TASK_STACK - THREAD(r11); /* this thread's kernel stack */\
208 addi r11,r11,THREAD_SIZE - INT_FRAME_SIZE; /* allocate stack frame */\
210 /* COMING FROM USER MODE */ \
211 stw r9,_CCR(r11); /* save CR */\
212 lwz r10,GPR10(r8); /* copy regs from exception stack */\
214 stw r10,GPR10(r11); \
217 stw r10,GPR11(r11); \
219 /* COMING FROM PRIV MODE */ \
221 2: mfspr r8,SPRN_SPRG_RSCRATCH_##exc_level; \
222 stw r12,GPR12(r11); /* save various registers */\
224 stw r10,_LINK(r11); \
225 mfspr r12,SPRN_DEAR; /* save DEAR and ESR in the frame */\
226 stw r12,_DEAR(r11); /* since they may have had stuff */\
227 mfspr r9,SPRN_ESR; /* in them at the point where the */\
228 stw r9,_ESR(r11); /* exception was taken */\
229 mfspr r12,exc_level_srr0; \
231 mfspr r9,exc_level_srr1; \
234 rlwinm r9,r9,0,14,12; /* clear MSR_WE (necessary?) */\
235 COMMON_EXCEPTION_PROLOG_END trapno
237 #define SAVE_xSRR(xSRR) \
238 mfspr r0,SPRN_##xSRR##0; \
239 stw r0,_##xSRR##0(r1); \
240 mfspr r0,SPRN_##xSRR##1; \
241 stw r0,_##xSRR##1(r1)
245 #ifdef CONFIG_PPC_E500
256 #ifdef CONFIG_PHYS_64BIT
259 #endif /* CONFIG_PHYS_64BIT */
260 #endif /* CONFIG_PPC_E500 */
267 #define CRITICAL_EXCEPTION_PROLOG(trapno, intno) \
268 EXC_LEVEL_EXCEPTION_PROLOG(CRIT, trapno+2, intno, SPRN_CSRR0, SPRN_CSRR1)
269 #define DEBUG_EXCEPTION_PROLOG(trapno) \
270 EXC_LEVEL_EXCEPTION_PROLOG(DBG, trapno+8, DEBUG, SPRN_DSRR0, SPRN_DSRR1)
271 #define MCHECK_EXCEPTION_PROLOG(trapno) \
272 EXC_LEVEL_EXCEPTION_PROLOG(MC, trapno+4, MACHINE_CHECK, \
273 SPRN_MCSRR0, SPRN_MCSRR1)
276 * Guest Doorbell -- this is a bit odd in that uses GSRR0/1 despite
277 * being delivered to the host. This exception can only happen
278 * inside a KVM guest -- so we just handle up to the DO_KVM rather
279 * than try to fit this into one of the existing prolog macros.
281 #define GUEST_DOORBELL_EXCEPTION \
282 START_EXCEPTION(GuestDoorbell); \
283 mtspr SPRN_SPRG_WSCRATCH0, r10; /* save one register */ \
284 mfspr r10, SPRN_SPRG_THREAD; \
285 stw r11, THREAD_NORMSAVE(0)(r10); \
286 mfspr r11, SPRN_SRR1; \
287 stw r13, THREAD_NORMSAVE(2)(r10); \
288 mfcr r13; /* save CR in r13 for now */\
289 DO_KVM BOOKE_INTERRUPT_GUEST_DBELL SPRN_GSRR1; \
295 #define START_EXCEPTION(label) \
299 #define EXCEPTION(n, intno, label, hdlr) \
300 START_EXCEPTION(label); \
301 NORMAL_EXCEPTION_PROLOG(n, intno); \
302 prepare_transfer_to_handler; \
306 #define CRITICAL_EXCEPTION(n, intno, label, hdlr) \
307 START_EXCEPTION(label); \
308 CRITICAL_EXCEPTION_PROLOG(n, intno); \
311 prepare_transfer_to_handler; \
315 #define MCHECK_EXCEPTION(n, label, hdlr) \
316 START_EXCEPTION(label); \
317 MCHECK_EXCEPTION_PROLOG(n); \
324 prepare_transfer_to_handler; \
326 b ret_from_mcheck_exc
328 /* Check for a single step debug exception while in an exception
329 * handler before state has been saved. This is to catch the case
330 * where an instruction that we are trying to single step causes
331 * an exception (eg ITLB/DTLB miss) and thus the first instruction of
332 * the exception handler generates a single step debug exception.
334 * If we get a debug trap on the first instruction of an exception handler,
335 * we reset the MSR_DE in the _exception handler's_ MSR (the debug trap is
336 * a critical exception, so we are using SPRN_CSRR1 to manipulate the MSR).
337 * The exception handler was handling a non-critical interrupt, so it will
338 * save (and later restore) the MSR via SPRN_CSRR1, which will still have
339 * the MSR_DE bit set.
341 #define DEBUG_DEBUG_EXCEPTION \
342 START_EXCEPTION(DebugDebug); \
343 DEBUG_EXCEPTION_PROLOG(2000); \
346 * If there is a single step or branch-taken exception in an \
347 * exception entry sequence, it was probably meant to apply to \
348 * the code where the exception occurred (since exception entry \
349 * doesn't turn off DE automatically). We simulate the effect \
350 * of turning off DE on entry to an exception handler by turning \
351 * off DE in the DSRR1 value and clearing the debug status. \
353 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
354 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
357 lis r10,interrupt_base@h; /* check if exception in vectors */ \
358 ori r10,r10,interrupt_base@l; \
360 blt+ 2f; /* addr below exception vectors */ \
362 lis r10,interrupt_end@h; \
363 ori r10,r10,interrupt_end@l; \
365 bgt+ 2f; /* addr above exception vectors */ \
367 /* here it looks like we got an inappropriate debug exception. */ \
368 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CDRR1 value */ \
369 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
370 mtspr SPRN_DBSR,r10; \
371 /* restore state and get out */ \
376 mtspr SPRN_DSRR0,r12; \
377 mtspr SPRN_DSRR1,r9; \
379 lwz r12,GPR12(r11); \
380 mtspr SPRN_SPRG_WSCRATCH_DBG,r8; \
381 BOOKE_LOAD_EXC_LEVEL_STACK(DBG); /* r8 points to the debug stack */ \
384 mfspr r8,SPRN_SPRG_RSCRATCH_DBG; \
389 /* continue normal handling for a debug exception... */ \
390 2: mfspr r4,SPRN_DBSR; \
391 stw r4,_ESR(r11); /* DebugException takes DBSR in _ESR */\
395 prepare_transfer_to_handler; \
399 #define DEBUG_CRIT_EXCEPTION \
400 START_EXCEPTION(DebugCrit); \
401 CRITICAL_EXCEPTION_PROLOG(2000,DEBUG); \
404 * If there is a single step or branch-taken exception in an \
405 * exception entry sequence, it was probably meant to apply to \
406 * the code where the exception occurred (since exception entry \
407 * doesn't turn off DE automatically). We simulate the effect \
408 * of turning off DE on entry to an exception handler by turning \
409 * off DE in the CSRR1 value and clearing the debug status. \
411 mfspr r10,SPRN_DBSR; /* check single-step/branch taken */ \
412 andis. r10,r10,(DBSR_IC|DBSR_BT)@h; \
415 lis r10,interrupt_base@h; /* check if exception in vectors */ \
416 ori r10,r10,interrupt_base@l; \
418 blt+ 2f; /* addr below exception vectors */ \
420 lis r10,interrupt_end@h; \
421 ori r10,r10,interrupt_end@l; \
423 bgt+ 2f; /* addr above exception vectors */ \
425 /* here it looks like we got an inappropriate debug exception. */ \
426 1: rlwinm r9,r9,0,~MSR_DE; /* clear DE in the CSRR1 value */ \
427 lis r10,(DBSR_IC|DBSR_BT)@h; /* clear the IC event */ \
428 mtspr SPRN_DBSR,r10; \
429 /* restore state and get out */ \
434 mtspr SPRN_CSRR0,r12; \
435 mtspr SPRN_CSRR1,r9; \
437 lwz r12,GPR12(r11); \
438 mtspr SPRN_SPRG_WSCRATCH_CRIT,r8; \
439 BOOKE_LOAD_EXC_LEVEL_STACK(CRIT); /* r8 points to the debug stack */ \
442 mfspr r8,SPRN_SPRG_RSCRATCH_CRIT; \
447 /* continue normal handling for a critical exception... */ \
448 2: mfspr r4,SPRN_DBSR; \
449 stw r4,_ESR(r11); /* DebugException takes DBSR in _ESR */\
452 prepare_transfer_to_handler; \
456 #define DATA_STORAGE_EXCEPTION \
457 START_EXCEPTION(DataStorage) \
458 NORMAL_EXCEPTION_PROLOG(0x300, DATA_STORAGE); \
459 mfspr r5,SPRN_ESR; /* Grab the ESR and save it */ \
461 mfspr r4,SPRN_DEAR; /* Grab the DEAR */ \
462 stw r4, _DEAR(r11); \
463 prepare_transfer_to_handler; \
468 * Instruction TLB Error interrupt handlers may call InstructionStorage
469 * directly without clearing ESR, so the ESR at this point may be left over
470 * from a prior interrupt.
472 * In any case, do_page_fault for BOOK3E does not use ESR and always expects
473 * dsisr to be 0. ESR_DST from a prior store in particular would confuse fault
476 #define INSTRUCTION_STORAGE_EXCEPTION \
477 START_EXCEPTION(InstructionStorage) \
478 NORMAL_EXCEPTION_PROLOG(0x400, INST_STORAGE); \
479 li r5,0; /* Store 0 in regs->esr (dsisr) */ \
481 stw r12, _DEAR(r11); /* Set regs->dear (dar) to SRR0 */ \
482 prepare_transfer_to_handler; \
486 #define ALIGNMENT_EXCEPTION \
487 START_EXCEPTION(Alignment) \
488 NORMAL_EXCEPTION_PROLOG(0x600, ALIGNMENT); \
489 mfspr r4,SPRN_DEAR; /* Grab the DEAR and save it */ \
491 prepare_transfer_to_handler; \
492 bl alignment_exception; \
496 #define PROGRAM_EXCEPTION \
497 START_EXCEPTION(Program) \
498 NORMAL_EXCEPTION_PROLOG(0x700, PROGRAM); \
499 mfspr r4,SPRN_ESR; /* Grab the ESR and save it */ \
501 prepare_transfer_to_handler; \
502 bl program_check_exception; \
506 #define DECREMENTER_EXCEPTION \
507 START_EXCEPTION(Decrementer) \
508 NORMAL_EXCEPTION_PROLOG(0x900, DECREMENTER); \
509 lis r0,TSR_DIS@h; /* Setup the DEC interrupt mask */ \
510 mtspr SPRN_TSR,r0; /* Clear the DEC interrupt */ \
511 prepare_transfer_to_handler; \
512 bl timer_interrupt; \
515 #define FP_UNAVAILABLE_EXCEPTION \
516 START_EXCEPTION(FloatingPointUnavailable) \
517 NORMAL_EXCEPTION_PROLOG(0x800, FP_UNAVAIL); \
519 bl load_up_fpu; /* if from user, just load it up */ \
520 b fast_exception_return; \
521 1: prepare_transfer_to_handler; \
522 bl kernel_fp_unavailable_exception; \
525 #endif /* __ASSEMBLY__ */
526 #endif /* __HEAD_BOOKE_H__ */