3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Low-level exception handlers and MMU support
7 * rewritten by Paul Mackerras.
8 * Copyright (C) 1996 Paul Mackerras.
9 * MPC8xx modifications by Dan Malek
10 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains low-level support and setup for PowerPC 8xx
13 * embedded processors, including trap and interrupt dispatch.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
22 #include <linux/init.h>
23 #include <asm/processor.h>
26 #include <asm/cache.h>
27 #include <asm/pgtable.h>
28 #include <asm/cputable.h>
29 #include <asm/thread_info.h>
30 #include <asm/ppc_asm.h>
31 #include <asm/asm-offsets.h>
32 #include <asm/ptrace.h>
33 #include <asm/fixmap.h>
34 #include <asm/export.h>
36 /* Macro to make the code more readable. */
37 #ifdef CONFIG_8xx_CPU6
38 #define SPRN_MI_TWC_ADDR 0x2b80
39 #define SPRN_MI_RPN_ADDR 0x2d80
40 #define SPRN_MD_TWC_ADDR 0x3b80
41 #define SPRN_MD_RPN_ADDR 0x3d80
43 #define MTSPR_CPU6(spr, reg, treg) \
44 li treg, spr##_ADDR; \
49 #define MTSPR_CPU6(spr, reg, treg) \
53 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
54 /* By simply checking Address >= 0x80000000, we know if its a kernel address */
55 #define SIMPLE_KERNEL_ADDRESS 1
59 * We need an ITLB miss handler for kernel addresses if:
60 * - Either we have modules
61 * - Or we have not pinned the first 8M
63 #if defined(CONFIG_MODULES) || !defined(CONFIG_PIN_TLB_TEXT) || \
64 defined(CONFIG_DEBUG_PAGEALLOC)
65 #define ITLB_MISS_KERNEL 1
69 * Value for the bits that have fixed value in RPN entries.
70 * Also used for tagging DAR for DTLBerror.
72 #ifdef CONFIG_PPC_16K_PAGES
73 #define RPN_PATTERN (0x00f0 | MD_SPS16K)
75 #define RPN_PATTERN 0x00f0
78 #define PAGE_SHIFT_512K 19
79 #define PAGE_SHIFT_8M 23
86 * This port was done on an MBX board with an 860. Right now I only
87 * support an ELF compressed (zImage) boot from EPPC-Bug because the
88 * code there loads up some registers before calling us:
89 * r3: ptr to board info data
90 * r4: initrd_start or if no initrd then 0
91 * r5: initrd_end - unused if r4 is 0
92 * r6: Start of command line string
93 * r7: End of command line string
95 * I decided to use conditional compilation instead of checking PVR and
96 * adding more processor specific branches around code I don't need.
97 * Since this is an embedded processor, I also appreciate any memory
100 * The MPC8xx does not have any BATs, but it supports large page sizes.
101 * We first initialize the MMU to support 8M byte pages, then load one
102 * entry into each of the instruction and data TLBs to map the first
103 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
104 * the "internal" processor registers before MMU_init is called.
110 mr r31,r3 /* save device tree ptr */
112 /* We have to turn on the MMU right away so we get cache modes
117 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
123 ori r0,r0,MSR_DR|MSR_IR
126 ori r0,r0,start_here@l
128 rfi /* enables MMU */
131 * Exception entry code. This code runs with address translation
132 * turned off, i.e. using physical addresses.
133 * We assume sprg3 has the physical address of the current
134 * task's thread_struct.
136 #define EXCEPTION_PROLOG \
137 EXCEPTION_PROLOG_0; \
139 EXCEPTION_PROLOG_1; \
142 #define EXCEPTION_PROLOG_0 \
143 mtspr SPRN_SPRG_SCRATCH0,r10; \
144 mtspr SPRN_SPRG_SCRATCH1,r11
146 #define EXCEPTION_PROLOG_1 \
147 mfspr r11,SPRN_SRR1; /* check whether user or kernel */ \
148 andi. r11,r11,MSR_PR; \
149 tophys(r11,r1); /* use tophys(r1) if kernel */ \
151 mfspr r11,SPRN_SPRG_THREAD; \
152 lwz r11,THREAD_INFO-THREAD(r11); \
153 addi r11,r11,THREAD_SIZE; \
155 1: subi r11,r11,INT_FRAME_SIZE /* alloc exc. frame */
158 #define EXCEPTION_PROLOG_2 \
159 stw r10,_CCR(r11); /* save registers */ \
160 stw r12,GPR12(r11); \
162 mfspr r10,SPRN_SPRG_SCRATCH0; \
163 stw r10,GPR10(r11); \
164 mfspr r12,SPRN_SPRG_SCRATCH1; \
165 stw r12,GPR11(r11); \
167 stw r10,_LINK(r11); \
168 mfspr r12,SPRN_SRR0; \
169 mfspr r9,SPRN_SRR1; \
172 tovirt(r1,r11); /* set new kernel sp */ \
173 li r10,MSR_KERNEL & ~(MSR_IR|MSR_DR); /* can take exceptions */ \
176 SAVE_4GPRS(3, r11); \
180 * Exception exit code.
182 #define EXCEPTION_EPILOG_0 \
183 mfspr r10,SPRN_SPRG_SCRATCH0; \
184 mfspr r11,SPRN_SPRG_SCRATCH1
187 * Note: code which follows this uses cr0.eq (set if from kernel),
188 * r11, r12 (SRR0), and r9 (SRR1).
190 * Note2: once we have set r1 we are in a position to take exceptions
191 * again, and we could thus set MSR:RI at that point.
197 #define EXCEPTION(n, label, hdlr, xfer) \
201 addi r3,r1,STACK_FRAME_OVERHEAD; \
204 #define EXC_XFER_TEMPLATE(n, hdlr, trap, copyee, tfer, ret) \
206 stw r10,_TRAP(r11); \
214 #define COPY_EE(d, s) rlwimi d,s,0,16,16
217 #define EXC_XFER_STD(n, hdlr) \
218 EXC_XFER_TEMPLATE(n, hdlr, n, NOCOPY, transfer_to_handler_full, \
219 ret_from_except_full)
221 #define EXC_XFER_LITE(n, hdlr) \
222 EXC_XFER_TEMPLATE(n, hdlr, n+1, NOCOPY, transfer_to_handler, \
225 #define EXC_XFER_EE(n, hdlr) \
226 EXC_XFER_TEMPLATE(n, hdlr, n, COPY_EE, transfer_to_handler_full, \
227 ret_from_except_full)
229 #define EXC_XFER_EE_LITE(n, hdlr) \
230 EXC_XFER_TEMPLATE(n, hdlr, n+1, COPY_EE, transfer_to_handler, \
234 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
243 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
246 addi r3,r1,STACK_FRAME_OVERHEAD
247 EXC_XFER_STD(0x200, machine_check_exception)
249 /* Data access exception.
250 * This is "never generated" by the MPC8xx.
255 /* Instruction access exception.
256 * This is "never generated" by the MPC8xx.
261 /* External interrupt */
262 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
264 /* Alignment exception */
271 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
274 addi r3,r1,STACK_FRAME_OVERHEAD
275 EXC_XFER_EE(0x600, alignment_exception)
277 /* Program check exception */
278 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
280 /* No FPU on MPC8xx. This exception is not supposed to happen.
282 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
285 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
287 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_EE)
288 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_EE)
294 EXC_XFER_EE_LITE(0xc00, DoSyscall)
296 /* Single step - not used on 601 */
297 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
298 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_EE)
299 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_EE)
301 /* On the MPC8xx, this is a software emulation interrupt. It occurs
302 * for all unimplemented and illegal instructions.
304 EXCEPTION(0x1000, SoftEmu, emulation_assist_interrupt, EXC_XFER_STD)
308 * For the MPC8xx, this is a software tablewalk to load the instruction
309 * TLB. The task switch loads the M_TW register with the pointer to the first
311 * If we discover there is no second level table (value is zero) or if there
312 * is an invalid pte, we load that into the TLB, which causes another fault
313 * into the TLB Error interrupt where we can handle such problems.
314 * We have to use the MD_xxx registers for the tablewalk because the
315 * equivalent MI_xxx registers only perform the attribute functions.
318 #ifdef CONFIG_8xx_CPU15
319 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr) \
320 addi tmp, addr, PAGE_SIZE; \
322 addi tmp, addr, -PAGE_SIZE; \
325 #define INVALIDATE_ADJACENT_PAGES_CPU15(tmp, addr)
329 #if defined(CONFIG_8xx_CPU6) || defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
330 mtspr SPRN_SPRG_SCRATCH2, r3
333 #ifdef CONFIG_PPC_8xx_PERF_EVENT
334 lis r10, (itlb_miss_counter - PAGE_OFFSET)@ha
335 lwz r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
337 stw r11, (itlb_miss_counter - PAGE_OFFSET)@l(r10)
340 /* If we are faulting a kernel address, we have to use the
341 * kernel page tables.
343 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
344 INVALIDATE_ADJACENT_PAGES_CPU15(r11, r10)
345 /* Only modules will cause ITLB Misses as we always
346 * pin the first 8MB of kernel memory */
347 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
350 #ifdef ITLB_MISS_KERNEL
351 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
352 andis. r11, r10, 0x8000 /* Address >= 0x80000000 */
354 rlwinm r11, r10, 16, 0xfff8
355 cmpli cr0, r11, PAGE_OFFSET@h
356 #ifndef CONFIG_PIN_TLB_TEXT
357 /* It is assumed that kernel code fits into the first 8M page */
359 cmpli cr7, r11, (PAGE_OFFSET + 0x0800000)@h
363 mfspr r11, SPRN_M_TW /* Get level 1 table */
364 #ifdef ITLB_MISS_KERNEL
365 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
370 #ifndef CONFIG_PIN_TLB_TEXT
371 blt cr7, ITLBMissLinear
373 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
376 /* Insert level 1 index */
377 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
378 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
380 /* Extract level 2 index */
381 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
382 #ifdef CONFIG_HUGETLB_PAGE
384 bt- 28, 10f /* bit 28 = Large page (8M) */
385 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */
387 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
388 lwz r10, 0(r10) /* Get the pte */
390 #if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
393 /* Insert the APG into the TWC from the Linux PTE. */
394 rlwimi r11, r10, 0, 25, 26
395 /* Load the MI_TWC with the attributes for this "segment." */
396 MTSPR_CPU6(SPRN_MI_TWC, r11, r3) /* Set segment attributes */
398 #if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES)
399 rlwimi r10, r11, 1, MI_SPS16K
401 rlwinm r11, r10, 32-11, _PAGE_PRESENT
403 rlwimi r10, r11, 0, _PAGE_PRESENT
405 /* The Linux PTE won't go exactly into the MMU TLB.
406 * Software indicator bits 20-23 and 28 must be clear.
407 * Software indicator bits 24, 25, 26, and 27 must be
408 * set. All other Linux PTE bits control the behavior
411 #if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES)
412 rlwimi r10, r11, 0, 0x0ff0 /* Set 24-27, clear 20-23 */
414 rlwimi r10, r11, 0, 0x0ff8 /* Set 24-27, clear 20-23,28 */
416 MTSPR_CPU6(SPRN_MI_RPN, r10, r3) /* Update TLB entry */
418 /* Restore registers */
419 #if defined(CONFIG_8xx_CPU6) || defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
420 mfspr r3, SPRN_SPRG_SCRATCH2
425 #ifdef CONFIG_HUGETLB_PAGE
427 #ifdef CONFIG_PPC_16K_PAGES
428 /* Extract level 2 index */
429 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
430 /* Add level 2 base */
431 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
434 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK
436 lwz r10, 0(r10) /* Get the pte */
437 rlwinm r11, r11, 0, 0xf
441 /* Extract level 2 index */
442 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
443 /* Add level 2 base */
444 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
445 lwz r10, 0(r10) /* Get the pte */
446 rlwinm r11, r11, 0, 0xf
452 mtspr SPRN_SPRG_SCRATCH2, r3
454 #ifdef CONFIG_PPC_8xx_PERF_EVENT
455 lis r10, (dtlb_miss_counter - PAGE_OFFSET)@ha
456 lwz r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
458 stw r11, (dtlb_miss_counter - PAGE_OFFSET)@l(r10)
462 /* If we are faulting a kernel address, we have to use the
463 * kernel page tables.
465 mfspr r10, SPRN_MD_EPN
466 rlwinm r11, r10, 16, 0xfff8
467 cmpli cr0, r11, PAGE_OFFSET@h
468 mfspr r11, SPRN_M_TW /* Get level 1 table */
470 rlwinm r11, r10, 16, 0xfff8
471 #ifndef CONFIG_PIN_TLB_IMMR
472 cmpli cr0, r11, VIRT_IMMR_BASE@h
475 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
476 #ifndef CONFIG_PIN_TLB_IMMR
480 blt cr7, DTLBMissLinear
481 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
484 /* Insert level 1 index */
485 rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
486 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
488 /* We have a pte table, so load fetch the pte from the table.
490 /* Extract level 2 index */
491 rlwinm r10, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
492 #ifdef CONFIG_HUGETLB_PAGE
494 bt- 28, 10f /* bit 28 = Large page (8M) */
495 bt- 29, 20f /* bit 29 = Large page (8M or 512k) */
497 rlwimi r10, r11, 0, 0, 32 - PAGE_SHIFT - 1 /* Add level 2 base */
498 lwz r10, 0(r10) /* Get the pte */
502 /* Insert the Guarded flag and APG into the TWC from the Linux PTE.
503 * It is bit 26-27 of both the Linux PTE and the TWC (at least
504 * I got that right :-). It will be better when we can put
505 * this into the Linux pgd/pmd and load it in the operation
508 rlwimi r11, r10, 0, 26, 27
509 /* Insert the WriteThru flag into the TWC from the Linux PTE.
510 * It is bit 25 in the Linux PTE and bit 30 in the TWC
512 rlwimi r11, r10, 32-5, 30, 30
513 MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
515 /* In 4k pages mode, SPS (bit 28) in RPN must match PS[1] (bit 29)
516 * In 16k pages mode, SPS is always 1 */
517 #if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES)
518 rlwimi r10, r11, 1, MD_SPS16K
520 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
521 * We also need to know if the insn is a load/store, so:
522 * Clear _PAGE_PRESENT and load that which will
523 * trap into DTLB Error with store bit set accordinly.
525 /* PRESENT=0x1, ACCESSED=0x20
526 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
527 * r10 = (r10 & ~PRESENT) | r11;
529 rlwinm r11, r10, 32-11, _PAGE_PRESENT
531 rlwimi r10, r11, 0, _PAGE_PRESENT
532 /* The Linux PTE won't go exactly into the MMU TLB.
533 * Software indicator bits 22 and 28 must be clear.
534 * Software indicator bits 24, 25, 26, and 27 must be
535 * set. All other Linux PTE bits control the behavior
539 #if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES)
540 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */
542 rlwimi r10, r11, 0, 24, 28 /* Set 24-27, clear 28 */
544 rlwimi r10, r11, 0, 20, 20 /* clear 20 */
545 MTSPR_CPU6(SPRN_MD_RPN, r10, r3) /* Update TLB entry */
547 /* Restore registers */
548 mfspr r3, SPRN_SPRG_SCRATCH2
549 mtspr SPRN_DAR, r11 /* Tag DAR */
553 #ifdef CONFIG_HUGETLB_PAGE
555 /* Extract level 2 index */
556 #ifdef CONFIG_PPC_16K_PAGES
557 rlwinm r10, r10, 32 - (PAGE_SHIFT_8M - PAGE_SHIFT), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
558 /* Add level 2 base */
559 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
562 rlwinm r10, r11, 0, ~HUGEPD_SHIFT_MASK
564 lwz r10, 0(r10) /* Get the pte */
565 rlwinm r11, r11, 0, 0xf
569 /* Extract level 2 index */
570 rlwinm r10, r10, 32 - (PAGE_SHIFT_512K - PAGE_SHIFT), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
571 /* Add level 2 base */
572 rlwimi r10, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
573 lwz r10, 0(r10) /* Get the pte */
574 rlwinm r11, r11, 0, 0xf
578 /* This is an instruction TLB error on the MPC8xx. This could be due
579 * to many reasons, such as executing guarded memory or illegal instruction
580 * addresses. There is nothing to do but handle a big time error fault.
586 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
587 andis. r10,r9,SRR1_ISI_NOPT@h
591 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
592 1: EXC_XFER_LITE(0x400, handle_page_fault)
594 /* This is the data TLB error on the MPC8xx. This could be due to
595 * many reasons, including a dirty update to a pte. We bail out to
596 * a higher level function that can handle it.
604 cmpwi cr0, r11, RPN_PATTERN
605 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
606 DARFixed:/* Return from dcbx instruction bug workaround */
612 andis. r10,r5,DSISR_NOHPTE@h
616 1: li r10,RPN_PATTERN
617 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
618 /* 0x300 is DataAccess exception, needed by bad_page_fault() */
619 EXC_XFER_LITE(0x300, handle_page_fault)
621 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_EE)
622 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_EE)
623 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_EE)
624 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_EE)
625 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_EE)
626 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_EE)
627 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_EE)
629 /* On the MPC8xx, these next four traps are used for development
630 * support of breakpoints and such. Someday I will get around to
638 cmplwi cr0, r11, (dtlbie - PAGE_OFFSET)@l
639 cmplwi cr7, r11, (itlbie - PAGE_OFFSET)@l
644 addi r3,r1,STACK_FRAME_OVERHEAD
648 EXC_XFER_EE(0x1c00, do_break)
654 #ifdef CONFIG_PPC_8xx_PERF_EVENT
656 InstructionBreakpoint:
658 lis r10, (instruction_counter - PAGE_OFFSET)@ha
659 lwz r11, (instruction_counter - PAGE_OFFSET)@l(r10)
661 stw r11, (instruction_counter - PAGE_OFFSET)@l(r10)
664 mtspr SPRN_COUNTA, r10
668 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_EE)
670 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_EE)
671 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_EE)
676 * Bottom part of DataStoreTLBMiss handlers for IMMR area and linear RAM.
677 * not enough space in the DataStoreTLBMiss area.
681 /* Set 512k byte guarded page and mark it valid */
682 li r10, MD_PS512K | MD_GUARDED | MD_SVALID
683 MTSPR_CPU6(SPRN_MD_TWC, r10, r11)
684 mfspr r10, SPRN_IMMR /* Get current IMMR */
685 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
686 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
687 _PAGE_PRESENT | _PAGE_NO_CACHE
688 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */
691 mtspr SPRN_DAR, r11 /* Tag DAR */
692 mfspr r3, SPRN_SPRG_SCRATCH2
698 /* Set 8M byte page and mark it valid */
699 li r11, MD_PS8MEG | MD_SVALID
700 MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
701 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
702 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
704 MTSPR_CPU6(SPRN_MD_RPN, r10, r11) /* Update TLB entry */
707 mtspr SPRN_DAR, r11 /* Tag DAR */
708 mfspr r3, SPRN_SPRG_SCRATCH2
712 #ifndef CONFIG_PIN_TLB_TEXT
715 /* Set 8M byte page and mark it valid */
716 li r11, MI_PS8MEG | MI_SVALID | _PAGE_EXEC
717 MTSPR_CPU6(SPRN_MI_TWC, r11, r3)
718 rlwinm r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
719 ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
721 MTSPR_CPU6(SPRN_MI_RPN, r10, r11) /* Update TLB entry */
723 mfspr r3, SPRN_SPRG_SCRATCH2
728 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
729 * by decoding the registers used by the dcbx instruction and adding them.
730 * DAR is set to the calculated address.
732 /* define if you don't want to use self modifying code */
733 #define NO_SELF_MODIFYING_CODE
734 FixupDAR:/* Entry point for dcbx workaround. */
735 mtspr SPRN_SPRG_SCRATCH2, r10
736 /* fetch instruction from memory. */
738 rlwinm r11, r10, 16, 0xfff8
739 cmpli cr0, r11, PAGE_OFFSET@h
740 mfspr r11, SPRN_M_TW /* Get level 1 table */
742 rlwinm r11, r10, 16, 0xfff8
744 cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
745 /* create physical page address from effective address */
748 lis r11, (swapper_pg_dir-PAGE_OFFSET)@ha
749 /* Insert level 1 index */
750 3: rlwimi r11, r10, 32 - ((PAGE_SHIFT - 2) << 1), (PAGE_SHIFT - 2) << 1, 29
751 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
753 bt 28,200f /* bit 28 = Large page (8M) */
754 bt 29,202f /* bit 29 = Large page (8M or 512K) */
755 rlwinm r11, r11,0,0,19 /* Extract page descriptor page address */
756 /* Insert level 2 index */
757 rlwimi r11, r10, 32 - (PAGE_SHIFT - 2), 32 - PAGE_SHIFT, 29
758 lwz r11, 0(r11) /* Get the pte */
759 /* concat physical page address(r11) and page offset(r10) */
760 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
762 /* Check if it really is a dcbx instruction. */
763 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
764 * no need to include them here */
765 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
766 rlwinm r10, r10, 0, 21, 5
767 cmpwi cr0, r10, 2028 /* Is dcbz? */
769 cmpwi cr0, r10, 940 /* Is dcbi? */
771 cmpwi cr0, r10, 108 /* Is dcbst? */
772 beq+ 144f /* Fix up store bit! */
773 cmpwi cr0, r10, 172 /* Is dcbf? */
775 cmpwi cr0, r10, 1964 /* Is icbi? */
777 141: mfspr r10,SPRN_SPRG_SCRATCH2
778 b DARFixed /* Nope, go back to normal TLB processing */
780 /* concat physical page address(r11) and page offset(r10) */
782 #ifdef CONFIG_PPC_16K_PAGES
783 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1) - 1
784 rlwimi r11, r10, 32 - (PAGE_SHIFT_8M - 2), 32 + PAGE_SHIFT_8M - (PAGE_SHIFT << 1), 29
786 rlwinm r11, r10, 0, ~HUGEPD_SHIFT_MASK
788 lwz r11, 0(r11) /* Get the pte */
789 /* concat physical page address(r11) and page offset(r10) */
790 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
794 rlwinm r11, r11, 0, 0, 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1) - 1
795 rlwimi r11, r10, 32 - (PAGE_SHIFT_512K - 2), 32 + PAGE_SHIFT_512K - (PAGE_SHIFT << 1), 29
796 lwz r11, 0(r11) /* Get the pte */
797 /* concat physical page address(r11) and page offset(r10) */
798 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31
801 144: mfspr r10, SPRN_DSISR
802 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
803 mtspr SPRN_DSISR, r10
804 142: /* continue, it was a dcbx, dcbi instruction. */
805 #ifndef NO_SELF_MODIFYING_CODE
806 andis. r10,r11,0x1f /* test if reg RA is r0 */
807 li r10,modified_instr@l
808 dcbtst r0,r10 /* touch for store */
809 rlwinm r11,r11,0,0,20 /* Zero lower 10 bits */
810 oris r11,r11,640 /* Transform instr. to a "add r10,RA,RB" */
812 stw r11,0(r10) /* store add/and instruction */
813 dcbf 0,r10 /* flush new instr. to memory. */
814 icbi 0,r10 /* invalidate instr. cache line */
815 mfspr r11, SPRN_SPRG_SCRATCH1 /* restore r11 */
816 mfspr r10, SPRN_SPRG_SCRATCH0 /* restore r10 */
817 isync /* Wait until new instr is loaded from memory */
819 .space 4 /* this is where the add instr. is stored */
821 subf r10,r0,r10 /* r10=r10-r0, only if reg RA is r0 */
822 143: mtdar r10 /* store faulting EA in DAR */
823 mfspr r10,SPRN_SPRG_SCRATCH2
824 b DARFixed /* Go back to normal TLB handling */
827 mtdar r10 /* save ctr reg in DAR */
828 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
829 addi r10, r10, 150f@l /* add start of table */
830 mtctr r10 /* load ctr with jump address */
831 xor r10, r10, r10 /* sum starts at zero */
832 bctr /* jump into table */
834 add r10, r10, r0 ;b 151f
835 add r10, r10, r1 ;b 151f
836 add r10, r10, r2 ;b 151f
837 add r10, r10, r3 ;b 151f
838 add r10, r10, r4 ;b 151f
839 add r10, r10, r5 ;b 151f
840 add r10, r10, r6 ;b 151f
841 add r10, r10, r7 ;b 151f
842 add r10, r10, r8 ;b 151f
843 add r10, r10, r9 ;b 151f
844 mtctr r11 ;b 154f /* r10 needs special handling */
845 mtctr r11 ;b 153f /* r11 needs special handling */
846 add r10, r10, r12 ;b 151f
847 add r10, r10, r13 ;b 151f
848 add r10, r10, r14 ;b 151f
849 add r10, r10, r15 ;b 151f
850 add r10, r10, r16 ;b 151f
851 add r10, r10, r17 ;b 151f
852 add r10, r10, r18 ;b 151f
853 add r10, r10, r19 ;b 151f
854 add r10, r10, r20 ;b 151f
855 add r10, r10, r21 ;b 151f
856 add r10, r10, r22 ;b 151f
857 add r10, r10, r23 ;b 151f
858 add r10, r10, r24 ;b 151f
859 add r10, r10, r25 ;b 151f
860 add r10, r10, r26 ;b 151f
861 add r10, r10, r27 ;b 151f
862 add r10, r10, r28 ;b 151f
863 add r10, r10, r29 ;b 151f
864 add r10, r10, r30 ;b 151f
867 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
868 beq 152f /* if reg RA is zero, don't add it */
869 addi r11, r11, 150b@l /* add start of table */
870 mtctr r11 /* load ctr with jump address */
871 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
872 bctr /* jump into table */
875 mtctr r11 /* restore ctr reg from DAR */
876 mtdar r10 /* save fault EA to DAR */
877 mfspr r10,SPRN_SPRG_SCRATCH2
878 b DARFixed /* Go back to normal TLB handling */
880 /* special handling for r10,r11 since these are modified already */
881 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
882 add r10, r10, r11 /* add it */
883 mfctr r11 /* restore r11 */
885 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
886 add r10, r10, r11 /* add it */
887 mfctr r11 /* restore r11 */
892 * This is where the main kernel code starts.
897 ori r2,r2,init_task@l
899 /* ptr to phys current thread */
901 addi r4,r4,THREAD /* init task's THREAD */
902 mtspr SPRN_SPRG_THREAD,r4
905 lis r1,init_thread_union@ha
906 addi r1,r1,init_thread_union@l
908 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
910 bl early_init /* We have to do this with MMU on */
913 * Decide what sort of machine this is and initialize the MMU.
921 * Go back to running unmapped so we can load up new values
922 * and change to using our exception vectors.
923 * On the 8xx, all we have to do is invalidate the TLB to clear
924 * the old 8M byte TLB mappings and load the page table base register.
926 /* The right way to do this would be to track it down through
927 * init's THREAD like the context switch code does, but this is
928 * easier......until someone changes init's static structures.
930 lis r6, swapper_pg_dir@ha
932 #ifdef CONFIG_8xx_CPU6
933 lis r4, cpu6_errata_word@h
934 ori r4, r4, cpu6_errata_word@l
943 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
947 /* Load up the kernel context */
949 tlbia /* Clear all TLB entries */
950 sync /* wait for tlbia/tlbie to finish */
952 /* set up the PTE pointers for the Abatron bdiGDB.
955 lis r5, abatron_pteptrs@h
956 ori r5, r5, abatron_pteptrs@l
957 stw r5, 0xf0(0) /* Must match your Abatron config file */
961 /* Now turn on the MMU for real! */
963 lis r3,start_kernel@h
964 ori r3,r3,start_kernel@l
967 rfi /* enable MMU and jump to start_kernel */
969 /* Set up the initial MMU state so we can do the first level of
970 * kernel initialization. This maps the first 8 MBytes of memory 1:1
971 * virtual to physical. Also, set the cache mode since that is defined
972 * by TLB entries and perform any additional mapping (like of the IMMR).
973 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
974 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
975 * these mappings is mapped by page tables.
979 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
980 lis r10, MD_RESETVAL@h
981 #ifndef CONFIG_8xx_COPYBACK
982 oris r10, r10, MD_WTDEF@h
984 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */
986 tlbia /* Invalidate all TLB entries */
987 #ifdef CONFIG_PIN_TLB_TEXT
991 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
994 #ifdef CONFIG_PIN_TLB_DATA
995 oris r10, r10, MD_RSV4I@h
996 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
999 /* Now map the lower 8 Meg into the ITLB. */
1000 lis r8, KERNELBASE@h /* Create vaddr for TLB */
1001 ori r8, r8, MI_EVALID /* Mark it valid */
1002 mtspr SPRN_MI_EPN, r8
1003 li r8, MI_PS8MEG | (2 << 5) /* Set 8M byte page, APG 2 */
1004 ori r8, r8, MI_SVALID /* Make it valid */
1005 mtspr SPRN_MI_TWC, r8
1006 li r8, MI_BOOTINIT /* Create RPN for address 0 */
1007 mtspr SPRN_MI_RPN, r8 /* Store TLB entry */
1009 lis r8, MI_APG_INIT@h /* Set protection modes */
1010 ori r8, r8, MI_APG_INIT@l
1011 mtspr SPRN_MI_AP, r8
1012 lis r8, MD_APG_INIT@h
1013 ori r8, r8, MD_APG_INIT@l
1014 mtspr SPRN_MD_AP, r8
1016 /* Map a 512k page for the IMMR to get the processor
1017 * internal registers (among other things).
1019 #ifdef CONFIG_PIN_TLB_IMMR
1020 oris r10, r10, MD_RSV4I@h
1021 ori r10, r10, 0x1c00
1022 mtspr SPRN_MD_CTR, r10
1024 mfspr r9, 638 /* Get current IMMR */
1025 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */
1027 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */
1028 ori r8, r8, MD_EVALID /* Mark it valid */
1029 mtspr SPRN_MD_EPN, r8
1030 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */
1031 ori r8, r8, MD_SVALID /* Make it valid */
1032 mtspr SPRN_MD_TWC, r8
1033 mr r8, r9 /* Create paddr for TLB */
1034 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
1035 mtspr SPRN_MD_RPN, r8
1038 /* Since the cache is enabled according to the information we
1039 * just loaded into the TLB, invalidate and enable the caches here.
1040 * We should probably check/set other modes....later.
1042 lis r8, IDC_INVALL@h
1043 mtspr SPRN_IC_CST, r8
1044 mtspr SPRN_DC_CST, r8
1045 lis r8, IDC_ENABLE@h
1046 mtspr SPRN_IC_CST, r8
1047 #ifdef CONFIG_8xx_COPYBACK
1048 mtspr SPRN_DC_CST, r8
1050 /* For a debug option, I left this here to easily enable
1051 * the write through cache mode
1054 mtspr SPRN_DC_CST, r8
1055 lis r8, IDC_ENABLE@h
1056 mtspr SPRN_DC_CST, r8
1058 /* Disable debug mode entry on breakpoints */
1060 #ifdef CONFIG_PPC_8xx_PERF_EVENT
1061 rlwinm r8, r8, 0, ~0xc
1063 rlwinm r8, r8, 0, ~0x8
1070 * We put a few things here that have to be page-aligned.
1071 * This stuff goes at the beginning of the data segment,
1072 * which is page-aligned.
1077 .globl empty_zero_page
1081 EXPORT_SYMBOL(empty_zero_page)
1083 .globl swapper_pg_dir
1085 .space PGD_TABLE_SIZE
1087 /* Room for two PTE table poiners, usually the kernel and current user
1088 * pointer to their respective root page table (pgdir).
1093 #ifdef CONFIG_8xx_CPU6
1094 .globl cpu6_errata_word
1099 #ifdef CONFIG_PPC_8xx_PERF_EVENT
1100 .globl itlb_miss_counter
1104 .globl dtlb_miss_counter
1108 .globl instruction_counter
1109 instruction_counter: