1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications by Dan Malek
11 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 * This file contains low-level support and setup for PowerPC 8xx
14 * embedded processors, including trap and interrupt dispatch.
17 #include <linux/init.h>
18 #include <linux/magic.h>
19 #include <asm/processor.h>
22 #include <asm/cache.h>
23 #include <asm/pgtable.h>
24 #include <asm/cputable.h>
25 #include <asm/thread_info.h>
26 #include <asm/ppc_asm.h>
27 #include <asm/asm-offsets.h>
28 #include <asm/ptrace.h>
29 #include <asm/export.h>
30 #include <asm/code-patching-asm.h>
34 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
35 /* By simply checking Address >= 0x80000000, we know if its a kernel address */
36 #define SIMPLE_KERNEL_ADDRESS 1
40 * We need an ITLB miss handler for kernel addresses if:
41 * - Either we have modules
42 * - Or we have not pinned the first 8M
44 #if defined(CONFIG_MODULES) || !defined(CONFIG_PIN_TLB_TEXT) || \
45 defined(CONFIG_DEBUG_PAGEALLOC)
46 #define ITLB_MISS_KERNEL 1
50 * Value for the bits that have fixed value in RPN entries.
51 * Also used for tagging DAR for DTLBerror.
53 #define RPN_PATTERN 0x00f0
55 #define PAGE_SHIFT_512K 19
56 #define PAGE_SHIFT_8M 23
63 * This port was done on an MBX board with an 860. Right now I only
64 * support an ELF compressed (zImage) boot from EPPC-Bug because the
65 * code there loads up some registers before calling us:
66 * r3: ptr to board info data
67 * r4: initrd_start or if no initrd then 0
68 * r5: initrd_end - unused if r4 is 0
69 * r6: Start of command line string
70 * r7: End of command line string
72 * I decided to use conditional compilation instead of checking PVR and
73 * adding more processor specific branches around code I don't need.
74 * Since this is an embedded processor, I also appreciate any memory
77 * The MPC8xx does not have any BATs, but it supports large page sizes.
78 * We first initialize the MMU to support 8M byte pages, then load one
79 * entry into each of the instruction and data TLBs to map the first
80 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
81 * the "internal" processor registers before MMU_init is called.
87 mr r31,r3 /* save device tree ptr */
89 /* We have to turn on the MMU right away so we get cache modes
94 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
100 ori r0,r0,MSR_DR|MSR_IR
103 ori r0,r0,start_here@l
105 rfi /* enables MMU */
108 #ifdef CONFIG_PERF_EVENTS
111 .globl itlb_miss_counter
115 .globl dtlb_miss_counter
119 .globl instruction_counter
125 EXCEPTION(0x100, Reset, system_reset_exception, EXC_XFER_STD)
134 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
137 addi r3,r1,STACK_FRAME_OVERHEAD
138 EXC_XFER_STD(0x200, machine_check_exception)
140 /* Data access exception.
141 * This is "never generated" by the MPC8xx.
146 /* Instruction access exception.
147 * This is "never generated" by the MPC8xx.
152 /* External interrupt */
153 EXCEPTION(0x500, HardwareInterrupt, do_IRQ, EXC_XFER_LITE)
155 /* Alignment exception */
162 mtspr SPRN_DAR,r5 /* Tag DAR, to be used in DTLB Error */
165 addi r3,r1,STACK_FRAME_OVERHEAD
166 EXC_XFER_STD(0x600, alignment_exception)
168 /* Program check exception */
169 EXCEPTION(0x700, ProgramCheck, program_check_exception, EXC_XFER_STD)
171 /* No FPU on MPC8xx. This exception is not supposed to happen.
173 EXCEPTION(0x800, FPUnavailable, unknown_exception, EXC_XFER_STD)
176 EXCEPTION(0x900, Decrementer, timer_interrupt, EXC_XFER_LITE)
178 EXCEPTION(0xa00, Trap_0a, unknown_exception, EXC_XFER_STD)
179 EXCEPTION(0xb00, Trap_0b, unknown_exception, EXC_XFER_STD)
186 /* Single step - not used on 601 */
187 EXCEPTION(0xd00, SingleStep, single_step_exception, EXC_XFER_STD)
188 EXCEPTION(0xe00, Trap_0e, unknown_exception, EXC_XFER_STD)
189 EXCEPTION(0xf00, Trap_0f, unknown_exception, EXC_XFER_STD)
191 /* On the MPC8xx, this is a software emulation interrupt. It occurs
192 * for all unimplemented and illegal instructions.
194 EXCEPTION(0x1000, SoftEmu, emulation_assist_interrupt, EXC_XFER_STD)
196 /* Called from DataStoreTLBMiss when perf TLB misses events are activated */
197 #ifdef CONFIG_PERF_EVENTS
198 patch_site 0f, patch__dtlbmiss_perf
199 0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
201 stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
202 mfspr r10, SPRN_SPRG_SCRATCH0
203 mfspr r11, SPRN_SPRG_SCRATCH1
209 * For the MPC8xx, this is a software tablewalk to load the instruction
210 * TLB. The task switch loads the M_TWB register with the pointer to the first
212 * If we discover there is no second level table (value is zero) or if there
213 * is an invalid pte, we load that into the TLB, which causes another fault
214 * into the TLB Error interrupt where we can handle such problems.
215 * We have to use the MD_xxx registers for the tablewalk because the
216 * equivalent MI_xxx registers only perform the attribute functions.
219 #ifdef CONFIG_8xx_CPU15
220 #define INVALIDATE_ADJACENT_PAGES_CPU15(addr) \
221 addi addr, addr, PAGE_SIZE; \
223 addi addr, addr, -(PAGE_SIZE << 1); \
225 addi addr, addr, PAGE_SIZE
227 #define INVALIDATE_ADJACENT_PAGES_CPU15(addr)
231 mtspr SPRN_SPRG_SCRATCH0, r10
232 mtspr SPRN_SPRG_SCRATCH1, r11
234 /* If we are faulting a kernel address, we have to use the
235 * kernel page tables.
237 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
238 INVALIDATE_ADJACENT_PAGES_CPU15(r10)
239 mtspr SPRN_MD_EPN, r10
240 /* Only modules will cause ITLB Misses as we always
241 * pin the first 8MB of kernel memory */
242 #ifdef ITLB_MISS_KERNEL
244 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
245 cmpi cr0, r10, 0 /* Address >= 0x80000000 */
247 rlwinm r10, r10, 16, 0xfff8
248 cmpli cr0, r10, PAGE_OFFSET@h
249 #ifndef CONFIG_PIN_TLB_TEXT
250 /* It is assumed that kernel code fits into the first 32M */
251 0: cmpli cr7, r10, (PAGE_OFFSET + 0x2000000)@h
252 patch_site 0b, patch__itlbmiss_linmem_top
256 mfspr r10, SPRN_M_TWB /* Get level 1 table */
257 #ifdef ITLB_MISS_KERNEL
258 #if defined(SIMPLE_KERNEL_ADDRESS) && defined(CONFIG_PIN_TLB_TEXT)
263 #ifndef CONFIG_PIN_TLB_TEXT
264 blt cr7, ITLBMissLinear
266 rlwinm r10, r10, 0, 20, 31
267 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
270 lwz r10, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
271 mtspr SPRN_MI_TWC, r10 /* Set segment attributes */
273 mtspr SPRN_MD_TWC, r10
274 mfspr r10, SPRN_MD_TWC
275 lwz r10, 0(r10) /* Get the pte */
276 #ifdef ITLB_MISS_KERNEL
279 rlwinm r11, r10, 32-7, _PAGE_PRESENT
281 rlwimi r10, r11, 0, _PAGE_PRESENT
282 /* The Linux PTE won't go exactly into the MMU TLB.
283 * Software indicator bits 20 and 23 must be clear.
284 * Software indicator bits 22, 24, 25, 26, and 27 must be
285 * set. All other Linux PTE bits control the behavior
288 rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */
289 rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
290 ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
291 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
293 /* Restore registers */
294 0: mfspr r10, SPRN_SPRG_SCRATCH0
295 mfspr r11, SPRN_SPRG_SCRATCH1
297 patch_site 0b, patch__itlbmiss_exit_1
299 #ifdef CONFIG_PERF_EVENTS
300 patch_site 0f, patch__itlbmiss_perf
301 0: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
303 stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
304 mfspr r10, SPRN_SPRG_SCRATCH0
305 mfspr r11, SPRN_SPRG_SCRATCH1
309 #ifndef CONFIG_PIN_TLB_TEXT
312 #if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_ETEXT_SHIFT < 23
313 patch_site 0f, patch__itlbmiss_linmem_top8
316 0: subis r11, r10, (PAGE_OFFSET - 0x80000000)@ha
317 rlwinm r11, r11, 4, MI_PS8MEG ^ MI_PS512K
318 ori r11, r11, MI_PS512K | MI_SVALID
319 rlwinm r10, r10, 0, 0x0ff80000 /* 8xx supports max 256Mb RAM */
321 /* Set 8M byte page and mark it valid */
322 li r11, MI_PS8MEG | MI_SVALID
323 rlwinm r10, r10, 20, 0x0f800000 /* 8xx supports max 256Mb RAM */
325 mtspr SPRN_MI_TWC, r11
326 ori r10, r10, 0xf0 | MI_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
328 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
330 0: mfspr r10, SPRN_SPRG_SCRATCH0
331 mfspr r11, SPRN_SPRG_SCRATCH1
333 patch_site 0b, patch__itlbmiss_exit_2
338 mtspr SPRN_SPRG_SCRATCH0, r10
339 mtspr SPRN_SPRG_SCRATCH1, r11
342 /* If we are faulting a kernel address, we have to use the
343 * kernel page tables.
345 mfspr r10, SPRN_MD_EPN
346 rlwinm r10, r10, 16, 0xfff8
347 cmpli cr0, r10, PAGE_OFFSET@h
348 #ifndef CONFIG_PIN_TLB_IMMR
349 cmpli cr6, r10, VIRT_IMMR_BASE@h
351 0: cmpli cr7, r10, (PAGE_OFFSET + 0x2000000)@h
352 patch_site 0b, patch__dtlbmiss_linmem_top
354 mfspr r10, SPRN_M_TWB /* Get level 1 table */
356 #ifndef CONFIG_PIN_TLB_IMMR
357 0: beq- cr6, DTLBMissIMMR
358 patch_site 0b, patch__dtlbmiss_immr_jmp
360 blt cr7, DTLBMissLinear
361 rlwinm r10, r10, 0, 20, 31
362 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
365 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
367 mtspr SPRN_MD_TWC, r11
368 mfspr r10, SPRN_MD_TWC
369 lwz r10, 0(r10) /* Get the pte */
371 /* Insert the Guarded flag into the TWC from the Linux PTE.
372 * It is bit 27 of both the Linux PTE and the TWC (at least
373 * I got that right :-). It will be better when we can put
374 * this into the Linux pgd/pmd and load it in the operation
377 rlwimi r11, r10, 0, _PAGE_GUARDED
378 mtspr SPRN_MD_TWC, r11
380 /* Both _PAGE_ACCESSED and _PAGE_PRESENT has to be set.
381 * We also need to know if the insn is a load/store, so:
382 * Clear _PAGE_PRESENT and load that which will
383 * trap into DTLB Error with store bit set accordinly.
385 /* PRESENT=0x1, ACCESSED=0x20
386 * r11 = ((r10 & PRESENT) & ((r10 & ACCESSED) >> 5));
387 * r10 = (r10 & ~PRESENT) | r11;
389 rlwinm r11, r10, 32-7, _PAGE_PRESENT
391 rlwimi r10, r11, 0, _PAGE_PRESENT
392 /* The Linux PTE won't go exactly into the MMU TLB.
393 * Software indicator bits 24, 25, 26, and 27 must be
394 * set. All other Linux PTE bits control the behavior
398 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */
399 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
401 /* Restore registers */
402 mtspr SPRN_DAR, r11 /* Tag DAR */
404 0: mfspr r10, SPRN_SPRG_SCRATCH0
405 mfspr r11, SPRN_SPRG_SCRATCH1
407 patch_site 0b, patch__dtlbmiss_exit_1
411 /* Set 512k byte guarded page and mark it valid */
412 li r10, MD_PS512K | MD_GUARDED | MD_SVALID
413 mtspr SPRN_MD_TWC, r10
414 mfspr r10, SPRN_IMMR /* Get current IMMR */
415 rlwinm r10, r10, 0, 0xfff80000 /* Get 512 kbytes boundary */
416 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
417 _PAGE_PRESENT | _PAGE_NO_CACHE
418 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
421 mtspr SPRN_DAR, r11 /* Tag DAR */
423 0: mfspr r10, SPRN_SPRG_SCRATCH0
424 mfspr r11, SPRN_SPRG_SCRATCH1
426 patch_site 0b, patch__dtlbmiss_exit_2
430 rlwinm r10, r10, 20, 0x0f800000 /* 8xx supports max 256Mb RAM */
431 #if defined(CONFIG_STRICT_KERNEL_RWX) && CONFIG_DATA_SHIFT < 23
432 patch_site 0f, patch__dtlbmiss_romem_top8
434 0: subis r11, r10, (PAGE_OFFSET - 0x80000000)@ha
435 rlwinm r11, r11, 0, 0xff800000
438 rlwinm r11, r11, 4, MI_PS8MEG ^ MI_PS512K
439 ori r11, r11, MI_PS512K | MI_SVALID
440 mfspr r10, SPRN_MD_EPN
441 rlwinm r10, r10, 0, 0x0ff80000 /* 8xx supports max 256Mb RAM */
443 /* Set 8M byte page and mark it valid */
444 li r11, MD_PS8MEG | MD_SVALID
446 mtspr SPRN_MD_TWC, r11
447 #ifdef CONFIG_STRICT_KERNEL_RWX
448 patch_site 0f, patch__dtlbmiss_romem_top
451 rlwimi r10, r11, 11, _PAGE_RO
453 ori r10, r10, 0xf0 | MD_SPS16K | _PAGE_SH | _PAGE_DIRTY | \
455 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
458 mtspr SPRN_DAR, r11 /* Tag DAR */
460 0: mfspr r10, SPRN_SPRG_SCRATCH0
461 mfspr r11, SPRN_SPRG_SCRATCH1
463 patch_site 0b, patch__dtlbmiss_exit_3
465 /* This is an instruction TLB error on the MPC8xx. This could be due
466 * to many reasons, such as executing guarded memory or illegal instruction
467 * addresses. There is nothing to do but handle a big time error fault.
473 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
474 andis. r10,r9,SRR1_ISI_NOPT@h
477 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
479 EXC_XFER_LITE(0x400, handle_page_fault)
481 /* This is the data TLB error on the MPC8xx. This could be due to
482 * many reasons, including a dirty update to a pte. We bail out to
483 * a higher level function that can handle it.
487 mtspr SPRN_SPRG_SCRATCH0, r10
488 mtspr SPRN_SPRG_SCRATCH1, r11
492 cmpwi cr0, r11, RPN_PATTERN
493 beq- FixupDAR /* must be a buggy dcbX, icbi insn. */
494 DARFixed:/* Return from dcbx instruction bug workaround */
500 andis. r10,r5,DSISR_NOHPTE@h
505 mtspr SPRN_DAR,r10 /* Tag DAR, to be used in DTLB Error */
506 /* 0x300 is DataAccess exception, needed by bad_page_fault() */
507 EXC_XFER_LITE(0x300, handle_page_fault)
509 EXCEPTION(0x1500, Trap_15, unknown_exception, EXC_XFER_STD)
510 EXCEPTION(0x1600, Trap_16, unknown_exception, EXC_XFER_STD)
511 EXCEPTION(0x1700, Trap_17, unknown_exception, EXC_XFER_STD)
512 EXCEPTION(0x1800, Trap_18, unknown_exception, EXC_XFER_STD)
513 EXCEPTION(0x1900, Trap_19, unknown_exception, EXC_XFER_STD)
514 EXCEPTION(0x1a00, Trap_1a, unknown_exception, EXC_XFER_STD)
515 EXCEPTION(0x1b00, Trap_1b, unknown_exception, EXC_XFER_STD)
517 /* On the MPC8xx, these next four traps are used for development
518 * support of breakpoints and such. Someday I will get around to
523 mtspr SPRN_SPRG_SCRATCH0, r10
524 mtspr SPRN_SPRG_SCRATCH1, r11
527 cmplwi cr0, r11, (.Ldtlbie - PAGE_OFFSET)@l
528 cmplwi cr7, r11, (.Litlbie - PAGE_OFFSET)@l
533 addi r3,r1,STACK_FRAME_OVERHEAD
537 EXC_XFER_STD(0x1c00, do_break)
540 mfspr r10, SPRN_SPRG_SCRATCH0
541 mfspr r11, SPRN_SPRG_SCRATCH1
544 #ifdef CONFIG_PERF_EVENTS
546 InstructionBreakpoint:
547 mtspr SPRN_SPRG_SCRATCH0, r10
548 lwz r10, (instruction_counter - PAGE_OFFSET)@l(0)
550 stw r10, (instruction_counter - PAGE_OFFSET)@l(0)
553 mtspr SPRN_COUNTA, r10
554 mfspr r10, SPRN_SPRG_SCRATCH0
557 EXCEPTION(0x1d00, Trap_1d, unknown_exception, EXC_XFER_STD)
559 EXCEPTION(0x1e00, Trap_1e, unknown_exception, EXC_XFER_STD)
560 EXCEPTION(0x1f00, Trap_1f, unknown_exception, EXC_XFER_STD)
564 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
565 * by decoding the registers used by the dcbx instruction and adding them.
566 * DAR is set to the calculated address.
568 FixupDAR:/* Entry point for dcbx workaround. */
570 /* fetch instruction from memory. */
572 mtspr SPRN_MD_EPN, r10
573 rlwinm r11, r10, 16, 0xfff8
574 cmpli cr0, r11, PAGE_OFFSET@h
575 mfspr r11, SPRN_M_TWB /* Get level 1 table */
577 rlwinm r11, r10, 16, 0xfff8
579 0: cmpli cr7, r11, (PAGE_OFFSET + 0x1800000)@h
580 patch_site 0b, patch__fixupdar_linmem_top
582 /* create physical page address from effective address */
585 mfspr r11, SPRN_M_TWB /* Get level 1 table */
586 rlwinm r11, r11, 0, 20, 31
587 oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
589 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
590 mtspr SPRN_MD_TWC, r11
592 mfspr r11, SPRN_MD_TWC
593 lwz r11, 0(r11) /* Get the pte */
594 bt 28,200f /* bit 28 = Large page (8M) */
595 bt 29,202f /* bit 29 = Large page (8M or 512K) */
596 /* concat physical page address(r11) and page offset(r10) */
597 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
599 /* Check if it really is a dcbx instruction. */
600 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
601 * no need to include them here */
602 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
603 rlwinm r10, r10, 0, 21, 5
604 cmpwi cr0, r10, 2028 /* Is dcbz? */
606 cmpwi cr0, r10, 940 /* Is dcbi? */
608 cmpwi cr0, r10, 108 /* Is dcbst? */
609 beq+ 144f /* Fix up store bit! */
610 cmpwi cr0, r10, 172 /* Is dcbf? */
612 cmpwi cr0, r10, 1964 /* Is icbi? */
614 141: mfspr r10,SPRN_M_TW
615 b DARFixed /* Nope, go back to normal TLB processing */
618 /* concat physical page address(r11) and page offset(r10) */
619 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
623 /* concat physical page address(r11) and page offset(r10) */
624 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_512K, 31
627 144: mfspr r10, SPRN_DSISR
628 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
629 mtspr SPRN_DSISR, r10
630 142: /* continue, it was a dcbx, dcbi instruction. */
632 mtdar r10 /* save ctr reg in DAR */
633 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
634 addi r10, r10, 150f@l /* add start of table */
635 mtctr r10 /* load ctr with jump address */
636 xor r10, r10, r10 /* sum starts at zero */
637 bctr /* jump into table */
639 add r10, r10, r0 ;b 151f
640 add r10, r10, r1 ;b 151f
641 add r10, r10, r2 ;b 151f
642 add r10, r10, r3 ;b 151f
643 add r10, r10, r4 ;b 151f
644 add r10, r10, r5 ;b 151f
645 add r10, r10, r6 ;b 151f
646 add r10, r10, r7 ;b 151f
647 add r10, r10, r8 ;b 151f
648 add r10, r10, r9 ;b 151f
649 mtctr r11 ;b 154f /* r10 needs special handling */
650 mtctr r11 ;b 153f /* r11 needs special handling */
651 add r10, r10, r12 ;b 151f
652 add r10, r10, r13 ;b 151f
653 add r10, r10, r14 ;b 151f
654 add r10, r10, r15 ;b 151f
655 add r10, r10, r16 ;b 151f
656 add r10, r10, r17 ;b 151f
657 add r10, r10, r18 ;b 151f
658 add r10, r10, r19 ;b 151f
659 add r10, r10, r20 ;b 151f
660 add r10, r10, r21 ;b 151f
661 add r10, r10, r22 ;b 151f
662 add r10, r10, r23 ;b 151f
663 add r10, r10, r24 ;b 151f
664 add r10, r10, r25 ;b 151f
665 add r10, r10, r26 ;b 151f
666 add r10, r10, r27 ;b 151f
667 add r10, r10, r28 ;b 151f
668 add r10, r10, r29 ;b 151f
669 add r10, r10, r30 ;b 151f
672 rlwinm. r11,r11,19,24,28 /* offset into jump table for reg RA */
673 beq 152f /* if reg RA is zero, don't add it */
674 addi r11, r11, 150b@l /* add start of table */
675 mtctr r11 /* load ctr with jump address */
676 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
677 bctr /* jump into table */
680 mtctr r11 /* restore ctr reg from DAR */
681 mtdar r10 /* save fault EA to DAR */
683 b DARFixed /* Go back to normal TLB handling */
685 /* special handling for r10,r11 since these are modified already */
686 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
687 add r10, r10, r11 /* add it */
688 mfctr r11 /* restore r11 */
690 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
691 add r10, r10, r11 /* add it */
692 mfctr r11 /* restore r11 */
696 * This is where the main kernel code starts.
701 ori r2,r2,init_task@l
703 /* ptr to phys current thread */
705 addi r4,r4,THREAD /* init task's THREAD */
706 mtspr SPRN_SPRG_THREAD,r4
709 lis r1,init_thread_union@ha
710 addi r1,r1,init_thread_union@l
711 lis r0, STACK_END_MAGIC@h
712 ori r0, r0, STACK_END_MAGIC@l
715 stwu r0,THREAD_SIZE-STACK_FRAME_OVERHEAD(r1)
717 lis r6, swapper_pg_dir@ha
721 bl early_init /* We have to do this with MMU on */
724 * Decide what sort of machine this is and initialize the MMU.
735 * Go back to running unmapped so we can load up new values
736 * and change to using our exception vectors.
737 * On the 8xx, all we have to do is invalidate the TLB to clear
738 * the old 8M byte TLB mappings and load the page table base register.
740 /* The right way to do this would be to track it down through
741 * init's THREAD like the context switch code does, but this is
742 * easier......until someone changes init's static structures.
747 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
751 /* Load up the kernel context */
753 tlbia /* Clear all TLB entries */
754 sync /* wait for tlbia/tlbie to finish */
756 /* set up the PTE pointers for the Abatron bdiGDB.
758 lis r5, abatron_pteptrs@h
759 ori r5, r5, abatron_pteptrs@l
760 stw r5, 0xf0(0) /* Must match your Abatron config file */
762 lis r6, swapper_pg_dir@h
763 ori r6, r6, swapper_pg_dir@l
766 /* Now turn on the MMU for real! */
768 lis r3,start_kernel@h
769 ori r3,r3,start_kernel@l
772 rfi /* enable MMU and jump to start_kernel */
774 /* Set up the initial MMU state so we can do the first level of
775 * kernel initialization. This maps the first 8 MBytes of memory 1:1
776 * virtual to physical. Also, set the cache mode since that is defined
777 * by TLB entries and perform any additional mapping (like of the IMMR).
778 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
779 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
780 * these mappings is mapped by page tables.
784 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
785 lis r10, MD_RESETVAL@h
786 #ifndef CONFIG_8xx_COPYBACK
787 oris r10, r10, MD_WTDEF@h
789 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */
791 tlbia /* Invalidate all TLB entries */
792 #ifdef CONFIG_PIN_TLB_DATA
793 oris r10, r10, MD_RSV4I@h
794 mtspr SPRN_MD_CTR, r10 /* Set data TLB control */
797 lis r8, MI_APG_INIT@h /* Set protection modes */
798 ori r8, r8, MI_APG_INIT@l
800 lis r8, MD_APG_INIT@h
801 ori r8, r8, MD_APG_INIT@l
804 /* Map a 512k page for the IMMR to get the processor
805 * internal registers (among other things).
807 #ifdef CONFIG_PIN_TLB_IMMR
808 oris r10, r10, MD_RSV4I@h
810 mtspr SPRN_MD_CTR, r10
812 mfspr r9, 638 /* Get current IMMR */
813 andis. r9, r9, 0xfff8 /* Get 512 kbytes boundary */
815 lis r8, VIRT_IMMR_BASE@h /* Create vaddr for TLB */
816 ori r8, r8, MD_EVALID /* Mark it valid */
817 mtspr SPRN_MD_EPN, r8
818 li r8, MD_PS512K | MD_GUARDED /* Set 512k byte page */
819 ori r8, r8, MD_SVALID /* Make it valid */
820 mtspr SPRN_MD_TWC, r8
821 mr r8, r9 /* Create paddr for TLB */
822 ori r8, r8, MI_BOOTINIT|0x2 /* Inhibit cache -- Cort */
823 mtspr SPRN_MD_RPN, r8
826 /* Now map the lower RAM (up to 32 Mbytes) into the ITLB. */
827 #ifdef CONFIG_PIN_TLB_TEXT
831 li r9, 4 /* up to 4 pages of 8M */
833 lis r9, KERNELBASE@h /* Create vaddr for TLB */
834 li r10, MI_PS8MEG | MI_SVALID /* Set 8M byte page */
835 li r11, MI_BOOTINIT /* Create RPN for address 0 */
836 lis r12, _einittext@h
837 ori r12, r12, _einittext@l
839 #ifdef CONFIG_PIN_TLB_TEXT
840 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
844 ori r0, r9, MI_EVALID /* Mark it valid */
845 mtspr SPRN_MI_EPN, r0
846 mtspr SPRN_MI_TWC, r10
847 mtspr SPRN_MI_RPN, r11 /* Store TLB entry */
854 /* Since the cache is enabled according to the information we
855 * just loaded into the TLB, invalidate and enable the caches here.
856 * We should probably check/set other modes....later.
859 mtspr SPRN_IC_CST, r8
860 mtspr SPRN_DC_CST, r8
862 mtspr SPRN_IC_CST, r8
863 #ifdef CONFIG_8xx_COPYBACK
864 mtspr SPRN_DC_CST, r8
866 /* For a debug option, I left this here to easily enable
867 * the write through cache mode
870 mtspr SPRN_DC_CST, r8
872 mtspr SPRN_DC_CST, r8
874 /* Disable debug mode entry on breakpoints */
876 #ifdef CONFIG_PERF_EVENTS
877 rlwinm r8, r8, 0, ~0xc
879 rlwinm r8, r8, 0, ~0x8
886 * We put a few things here that have to be page-aligned.
887 * This stuff goes at the beginning of the data segment,
888 * which is page-aligned.
893 .globl empty_zero_page
897 EXPORT_SYMBOL(empty_zero_page)
899 .globl swapper_pg_dir
901 .space PGD_TABLE_SIZE
903 /* Room for two PTE table poiners, usually the kernel and current user
904 * pointer to their respective root page table (pgdir).
906 .globl abatron_pteptrs