1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
5 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
6 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications by Dan Malek
11 * Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
13 * This file contains low-level support and setup for PowerPC 8xx
14 * embedded processors, including trap and interrupt dispatch.
17 #include <linux/init.h>
18 #include <linux/magic.h>
19 #include <linux/pgtable.h>
20 #include <linux/sizes.h>
21 #include <linux/linkage.h>
23 #include <asm/processor.h>
26 #include <asm/cache.h>
27 #include <asm/cputable.h>
28 #include <asm/thread_info.h>
29 #include <asm/ppc_asm.h>
30 #include <asm/asm-offsets.h>
31 #include <asm/ptrace.h>
32 #include <asm/code-patching-asm.h>
33 #include <asm/interrupt.h>
36 * Value for the bits that have fixed value in RPN entries.
37 * Also used for tagging DAR for DTLBerror.
39 #define RPN_PATTERN 0x00f0
43 .macro compare_to_kernel_boundary scratch, addr
44 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
45 /* By simply checking Address >= 0x80000000, we know if its a kernel address */
48 rlwinm \scratch, \addr, 16, 0xfff8
49 cmpli cr0, \scratch, PAGE_OFFSET@h
53 #define PAGE_SHIFT_512K 19
54 #define PAGE_SHIFT_8M 23
61 * This port was done on an MBX board with an 860. Right now I only
62 * support an ELF compressed (zImage) boot from EPPC-Bug because the
63 * code there loads up some registers before calling us:
64 * r3: ptr to board info data
65 * r4: initrd_start or if no initrd then 0
66 * r5: initrd_end - unused if r4 is 0
67 * r6: Start of command line string
68 * r7: End of command line string
70 * I decided to use conditional compilation instead of checking PVR and
71 * adding more processor specific branches around code I don't need.
72 * Since this is an embedded processor, I also appreciate any memory
75 * The MPC8xx does not have any BATs, but it supports large page sizes.
76 * We first initialize the MMU to support 8M byte pages, then load one
77 * entry into each of the instruction and data TLBs to map the first
78 * 8M 1:1. I also mapped an additional I/O space 1:1 so we can get to
79 * the "internal" processor registers before MMU_init is called.
85 mr r31,r3 /* save device tree ptr */
87 /* We have to turn on the MMU right away so we get cache modes
92 /* We now have the lower 8 Meg mapped into TLB entries, and the caches
98 ori r0,r0,MSR_DR|MSR_IR
101 ori r0,r0,start_here@l
103 rfi /* enables MMU */
106 #ifdef CONFIG_PERF_EVENTS
109 .globl itlb_miss_counter
113 .globl dtlb_miss_counter
117 .globl instruction_counter
123 EXCEPTION(INTERRUPT_SYSTEM_RESET, Reset, system_reset_exception)
126 START_EXCEPTION(INTERRUPT_MACHINE_CHECK, MachineCheck)
127 EXCEPTION_PROLOG INTERRUPT_MACHINE_CHECK MachineCheck handle_dar_dsisr=1
128 prepare_transfer_to_handler
129 bl machine_check_exception
132 /* External interrupt */
133 EXCEPTION(INTERRUPT_EXTERNAL, HardwareInterrupt, do_IRQ)
135 /* Alignment exception */
136 START_EXCEPTION(INTERRUPT_ALIGNMENT, Alignment)
137 EXCEPTION_PROLOG INTERRUPT_ALIGNMENT Alignment handle_dar_dsisr=1
138 prepare_transfer_to_handler
139 bl alignment_exception
143 /* Program check exception */
144 START_EXCEPTION(INTERRUPT_PROGRAM, ProgramCheck)
145 EXCEPTION_PROLOG INTERRUPT_PROGRAM ProgramCheck
146 prepare_transfer_to_handler
147 bl program_check_exception
152 EXCEPTION(INTERRUPT_DECREMENTER, Decrementer, timer_interrupt)
155 START_EXCEPTION(INTERRUPT_SYSCALL, SystemCall)
156 SYSCALL_ENTRY INTERRUPT_SYSCALL
158 /* Single step - not used on 601 */
159 EXCEPTION(INTERRUPT_TRACE, SingleStep, single_step_exception)
161 /* On the MPC8xx, this is a software emulation interrupt. It occurs
162 * for all unimplemented and illegal instructions.
164 START_EXCEPTION(INTERRUPT_SOFT_EMU_8xx, SoftEmu)
165 EXCEPTION_PROLOG INTERRUPT_SOFT_EMU_8xx SoftEmu
166 prepare_transfer_to_handler
167 bl emulation_assist_interrupt
172 * For the MPC8xx, this is a software tablewalk to load the instruction
173 * TLB. The task switch loads the M_TWB register with the pointer to the first
175 * If we discover there is no second level table (value is zero) or if there
176 * is an invalid pte, we load that into the TLB, which causes another fault
177 * into the TLB Error interrupt where we can handle such problems.
178 * We have to use the MD_xxx registers for the tablewalk because the
179 * equivalent MI_xxx registers only perform the attribute functions.
182 #ifdef CONFIG_8xx_CPU15
183 #define INVALIDATE_ADJACENT_PAGES_CPU15(addr, tmp) \
184 addi tmp, addr, PAGE_SIZE; \
186 addi tmp, addr, -PAGE_SIZE; \
189 #define INVALIDATE_ADJACENT_PAGES_CPU15(addr, tmp)
192 START_EXCEPTION(INTERRUPT_INST_TLB_MISS_8xx, InstructionTLBMiss)
193 mtspr SPRN_SPRG_SCRATCH2, r10
196 /* If we are faulting a kernel address, we have to use the
197 * kernel page tables.
199 mfspr r10, SPRN_SRR0 /* Get effective address of fault */
200 INVALIDATE_ADJACENT_PAGES_CPU15(r10, r11)
201 mtspr SPRN_MD_EPN, r10
202 #ifdef CONFIG_MODULES
204 compare_to_kernel_boundary r10, r10
206 mfspr r10, SPRN_M_TWB /* Get level 1 table */
207 #ifdef CONFIG_MODULES
209 rlwinm r10, r10, 0, 20, 31
210 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
214 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
215 mtspr SPRN_MD_TWC, r11
216 mfspr r10, SPRN_MD_TWC
217 lwz r10, 0(r10) /* Get the pte */
218 rlwimi r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED
219 rlwimi r11, r10, 32 - 9, _PMD_PAGE_512K
220 mtspr SPRN_MI_TWC, r11
221 /* The Linux PTE won't go exactly into the MMU TLB.
222 * Software indicator bits 20 and 23 must be clear.
223 * Software indicator bits 22, 24, 25, 26, and 27 must be
224 * set. All other Linux PTE bits control the behavior
227 rlwinm r10, r10, 0, ~0x0f00 /* Clear bits 20-23 */
228 rlwimi r10, r10, 4, 0x0400 /* Copy _PAGE_EXEC into bit 21 */
229 ori r10, r10, RPN_PATTERN | 0x200 /* Set 22 and 24-27 */
230 mtspr SPRN_MI_RPN, r10 /* Update TLB entry */
232 /* Restore registers */
233 0: mfspr r10, SPRN_SPRG_SCRATCH2
236 patch_site 0b, patch__itlbmiss_exit_1
238 #ifdef CONFIG_PERF_EVENTS
239 patch_site 0f, patch__itlbmiss_perf
240 0: lwz r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
242 stw r10, (itlb_miss_counter - PAGE_OFFSET)@l(0)
243 mfspr r10, SPRN_SPRG_SCRATCH2
248 START_EXCEPTION(INTERRUPT_DATA_TLB_MISS_8xx, DataStoreTLBMiss)
249 mtspr SPRN_SPRG_SCRATCH2, r10
253 /* If we are faulting a kernel address, we have to use the
254 * kernel page tables.
256 mfspr r10, SPRN_MD_EPN
257 compare_to_kernel_boundary r10, r10
258 mfspr r10, SPRN_M_TWB /* Get level 1 table */
260 rlwinm r10, r10, 0, 20, 31
261 oris r10, r10, (swapper_pg_dir - PAGE_OFFSET)@ha
264 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r10) /* Get level 1 entry */
266 mtspr SPRN_MD_TWC, r11
267 mfspr r10, SPRN_MD_TWC
268 lwz r10, 0(r10) /* Get the pte */
270 /* Insert Guarded and Accessed flags into the TWC from the Linux PTE.
271 * It is bit 27 of both the Linux PTE and the TWC (at least
272 * I got that right :-). It will be better when we can put
273 * this into the Linux pgd/pmd and load it in the operation
276 rlwimi r11, r10, 0, _PAGE_GUARDED | _PAGE_ACCESSED
277 rlwimi r11, r10, 32 - 9, _PMD_PAGE_512K
278 mtspr SPRN_MD_TWC, r11
280 /* The Linux PTE won't go exactly into the MMU TLB.
281 * Software indicator bits 24, 25, 26, and 27 must be
282 * set. All other Linux PTE bits control the behavior
286 rlwimi r10, r11, 0, 24, 27 /* Set 24-27 */
287 mtspr SPRN_MD_RPN, r10 /* Update TLB entry */
288 mtspr SPRN_DAR, r11 /* Tag DAR */
290 /* Restore registers */
292 0: mfspr r10, SPRN_SPRG_SCRATCH2
295 patch_site 0b, patch__dtlbmiss_exit_1
297 #ifdef CONFIG_PERF_EVENTS
298 patch_site 0f, patch__dtlbmiss_perf
299 0: lwz r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
301 stw r10, (dtlb_miss_counter - PAGE_OFFSET)@l(0)
302 mfspr r10, SPRN_SPRG_SCRATCH2
307 /* This is an instruction TLB error on the MPC8xx. This could be due
308 * to many reasons, such as executing guarded memory or illegal instruction
309 * addresses. There is nothing to do but handle a big time error fault.
311 START_EXCEPTION(INTERRUPT_INST_TLB_ERROR_8xx, InstructionTLBError)
312 /* 0x400 is InstructionAccess exception, needed by bad_page_fault() */
313 EXCEPTION_PROLOG INTERRUPT_INST_STORAGE InstructionTLBError
314 andis. r5,r9,DSISR_SRR1_MATCH_32S@h /* Filter relevant SRR1 bits */
315 andis. r10,r9,SRR1_ISI_NOPT@h
321 prepare_transfer_to_handler
325 /* This is the data TLB error on the MPC8xx. This could be due to
326 * many reasons, including a dirty update to a pte. We bail out to
327 * a higher level function that can handle it.
329 START_EXCEPTION(INTERRUPT_DATA_TLB_ERROR_8xx, DataTLBError)
330 EXCEPTION_PROLOG_0 handle_dar_dsisr=1
332 cmpwi cr1, r11, RPN_PATTERN
333 beq- cr1, FixupDAR /* must be a buggy dcbX, icbi insn. */
334 DARFixed:/* Return from dcbx instruction bug workaround */
336 /* 0x300 is DataAccess exception, needed by bad_page_fault() */
337 EXCEPTION_PROLOG_2 INTERRUPT_DATA_STORAGE DataTLBError handle_dar_dsisr=1
340 andis. r10,r5,DSISR_NOHPTE@h
344 prepare_transfer_to_handler
348 #ifdef CONFIG_VMAP_STACK
349 vmap_stack_overflow_exception
352 /* On the MPC8xx, these next four traps are used for development
353 * support of breakpoints and such. Someday I will get around to
356 START_EXCEPTION(INTERRUPT_DATA_BREAKPOINT_8xx, DataBreakpoint)
357 EXCEPTION_PROLOG_0 handle_dar_dsisr=1
359 cmplwi cr1, r11, (.Ldtlbie - PAGE_OFFSET)@l
360 cmplwi cr7, r11, (.Litlbie - PAGE_OFFSET)@l
361 cror 4*cr1+eq, 4*cr1+eq, 4*cr7+eq
364 mfspr r10, SPRN_SPRG_SCRATCH0
365 mfspr r11, SPRN_SPRG_SCRATCH1
368 1: EXCEPTION_PROLOG_1
369 EXCEPTION_PROLOG_2 INTERRUPT_DATA_BREAKPOINT_8xx DataBreakpoint handle_dar_dsisr=1
372 prepare_transfer_to_handler
377 #ifdef CONFIG_PERF_EVENTS
378 START_EXCEPTION(INTERRUPT_INST_BREAKPOINT_8xx, InstructionBreakpoint)
379 mtspr SPRN_SPRG_SCRATCH0, r10
380 lwz r10, (instruction_counter - PAGE_OFFSET)@l(0)
382 stw r10, (instruction_counter - PAGE_OFFSET)@l(0)
385 mtspr SPRN_COUNTA, r10
386 mfspr r10, SPRN_SPRG_SCRATCH0
389 EXCEPTION(INTERRUPT_INST_BREAKPOINT_8xx, Trap_1d, unknown_exception)
391 EXCEPTION(0x1e00, Trap_1e, unknown_exception)
392 EXCEPTION(0x1f00, Trap_1f, unknown_exception)
397 /* This is the procedure to calculate the data EA for buggy dcbx,dcbi instructions
398 * by decoding the registers used by the dcbx instruction and adding them.
399 * DAR is set to the calculated address.
401 FixupDAR:/* Entry point for dcbx workaround. */
403 /* fetch instruction from memory. */
405 mtspr SPRN_MD_EPN, r10
406 rlwinm r11, r10, 16, 0xfff8
407 cmpli cr1, r11, PAGE_OFFSET@h
408 mfspr r11, SPRN_M_TWB /* Get level 1 table */
411 /* create physical page address from effective address */
413 mfspr r11, SPRN_M_TWB /* Get level 1 table */
414 rlwinm r11, r11, 0, 20, 31
415 oris r11, r11, (swapper_pg_dir - PAGE_OFFSET)@ha
417 lwz r11, (swapper_pg_dir-PAGE_OFFSET)@l(r11) /* Get the level 1 entry */
418 mtspr SPRN_MD_TWC, r11
420 mfspr r11, SPRN_MD_TWC
421 lwz r11, 0(r11) /* Get the pte */
422 bt 28,200f /* bit 28 = Large page (8M) */
423 /* concat physical page address(r11) and page offset(r10) */
424 rlwimi r11, r10, 0, 32 - PAGE_SHIFT, 31
426 /* Check if it really is a dcbx instruction. */
427 /* dcbt and dcbtst does not generate DTLB Misses/Errors,
428 * no need to include them here */
429 xoris r10, r11, 0x7c00 /* check if major OP code is 31 */
430 rlwinm r10, r10, 0, 21, 5
431 cmpwi cr1, r10, 2028 /* Is dcbz? */
433 cmpwi cr1, r10, 940 /* Is dcbi? */
435 cmpwi cr1, r10, 108 /* Is dcbst? */
436 beq+ cr1, 144f /* Fix up store bit! */
437 cmpwi cr1, r10, 172 /* Is dcbf? */
439 cmpwi cr1, r10, 1964 /* Is icbi? */
441 141: mfspr r10,SPRN_M_TW
442 b DARFixed /* Nope, go back to normal TLB processing */
445 /* concat physical page address(r11) and page offset(r10) */
446 rlwimi r11, r10, 0, 32 - PAGE_SHIFT_8M, 31
449 144: mfspr r10, SPRN_DSISR
450 rlwinm r10, r10,0,7,5 /* Clear store bit for buggy dcbst insn */
451 mtspr SPRN_DSISR, r10
452 142: /* continue, it was a dcbx, dcbi instruction. */
454 mtdar r10 /* save ctr reg in DAR */
455 rlwinm r10, r11, 24, 24, 28 /* offset into jump table for reg RB */
456 addi r10, r10, 150f@l /* add start of table */
457 mtctr r10 /* load ctr with jump address */
458 xor r10, r10, r10 /* sum starts at zero */
459 bctr /* jump into table */
461 add r10, r10, r0 ;b 151f
462 add r10, r10, r1 ;b 151f
463 add r10, r10, r2 ;b 151f
464 add r10, r10, r3 ;b 151f
465 add r10, r10, r4 ;b 151f
466 add r10, r10, r5 ;b 151f
467 add r10, r10, r6 ;b 151f
468 add r10, r10, r7 ;b 151f
469 add r10, r10, r8 ;b 151f
470 add r10, r10, r9 ;b 151f
471 mtctr r11 ;b 154f /* r10 needs special handling */
472 mtctr r11 ;b 153f /* r11 needs special handling */
473 add r10, r10, r12 ;b 151f
474 add r10, r10, r13 ;b 151f
475 add r10, r10, r14 ;b 151f
476 add r10, r10, r15 ;b 151f
477 add r10, r10, r16 ;b 151f
478 add r10, r10, r17 ;b 151f
479 add r10, r10, r18 ;b 151f
480 add r10, r10, r19 ;b 151f
481 add r10, r10, r20 ;b 151f
482 add r10, r10, r21 ;b 151f
483 add r10, r10, r22 ;b 151f
484 add r10, r10, r23 ;b 151f
485 add r10, r10, r24 ;b 151f
486 add r10, r10, r25 ;b 151f
487 add r10, r10, r26 ;b 151f
488 add r10, r10, r27 ;b 151f
489 add r10, r10, r28 ;b 151f
490 add r10, r10, r29 ;b 151f
491 add r10, r10, r30 ;b 151f
494 rlwinm r11,r11,19,24,28 /* offset into jump table for reg RA */
496 beq cr1, 152f /* if reg RA is zero, don't add it */
497 addi r11, r11, 150b@l /* add start of table */
498 mtctr r11 /* load ctr with jump address */
499 rlwinm r11,r11,0,16,10 /* make sure we don't execute this more than once */
500 bctr /* jump into table */
503 mtctr r11 /* restore ctr reg from DAR */
504 mfspr r11, SPRN_SPRG_THREAD
506 mfspr r10, SPRN_DSISR
509 b DARFixed /* Go back to normal TLB handling */
511 /* special handling for r10,r11 since these are modified already */
512 153: mfspr r11, SPRN_SPRG_SCRATCH1 /* load r11 from SPRN_SPRG_SCRATCH1 */
513 add r10, r10, r11 /* add it */
514 mfctr r11 /* restore r11 */
516 154: mfspr r11, SPRN_SPRG_SCRATCH0 /* load r10 from SPRN_SPRG_SCRATCH0 */
517 add r10, r10, r11 /* add it */
518 mfctr r11 /* restore r11 */
522 * This is where the main kernel code starts.
527 ori r2,r2,init_task@l
529 /* ptr to phys current thread */
531 addi r4,r4,THREAD /* init task's THREAD */
532 mtspr SPRN_SPRG_THREAD,r4
535 lis r1,init_thread_union@ha
536 addi r1,r1,init_thread_union@l
537 lis r0, STACK_END_MAGIC@h
538 ori r0, r0, STACK_END_MAGIC@l
541 stwu r0,THREAD_SIZE-STACK_FRAME_MIN_SIZE(r1)
543 lis r6, swapper_pg_dir@ha
547 bl early_init /* We have to do this with MMU on */
550 * Decide what sort of machine this is and initialize the MMU.
561 * Go back to running unmapped so we can load up new values
562 * and change to using our exception vectors.
563 * On the 8xx, all we have to do is invalidate the TLB to clear
564 * the old 8M byte TLB mappings and load the page table base register.
566 /* The right way to do this would be to track it down through
567 * init's THREAD like the context switch code does, but this is
568 * easier......until someone changes init's static structures.
573 li r3,MSR_KERNEL & ~(MSR_IR|MSR_DR)
577 /* Load up the kernel context */
579 #ifdef CONFIG_PIN_TLB_IMMR
582 mtspr SPRN_MD_CTR, r0
583 LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID)
585 mtspr SPRN_MD_EPN, r0
586 LOAD_REG_IMMEDIATE(r0, MD_SVALID | MD_PS512K | MD_GUARDED)
587 mtspr SPRN_MD_TWC, r0
589 rlwinm r0, r0, 0, 0xfff80000
590 ori r0, r0, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \
591 _PAGE_NO_CACHE | _PAGE_PRESENT
592 mtspr SPRN_MD_RPN, r0
593 lis r0, (MD_TWAM | MD_RSV4I)@h
594 mtspr SPRN_MD_CTR, r0
596 #if !defined(CONFIG_PIN_TLB_DATA) && !defined(CONFIG_PIN_TLB_IMMR)
598 mtspr SPRN_MD_CTR, r0
600 tlbia /* Clear all TLB entries */
601 sync /* wait for tlbia/tlbie to finish */
603 /* set up the PTE pointers for the Abatron bdiGDB.
605 lis r5, abatron_pteptrs@h
606 ori r5, r5, abatron_pteptrs@l
607 stw r5, 0xf0(0) /* Must match your Abatron config file */
609 lis r6, swapper_pg_dir@h
610 ori r6, r6, swapper_pg_dir@l
613 /* Now turn on the MMU for real! */
615 lis r3,start_kernel@h
616 ori r3,r3,start_kernel@l
619 rfi /* enable MMU and jump to start_kernel */
621 /* Set up the initial MMU state so we can do the first level of
622 * kernel initialization. This maps the first 8 MBytes of memory 1:1
623 * virtual to physical. Also, set the cache mode since that is defined
624 * by TLB entries and perform any additional mapping (like of the IMMR).
625 * If configured to pin some TLBs, we pin the first 8 Mbytes of kernel,
626 * 24 Mbytes of data, and the 512k IMMR space. Anything not covered by
627 * these mappings is mapped by page tables.
629 SYM_FUNC_START_LOCAL(initial_mmu)
631 mtspr SPRN_MI_CTR, r8 /* remove PINNED ITLB entries */
633 mtspr SPRN_MD_CTR, r10 /* remove PINNED DTLB entries */
635 tlbia /* Invalidate all TLB entries */
637 lis r8, MI_APG_INIT@h /* Set protection modes */
638 ori r8, r8, MI_APG_INIT@l
640 lis r8, MD_APG_INIT@h
641 ori r8, r8, MD_APG_INIT@l
644 /* Map the lower RAM (up to 32 Mbytes) into the ITLB and DTLB */
647 oris r12, r10, MD_RSV4I@h
649 li r9, 4 /* up to 4 pages of 8M */
651 lis r9, KERNELBASE@h /* Create vaddr for TLB */
652 li r10, MI_PS8MEG | _PMD_ACCESSED | MI_SVALID
653 li r11, MI_BOOTINIT /* Create RPN for address 0 */
655 mtspr SPRN_MI_CTR, r8 /* Set instruction MMU control */
657 ori r0, r9, MI_EVALID /* Mark it valid */
658 mtspr SPRN_MI_EPN, r0
659 mtspr SPRN_MI_TWC, r10
660 mtspr SPRN_MI_RPN, r11 /* Store TLB entry */
661 mtspr SPRN_MD_CTR, r12
663 mtspr SPRN_MD_EPN, r0
664 mtspr SPRN_MD_TWC, r10
665 mtspr SPRN_MD_RPN, r11
671 /* Since the cache is enabled according to the information we
672 * just loaded into the TLB, invalidate and enable the caches here.
673 * We should probably check/set other modes....later.
676 mtspr SPRN_IC_CST, r8
677 mtspr SPRN_DC_CST, r8
679 mtspr SPRN_IC_CST, r8
680 mtspr SPRN_DC_CST, r8
681 /* Disable debug mode entry on breakpoints */
683 #ifdef CONFIG_PERF_EVENTS
684 rlwinm r8, r8, 0, ~0xc
686 rlwinm r8, r8, 0, ~0x8
690 SYM_FUNC_END(initial_mmu)
693 lis r9, (1f - PAGE_OFFSET)@h
694 ori r9, r9, (1f - PAGE_OFFSET)@l
697 li r12, MSR_KERNEL & ~(MSR_IR | MSR_DR | MSR_RI)
698 rlwinm r0, r10, 0, ~MSR_RI
699 rlwinm r0, r0, 0, ~MSR_EE
709 mtspr SPRN_MI_CTR, r5
710 mtspr SPRN_MD_CTR, r6
713 LOAD_REG_IMMEDIATE(r5, 28 << 8)
714 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET)
715 LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED)
716 LOAD_REG_IMMEDIATE(r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT)
717 LOAD_REG_ADDR(r9, _sinittext)
721 2: ori r0, r6, MI_EVALID
722 mtspr SPRN_MI_CTR, r5
723 mtspr SPRN_MI_EPN, r0
724 mtspr SPRN_MI_TWC, r7
725 mtspr SPRN_MI_RPN, r8
727 addis r6, r6, SZ_8M@h
728 addis r8, r8, SZ_8M@h
732 mtspr SPRN_MI_CTR, r0
734 LOAD_REG_IMMEDIATE(r5, 28 << 8 | MD_TWAM)
735 #ifdef CONFIG_PIN_TLB_DATA
736 LOAD_REG_IMMEDIATE(r6, PAGE_OFFSET)
737 LOAD_REG_IMMEDIATE(r7, MI_SVALID | MI_PS8MEG | _PMD_ACCESSED)
739 #ifdef CONFIG_PIN_TLB_IMMR
747 LOAD_REG_ADDR(r9, _sinittext)
749 2: ori r0, r6, MD_EVALID
750 ori r12, r8, 0xf0 | _PAGE_RO | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT
751 mtspr SPRN_MD_CTR, r5
752 mtspr SPRN_MD_EPN, r0
753 mtspr SPRN_MD_TWC, r7
754 mtspr SPRN_MD_RPN, r12
756 addis r6, r6, SZ_8M@h
757 addis r8, r8, SZ_8M@h
761 2: ori r0, r6, MD_EVALID
762 ori r12, r8, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | _PAGE_PRESENT
763 mtspr SPRN_MD_CTR, r5
764 mtspr SPRN_MD_EPN, r0
765 mtspr SPRN_MD_TWC, r7
766 mtspr SPRN_MD_RPN, r12
768 addis r6, r6, SZ_8M@h
769 addis r8, r8, SZ_8M@h
773 #ifdef CONFIG_PIN_TLB_IMMR
774 LOAD_REG_IMMEDIATE(r0, VIRT_IMMR_BASE | MD_EVALID)
775 LOAD_REG_IMMEDIATE(r7, MD_SVALID | MD_PS512K | MD_GUARDED | _PMD_ACCESSED)
777 rlwinm r8, r8, 0, 0xfff80000
778 ori r8, r8, 0xf0 | _PAGE_DIRTY | _PAGE_SPS | _PAGE_SH | \
779 _PAGE_NO_CACHE | _PAGE_PRESENT
780 mtspr SPRN_MD_CTR, r5
781 mtspr SPRN_MD_EPN, r0
782 mtspr SPRN_MD_TWC, r7
783 mtspr SPRN_MD_RPN, r8
785 #if defined(CONFIG_PIN_TLB_IMMR) || defined(CONFIG_PIN_TLB_DATA)
786 lis r0, (MD_RSV4I | MD_TWAM)@h
787 mtspr SPRN_MD_CTR, r0